From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBBDBC2D0F2 for ; Wed, 1 Apr 2020 08:26:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B8B5C2080C for ; Wed, 1 Apr 2020 08:26:31 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="VghYf4mc" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731759AbgDAI0b (ORCPT ); Wed, 1 Apr 2020 04:26:31 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:21958 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726197AbgDAI0a (ORCPT ); Wed, 1 Apr 2020 04:26:30 -0400 X-UUID: ae987413d5424ad39b5efb26be6d5138-20200401 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=KAc2JVwQuKcaNBn24f4yGzswCmaLnRG+W1Uvy/qyynU=; b=VghYf4mcfYRptzIJ5bf80ffxk+6Wyxc101JWAJ5potRTS6/IiC9Jb211RXWLY/VF+tCdN0LlN8Bskd+6W0qKtVxdrHpmGdWukUdfx+kQLcUR6/4hBELv7j6onzL3i0UcUJDB07CXPttHNwhpCg26mXNSu/164P9e2ydyVfij2ds=; X-UUID: ae987413d5424ad39b5efb26be6d5138-20200401 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 423719410; Wed, 01 Apr 2020 16:26:23 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 1 Apr 2020 16:26:19 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 1 Apr 2020 16:26:20 +0800 Message-ID: <1585729581.2029.2.camel@mtksdaap41> Subject: Re: [PATCH v10 3/5] mfd: Add support for the MediaTek MT6358 PMIC From: Hsin-hsiung Wang To: Lee Jones CC: Rob Herring , Alexandre Belloni , Matthias Brugger , Mark Rutland , Sean Wang , Sebastian Reichel , Eddie Huang , Alessandro Zummo , "Frank Wunderlich" , Thomas Gleixner , Richard Fontana , Josef Friedl , Ran Bi , , , , , , , Nicolas Boichat , Date: Wed, 1 Apr 2020 16:26:21 +0800 In-Reply-To: <20200325094326.GH442973@dell> References: <1583918223-22506-1-git-send-email-hsin-hsiung.wang@mediatek.com> <1583918223-22506-4-git-send-email-hsin-hsiung.wang@mediatek.com> <20200325094326.GH442973@dell> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: base64 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org SGksDQoNCk9uIFdlZCwgMjAyMC0wMy0yNSBhdCAwOTo0MyArMDAwMCwgTGVlIEpvbmVzIHdyb3Rl Og0KPiBPbiBXZWQsIDExIE1hciAyMDIwLCBIc2luLUhzaXVuZyBXYW5nIHdyb3RlOg0KPiANCj4g PiBUaGlzIGFkZHMgc3VwcG9ydCBmb3IgdGhlIE1lZGlhVGVrIE1UNjM1OCBQTUlDLiBUaGlzIGlz IGENCj4gPiBtdWx0aWZ1bmN0aW9uIGRldmljZSB3aXRoIHRoZSBmb2xsb3dpbmcgc3ViIG1vZHVs ZXM6DQo+ID4gDQo+ID4gLSBSZWd1bGF0b3INCj4gPiAtIFJUQw0KPiA+IC0gQ29kZWMNCj4gPiAt IEludGVycnVwdA0KPiA+IA0KPiA+IEl0IGlzIGludGVyZmFjZWQgdG8gdGhlIGhvc3QgY29udHJv bGxlciB1c2luZyBTUEkgaW50ZXJmYWNlDQo+ID4gYnkgYSBwcm9wcmlldGFyeSBoYXJkd2FyZSBj YWxsZWQgUE1JQyB3cmFwcGVyIG9yIHB3cmFwLg0KPiA+IE1UNjM1OCBNRkQgaXMgYSBjaGlsZCBk ZXZpY2Ugb2YgdGhlIHB3cmFwLg0KPiA+IA0KPiA+IFNpZ25lZC1vZmYtYnk6IEhzaW4tSHNpdW5n IFdhbmcgPGhzaW4taHNpdW5nLndhbmdAbWVkaWF0ZWsuY29tPg0KPiA+IC0tLQ0KPiA+ICBkcml2 ZXJzL21mZC9NYWtlZmlsZSAgICAgICAgICAgICAgICAgfCAgIDIgKy0NCj4gPiAgZHJpdmVycy9t ZmQvbXQ2MzU4LWlycS5jICAgICAgICAgICAgIHwgMjM2ICsrKysrKysrKysrKysrKysrKysrKysr KysrKysrDQo+ID4gIGRyaXZlcnMvbWZkL210NjM5Ny1jb3JlLmMgICAgICAgICAgICB8ICA1NSAr KysrKystDQo+ID4gIGluY2x1ZGUvbGludXgvbWZkL210NjM1OC9jb3JlLmggICAgICB8IDE1OCAr KysrKysrKysrKysrKysrKysrKw0KPiA+ICBpbmNsdWRlL2xpbnV4L21mZC9tdDYzNTgvcmVnaXN0 ZXJzLmggfCAyODIgKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysNCj4gPiAgaW5j bHVkZS9saW51eC9tZmQvbXQ2Mzk3L2NvcmUuaCAgICAgIHwgICAzICsNCj4gPiAgNiBmaWxlcyBj aGFuZ2VkLCA3MzEgaW5zZXJ0aW9ucygrKSwgNSBkZWxldGlvbnMoLSkNCj4gPiAgY3JlYXRlIG1v ZGUgMTAwNjQ0IGRyaXZlcnMvbWZkL210NjM1OC1pcnEuYw0KPiA+ICBjcmVhdGUgbW9kZSAxMDA2 NDQgaW5jbHVkZS9saW51eC9tZmQvbXQ2MzU4L2NvcmUuaA0KPiA+ICBjcmVhdGUgbW9kZSAxMDA2 NDQgaW5jbHVkZS9saW51eC9tZmQvbXQ2MzU4L3JlZ2lzdGVycy5oDQo+ID4gDQo+ID4gZGlmZiAt LWdpdCBhL2RyaXZlcnMvbWZkL01ha2VmaWxlIGIvZHJpdmVycy9tZmQvTWFrZWZpbGUNCj4gPiBp bmRleCBiODNmMTcyLi45YWYxNDE0IDEwMDY0NA0KPiA+IC0tLSBhL2RyaXZlcnMvbWZkL01ha2Vm aWxlDQo+ID4gKysrIGIvZHJpdmVycy9tZmQvTWFrZWZpbGUNCj4gPiBAQCAtMjM4LDcgKzIzOCw3 IEBAIG9iai0kKENPTkZJR19JTlRFTF9TT0NfUE1JQykJKz0gaW50ZWwtc29jLXBtaWMubw0KPiA+ ICBvYmotJChDT05GSUdfSU5URUxfU09DX1BNSUNfQlhUV0MpCSs9IGludGVsX3NvY19wbWljX2J4 dHdjLm8NCj4gPiAgb2JqLSQoQ09ORklHX0lOVEVMX1NPQ19QTUlDX0NIVFdDKQkrPSBpbnRlbF9z b2NfcG1pY19jaHR3Yy5vDQo+ID4gIG9iai0kKENPTkZJR19JTlRFTF9TT0NfUE1JQ19DSFREQ19U SSkJKz0gaW50ZWxfc29jX3BtaWNfY2h0ZGNfdGkubw0KPiA+IC1tdDYzOTctb2Jqcwk6PSBtdDYz OTctY29yZS5vIG10NjM5Ny1pcnEubw0KPiA+ICttdDYzOTctb2JqcwkJCTo9IG10NjM5Ny1jb3Jl Lm8gbXQ2Mzk3LWlycS5vIG10NjM1OC1pcnEubw0KPiA+ICBvYmotJChDT05GSUdfTUZEX01UNjM5 NykJKz0gbXQ2Mzk3Lm8NCj4gPiAgb2JqLSQoQ09ORklHX0lOVEVMX1NPQ19QTUlDX01SRkxEKQkr PSBpbnRlbF9zb2NfcG1pY19tcmZsZC5vDQo+ID4gIA0KPiA+IGRpZmYgLS1naXQgYS9kcml2ZXJz L21mZC9tdDYzNTgtaXJxLmMgYi9kcml2ZXJzL21mZC9tdDYzNTgtaXJxLmMNCj4gPiBuZXcgZmls ZSBtb2RlIDEwMDY0NA0KPiA+IGluZGV4IDAwMDAwMDAuLjAyMmU1ZjUNCj4gPiAtLS0gL2Rldi9u dWxsDQo+ID4gKysrIGIvZHJpdmVycy9tZmQvbXQ2MzU4LWlycS5jDQo+ID4gQEAgLTAsMCArMSwy MzYgQEANCj4gPiArLy8gU1BEWC1MaWNlbnNlLUlkZW50aWZpZXI6IEdQTC0yLjANCj4gPiArLy8N Cj4gPiArLy8gQ29weXJpZ2h0IChjKSAyMDE5IE1lZGlhVGVrIEluYy4NCj4gDQo+IFRoaXMgaXMg b3V0IG9mIGRhdGUuDQo+IA0KDQpUaGFua3MuIEkgd2lsbCB1cGRhdGUgaXQgaW4gdGhlIG5leHQg cGF0Y2guDQoNCj4gPiArI2luY2x1ZGUgPGxpbnV4L2ludGVycnVwdC5oPg0KPiA+ICsjaW5jbHVk ZSA8bGludXgvbWZkL210NjM1OC9jb3JlLmg+DQo+ID4gKyNpbmNsdWRlIDxsaW51eC9tZmQvbXQ2 MzU4L3JlZ2lzdGVycy5oPg0KPiA+ICsjaW5jbHVkZSA8bGludXgvbWZkL210NjM5Ny9jb3JlLmg+ DQo+ID4gKyNpbmNsdWRlIDxsaW51eC9tb2R1bGUuaD4NCj4gPiArI2luY2x1ZGUgPGxpbnV4L29m Lmg+DQo+ID4gKyNpbmNsdWRlIDxsaW51eC9vZl9kZXZpY2UuaD4NCj4gPiArI2luY2x1ZGUgPGxp bnV4L29mX2lycS5oPg0KPiA+ICsjaW5jbHVkZSA8bGludXgvcGxhdGZvcm1fZGV2aWNlLmg+DQo+ ID4gKyNpbmNsdWRlIDxsaW51eC9yZWdtYXAuaD4NCj4gPiArDQo+ID4gK3N0YXRpYyBzdHJ1Y3Qg aXJxX3RvcF90IG10NjM1OF9pbnRzW10gPSB7DQo+ID4gKwlNVDYzNThfVE9QX0dFTihCVUNLKSwN Cj4gPiArCU1UNjM1OF9UT1BfR0VOKExETyksDQo+ID4gKwlNVDYzNThfVE9QX0dFTihQU0MpLA0K PiA+ICsJTVQ2MzU4X1RPUF9HRU4oU0NLKSwNCj4gPiArCU1UNjM1OF9UT1BfR0VOKEJNKSwNCj4g PiArCU1UNjM1OF9UT1BfR0VOKEhLKSwNCj4gPiArCU1UNjM1OF9UT1BfR0VOKEFVRCksDQo+ID4g KwlNVDYzNThfVE9QX0dFTihNSVNDKSwNCj4gPiArfTsNCj4gPiArDQo+ID4gK3N0YXRpYyB2b2lk IHBtaWNfaXJxX2VuYWJsZShzdHJ1Y3QgaXJxX2RhdGEgKmRhdGEpDQo+ID4gK3sNCj4gPiArCXVu c2lnbmVkIGludCBod2lycSA9IGlycWRfdG9faHdpcnEoZGF0YSk7DQo+ID4gKwlzdHJ1Y3QgbXQ2 Mzk3X2NoaXAgKmNoaXAgPSBpcnFfZGF0YV9nZXRfaXJxX2NoaXBfZGF0YShkYXRhKTsNCj4gDQo+ IDYzOTc/DQo+IA0KPiBUaGlzIGRvZXMgbWFrZSBtZSB3b25kZXIgaG93IGRpZmZlcmVudCB0aGlz IGZpbGUgaXMgdG8gdGhlIGV4aXN0aW5nDQo+IHN1cHBvcnQgZm9yIHRoZSBNVDYzOTcuICBXaGF0 IGlzIHRoZSBqdXN0aWZpY2F0aW9uIGZvciBub3QgZXh0ZW5kaW5nDQo+IHRoYXQgaW5zdGVhZCBv ZiBjcmVhdGluZyBhIGJyYW5kIG5ldyBmaWxlPw0KPiANCg0KTVQ2MzU4IGlzIHNpbWlsYXIgdG8g TVQ2Mzk3IGZvciBtZmQgZHJpdmVyIGV4Y2VwdCB0aGUgaGFyZHdhcmUgZGVzaWduIG9mDQppbnRl cnJ1cHQgd2hpY2ggcHJvdmlkZXMgbW9yZSBpbnRlcnJ1cHRzIHRoYW4gTVQ2Mzk3Lg0KSSB0aGlu ayBNVDYzNTggY2FuIHJldXNlIHRoZSBvdGhlciBwYXJ0IG9mIE1UNjM5NyBtZmQgZHJpdmVyLCBz byBJIG9ubHkNCmFkZCB0aGUgaW50ZXJydXB0IHBhcnQgb2YgTVQ2MzU4Lg0KDQo+ID4gKwlzdHJ1 Y3QgcG1pY19pcnFfZGF0YSAqaXJxZCA9IGNoaXAtPmlycV9kYXRhOw0KPiA+ICsNCj4gPiArCWly cWQtPmVuYWJsZV9od2lycVtod2lycV0gPSB0cnVlOw0KPiA+ICt9DQo+ID4gKw0KPiA+ICtzdGF0 aWMgdm9pZCBwbWljX2lycV9kaXNhYmxlKHN0cnVjdCBpcnFfZGF0YSAqZGF0YSkNCj4gPiArew0K PiA+ICsJdW5zaWduZWQgaW50IGh3aXJxID0gaXJxZF90b19od2lycShkYXRhKTsNCj4gPiArCXN0 cnVjdCBtdDYzOTdfY2hpcCAqY2hpcCA9IGlycV9kYXRhX2dldF9pcnFfY2hpcF9kYXRhKGRhdGEp Ow0KPiA+ICsJc3RydWN0IHBtaWNfaXJxX2RhdGEgKmlycWQgPSBjaGlwLT5pcnFfZGF0YTsNCj4g PiArDQo+ID4gKwlpcnFkLT5lbmFibGVfaHdpcnFbaHdpcnFdID0gZmFsc2U7DQo+ID4gK30NCj4g PiArDQo+ID4gK3N0YXRpYyB2b2lkIHBtaWNfaXJxX2xvY2soc3RydWN0IGlycV9kYXRhICpkYXRh KQ0KPiA+ICt7DQo+ID4gKwlzdHJ1Y3QgbXQ2Mzk3X2NoaXAgKmNoaXAgPSBpcnFfZGF0YV9nZXRf aXJxX2NoaXBfZGF0YShkYXRhKTsNCj4gPiArDQo+ID4gKwltdXRleF9sb2NrKCZjaGlwLT5pcnFs b2NrKTsNCj4gPiArfQ0KPiA+ICsNCj4gPiArc3RhdGljIHZvaWQgcG1pY19pcnFfc3luY191bmxv Y2soc3RydWN0IGlycV9kYXRhICpkYXRhKQ0KPiA+ICt7DQo+ID4gKwl1bnNpZ25lZCBpbnQgaSwg dG9wX2dwLCBncF9vZmZzZXQsIGVuX3JlZywgaW50X3JlZ3MsIHNoaWZ0Ow0KPiA+ICsJc3RydWN0 IG10NjM5N19jaGlwICpjaGlwID0gaXJxX2RhdGFfZ2V0X2lycV9jaGlwX2RhdGEoZGF0YSk7DQo+ ID4gKwlzdHJ1Y3QgcG1pY19pcnFfZGF0YSAqaXJxZCA9IGNoaXAtPmlycV9kYXRhOw0KPiA+ICsN Cj4gPiArCWZvciAoaSA9IDA7IGkgPCBpcnFkLT5udW1fcG1pY19pcnFzOyBpKyspIHsNCj4gPiAr CQlpZiAoaXJxZC0+ZW5hYmxlX2h3aXJxW2ldID09IGlycWQtPmNhY2hlX2h3aXJxW2ldKQ0KPiA+ ICsJCQljb250aW51ZTsNCj4gPiArDQo+ID4gKwkJLyogRmluZCBvdXQgdGhlIElSUSBncm91cCAq Lw0KPiA+ICsJCXRvcF9ncCA9IDA7DQo+ID4gKwkJd2hpbGUgKCh0b3BfZ3AgKyAxKSA8IGlycWQt Pm51bV90b3AgJiYNCj4gPiArCQkgICAgICAgaSA+PSBtdDYzNThfaW50c1t0b3BfZ3AgKyAxXS5o d2lycV9iYXNlKQ0KPiA+ICsJCQl0b3BfZ3ArKzsNCj4gPiArDQo+ID4gKwkJLyogRmluZCB0aGUg aXJxIHJlZ2lzdGVycyAqLw0KPiANCj4gTml0OiAiSVJRIg0KPiANCg0KVGhhbmtzLiBJIHdpbGwg dXBkYXRlIGl0IGluIHRoZSBuZXh0IHBhdGNoLg0KDQo+ID4gKwkJZ3Bfb2Zmc2V0ID0gaSAtIG10 NjM1OF9pbnRzW3RvcF9ncF0uaHdpcnFfYmFzZTsNCj4gPiArCQlpbnRfcmVncyA9IGdwX29mZnNl dCAvIE1UNjM1OF9SRUdfV0lEVEg7DQo+ID4gKwkJc2hpZnQgPSBncF9vZmZzZXQgJSBNVDYzNThf UkVHX1dJRFRIOw0KPiA+ICsJCWVuX3JlZyA9IG10NjM1OF9pbnRzW3RvcF9ncF0uZW5fcmVnICsN Cj4gPiArCQkJIChtdDYzNThfaW50c1t0b3BfZ3BdLmVuX3JlZ19zaGlmdCAqIGludF9yZWdzKTsN Cj4gPiArDQo+ID4gKwkJcmVnbWFwX3VwZGF0ZV9iaXRzKGNoaXAtPnJlZ21hcCwgZW5fcmVnLCBC SVQoc2hpZnQpLA0KPiA+ICsJCQkJICAgaXJxZC0+ZW5hYmxlX2h3aXJxW2ldIDw8IHNoaWZ0KTsN Cj4gPiArDQo+ID4gKwkJaXJxZC0+Y2FjaGVfaHdpcnFbaV0gPSBpcnFkLT5lbmFibGVfaHdpcnFb aV07DQo+ID4gKwl9DQo+ID4gKwltdXRleF91bmxvY2soJmNoaXAtPmlycWxvY2spOw0KPiA+ICt9 DQo+IA0KPiBbLi4uXQ0KPiANCj4gPiAraW50IG10NjM1OF9pcnFfaW5pdChzdHJ1Y3QgbXQ2Mzk3 X2NoaXAgKmNoaXApDQo+ID4gK3sNCj4gPiArCWludCBpLCBqLCByZXQ7DQo+ID4gKwlzdHJ1Y3Qg cG1pY19pcnFfZGF0YSAqaXJxZDsNCj4gPiArDQo+ID4gKwlpcnFkID0gZGV2bV9remFsbG9jKGNo aXAtPmRldiwgc2l6ZW9mKHN0cnVjdCBwbWljX2lycV9kYXRhICopLA0KPiANCj4gc2l6ZW9mKCpp cnFkKQ0KPiANCg0KVGhhbmtzLiBJIHdpbGwgdXBkYXRlIGl0IGluIHRoZSBuZXh0IHBhdGNoLg0K DQo+IFsuLi5dDQo+IA0KPiA+ICBzdGF0aWMgY29uc3Qgc3RydWN0IGNoaXBfZGF0YSBtdDYzOTdf Y29yZSA9IHsNCj4gPiAgCS5jaWRfYWRkciA9IE1UNjM5N19DSUQsDQo+ID4gIAkuY2lkX3NoaWZ0 ID0gMCwNCj4gPiBAQCAtMTU0LDE5ICsxODQsMzMgQEAgc3RhdGljIGludCBtdDYzOTdfcHJvYmUo c3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRldikNCj4gPiAgCWlmIChwbWljLT5pcnEgPD0gMCkN Cj4gPiAgCQlyZXR1cm4gcG1pYy0+aXJxOw0KPiA+ICANCj4gPiAtCXJldCA9IG10NjM5N19pcnFf aW5pdChwbWljKTsNCj4gPiAtCWlmIChyZXQpDQo+ID4gLQkJcmV0dXJuIHJldDsNCj4gPiAtDQo+ ID4gIAlzd2l0Y2ggKHBtaWMtPmNoaXBfaWQpIHsNCj4gPiAgCWNhc2UgTVQ2MzIzX0NISVBfSUQ6 DQo+ID4gKwkJcmV0ID0gbXQ2Mzk3X2lycV9pbml0KHBtaWMpOw0KPiA+ICsJCWlmIChyZXQpDQo+ ID4gKwkJCXJldHVybiByZXQ7DQo+ID4gKw0KPiA+ICAJCXJldCA9IGRldm1fbWZkX2FkZF9kZXZp Y2VzKCZwZGV2LT5kZXYsIFBMQVRGT1JNX0RFVklEX05PTkUsDQo+ID4gIAkJCQkJICAgbXQ2MzIz X2RldnMsIEFSUkFZX1NJWkUobXQ2MzIzX2RldnMpLA0KPiA+ICAJCQkJCSAgIE5VTEwsIDAsIHBt aWMtPmlycV9kb21haW4pOw0KPiA+ICAJCWJyZWFrOw0KPiA+ICANCj4gPiArCWNhc2UgTVQ2MzU4 X0NISVBfSUQ6DQo+ID4gKwkJcmV0ID0gbXQ2MzU4X2lycV9pbml0KHBtaWMpOw0KPiA+ICsJCWlm IChyZXQpDQo+ID4gKwkJCXJldHVybiByZXQ7DQo+ID4gKw0KPiA+ICsJCXJldCA9IGRldm1fbWZk X2FkZF9kZXZpY2VzKCZwZGV2LT5kZXYsIFBMQVRGT1JNX0RFVklEX05PTkUsDQo+ID4gKwkJCQkJ ICAgbXQ2MzU4X2RldnMsIEFSUkFZX1NJWkUobXQ2MzU4X2RldnMpLA0KPiA+ICsJCQkJCSAgIE5V TEwsIDAsIHBtaWMtPmlycV9kb21haW4pOw0KPiANCj4gSW4gYSBzdWJzZXF1ZW50IHBhdGNoIHlv dSBjYW4gY2hvb3NlIHRoZSBjb3JyZWN0IG10WFhYWF9kZXZzIHN0cnVjdHVyZQ0KPiB0byBwYXNz IGFuZCBjYWxsIGRldm1fbWZkX2FkZF9kZXZpY2VzKCkgb25seSBvbmNlIGJlbG93IHRoZSBzd2l0 Y2goKS4NCj4gDQoNClRoYW5rcyBmb3IgeW91ciBjb21tZW50LiBJIHdpbGwgcmV3cml0ZSB0aGlz IGluIHRoZSBuZXh0IHBhdGNoLg0KDQo+ID4gKwkJYnJlYWs7DQo+ID4gKw0KPiA+ICAJY2FzZSBN VDYzOTFfQ0hJUF9JRDoNCj4gPiAgCWNhc2UgTVQ2Mzk3X0NISVBfSUQ6DQo+ID4gKwkJcmV0ID0g bXQ2Mzk3X2lycV9pbml0KHBtaWMpOw0KPiA+ICsJCWlmIChyZXQpDQo+ID4gKwkJCXJldHVybiBy ZXQ7DQo+ID4gKw0KPiA+ICAJCXJldCA9IGRldm1fbWZkX2FkZF9kZXZpY2VzKCZwZGV2LT5kZXYs IFBMQVRGT1JNX0RFVklEX05PTkUsDQo+ID4gIAkJCQkJICAgbXQ2Mzk3X2RldnMsIEFSUkFZX1NJ WkUobXQ2Mzk3X2RldnMpLA0KPiA+ICAJCQkJCSAgIE5VTEwsIDAsIHBtaWMtPmlycV9kb21haW4p Ow0KPiANCj4gWy4uLl0NCj4gDQoNCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45187C43331 for ; Wed, 1 Apr 2020 08:26:45 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 18A7620719 for ; Wed, 1 Apr 2020 08:26:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="L0lM3lb8"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="a1l0Kn60" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 18A7620719 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Date:To:From:Subject:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=viYEX05DJSA7MKAQ6oTFQ+2BularSU3CV8Pg5XOQNcs=; b=L0lM3lb8oaUIYj ep5nLVckaYkOEwEp1DG+GHPpUjjBwSmd2dfj+8AjOrbGV345TDdWUXl/4cZ5D2nUo+7OdoIUnQB40 iVBnfnjIbf971PhikBmu10Nf+A1asfV36gGqXsr1ZWVOzJWSSyllczVmIwd1+dZbjeMJmvgLWSmRy yk49aLrNOPU+z31GlXuJyTGkFoYkcEgYPJWsE6HYIT6QmT9y/TWkWrDKP+rYw2Bxxu4L8k7pwtS7U 3VphVUJCXuPDMmglc1Ou+Cf4nOkWHURaToKB2UeXK+U+UY2kfDhmLaNR6U5xXixCOFOPAJ0DE1+/G j2+R53C/h8B0Gc9NgMoA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jJYhm-0006sk-6d; Wed, 01 Apr 2020 08:26:34 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jJYhf-0006lW-1O; Wed, 01 Apr 2020 08:26:28 +0000 X-UUID: 1aba86798d5a48c6897f4a718828a260-20200401 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=KAc2JVwQuKcaNBn24f4yGzswCmaLnRG+W1Uvy/qyynU=; b=a1l0Kn60T951eePkQkVfwHCdndZk0Mqx1kqtdJJKYulkQ6UYDie0B87rdD/3hRIHzIfUHU7zhLxWCLL9ztfMSGeLlYs7uhaiWrIjOi6vvqRzqw1Ze8dGjLvT8Y9ii4EhO9cpM79P1wd6glknZyhstmLOqaMpRhduqgHVFXp8xZA=; X-UUID: 1aba86798d5a48c6897f4a718828a260-20200401 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1769463170; Wed, 01 Apr 2020 00:26:19 -0800 Received: from MTKMBS01N1.mediatek.inc (172.21.101.68) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 1 Apr 2020 01:26:22 -0700 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 1 Apr 2020 16:26:19 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 1 Apr 2020 16:26:20 +0800 Message-ID: <1585729581.2029.2.camel@mtksdaap41> Subject: Re: [PATCH v10 3/5] mfd: Add support for the MediaTek MT6358 PMIC From: Hsin-hsiung Wang To: Lee Jones Date: Wed, 1 Apr 2020 16:26:21 +0800 In-Reply-To: <20200325094326.GH442973@dell> References: <1583918223-22506-1-git-send-email-hsin-hsiung.wang@mediatek.com> <1583918223-22506-4-git-send-email-hsin-hsiung.wang@mediatek.com> <20200325094326.GH442973@dell> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200401_012627_087658_3E9C916C X-CRM114-Status: GOOD ( 28.82 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Alessandro Zummo , Alexandre Belloni , Nicolas Boichat , srv_heupstream@mediatek.com, Frank Wunderlich , Josef Friedl , Ran Bi , Sean Wang , Sebastian Reichel , linux-kernel@vger.kernel.org, Richard Fontana , devicetree@vger.kernel.org, Rob Herring , linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, Matthias Brugger , Thomas Gleixner , Eddie Huang , linux-arm-kernel@lists.infradead.org, linux-rtc@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Hi, On Wed, 2020-03-25 at 09:43 +0000, Lee Jones wrote: > On Wed, 11 Mar 2020, Hsin-Hsiung Wang wrote: > > > This adds support for the MediaTek MT6358 PMIC. This is a > > multifunction device with the following sub modules: > > > > - Regulator > > - RTC > > - Codec > > - Interrupt > > > > It is interfaced to the host controller using SPI interface > > by a proprietary hardware called PMIC wrapper or pwrap. > > MT6358 MFD is a child device of the pwrap. > > > > Signed-off-by: Hsin-Hsiung Wang > > --- > > drivers/mfd/Makefile | 2 +- > > drivers/mfd/mt6358-irq.c | 236 +++++++++++++++++++++++++++++ > > drivers/mfd/mt6397-core.c | 55 ++++++- > > include/linux/mfd/mt6358/core.h | 158 ++++++++++++++++++++ > > include/linux/mfd/mt6358/registers.h | 282 +++++++++++++++++++++++++++++++++++ > > include/linux/mfd/mt6397/core.h | 3 + > > 6 files changed, 731 insertions(+), 5 deletions(-) > > create mode 100644 drivers/mfd/mt6358-irq.c > > create mode 100644 include/linux/mfd/mt6358/core.h > > create mode 100644 include/linux/mfd/mt6358/registers.h > > > > diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile > > index b83f172..9af1414 100644 > > --- a/drivers/mfd/Makefile > > +++ b/drivers/mfd/Makefile > > @@ -238,7 +238,7 @@ obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o > > obj-$(CONFIG_INTEL_SOC_PMIC_BXTWC) += intel_soc_pmic_bxtwc.o > > obj-$(CONFIG_INTEL_SOC_PMIC_CHTWC) += intel_soc_pmic_chtwc.o > > obj-$(CONFIG_INTEL_SOC_PMIC_CHTDC_TI) += intel_soc_pmic_chtdc_ti.o > > -mt6397-objs := mt6397-core.o mt6397-irq.o > > +mt6397-objs := mt6397-core.o mt6397-irq.o mt6358-irq.o > > obj-$(CONFIG_MFD_MT6397) += mt6397.o > > obj-$(CONFIG_INTEL_SOC_PMIC_MRFLD) += intel_soc_pmic_mrfld.o > > > > diff --git a/drivers/mfd/mt6358-irq.c b/drivers/mfd/mt6358-irq.c > > new file mode 100644 > > index 0000000..022e5f5 > > --- /dev/null > > +++ b/drivers/mfd/mt6358-irq.c > > @@ -0,0 +1,236 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +// > > +// Copyright (c) 2019 MediaTek Inc. > > This is out of date. > Thanks. I will update it in the next patch. > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +static struct irq_top_t mt6358_ints[] = { > > + MT6358_TOP_GEN(BUCK), > > + MT6358_TOP_GEN(LDO), > > + MT6358_TOP_GEN(PSC), > > + MT6358_TOP_GEN(SCK), > > + MT6358_TOP_GEN(BM), > > + MT6358_TOP_GEN(HK), > > + MT6358_TOP_GEN(AUD), > > + MT6358_TOP_GEN(MISC), > > +}; > > + > > +static void pmic_irq_enable(struct irq_data *data) > > +{ > > + unsigned int hwirq = irqd_to_hwirq(data); > > + struct mt6397_chip *chip = irq_data_get_irq_chip_data(data); > > 6397? > > This does make me wonder how different this file is to the existing > support for the MT6397. What is the justification for not extending > that instead of creating a brand new file? > MT6358 is similar to MT6397 for mfd driver except the hardware design of interrupt which provides more interrupts than MT6397. I think MT6358 can reuse the other part of MT6397 mfd driver, so I only add the interrupt part of MT6358. > > + struct pmic_irq_data *irqd = chip->irq_data; > > + > > + irqd->enable_hwirq[hwirq] = true; > > +} > > + > > +static void pmic_irq_disable(struct irq_data *data) > > +{ > > + unsigned int hwirq = irqd_to_hwirq(data); > > + struct mt6397_chip *chip = irq_data_get_irq_chip_data(data); > > + struct pmic_irq_data *irqd = chip->irq_data; > > + > > + irqd->enable_hwirq[hwirq] = false; > > +} > > + > > +static void pmic_irq_lock(struct irq_data *data) > > +{ > > + struct mt6397_chip *chip = irq_data_get_irq_chip_data(data); > > + > > + mutex_lock(&chip->irqlock); > > +} > > + > > +static void pmic_irq_sync_unlock(struct irq_data *data) > > +{ > > + unsigned int i, top_gp, gp_offset, en_reg, int_regs, shift; > > + struct mt6397_chip *chip = irq_data_get_irq_chip_data(data); > > + struct pmic_irq_data *irqd = chip->irq_data; > > + > > + for (i = 0; i < irqd->num_pmic_irqs; i++) { > > + if (irqd->enable_hwirq[i] == irqd->cache_hwirq[i]) > > + continue; > > + > > + /* Find out the IRQ group */ > > + top_gp = 0; > > + while ((top_gp + 1) < irqd->num_top && > > + i >= mt6358_ints[top_gp + 1].hwirq_base) > > + top_gp++; > > + > > + /* Find the irq registers */ > > Nit: "IRQ" > Thanks. I will update it in the next patch. > > + gp_offset = i - mt6358_ints[top_gp].hwirq_base; > > + int_regs = gp_offset / MT6358_REG_WIDTH; > > + shift = gp_offset % MT6358_REG_WIDTH; > > + en_reg = mt6358_ints[top_gp].en_reg + > > + (mt6358_ints[top_gp].en_reg_shift * int_regs); > > + > > + regmap_update_bits(chip->regmap, en_reg, BIT(shift), > > + irqd->enable_hwirq[i] << shift); > > + > > + irqd->cache_hwirq[i] = irqd->enable_hwirq[i]; > > + } > > + mutex_unlock(&chip->irqlock); > > +} > > [...] > > > +int mt6358_irq_init(struct mt6397_chip *chip) > > +{ > > + int i, j, ret; > > + struct pmic_irq_data *irqd; > > + > > + irqd = devm_kzalloc(chip->dev, sizeof(struct pmic_irq_data *), > > sizeof(*irqd) > Thanks. I will update it in the next patch. > [...] > > > static const struct chip_data mt6397_core = { > > .cid_addr = MT6397_CID, > > .cid_shift = 0, > > @@ -154,19 +184,33 @@ static int mt6397_probe(struct platform_device *pdev) > > if (pmic->irq <= 0) > > return pmic->irq; > > > > - ret = mt6397_irq_init(pmic); > > - if (ret) > > - return ret; > > - > > switch (pmic->chip_id) { > > case MT6323_CHIP_ID: > > + ret = mt6397_irq_init(pmic); > > + if (ret) > > + return ret; > > + > > ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, > > mt6323_devs, ARRAY_SIZE(mt6323_devs), > > NULL, 0, pmic->irq_domain); > > break; > > > > + case MT6358_CHIP_ID: > > + ret = mt6358_irq_init(pmic); > > + if (ret) > > + return ret; > > + > > + ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, > > + mt6358_devs, ARRAY_SIZE(mt6358_devs), > > + NULL, 0, pmic->irq_domain); > > In a subsequent patch you can choose the correct mtXXXX_devs structure > to pass and call devm_mfd_add_devices() only once below the switch(). > Thanks for your comment. I will rewrite this in the next patch. > > + break; > > + > > case MT6391_CHIP_ID: > > case MT6397_CHIP_ID: > > + ret = mt6397_irq_init(pmic); > > + if (ret) > > + return ret; > > + > > ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, > > mt6397_devs, ARRAY_SIZE(mt6397_devs), > > NULL, 0, pmic->irq_domain); > > [...] > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77E57C43331 for ; Wed, 1 Apr 2020 08:26:31 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 44A6E20787 for ; Wed, 1 Apr 2020 08:26:31 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="D/spW1uM"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="a1l0Kn60" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 44A6E20787 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Date:To:From:Subject:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=4aQntXYZGIaRTmck6gLPb7bzzYVorg0rNarwW9C7i2w=; b=D/spW1uMo6uWlS GGEaFgs33mEcdQhJ2jgzbUqhdzFxmGZUa3r1bMZkWFBYrQYK+M3s8SkziOT5j1kvYrkLkzpP2JkVo 37onV/pthrCd3qgAwjXMjiYmh1fvgzLolVTHNaR7VFWOjbW2yoL5/kwyNYiDphEat547SVogkMQUr XK4hA1yxE4sGrD+Y/kPfWFB2qRTPq2Yng586N6eER0VvPTSJQjlheEWJjacvwOYSrmiKycaWabw// RYU8Fsj4PVzI5TvkNX79sMQHCNd7SDR0nvSdc7UDcBp4R3aLh/5bcwFFvOh79S24PGDcMPluSOcaP ywxbXfR1ojSt7sx+Z4nQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jJYhi-0006mJ-4p; Wed, 01 Apr 2020 08:26:30 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jJYhf-0006lW-1O; Wed, 01 Apr 2020 08:26:28 +0000 X-UUID: 1aba86798d5a48c6897f4a718828a260-20200401 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=KAc2JVwQuKcaNBn24f4yGzswCmaLnRG+W1Uvy/qyynU=; b=a1l0Kn60T951eePkQkVfwHCdndZk0Mqx1kqtdJJKYulkQ6UYDie0B87rdD/3hRIHzIfUHU7zhLxWCLL9ztfMSGeLlYs7uhaiWrIjOi6vvqRzqw1Ze8dGjLvT8Y9ii4EhO9cpM79P1wd6glknZyhstmLOqaMpRhduqgHVFXp8xZA=; X-UUID: 1aba86798d5a48c6897f4a718828a260-20200401 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1769463170; Wed, 01 Apr 2020 00:26:19 -0800 Received: from MTKMBS01N1.mediatek.inc (172.21.101.68) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 1 Apr 2020 01:26:22 -0700 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 1 Apr 2020 16:26:19 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 1 Apr 2020 16:26:20 +0800 Message-ID: <1585729581.2029.2.camel@mtksdaap41> Subject: Re: [PATCH v10 3/5] mfd: Add support for the MediaTek MT6358 PMIC From: Hsin-hsiung Wang To: Lee Jones Date: Wed, 1 Apr 2020 16:26:21 +0800 In-Reply-To: <20200325094326.GH442973@dell> References: <1583918223-22506-1-git-send-email-hsin-hsiung.wang@mediatek.com> <1583918223-22506-4-git-send-email-hsin-hsiung.wang@mediatek.com> <20200325094326.GH442973@dell> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200401_012627_087658_3E9C916C X-CRM114-Status: GOOD ( 28.82 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Alessandro Zummo , Alexandre Belloni , Nicolas Boichat , srv_heupstream@mediatek.com, Frank Wunderlich , Josef Friedl , Ran Bi , Sean Wang , Sebastian Reichel , linux-kernel@vger.kernel.org, Richard Fontana , devicetree@vger.kernel.org, Rob Herring , linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, Matthias Brugger , Thomas Gleixner , Eddie Huang , linux-arm-kernel@lists.infradead.org, linux-rtc@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, On Wed, 2020-03-25 at 09:43 +0000, Lee Jones wrote: > On Wed, 11 Mar 2020, Hsin-Hsiung Wang wrote: > > > This adds support for the MediaTek MT6358 PMIC. This is a > > multifunction device with the following sub modules: > > > > - Regulator > > - RTC > > - Codec > > - Interrupt > > > > It is interfaced to the host controller using SPI interface > > by a proprietary hardware called PMIC wrapper or pwrap. > > MT6358 MFD is a child device of the pwrap. > > > > Signed-off-by: Hsin-Hsiung Wang > > --- > > drivers/mfd/Makefile | 2 +- > > drivers/mfd/mt6358-irq.c | 236 +++++++++++++++++++++++++++++ > > drivers/mfd/mt6397-core.c | 55 ++++++- > > include/linux/mfd/mt6358/core.h | 158 ++++++++++++++++++++ > > include/linux/mfd/mt6358/registers.h | 282 +++++++++++++++++++++++++++++++++++ > > include/linux/mfd/mt6397/core.h | 3 + > > 6 files changed, 731 insertions(+), 5 deletions(-) > > create mode 100644 drivers/mfd/mt6358-irq.c > > create mode 100644 include/linux/mfd/mt6358/core.h > > create mode 100644 include/linux/mfd/mt6358/registers.h > > > > diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile > > index b83f172..9af1414 100644 > > --- a/drivers/mfd/Makefile > > +++ b/drivers/mfd/Makefile > > @@ -238,7 +238,7 @@ obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o > > obj-$(CONFIG_INTEL_SOC_PMIC_BXTWC) += intel_soc_pmic_bxtwc.o > > obj-$(CONFIG_INTEL_SOC_PMIC_CHTWC) += intel_soc_pmic_chtwc.o > > obj-$(CONFIG_INTEL_SOC_PMIC_CHTDC_TI) += intel_soc_pmic_chtdc_ti.o > > -mt6397-objs := mt6397-core.o mt6397-irq.o > > +mt6397-objs := mt6397-core.o mt6397-irq.o mt6358-irq.o > > obj-$(CONFIG_MFD_MT6397) += mt6397.o > > obj-$(CONFIG_INTEL_SOC_PMIC_MRFLD) += intel_soc_pmic_mrfld.o > > > > diff --git a/drivers/mfd/mt6358-irq.c b/drivers/mfd/mt6358-irq.c > > new file mode 100644 > > index 0000000..022e5f5 > > --- /dev/null > > +++ b/drivers/mfd/mt6358-irq.c > > @@ -0,0 +1,236 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +// > > +// Copyright (c) 2019 MediaTek Inc. > > This is out of date. > Thanks. I will update it in the next patch. > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +static struct irq_top_t mt6358_ints[] = { > > + MT6358_TOP_GEN(BUCK), > > + MT6358_TOP_GEN(LDO), > > + MT6358_TOP_GEN(PSC), > > + MT6358_TOP_GEN(SCK), > > + MT6358_TOP_GEN(BM), > > + MT6358_TOP_GEN(HK), > > + MT6358_TOP_GEN(AUD), > > + MT6358_TOP_GEN(MISC), > > +}; > > + > > +static void pmic_irq_enable(struct irq_data *data) > > +{ > > + unsigned int hwirq = irqd_to_hwirq(data); > > + struct mt6397_chip *chip = irq_data_get_irq_chip_data(data); > > 6397? > > This does make me wonder how different this file is to the existing > support for the MT6397. What is the justification for not extending > that instead of creating a brand new file? > MT6358 is similar to MT6397 for mfd driver except the hardware design of interrupt which provides more interrupts than MT6397. I think MT6358 can reuse the other part of MT6397 mfd driver, so I only add the interrupt part of MT6358. > > + struct pmic_irq_data *irqd = chip->irq_data; > > + > > + irqd->enable_hwirq[hwirq] = true; > > +} > > + > > +static void pmic_irq_disable(struct irq_data *data) > > +{ > > + unsigned int hwirq = irqd_to_hwirq(data); > > + struct mt6397_chip *chip = irq_data_get_irq_chip_data(data); > > + struct pmic_irq_data *irqd = chip->irq_data; > > + > > + irqd->enable_hwirq[hwirq] = false; > > +} > > + > > +static void pmic_irq_lock(struct irq_data *data) > > +{ > > + struct mt6397_chip *chip = irq_data_get_irq_chip_data(data); > > + > > + mutex_lock(&chip->irqlock); > > +} > > + > > +static void pmic_irq_sync_unlock(struct irq_data *data) > > +{ > > + unsigned int i, top_gp, gp_offset, en_reg, int_regs, shift; > > + struct mt6397_chip *chip = irq_data_get_irq_chip_data(data); > > + struct pmic_irq_data *irqd = chip->irq_data; > > + > > + for (i = 0; i < irqd->num_pmic_irqs; i++) { > > + if (irqd->enable_hwirq[i] == irqd->cache_hwirq[i]) > > + continue; > > + > > + /* Find out the IRQ group */ > > + top_gp = 0; > > + while ((top_gp + 1) < irqd->num_top && > > + i >= mt6358_ints[top_gp + 1].hwirq_base) > > + top_gp++; > > + > > + /* Find the irq registers */ > > Nit: "IRQ" > Thanks. I will update it in the next patch. > > + gp_offset = i - mt6358_ints[top_gp].hwirq_base; > > + int_regs = gp_offset / MT6358_REG_WIDTH; > > + shift = gp_offset % MT6358_REG_WIDTH; > > + en_reg = mt6358_ints[top_gp].en_reg + > > + (mt6358_ints[top_gp].en_reg_shift * int_regs); > > + > > + regmap_update_bits(chip->regmap, en_reg, BIT(shift), > > + irqd->enable_hwirq[i] << shift); > > + > > + irqd->cache_hwirq[i] = irqd->enable_hwirq[i]; > > + } > > + mutex_unlock(&chip->irqlock); > > +} > > [...] > > > +int mt6358_irq_init(struct mt6397_chip *chip) > > +{ > > + int i, j, ret; > > + struct pmic_irq_data *irqd; > > + > > + irqd = devm_kzalloc(chip->dev, sizeof(struct pmic_irq_data *), > > sizeof(*irqd) > Thanks. I will update it in the next patch. > [...] > > > static const struct chip_data mt6397_core = { > > .cid_addr = MT6397_CID, > > .cid_shift = 0, > > @@ -154,19 +184,33 @@ static int mt6397_probe(struct platform_device *pdev) > > if (pmic->irq <= 0) > > return pmic->irq; > > > > - ret = mt6397_irq_init(pmic); > > - if (ret) > > - return ret; > > - > > switch (pmic->chip_id) { > > case MT6323_CHIP_ID: > > + ret = mt6397_irq_init(pmic); > > + if (ret) > > + return ret; > > + > > ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, > > mt6323_devs, ARRAY_SIZE(mt6323_devs), > > NULL, 0, pmic->irq_domain); > > break; > > > > + case MT6358_CHIP_ID: > > + ret = mt6358_irq_init(pmic); > > + if (ret) > > + return ret; > > + > > + ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, > > + mt6358_devs, ARRAY_SIZE(mt6358_devs), > > + NULL, 0, pmic->irq_domain); > > In a subsequent patch you can choose the correct mtXXXX_devs structure > to pass and call devm_mfd_add_devices() only once below the switch(). > Thanks for your comment. I will rewrite this in the next patch. > > + break; > > + > > case MT6391_CHIP_ID: > > case MT6397_CHIP_ID: > > + ret = mt6397_irq_init(pmic); > > + if (ret) > > + return ret; > > + > > ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, > > mt6397_devs, ARRAY_SIZE(mt6397_devs), > > NULL, 0, pmic->irq_domain); > > [...] > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel