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* [Intel-gfx] [PATCH v2 1/8] drm/i915/display: Move out code to return the digital_port of the aux ch
@ 2020-04-07  1:11 José Roberto de Souza
  2020-04-07  1:11 ` [Intel-gfx] [PATCH v2 2/8] drm/i915/display: Add intel_legacy_aux_to_power_domain() José Roberto de Souza
                   ` (11 more replies)
  0 siblings, 12 replies; 25+ messages in thread
From: José Roberto de Souza @ 2020-04-07  1:11 UTC (permalink / raw)
  To: intel-gfx; +Cc: You-Sheng Yang

Moving the code to return the digital port of the aux channel also
removing the intel_phy_is_tc() to make it generic.
digital_port will be needed in icl_tc_phy_aux_power_well_enable()
so adding it as a parameter to icl_tc_port_assert_ref_held().

While at at removing the duplicated call to icl_tc_phy_aux_ch() in
icl_tc_port_assert_ref_held().

v2:
- fixed build when DRM_I915_DEBUG_RUNTIME_PM is not set
- moved to before hsw_wait_for_power_well_enable() as it will be
needed by hsw_wait_for_power_well_enable() in a future patch

Cc: You-Sheng Yang <vicamo@gmail.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 .../drm/i915/display/intel_display_power.c    | 69 ++++++++++---------
 1 file changed, 37 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 433e5a81dd4d..f2f42b5960df 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -282,6 +282,33 @@ static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
 		gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
 }
 
+static struct intel_digital_port *
+aux_ch_to_digital_port(struct drm_i915_private *dev_priv,
+		       enum aux_ch aux_ch)
+{
+	struct intel_digital_port *dig_port = NULL;
+	struct intel_encoder *encoder;
+
+	for_each_intel_encoder(&dev_priv->drm, encoder) {
+		/* We'll check the MST primary port */
+		if (encoder->type == INTEL_OUTPUT_DP_MST)
+			continue;
+
+		dig_port = enc_to_dig_port(encoder);
+		if (drm_WARN_ON(&dev_priv->drm, !dig_port))
+			continue;
+
+		if (dig_port->aux_ch != aux_ch) {
+			dig_port = NULL;
+			continue;
+		}
+
+		break;
+	}
+
+	return dig_port;
+}
+
 static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
 					   struct i915_power_well *power_well)
 {
@@ -501,41 +528,14 @@ static int power_well_async_ref_count(struct drm_i915_private *dev_priv,
 }
 
 static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
-					struct i915_power_well *power_well)
+					struct i915_power_well *power_well,
+					struct intel_digital_port *dig_port)
 {
-	enum aux_ch aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
-	struct intel_digital_port *dig_port = NULL;
-	struct intel_encoder *encoder;
-
 	/* Bypass the check if all references are released asynchronously */
 	if (power_well_async_ref_count(dev_priv, power_well) ==
 	    power_well->count)
 		return;
 
-	aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
-
-	for_each_intel_encoder(&dev_priv->drm, encoder) {
-		enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
-
-		if (!intel_phy_is_tc(dev_priv, phy))
-			continue;
-
-		/* We'll check the MST primary port */
-		if (encoder->type == INTEL_OUTPUT_DP_MST)
-			continue;
-
-		dig_port = enc_to_dig_port(encoder);
-		if (drm_WARN_ON(&dev_priv->drm, !dig_port))
-			continue;
-
-		if (dig_port->aux_ch != aux_ch) {
-			dig_port = NULL;
-			continue;
-		}
-
-		break;
-	}
-
 	if (drm_WARN_ON(&dev_priv->drm, !dig_port))
 		return;
 
@@ -545,7 +545,8 @@ static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
 #else
 
 static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
-					struct i915_power_well *power_well)
+					struct i915_power_well *power_well,
+					struct intel_digital_port *dig_port)
 {
 }
 
@@ -558,9 +559,10 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
 				 struct i915_power_well *power_well)
 {
 	enum aux_ch aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
+	struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv, aux_ch);
 	u32 val;
 
-	icl_tc_port_assert_ref_held(dev_priv, power_well);
+	icl_tc_port_assert_ref_held(dev_priv, power_well, dig_port);
 
 	val = intel_de_read(dev_priv, DP_AUX_CH_CTL(aux_ch));
 	val &= ~DP_AUX_CH_CTL_TBT_IO;
@@ -588,7 +590,10 @@ static void
 icl_tc_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
 				  struct i915_power_well *power_well)
 {
-	icl_tc_port_assert_ref_held(dev_priv, power_well);
+	enum aux_ch aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
+	struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv, aux_ch);
+
+	icl_tc_port_assert_ref_held(dev_priv, power_well, dig_port);
 
 	hsw_power_well_disable(dev_priv, power_well);
 }
-- 
2.26.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [Intel-gfx] [PATCH v2 2/8] drm/i915/display: Add intel_legacy_aux_to_power_domain()
  2020-04-07  1:11 [Intel-gfx] [PATCH v2 1/8] drm/i915/display: Move out code to return the digital_port of the aux ch José Roberto de Souza
@ 2020-04-07  1:11 ` José Roberto de Souza
  2020-04-07 15:15   ` Imre Deak
  2020-04-07  1:11 ` [Intel-gfx] [PATCH v2 3/8] drm/i915/display: Split hsw_power_well_enable() into two José Roberto de Souza
                   ` (10 subsequent siblings)
  11 siblings, 1 reply; 25+ messages in thread
From: José Roberto de Souza @ 2020-04-07  1:11 UTC (permalink / raw)
  To: intel-gfx; +Cc: Cooper Chiou, Kai-Heng Feng

This is a similar function to intel_aux_power_domain() but it do not
care about TBT ports, this will be needed by ICL TC sequences.

v2:
- renamed to intel_legacy_aux_to_power_domain()

Cc: Imre Deak <imre.deak@intel.com>
Cc: Cooper Chiou <cooper.chiou@intel.com>
Cc: Kai-Heng Feng <kai.heng.feng@canonical.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 14 ++++++++++++--
 drivers/gpu/drm/i915/display/intel_display.h |  2 ++
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 70ec301fe6e3..a95960b71001 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7291,7 +7291,17 @@ intel_aux_power_domain(struct intel_digital_port *dig_port)
 		}
 	}
 
-	switch (dig_port->aux_ch) {
+	return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
+}
+
+/*
+ * Converts aux_ch to power_domain without caring about TBT ports for that use
+ * intel_aux_power_domain()
+ */
+enum intel_display_power_domain
+intel_legacy_aux_to_power_domain(enum aux_ch aux_ch)
+{
+	switch (aux_ch) {
 	case AUX_CH_A:
 		return POWER_DOMAIN_AUX_A;
 	case AUX_CH_B:
@@ -7307,7 +7317,7 @@ intel_aux_power_domain(struct intel_digital_port *dig_port)
 	case AUX_CH_G:
 		return POWER_DOMAIN_AUX_G;
 	default:
-		MISSING_CASE(dig_port->aux_ch);
+		MISSING_CASE(aux_ch);
 		return POWER_DOMAIN_AUX_A;
 	}
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index cc7f287804d7..8d872ed0de36 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -583,6 +583,8 @@ void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
 enum intel_display_power_domain
 intel_aux_power_domain(struct intel_digital_port *dig_port);
+enum intel_display_power_domain
+intel_legacy_aux_to_power_domain(enum aux_ch aux_ch);
 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
 				 struct intel_crtc_state *pipe_config);
 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
-- 
2.26.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [Intel-gfx] [PATCH v2 3/8] drm/i915/display: Split hsw_power_well_enable() into two
  2020-04-07  1:11 [Intel-gfx] [PATCH v2 1/8] drm/i915/display: Move out code to return the digital_port of the aux ch José Roberto de Souza
  2020-04-07  1:11 ` [Intel-gfx] [PATCH v2 2/8] drm/i915/display: Add intel_legacy_aux_to_power_domain() José Roberto de Souza
@ 2020-04-07  1:11 ` José Roberto de Souza
  2020-04-07 15:20   ` Imre Deak
  2020-04-07  1:11 ` [Intel-gfx] [PATCH v2 4/8] drm/i915/tc/icl: Implement TC cold sequences José Roberto de Souza
                   ` (9 subsequent siblings)
  11 siblings, 1 reply; 25+ messages in thread
From: José Roberto de Souza @ 2020-04-07  1:11 UTC (permalink / raw)
  To: intel-gfx

This is a preparation for ICL TC cold exit sequences.

v2:
- renamed new functions to hsw_power_well_enable_prepare()/complete()

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 .../drm/i915/display/intel_display_power.c    | 39 +++++++++++++++----
 1 file changed, 32 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index f2f42b5960df..62e49f06d467 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -380,16 +380,16 @@ static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv,
 					  SKL_FUSE_PG_DIST_STATUS(pg), 1));
 }
 
-static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
-				  struct i915_power_well *power_well)
+static void hsw_power_well_enable_prepare(struct drm_i915_private *dev_priv,
+					  struct i915_power_well *power_well)
 {
 	const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
 	int pw_idx = power_well->desc->hsw.idx;
-	bool wait_fuses = power_well->desc->hsw.has_fuses;
-	enum skl_power_gate uninitialized_var(pg);
 	u32 val;
 
-	if (wait_fuses) {
+	if (power_well->desc->hsw.has_fuses) {
+		enum skl_power_gate pg;
+
 		pg = INTEL_GEN(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
 						 SKL_PW_CTL_IDX_TO_PG(pw_idx);
 		/*
@@ -406,25 +406,46 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
 	val = intel_de_read(dev_priv, regs->driver);
 	intel_de_write(dev_priv, regs->driver,
 		       val | HSW_PWR_WELL_CTL_REQ(pw_idx));
+}
+
+static void hsw_power_well_enable_complete(struct drm_i915_private *dev_priv,
+					   struct i915_power_well *power_well)
+{
+	int pw_idx = power_well->desc->hsw.idx;
+
 	hsw_wait_for_power_well_enable(dev_priv, power_well);
 
 	/* Display WA #1178: cnl */
 	if (IS_CANNONLAKE(dev_priv) &&
 	    pw_idx >= GLK_PW_CTL_IDX_AUX_B &&
 	    pw_idx <= CNL_PW_CTL_IDX_AUX_F) {
+		u32 val;
+
 		val = intel_de_read(dev_priv, CNL_AUX_ANAOVRD1(pw_idx));
 		val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS;
 		intel_de_write(dev_priv, CNL_AUX_ANAOVRD1(pw_idx), val);
 	}
 
-	if (wait_fuses)
+	if (power_well->desc->hsw.has_fuses) {
+		enum skl_power_gate pg;
+
+		pg = INTEL_GEN(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
+						 SKL_PW_CTL_IDX_TO_PG(pw_idx);
 		gen9_wait_for_power_well_fuses(dev_priv, pg);
+	}
 
 	hsw_power_well_post_enable(dev_priv,
 				   power_well->desc->hsw.irq_pipe_mask,
 				   power_well->desc->hsw.has_vga);
 }
 
+static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
+				  struct i915_power_well *power_well)
+{
+	hsw_power_well_enable_prepare(dev_priv, power_well);
+	hsw_power_well_enable_complete(dev_priv, power_well);
+}
+
 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
 				   struct i915_power_well *power_well)
 {
@@ -570,7 +591,11 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
 		val |= DP_AUX_CH_CTL_TBT_IO;
 	intel_de_write(dev_priv, DP_AUX_CH_CTL(aux_ch), val);
 
-	hsw_power_well_enable(dev_priv, power_well);
+	hsw_power_well_enable_prepare(dev_priv, power_well);
+
+	/* TODO ICL TC cold handling */
+
+	hsw_power_well_enable_complete(dev_priv, power_well);
 
 	if (INTEL_GEN(dev_priv) >= 12 && !power_well->desc->hsw.is_tc_tbt) {
 		enum tc_port tc_port;
-- 
2.26.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [Intel-gfx] [PATCH v2 4/8] drm/i915/tc/icl: Implement TC cold sequences
  2020-04-07  1:11 [Intel-gfx] [PATCH v2 1/8] drm/i915/display: Move out code to return the digital_port of the aux ch José Roberto de Souza
  2020-04-07  1:11 ` [Intel-gfx] [PATCH v2 2/8] drm/i915/display: Add intel_legacy_aux_to_power_domain() José Roberto de Souza
  2020-04-07  1:11 ` [Intel-gfx] [PATCH v2 3/8] drm/i915/display: Split hsw_power_well_enable() into two José Roberto de Souza
@ 2020-04-07  1:11 ` José Roberto de Souza
  2020-04-07 15:42   ` Imre Deak
  2020-04-07  1:11 ` [Intel-gfx] [PATCH v2 5/8] drm/i915/tc: Skip ref held check for TC legacy aux power wells José Roberto de Souza
                   ` (8 subsequent siblings)
  11 siblings, 1 reply; 25+ messages in thread
From: José Roberto de Souza @ 2020-04-07  1:11 UTC (permalink / raw)
  To: intel-gfx; +Cc: Cooper Chiou, Kai-Heng Feng

This is required for legacy/static TC ports as IOM is not aware of
the connection and will not trigger the TC cold exit.

Just request PCODE to exit TCCOLD is not enough as it could enter
again before driver makes use of the port, to prevent it BSpec states
that aux powerwell should be held.

So here embedding the TC cold exit sequence into ICL aux enable,
it will enable aux and then request TC cold to exit.

The TC cold block(exit and aux hold) and unblock was added to some
exported TC functions for the others and to access PHY registers,
callers should enable and keep aux powerwell enabled during access.

Also adding TC cold check and warnig in tc_port_load_fia_params() as
at this point of the driver initialization we can't request power
wells, if we get this warning we will need to figure out how to handle
it.

v2:
- moved ICL TC cold exit function to intel_display_power
- using dig_port->tc_legacy_port to only execute sequences for legacy
ports, hopefully VBTs will have this right
- fixed check to call _hsw_power_well_continue_enable()
- calling _hsw_power_well_continue_enable() unconditionally in
icl_tc_phy_aux_power_well_enable(), if needed we will surpress timeout
warnings of TC legacy ports
- only blocking TC cold around fia access

BSpec: 21750
Fixes: https://gitlab.freedesktop.org/drm/intel/issues/1296
Cc: Imre Deak <imre.deak@intel.com>
Cc: Cooper Chiou <cooper.chiou@intel.com>
Cc: Kai-Heng Feng <kai.heng.feng@canonical.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>

squash icl
---
 .../drm/i915/display/intel_display_power.c    | 22 ++++++-
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_tc.c       | 64 +++++++++++++++++--
 drivers/gpu/drm/i915/i915_reg.h               |  1 +
 4 files changed, 80 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 62e49f06d467..1336247743c4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -575,6 +575,25 @@ static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
 
 #define TGL_AUX_PW_TO_TC_PORT(pw_idx)	((pw_idx) - TGL_PW_CTL_IDX_AUX_TC1)
 
+static void icl_tc_cold_exit(struct drm_i915_private *i915)
+{
+	int ret;
+
+	do {
+		ret = sandybridge_pcode_write_timeout(i915,
+						      ICL_PCODE_EXIT_TCCOLD,
+						      0, 250, 1);
+
+	} while (ret == -EAGAIN);
+
+	/* Spec states that TC cold exit can take up to 1ms to complete */
+	if (!ret)
+		msleep(1);
+
+	drm_dbg_kms(&i915->drm, "TC cold block %s\n", ret == 0 ? "succeeded" :
+		    "failed");
+}
+
 static void
 icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
 				 struct i915_power_well *power_well)
@@ -593,7 +612,8 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
 
 	hsw_power_well_enable_prepare(dev_priv, power_well);
 
-	/* TODO ICL TC cold handling */
+	if (INTEL_GEN(dev_priv) == 11 && dig_port->tc_legacy_port)
+		icl_tc_cold_exit(dev_priv);
 
 	hsw_power_well_enable_complete(dev_priv, power_well);
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 5a0adf14ebef..f7506ac40eb4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1400,6 +1400,7 @@ struct intel_digital_port {
 	enum intel_display_power_domain ddi_io_power_domain;
 	struct mutex tc_lock;	/* protects the TypeC port mode */
 	intel_wakeref_t tc_lock_wakeref;
+	intel_wakeref_t tc_cold_wakeref;
 	int tc_link_refcount;
 	bool tc_legacy_port:1;
 	char tc_port_name[8];
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 9b850c11aa78..7564259d677e 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -34,6 +34,7 @@ tc_port_load_fia_params(struct drm_i915_private *i915,
 	if (INTEL_INFO(i915)->display.has_modular_fia) {
 		modular_fia = intel_uncore_read(&i915->uncore,
 						PORT_TX_DFLEXDPSP(FIA1));
+		drm_WARN_ON(&i915->drm, modular_fia == 0xffffffff);
 		modular_fia &= MODULAR_FIA_MASK;
 	} else {
 		modular_fia = 0;
@@ -52,6 +53,37 @@ tc_port_load_fia_params(struct drm_i915_private *i915,
 	}
 }
 
+static intel_wakeref_t
+tc_cold_block(struct intel_digital_port *dig_port)
+{
+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+	enum intel_display_power_domain domain;
+
+	if (INTEL_GEN(i915) != 11 || !dig_port->tc_legacy_port)
+		return 0;
+
+	domain = intel_legacy_aux_to_power_domain(dig_port->aux_ch);
+	return intel_display_power_get(i915, domain);
+}
+
+static void
+tc_cold_unblock(struct intel_digital_port *dig_port, intel_wakeref_t wakeref)
+{
+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+	enum intel_display_power_domain domain;
+
+	/*
+	 * wakeref == -1, means some error happened saving save_depot_stack but
+	 * power should still be put down and 0 is a invalid save_depot_stack
+	 * id so can be used to skip it for non TC legacy ports.
+	 */
+	if (wakeref == 0)
+		return;
+
+	domain = intel_legacy_aux_to_power_domain(dig_port->aux_ch);
+	intel_display_power_put_async(i915, domain, wakeref);
+}
+
 u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
 {
 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
@@ -415,9 +447,14 @@ static void intel_tc_port_reset_mode(struct intel_digital_port *dig_port,
 	enum tc_port_mode old_tc_mode = dig_port->tc_mode;
 
 	intel_display_power_flush_work(i915);
-	drm_WARN_ON(&i915->drm,
-		    intel_display_power_is_enabled(i915,
-					intel_aux_power_domain(dig_port)));
+	if (INTEL_GEN(i915) != 11 || !dig_port->tc_legacy_port) {
+		enum intel_display_power_domain aux_domain;
+		bool aux_powered;
+
+		aux_domain = intel_aux_power_domain(dig_port);
+		aux_powered = intel_display_power_is_enabled(i915, aux_domain);
+		drm_WARN_ON(&i915->drm, aux_powered);
+	}
 
 	icl_tc_phy_disconnect(dig_port);
 	icl_tc_phy_connect(dig_port, required_lanes);
@@ -439,9 +476,11 @@ intel_tc_port_link_init_refcount(struct intel_digital_port *dig_port,
 void intel_tc_port_sanitize(struct intel_digital_port *dig_port)
 {
 	struct intel_encoder *encoder = &dig_port->base;
+	intel_wakeref_t tc_cold_wref;
 	int active_links = 0;
 
 	mutex_lock(&dig_port->tc_lock);
+	tc_cold_wref = tc_cold_block(dig_port);
 
 	dig_port->tc_mode = intel_tc_port_get_current_mode(dig_port);
 	if (dig_port->dp.is_mst)
@@ -466,6 +505,7 @@ void intel_tc_port_sanitize(struct intel_digital_port *dig_port)
 		      dig_port->tc_port_name,
 		      tc_port_mode_name(dig_port->tc_mode));
 
+	tc_cold_unblock(dig_port, tc_cold_wref);
 	mutex_unlock(&dig_port->tc_lock);
 }
 
@@ -487,10 +527,15 @@ static bool intel_tc_port_needs_reset(struct intel_digital_port *dig_port)
 bool intel_tc_port_connected(struct intel_digital_port *dig_port)
 {
 	bool is_connected;
+	intel_wakeref_t tc_cold_wref;
 
 	intel_tc_port_lock(dig_port);
+	tc_cold_wref = tc_cold_block(dig_port);
+
 	is_connected = tc_port_live_status_mask(dig_port) &
 		       BIT(dig_port->tc_mode);
+
+	tc_cold_unblock(dig_port, tc_cold_wref);
 	intel_tc_port_unlock(dig_port);
 
 	return is_connected;
@@ -500,15 +545,20 @@ static void __intel_tc_port_lock(struct intel_digital_port *dig_port,
 				 int required_lanes)
 {
 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
-	intel_wakeref_t wakeref;
+	intel_wakeref_t wakeref, tc_cold_wref;
 
 	wakeref = intel_display_power_get(i915, POWER_DOMAIN_DISPLAY_CORE);
 
 	mutex_lock(&dig_port->tc_lock);
 
-	if (!dig_port->tc_link_refcount &&
-	    intel_tc_port_needs_reset(dig_port))
-		intel_tc_port_reset_mode(dig_port, required_lanes);
+	if (!dig_port->tc_link_refcount) {
+		tc_cold_wref = tc_cold_block(dig_port);
+
+		if (intel_tc_port_needs_reset(dig_port))
+			intel_tc_port_reset_mode(dig_port, required_lanes);
+
+		tc_cold_unblock(dig_port, tc_cold_wref);
+	}
 
 	drm_WARN_ON(&i915->drm, dig_port->tc_lock_wakeref);
 	dig_port->tc_lock_wakeref = wakeref;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8cebb7a86b8c..5cbcd01ac3d5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9107,6 +9107,7 @@ enum {
 #define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)	(((point) << 16) | (0x1 << 8))
 #define   GEN6_PCODE_READ_D_COMP		0x10
 #define   GEN6_PCODE_WRITE_D_COMP		0x11
+#define   ICL_PCODE_EXIT_TCCOLD			0x12
 #define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
 #define   DISPLAY_IPS_CONTROL			0x19
             /* See also IPS_CTL */
-- 
2.26.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [Intel-gfx] [PATCH v2 5/8] drm/i915/tc: Skip ref held check for TC legacy aux power wells
  2020-04-07  1:11 [Intel-gfx] [PATCH v2 1/8] drm/i915/display: Move out code to return the digital_port of the aux ch José Roberto de Souza
                   ` (2 preceding siblings ...)
  2020-04-07  1:11 ` [Intel-gfx] [PATCH v2 4/8] drm/i915/tc/icl: Implement TC cold sequences José Roberto de Souza
@ 2020-04-07  1:11 ` José Roberto de Souza
  2020-04-07 15:42   ` Imre Deak
  2020-04-07  1:11 ` [Intel-gfx] [PATCH v2 6/8] drm/i915/tc/tgl: Implement TC cold sequences José Roberto de Souza
                   ` (7 subsequent siblings)
  11 siblings, 1 reply; 25+ messages in thread
From: José Roberto de Souza @ 2020-04-07  1:11 UTC (permalink / raw)
  To: intel-gfx

As part of ICL TC cold exit sequences we need to request aux power
well before lock the access to TC ports, so skiping the
intel_tc_port_ref_held() check for TC legacy ports.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 1336247743c4..0383801a9acc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -560,6 +560,9 @@ static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
 	if (drm_WARN_ON(&dev_priv->drm, !dig_port))
 		return;
 
+	if (INTEL_GEN(dev_priv) == 11 && dig_port->tc_legacy_port)
+		return;
+
 	drm_WARN_ON(&dev_priv->drm, !intel_tc_port_ref_held(dig_port));
 }
 
-- 
2.26.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [Intel-gfx] [PATCH v2 6/8] drm/i915/tc/tgl: Implement TC cold sequences
  2020-04-07  1:11 [Intel-gfx] [PATCH v2 1/8] drm/i915/display: Move out code to return the digital_port of the aux ch José Roberto de Souza
                   ` (3 preceding siblings ...)
  2020-04-07  1:11 ` [Intel-gfx] [PATCH v2 5/8] drm/i915/tc: Skip ref held check for TC legacy aux power wells José Roberto de Souza
@ 2020-04-07  1:11 ` José Roberto de Souza
  2020-04-07 16:02   ` Imre Deak
  2020-04-07  1:11 ` [Intel-gfx] [PATCH v2 7/8] drm/i915/tc: Catch TC users accessing FIA registers without enable aux José Roberto de Souza
                   ` (6 subsequent siblings)
  11 siblings, 1 reply; 25+ messages in thread
From: José Roberto de Souza @ 2020-04-07  1:11 UTC (permalink / raw)
  To: intel-gfx; +Cc: Cooper Chiou, Kai-Heng Feng

TC ports can enter in TCCOLD to save power and is required to request
to PCODE to exit this state before use or read to TC registers.

For TGL there is a new MBOX command to do that with a parameter to ask
PCODE to exit and block TCCOLD entry or unblock TCCOLD entry.

So adding a new power domain to reuse the refcount and only allow
TC cold when all TC ports are not in use.

v2:
- fixed missing case in intel_display_power_domain_str()
- moved tgl_tc_cold_request to intel_display_power.c
- renamed TGL_TC_COLD_OFF to TGL_TC_COLD_OFF_POWER_DOMAINS
- added all TC and TBT aux power domains to
TGL_TC_COLD_OFF_POWER_DOMAINS

BSpec: 49294
Cc: Imre Deak <imre.deak@intel.com>
Cc: Cooper Chiou <cooper.chiou@intel.com>
Cc: Kai-Heng Feng <kai.heng.feng@canonical.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 .../drm/i915/display/intel_display_power.c    | 98 +++++++++++++++++++
 .../drm/i915/display/intel_display_power.h    |  1 +
 drivers/gpu/drm/i915/display/intel_tc.c       | 17 +++-
 drivers/gpu/drm/i915/i915_reg.h               |  3 +
 4 files changed, 116 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 0383801a9acc..5d33929f3724 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -151,6 +151,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
 		return "GT_IRQ";
 	case POWER_DOMAIN_DPLL_DC_OFF:
 		return "DPLL_DC_OFF";
+	case POWER_DOMAIN_TC_COLD_OFF:
+		return "TC_COLD_OFF";
 	default:
 		MISSING_CASE(domain);
 		return "?";
@@ -2858,6 +2860,21 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 #define TGL_AUX_I_TBT6_IO_POWER_DOMAINS (	\
 	BIT_ULL(POWER_DOMAIN_AUX_I_TBT))
 
+#define TGL_TC_COLD_OFF_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_AUX_D)	|	\
+	BIT_ULL(POWER_DOMAIN_AUX_E)	|	\
+	BIT_ULL(POWER_DOMAIN_AUX_F)	|	\
+	BIT_ULL(POWER_DOMAIN_AUX_G)	|	\
+	BIT_ULL(POWER_DOMAIN_AUX_H)	|	\
+	BIT_ULL(POWER_DOMAIN_AUX_I)	|	\
+	BIT_ULL(POWER_DOMAIN_AUX_D_TBT)	|	\
+	BIT_ULL(POWER_DOMAIN_AUX_E_TBT)	|	\
+	BIT_ULL(POWER_DOMAIN_AUX_F_TBT)	|	\
+	BIT_ULL(POWER_DOMAIN_AUX_G_TBT)	|	\
+	BIT_ULL(POWER_DOMAIN_AUX_H_TBT)	|	\
+	BIT_ULL(POWER_DOMAIN_AUX_I_TBT)	|	\
+	BIT_ULL(POWER_DOMAIN_TC_COLD_OFF))
+
 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
 	.sync_hw = i9xx_power_well_sync_hw_noop,
 	.enable = i9xx_always_on_power_well_noop,
@@ -3960,6 +3977,81 @@ static const struct i915_power_well_desc ehl_power_wells[] = {
 	},
 };
 
+static void
+tgl_tc_cold_request(struct drm_i915_private *i915, bool block)
+{
+	u32 low_val, high_val;
+	u8 tries = 0;
+	int ret;
+
+	do {
+		low_val = 0;
+		high_val = block ? 0 : TGL_PCODE_EXIT_TCCOLD_DATA_H_UNBLOCK_REQ;
+
+		/*
+		 * Spec states that we should timeout the request after 200us
+		 * but the function below will timeout after 500us
+		 */
+		ret = sandybridge_pcode_read(i915, TGL_PCODE_TCCOLD, &low_val,
+					     &high_val);
+		if (ret == 0) {
+			if (block &&
+			    (low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED))
+				ret = -EIO;
+			else
+				break;
+		}
+
+		if (ret != -EAGAIN)
+			tries++;
+	} while (tries < 3);
+
+	drm_dbg_kms(&i915->drm, "TC cold %sblock %s\n", block ? "" : "un",
+		    ret == 0 ? "succeeded" : "failed");
+}
+
+static void
+tgl_tc_cold_off_power_well_enable(struct drm_i915_private *i915,
+				  struct i915_power_well *power_well)
+{
+	tgl_tc_cold_request(i915, true);
+}
+
+static void
+tgl_tc_cold_off_power_well_disable(struct drm_i915_private *i915,
+				   struct i915_power_well *power_well)
+{
+	tgl_tc_cold_request(i915, false);
+}
+
+static void
+tgl_tc_cold_off_power_well_sync_hw(struct drm_i915_private *i915,
+				   struct i915_power_well *power_well)
+{
+	if (power_well->count > 0)
+		tgl_tc_cold_off_power_well_enable(i915, power_well);
+	else
+		tgl_tc_cold_off_power_well_disable(i915, power_well);
+}
+
+static bool
+tgl_tc_cold_off_power_well_is_enabled(struct drm_i915_private *dev_priv,
+				      struct i915_power_well *power_well)
+{
+	/*
+	 * Not the correctly implementation but there is no way to just read it
+	 * from PCODE, so returning count to avoid state mismatch errors
+	 */
+	return power_well->count;
+}
+
+static const struct i915_power_well_ops tgl_tc_cold_off_ops = {
+	.sync_hw = tgl_tc_cold_off_power_well_sync_hw,
+	.enable = tgl_tc_cold_off_power_well_enable,
+	.disable = tgl_tc_cold_off_power_well_disable,
+	.is_enabled = tgl_tc_cold_off_power_well_is_enabled,
+};
+
 static const struct i915_power_well_desc tgl_power_wells[] = {
 	{
 		.name = "always-on",
@@ -4287,6 +4379,12 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
 			.hsw.irq_pipe_mask = BIT(PIPE_D),
 		},
 	},
+	{
+		.name = "TC cold off",
+		.domains = TGL_TC_COLD_OFF_POWER_DOMAINS,
+		.ops = &tgl_tc_cold_off_ops,
+		.id = DISP_PW_ID_NONE,
+	},
 };
 
 static int
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index da64a5edae7a..070457e7b948 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -76,6 +76,7 @@ enum intel_display_power_domain {
 	POWER_DOMAIN_MODESET,
 	POWER_DOMAIN_GT_IRQ,
 	POWER_DOMAIN_DPLL_DC_OFF,
+	POWER_DOMAIN_TC_COLD_OFF,
 	POWER_DOMAIN_INIT,
 
 	POWER_DOMAIN_NUM,
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 7564259d677e..83861653768d 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -53,16 +53,27 @@ tc_port_load_fia_params(struct drm_i915_private *i915,
 	}
 }
 
+static enum intel_display_power_domain
+tc_cold_get_power_domain(struct intel_digital_port *dig_port)
+{
+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+
+	if (INTEL_GEN(i915) == 11)
+		return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
+	else
+		return POWER_DOMAIN_TC_COLD_OFF;
+}
+
 static intel_wakeref_t
 tc_cold_block(struct intel_digital_port *dig_port)
 {
 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 	enum intel_display_power_domain domain;
 
-	if (INTEL_GEN(i915) != 11 || !dig_port->tc_legacy_port)
+	if (INTEL_GEN(i915) == 11 && !dig_port->tc_legacy_port)
 		return 0;
 
-	domain = intel_legacy_aux_to_power_domain(dig_port->aux_ch);
+	domain = tc_cold_get_power_domain(dig_port);
 	return intel_display_power_get(i915, domain);
 }
 
@@ -80,7 +91,7 @@ tc_cold_unblock(struct intel_digital_port *dig_port, intel_wakeref_t wakeref)
 	if (wakeref == 0)
 		return;
 
-	domain = intel_legacy_aux_to_power_domain(dig_port->aux_ch);
+	domain = tc_cold_get_power_domain(dig_port);
 	intel_display_power_put_async(i915, domain, wakeref);
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5cbcd01ac3d5..e04eec003d4b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9110,6 +9110,9 @@ enum {
 #define   ICL_PCODE_EXIT_TCCOLD			0x12
 #define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
 #define   DISPLAY_IPS_CONTROL			0x19
+#define   TGL_PCODE_TCCOLD			0x26
+#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED   REG_BIT(0)
+#define     TGL_PCODE_EXIT_TCCOLD_DATA_H_UNBLOCK_REQ   REG_BIT(0)
             /* See also IPS_CTL */
 #define     IPS_PCODE_CONTROL			(1 << 30)
 #define   HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
-- 
2.26.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [Intel-gfx] [PATCH v2 7/8] drm/i915/tc: Catch TC users accessing FIA registers without enable aux
  2020-04-07  1:11 [Intel-gfx] [PATCH v2 1/8] drm/i915/display: Move out code to return the digital_port of the aux ch José Roberto de Souza
                   ` (4 preceding siblings ...)
  2020-04-07  1:11 ` [Intel-gfx] [PATCH v2 6/8] drm/i915/tc/tgl: Implement TC cold sequences José Roberto de Souza
@ 2020-04-07  1:11 ` José Roberto de Souza
  2020-04-07 16:04   ` Imre Deak
  2020-04-07  1:11 ` [Intel-gfx] [PATCH v2 8/8] drm/i915/tc: Do not warn when aux power well of static TC ports timeout José Roberto de Souza
                   ` (5 subsequent siblings)
  11 siblings, 1 reply; 25+ messages in thread
From: José Roberto de Souza @ 2020-04-07  1:11 UTC (permalink / raw)
  To: intel-gfx

As described in "drm/i915/tc/icl: Implement TC cold sequences" users
of TC functions should held aux power well during access to avoid
read garbage due HW in TC cold state.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_tc.c | 22 ++++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 83861653768d..e473bb4a9b0b 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -95,6 +95,20 @@ tc_cold_unblock(struct intel_digital_port *dig_port, intel_wakeref_t wakeref)
 	intel_display_power_put_async(i915, domain, wakeref);
 }
 
+static void
+is_tc_cold_blocked(struct intel_digital_port *dig_port)
+{
+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+	bool enabled;
+
+	if (INTEL_GEN(i915) == 11 && !dig_port->tc_legacy_port)
+		return;
+
+	enabled = intel_display_power_is_enabled(i915,
+						 tc_cold_get_power_domain(dig_port));
+	drm_WARN_ON(&i915->drm, !enabled);
+}
+
 u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
 {
 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
@@ -104,7 +118,7 @@ u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
 	lane_mask = intel_uncore_read(uncore,
 				      PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
 
-	drm_WARN_ON(&i915->drm, lane_mask == 0xffffffff);
+	is_tc_cold_blocked(dig_port);
 
 	lane_mask &= DP_LANE_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx);
 	return lane_mask >> DP_LANE_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
@@ -119,7 +133,7 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
 	pin_mask = intel_uncore_read(uncore,
 				     PORT_TX_DFLEXPA1(dig_port->tc_phy_fia));
 
-	drm_WARN_ON(&i915->drm, pin_mask == 0xffffffff);
+	is_tc_cold_blocked(dig_port);
 
 	return (pin_mask & DP_PIN_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx)) >>
 	       DP_PIN_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
@@ -134,6 +148,8 @@ int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
 	if (dig_port->tc_mode != TC_PORT_DP_ALT)
 		return 4;
 
+	is_tc_cold_blocked(dig_port);
+
 	lane_mask = 0;
 	with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
 		lane_mask = intel_tc_port_get_lane_mask(dig_port);
@@ -166,6 +182,8 @@ void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
 	drm_WARN_ON(&i915->drm,
 		    lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY);
 
+	is_tc_cold_blocked(dig_port);
+
 	val = intel_uncore_read(uncore,
 				PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia));
 	val &= ~DFLEXDPMLE1_DPMLETC_MASK(dig_port->tc_phy_fia_idx);
-- 
2.26.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [Intel-gfx] [PATCH v2 8/8] drm/i915/tc: Do not warn when aux power well of static TC ports timeout
  2020-04-07  1:11 [Intel-gfx] [PATCH v2 1/8] drm/i915/display: Move out code to return the digital_port of the aux ch José Roberto de Souza
                   ` (5 preceding siblings ...)
  2020-04-07  1:11 ` [Intel-gfx] [PATCH v2 7/8] drm/i915/tc: Catch TC users accessing FIA registers without enable aux José Roberto de Souza
@ 2020-04-07  1:11 ` José Roberto de Souza
  2020-04-07 16:18   ` Imre Deak
  2020-04-07  1:26 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/8] drm/i915/display: Move out code to return the digital_port of the aux ch Patchwork
                   ` (4 subsequent siblings)
  11 siblings, 1 reply; 25+ messages in thread
From: José Roberto de Souza @ 2020-04-07  1:11 UTC (permalink / raw)
  To: intel-gfx

This is a expected timeout of static TC ports not conneceted, so
not throwing warnings that would taint CI.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 .../drm/i915/display/intel_display_power.c    | 37 +++++++++++--------
 1 file changed, 21 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 5d33929f3724..50af5854658e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -284,6 +284,21 @@ static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
 		gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
 }
 
+#define ICL_AUX_PW_TO_CH(pw_idx)	\
+	((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A)
+
+#define ICL_TBT_AUX_PW_TO_CH(pw_idx)	\
+	((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C)
+
+static enum aux_ch icl_tc_phy_aux_ch(struct drm_i915_private *dev_priv,
+				     struct i915_power_well *power_well)
+{
+	int pw_idx = power_well->desc->hsw.idx;
+
+	return power_well->desc->hsw.is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) :
+						 ICL_AUX_PW_TO_CH(pw_idx);
+}
+
 static struct intel_digital_port *
 aux_ch_to_digital_port(struct drm_i915_private *dev_priv,
 		       enum aux_ch aux_ch)
@@ -320,11 +335,16 @@ static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
 	/* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
 	if (intel_de_wait_for_set(dev_priv, regs->driver,
 				  HSW_PWR_WELL_CTL_STATE(pw_idx), 1)) {
+		enum aux_ch aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
+		struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv, aux_ch);
+
 		drm_dbg_kms(&dev_priv->drm, "%s power well enable timeout\n",
 			    power_well->desc->name);
 
 		/* An AUX timeout is expected if the TBT DP tunnel is down. */
-		drm_WARN_ON(&dev_priv->drm, !power_well->desc->hsw.is_tc_tbt);
+		drm_WARN_ON(&dev_priv->drm, !power_well->desc->hsw.is_tc_tbt &&
+			    !(INTEL_GEN(dev_priv) == 11 && dig_port->tc_legacy_port));
+
 	}
 }
 
@@ -520,21 +540,6 @@ icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
 	hsw_wait_for_power_well_disable(dev_priv, power_well);
 }
 
-#define ICL_AUX_PW_TO_CH(pw_idx)	\
-	((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A)
-
-#define ICL_TBT_AUX_PW_TO_CH(pw_idx)	\
-	((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C)
-
-static enum aux_ch icl_tc_phy_aux_ch(struct drm_i915_private *dev_priv,
-				     struct i915_power_well *power_well)
-{
-	int pw_idx = power_well->desc->hsw.idx;
-
-	return power_well->desc->hsw.is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) :
-						 ICL_AUX_PW_TO_CH(pw_idx);
-}
-
 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
 
 static u64 async_put_domains_mask(struct i915_power_domains *power_domains);
-- 
2.26.0

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/8] drm/i915/display: Move out code to return the digital_port of the aux ch
  2020-04-07  1:11 [Intel-gfx] [PATCH v2 1/8] drm/i915/display: Move out code to return the digital_port of the aux ch José Roberto de Souza
                   ` (6 preceding siblings ...)
  2020-04-07  1:11 ` [Intel-gfx] [PATCH v2 8/8] drm/i915/tc: Do not warn when aux power well of static TC ports timeout José Roberto de Souza
@ 2020-04-07  1:26 ` Patchwork
  2020-04-07  1:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
                   ` (3 subsequent siblings)
  11 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2020-04-07  1:26 UTC (permalink / raw)
  To: José Roberto de Souza; +Cc: intel-gfx

== Series Details ==

Series: series starting with [v2,1/8] drm/i915/display: Move out code to return the digital_port of the aux ch
URL   : https://patchwork.freedesktop.org/series/75576/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
14654d404b1a drm/i915/display: Move out code to return the digital_port of the aux ch
d3f4ac71f6b3 drm/i915/display: Add intel_legacy_aux_to_power_domain()
c35b853ace69 drm/i915/display: Split hsw_power_well_enable() into two
4492ad74909c drm/i915/tc/icl: Implement TC cold sequences
-:68: WARNING:MSLEEP: msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.rst
#68: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:591:
+		msleep(1);

total: 0 errors, 1 warnings, 0 checks, 166 lines checked
ec375378fe3a drm/i915/tc: Skip ref held check for TC legacy aux power wells
08d2500517e6 drm/i915/tc/tgl: Implement TC cold sequences
c6c9a63090ff drm/i915/tc: Catch TC users accessing FIA registers without enable aux
ba04f3ced696 drm/i915/tc: Do not warn when aux power well of static TC ports timeout

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/8] drm/i915/display: Move out code to return the digital_port of the aux ch
  2020-04-07  1:11 [Intel-gfx] [PATCH v2 1/8] drm/i915/display: Move out code to return the digital_port of the aux ch José Roberto de Souza
                   ` (7 preceding siblings ...)
  2020-04-07  1:26 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/8] drm/i915/display: Move out code to return the digital_port of the aux ch Patchwork
@ 2020-04-07  1:49 ` Patchwork
  2020-04-07  7:35 ` [Intel-gfx] [v2, 1/8] " You-Sheng Yang
                   ` (2 subsequent siblings)
  11 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2020-04-07  1:49 UTC (permalink / raw)
  To: José Roberto de Souza; +Cc: intel-gfx

== Series Details ==

Series: series starting with [v2,1/8] drm/i915/display: Move out code to return the digital_port of the aux ch
URL   : https://patchwork.freedesktop.org/series/75576/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8264 -> Patchwork_17226
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/index.html

Known issues
------------

  Here are the changes found in Patchwork_17226 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6770hq:      [PASS][1] -> [DMESG-WARN][2] ([i915#203]) +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-skl-6770hq:      [PASS][3] -> [DMESG-FAIL][4] ([i915#165])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/fi-skl-6770hq/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/fi-skl-6770hq/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@prime_vgem@basic-fence-flip:
    - fi-skl-6770hq:      [PASS][5] -> [SKIP][6] ([fdo#109271]) +2 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/fi-skl-6770hq/igt@prime_vgem@basic-fence-flip.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/fi-skl-6770hq/igt@prime_vgem@basic-fence-flip.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s4-devices:
    - fi-tgl-y:           [FAIL][7] ([i915#1158]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/fi-tgl-y/igt@gem_exec_suspend@basic-s4-devices.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/fi-tgl-y/igt@gem_exec_suspend@basic-s4-devices.html

  * igt@i915_selftest@live@hangcheck:
    - fi-icl-y:           [INCOMPLETE][9] ([i915#1580]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/fi-icl-y/igt@i915_selftest@live@hangcheck.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/fi-icl-y/igt@i915_selftest@live@hangcheck.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1158]: https://gitlab.freedesktop.org/drm/intel/issues/1158
  [i915#1580]: https://gitlab.freedesktop.org/drm/intel/issues/1580
  [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
  [i915#203]: https://gitlab.freedesktop.org/drm/intel/issues/203


Participating hosts (53 -> 46)
------------------------------

  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8264 -> Patchwork_17226

  CI-20190529: 20190529
  CI_DRM_8264: e0104585f880a64d4a9b40803cf4fb51ab499f7c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5573: 9c582425d6b4fc1de9fc2ffc8015cc6f0a0d3e98 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17226: ba04f3ced69643939779e78860b0d7054875c784 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

ba04f3ced696 drm/i915/tc: Do not warn when aux power well of static TC ports timeout
c6c9a63090ff drm/i915/tc: Catch TC users accessing FIA registers without enable aux
08d2500517e6 drm/i915/tc/tgl: Implement TC cold sequences
ec375378fe3a drm/i915/tc: Skip ref held check for TC legacy aux power wells
4492ad74909c drm/i915/tc/icl: Implement TC cold sequences
c35b853ace69 drm/i915/display: Split hsw_power_well_enable() into two
d3f4ac71f6b3 drm/i915/display: Add intel_legacy_aux_to_power_domain()
14654d404b1a drm/i915/display: Move out code to return the digital_port of the aux ch

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [Intel-gfx] [v2, 1/8] drm/i915/display: Move out code to return the digital_port of the aux ch
  2020-04-07  1:11 [Intel-gfx] [PATCH v2 1/8] drm/i915/display: Move out code to return the digital_port of the aux ch José Roberto de Souza
                   ` (8 preceding siblings ...)
  2020-04-07  1:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-04-07  7:35 ` You-Sheng Yang
  2020-04-07 10:28 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/8] " Patchwork
  2020-04-07 15:13 ` [Intel-gfx] [PATCH v2 1/8] " Imre Deak
  11 siblings, 0 replies; 25+ messages in thread
From: You-Sheng Yang @ 2020-04-07  7:35 UTC (permalink / raw)
  To: José Roberto de Souza, intel-gfx


[-- Attachment #1.1.1: Type: text/plain, Size: 4949 bytes --]

This series works for me. Thank you.

Tested-by: You-Sheng Yang <vicamo.yang@canonical.com>

On 2020-04-07 09:11, José Roberto de Souza wrote:
> Moving the code to return the digital port of the aux channel also
> removing the intel_phy_is_tc() to make it generic.
> digital_port will be needed in icl_tc_phy_aux_power_well_enable()
> so adding it as a parameter to icl_tc_port_assert_ref_held().
> 
> While at at removing the duplicated call to icl_tc_phy_aux_ch() in
> icl_tc_port_assert_ref_held().
> 
> v2:
> - fixed build when DRM_I915_DEBUG_RUNTIME_PM is not set
> - moved to before hsw_wait_for_power_well_enable() as it will be
> needed by hsw_wait_for_power_well_enable() in a future patch
> 
> Cc: You-Sheng Yang <vicamo@gmail.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  .../drm/i915/display/intel_display_power.c    | 69 ++++++++++---------
>  1 file changed, 37 insertions(+), 32 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 433e5a81dd4d..f2f42b5960df 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -282,6 +282,33 @@ static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
>  		gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
>  }
>  
> +static struct intel_digital_port *
> +aux_ch_to_digital_port(struct drm_i915_private *dev_priv,
> +		       enum aux_ch aux_ch)
> +{
> +	struct intel_digital_port *dig_port = NULL;
> +	struct intel_encoder *encoder;
> +
> +	for_each_intel_encoder(&dev_priv->drm, encoder) {
> +		/* We'll check the MST primary port */
> +		if (encoder->type == INTEL_OUTPUT_DP_MST)
> +			continue;
> +
> +		dig_port = enc_to_dig_port(encoder);
> +		if (drm_WARN_ON(&dev_priv->drm, !dig_port))
> +			continue;
> +
> +		if (dig_port->aux_ch != aux_ch) {
> +			dig_port = NULL;
> +			continue;
> +		}
> +
> +		break;
> +	}
> +
> +	return dig_port;
> +}
> +
>  static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
>  					   struct i915_power_well *power_well)
>  {
> @@ -501,41 +528,14 @@ static int power_well_async_ref_count(struct drm_i915_private *dev_priv,
>  }
>  
>  static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
> -					struct i915_power_well *power_well)
> +					struct i915_power_well *power_well,
> +					struct intel_digital_port *dig_port)
>  {
> -	enum aux_ch aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
> -	struct intel_digital_port *dig_port = NULL;
> -	struct intel_encoder *encoder;
> -
>  	/* Bypass the check if all references are released asynchronously */
>  	if (power_well_async_ref_count(dev_priv, power_well) ==
>  	    power_well->count)
>  		return;
>  
> -	aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
> -
> -	for_each_intel_encoder(&dev_priv->drm, encoder) {
> -		enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> -
> -		if (!intel_phy_is_tc(dev_priv, phy))
> -			continue;
> -
> -		/* We'll check the MST primary port */
> -		if (encoder->type == INTEL_OUTPUT_DP_MST)
> -			continue;
> -
> -		dig_port = enc_to_dig_port(encoder);
> -		if (drm_WARN_ON(&dev_priv->drm, !dig_port))
> -			continue;
> -
> -		if (dig_port->aux_ch != aux_ch) {
> -			dig_port = NULL;
> -			continue;
> -		}
> -
> -		break;
> -	}
> -
>  	if (drm_WARN_ON(&dev_priv->drm, !dig_port))
>  		return;
>  
> @@ -545,7 +545,8 @@ static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
>  #else
>  
>  static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
> -					struct i915_power_well *power_well)
> +					struct i915_power_well *power_well,
> +					struct intel_digital_port *dig_port)
>  {
>  }
>  
> @@ -558,9 +559,10 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
>  				 struct i915_power_well *power_well)
>  {
>  	enum aux_ch aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
> +	struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv, aux_ch);
>  	u32 val;
>  
> -	icl_tc_port_assert_ref_held(dev_priv, power_well);
> +	icl_tc_port_assert_ref_held(dev_priv, power_well, dig_port);
>  
>  	val = intel_de_read(dev_priv, DP_AUX_CH_CTL(aux_ch));
>  	val &= ~DP_AUX_CH_CTL_TBT_IO;
> @@ -588,7 +590,10 @@ static void
>  icl_tc_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
>  				  struct i915_power_well *power_well)
>  {
> -	icl_tc_port_assert_ref_held(dev_priv, power_well);
> +	enum aux_ch aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
> +	struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv, aux_ch);
> +
> +	icl_tc_port_assert_ref_held(dev_priv, power_well, dig_port);
>  
>  	hsw_power_well_disable(dev_priv, power_well);
>  }
> 


[-- Attachment #1.2: OpenPGP digital signature --]
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[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/8] drm/i915/display: Move out code to return the digital_port of the aux ch
  2020-04-07  1:11 [Intel-gfx] [PATCH v2 1/8] drm/i915/display: Move out code to return the digital_port of the aux ch José Roberto de Souza
                   ` (9 preceding siblings ...)
  2020-04-07  7:35 ` [Intel-gfx] [v2, 1/8] " You-Sheng Yang
@ 2020-04-07 10:28 ` Patchwork
  2020-04-07 21:56   ` Souza, Jose
  2020-04-07 15:13 ` [Intel-gfx] [PATCH v2 1/8] " Imre Deak
  11 siblings, 1 reply; 25+ messages in thread
From: Patchwork @ 2020-04-07 10:28 UTC (permalink / raw)
  To: José Roberto de Souza; +Cc: intel-gfx

== Series Details ==

Series: series starting with [v2,1/8] drm/i915/display: Move out code to return the digital_port of the aux ch
URL   : https://patchwork.freedesktop.org/series/75576/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_8264_full -> Patchwork_17226_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_17226_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_17226_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_17226_full:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-tglb:         [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-tglb5/igt@i915_module_load@reload-with-fault-injection.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-tglb3/igt@i915_module_load@reload-with-fault-injection.html

  
Known issues
------------

  Here are the changes found in Patchwork_17226_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-snb:          [PASS][3] -> [FAIL][4] ([i915#1066])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-snb1/igt@i915_pm_rc6_residency@rc6-idle.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-snb2/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@i915_suspend@sysfs-reader:
    - shard-apl:          [PASS][5] -> [DMESG-WARN][6] ([i915#180])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-apl1/igt@i915_suspend@sysfs-reader.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-apl4/igt@i915_suspend@sysfs-reader.html

  * igt@kms_cursor_crc@pipe-a-cursor-256x256-sliding:
    - shard-kbl:          [PASS][7] -> [FAIL][8] ([i915#54] / [i915#93] / [i915#95])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-256x256-sliding.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-256x256-sliding.html

  * igt@kms_cursor_crc@pipe-a-cursor-64x21-onscreen:
    - shard-apl:          [PASS][9] -> [FAIL][10] ([i915#54] / [i915#95])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-apl3/igt@kms_cursor_crc@pipe-a-cursor-64x21-onscreen.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-apl3/igt@kms_cursor_crc@pipe-a-cursor-64x21-onscreen.html

  * igt@kms_cursor_crc@pipe-b-cursor-256x85-random:
    - shard-skl:          [PASS][11] -> [FAIL][12] ([i915#54])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-skl4/igt@kms_cursor_crc@pipe-b-cursor-256x85-random.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-skl5/igt@kms_cursor_crc@pipe-b-cursor-256x85-random.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-kbl:          [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +3 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-kbl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
    - shard-glk:          [PASS][15] -> [FAIL][16] ([i915#72])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-glk2/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-glk1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank:
    - shard-kbl:          [PASS][17] -> [FAIL][18] ([i915#34])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-kbl6/igt@kms_flip@flip-vs-absolute-wf_vblank.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-kbl7/igt@kms_flip@flip-vs-absolute-wf_vblank.html

  * igt@kms_flip@flip-vs-panning-interruptible:
    - shard-hsw:          [PASS][19] -> [INCOMPLETE][20] ([i915#61])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-hsw8/igt@kms_flip@flip-vs-panning-interruptible.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-hsw1/igt@kms_flip@flip-vs-panning-interruptible.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
    - shard-iclb:         [PASS][21] -> [INCOMPLETE][22] ([i915#1185] / [i915#250])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-iclb4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-iclb3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][23] -> [FAIL][24] ([fdo#108145] / [i915#265]) +1 similar issue
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr@psr2_cursor_mmap_cpu:
    - shard-iclb:         [PASS][25] -> [SKIP][26] ([fdo#109441]) +1 similar issue
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-iclb8/igt@kms_psr@psr2_cursor_mmap_cpu.html

  
#### Possible fixes ####

  * {igt@gem_ctx_isolation@preservation-s3@rcs0}:
    - shard-apl:          [DMESG-WARN][27] ([i915#180]) -> [PASS][28] +4 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-apl6/igt@gem_ctx_isolation@preservation-s3@rcs0.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-apl1/igt@gem_ctx_isolation@preservation-s3@rcs0.html

  * igt@gem_exec_balancer@hang:
    - shard-tglb:         [FAIL][29] ([i915#1277]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-tglb6/igt@gem_exec_balancer@hang.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-tglb2/igt@gem_exec_balancer@hang.html

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-hsw:          [FAIL][31] ([i915#1516]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-hsw1/igt@i915_pm_rc6_residency@rc6-idle.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-hsw8/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - shard-skl:          [FAIL][33] ([i915#138]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-skl5/igt@i915_pm_rpm@basic-pci-d3-state.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-skl8/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@i915_selftest@live@blt:
    - shard-snb:          [DMESG-FAIL][35] ([i915#1409]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-snb4/igt@i915_selftest@live@blt.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-snb5/igt@i915_selftest@live@blt.html

  * igt@i915_suspend@debugfs-reader:
    - shard-kbl:          [DMESG-WARN][37] ([i915#180]) -> [PASS][38] +1 similar issue
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-kbl2/igt@i915_suspend@debugfs-reader.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-kbl6/igt@i915_suspend@debugfs-reader.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-skl:          [INCOMPLETE][39] ([i915#69]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-skl3/igt@i915_suspend@fence-restore-tiled2untiled.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-skl6/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-kbl:          [DMESG-WARN][41] ([i915#180] / [i915#93] / [i915#95]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-kbl2/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@2x-plain-flip-ts-check:
    - shard-glk:          [FAIL][43] ([i915#34]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-glk5/igt@kms_flip@2x-plain-flip-ts-check.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-glk9/igt@kms_flip@2x-plain-flip-ts-check.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-apl:          [FAIL][45] ([i915#79]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-apl4/igt@kms_flip@flip-vs-expired-vblank.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-apl6/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-snb:          [DMESG-WARN][47] ([i915#42]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-snb6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-snb6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_plane_lowres@pipe-a-tiling-none:
    - shard-kbl:          [DMESG-WARN][49] ([i915#165] / [i915#78]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-kbl2/igt@kms_plane_lowres@pipe-a-tiling-none.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-kbl6/igt@kms_plane_lowres@pipe-a-tiling-none.html

  * igt@kms_psr@psr2_cursor_plane_onoff:
    - shard-iclb:         [SKIP][51] ([fdo#109441]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-iclb1/igt@kms_psr@psr2_cursor_plane_onoff.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html

  * {igt@perf@blocking-parameterized}:
    - shard-hsw:          [FAIL][53] ([i915#1542]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-hsw6/igt@perf@blocking-parameterized.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-hsw4/igt@perf@blocking-parameterized.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [i915#1066]: https://gitlab.freedesktop.org/drm/intel/issues/1066
  [i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185
  [i915#1277]: https://gitlab.freedesktop.org/drm/intel/issues/1277
  [i915#138]: https://gitlab.freedesktop.org/drm/intel/issues/138
  [i915#1409]: https://gitlab.freedesktop.org/drm/intel/issues/1409
  [i915#1516]: https://gitlab.freedesktop.org/drm/intel/issues/1516
  [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
  [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#250]: https://gitlab.freedesktop.org/drm/intel/issues/250
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
  [i915#42]: https://gitlab.freedesktop.org/drm/intel/issues/42
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
  [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
  [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
  [i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8264 -> Patchwork_17226

  CI-20190529: 20190529
  CI_DRM_8264: e0104585f880a64d4a9b40803cf4fb51ab499f7c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5573: 9c582425d6b4fc1de9fc2ffc8015cc6f0a0d3e98 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17226: ba04f3ced69643939779e78860b0d7054875c784 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [Intel-gfx] [PATCH v2 1/8] drm/i915/display: Move out code to return the digital_port of the aux ch
  2020-04-07  1:11 [Intel-gfx] [PATCH v2 1/8] drm/i915/display: Move out code to return the digital_port of the aux ch José Roberto de Souza
                   ` (10 preceding siblings ...)
  2020-04-07 10:28 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/8] " Patchwork
@ 2020-04-07 15:13 ` Imre Deak
  11 siblings, 0 replies; 25+ messages in thread
From: Imre Deak @ 2020-04-07 15:13 UTC (permalink / raw)
  To: José Roberto de Souza; +Cc: You-Sheng Yang, intel-gfx

On Mon, Apr 06, 2020 at 06:11:50PM -0700, José Roberto de Souza wrote:
> Moving the code to return the digital port of the aux channel also
> removing the intel_phy_is_tc() to make it generic.
> digital_port will be needed in icl_tc_phy_aux_power_well_enable()
> so adding it as a parameter to icl_tc_port_assert_ref_held().
> 
> While at at removing the duplicated call to icl_tc_phy_aux_ch() in
> icl_tc_port_assert_ref_held().
> 
> v2:
> - fixed build when DRM_I915_DEBUG_RUNTIME_PM is not set
> - moved to before hsw_wait_for_power_well_enable() as it will be
> needed by hsw_wait_for_power_well_enable() in a future patch
> 
> Cc: You-Sheng Yang <vicamo@gmail.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  .../drm/i915/display/intel_display_power.c    | 69 ++++++++++---------
>  1 file changed, 37 insertions(+), 32 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 433e5a81dd4d..f2f42b5960df 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -282,6 +282,33 @@ static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
>  		gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
>  }
>  
> +static struct intel_digital_port *
> +aux_ch_to_digital_port(struct drm_i915_private *dev_priv,
> +		       enum aux_ch aux_ch)
> +{
> +	struct intel_digital_port *dig_port = NULL;
> +	struct intel_encoder *encoder;
> +
> +	for_each_intel_encoder(&dev_priv->drm, encoder) {
> +		/* We'll check the MST primary port */
> +		if (encoder->type == INTEL_OUTPUT_DP_MST)
> +			continue;
> +
> +		dig_port = enc_to_dig_port(encoder);
> +		if (drm_WARN_ON(&dev_priv->drm, !dig_port))

This would not work on non-digital port encoders (DSI), so just
		if (!dig_port)

With that fixed:
Reviewed-by: Imre Deak <imre.deak@intel.com>

> +			continue;
> +
> +		if (dig_port->aux_ch != aux_ch) {
> +			dig_port = NULL;
> +			continue;
> +		}
> +
> +		break;
> +	}
> +
> +	return dig_port;
> +}
> +
>  static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
>  					   struct i915_power_well *power_well)
>  {
> @@ -501,41 +528,14 @@ static int power_well_async_ref_count(struct drm_i915_private *dev_priv,
>  }
>  
>  static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
> -					struct i915_power_well *power_well)
> +					struct i915_power_well *power_well,
> +					struct intel_digital_port *dig_port)
>  {
> -	enum aux_ch aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
> -	struct intel_digital_port *dig_port = NULL;
> -	struct intel_encoder *encoder;
> -
>  	/* Bypass the check if all references are released asynchronously */
>  	if (power_well_async_ref_count(dev_priv, power_well) ==
>  	    power_well->count)
>  		return;
>  
> -	aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
> -
> -	for_each_intel_encoder(&dev_priv->drm, encoder) {
> -		enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> -
> -		if (!intel_phy_is_tc(dev_priv, phy))
> -			continue;
> -
> -		/* We'll check the MST primary port */
> -		if (encoder->type == INTEL_OUTPUT_DP_MST)
> -			continue;
> -
> -		dig_port = enc_to_dig_port(encoder);
> -		if (drm_WARN_ON(&dev_priv->drm, !dig_port))
> -			continue;
> -
> -		if (dig_port->aux_ch != aux_ch) {
> -			dig_port = NULL;
> -			continue;
> -		}
> -
> -		break;
> -	}
> -
>  	if (drm_WARN_ON(&dev_priv->drm, !dig_port))
>  		return;
>  
> @@ -545,7 +545,8 @@ static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
>  #else
>  
>  static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
> -					struct i915_power_well *power_well)
> +					struct i915_power_well *power_well,
> +					struct intel_digital_port *dig_port)
>  {
>  }
>  
> @@ -558,9 +559,10 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
>  				 struct i915_power_well *power_well)
>  {
>  	enum aux_ch aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
> +	struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv, aux_ch);
>  	u32 val;
>  
> -	icl_tc_port_assert_ref_held(dev_priv, power_well);
> +	icl_tc_port_assert_ref_held(dev_priv, power_well, dig_port);
>  
>  	val = intel_de_read(dev_priv, DP_AUX_CH_CTL(aux_ch));
>  	val &= ~DP_AUX_CH_CTL_TBT_IO;
> @@ -588,7 +590,10 @@ static void
>  icl_tc_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
>  				  struct i915_power_well *power_well)
>  {
> -	icl_tc_port_assert_ref_held(dev_priv, power_well);
> +	enum aux_ch aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
> +	struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv, aux_ch);
> +
> +	icl_tc_port_assert_ref_held(dev_priv, power_well, dig_port);
>  
>  	hsw_power_well_disable(dev_priv, power_well);
>  }
> -- 
> 2.26.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [Intel-gfx] [PATCH v2 2/8] drm/i915/display: Add intel_legacy_aux_to_power_domain()
  2020-04-07  1:11 ` [Intel-gfx] [PATCH v2 2/8] drm/i915/display: Add intel_legacy_aux_to_power_domain() José Roberto de Souza
@ 2020-04-07 15:15   ` Imre Deak
  0 siblings, 0 replies; 25+ messages in thread
From: Imre Deak @ 2020-04-07 15:15 UTC (permalink / raw)
  To: José Roberto de Souza; +Cc: Cooper Chiou, intel-gfx, Kai-Heng Feng

On Mon, Apr 06, 2020 at 06:11:51PM -0700, José Roberto de Souza wrote:
> This is a similar function to intel_aux_power_domain() but it do not
> care about TBT ports, this will be needed by ICL TC sequences.
> 
> v2:
> - renamed to intel_legacy_aux_to_power_domain()
> 
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Cooper Chiou <cooper.chiou@intel.com>
> Cc: Kai-Heng Feng <kai.heng.feng@canonical.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 14 ++++++++++++--
>  drivers/gpu/drm/i915/display/intel_display.h |  2 ++
>  2 files changed, 14 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 70ec301fe6e3..a95960b71001 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7291,7 +7291,17 @@ intel_aux_power_domain(struct intel_digital_port *dig_port)
>  		}
>  	}
>  
> -	switch (dig_port->aux_ch) {
> +	return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
> +}
> +
> +/*
> + * Converts aux_ch to power_domain without caring about TBT ports for that use
> + * intel_aux_power_domain()
> + */
> +enum intel_display_power_domain
> +intel_legacy_aux_to_power_domain(enum aux_ch aux_ch)
> +{
> +	switch (aux_ch) {
>  	case AUX_CH_A:
>  		return POWER_DOMAIN_AUX_A;
>  	case AUX_CH_B:
> @@ -7307,7 +7317,7 @@ intel_aux_power_domain(struct intel_digital_port *dig_port)
>  	case AUX_CH_G:
>  		return POWER_DOMAIN_AUX_G;
>  	default:
> -		MISSING_CASE(dig_port->aux_ch);
> +		MISSING_CASE(aux_ch);
>  		return POWER_DOMAIN_AUX_A;
>  	}
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index cc7f287804d7..8d872ed0de36 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -583,6 +583,8 @@ void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
>  enum intel_display_power_domain intel_port_to_power_domain(enum port port);
>  enum intel_display_power_domain
>  intel_aux_power_domain(struct intel_digital_port *dig_port);
> +enum intel_display_power_domain
> +intel_legacy_aux_to_power_domain(enum aux_ch aux_ch);
>  void intel_mode_from_pipe_config(struct drm_display_mode *mode,
>  				 struct intel_crtc_state *pipe_config);
>  void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
> -- 
> 2.26.0
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [Intel-gfx] [PATCH v2 3/8] drm/i915/display: Split hsw_power_well_enable() into two
  2020-04-07  1:11 ` [Intel-gfx] [PATCH v2 3/8] drm/i915/display: Split hsw_power_well_enable() into two José Roberto de Souza
@ 2020-04-07 15:20   ` Imre Deak
  0 siblings, 0 replies; 25+ messages in thread
From: Imre Deak @ 2020-04-07 15:20 UTC (permalink / raw)
  To: José Roberto de Souza; +Cc: intel-gfx

On Mon, Apr 06, 2020 at 06:11:52PM -0700, José Roberto de Souza wrote:
> This is a preparation for ICL TC cold exit sequences.
> 
> v2:
> - renamed new functions to hsw_power_well_enable_prepare()/complete()
> 
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  .../drm/i915/display/intel_display_power.c    | 39 +++++++++++++++----
>  1 file changed, 32 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index f2f42b5960df..62e49f06d467 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -380,16 +380,16 @@ static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv,
>  					  SKL_FUSE_PG_DIST_STATUS(pg), 1));
>  }
>  
> -static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
> -				  struct i915_power_well *power_well)
> +static void hsw_power_well_enable_prepare(struct drm_i915_private *dev_priv,
> +					  struct i915_power_well *power_well)
>  {
>  	const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
>  	int pw_idx = power_well->desc->hsw.idx;
> -	bool wait_fuses = power_well->desc->hsw.has_fuses;
> -	enum skl_power_gate uninitialized_var(pg);
>  	u32 val;
>  
> -	if (wait_fuses) {
> +	if (power_well->desc->hsw.has_fuses) {
> +		enum skl_power_gate pg;
> +
>  		pg = INTEL_GEN(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
>  						 SKL_PW_CTL_IDX_TO_PG(pw_idx);
>  		/*
> @@ -406,25 +406,46 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
>  	val = intel_de_read(dev_priv, regs->driver);
>  	intel_de_write(dev_priv, regs->driver,
>  		       val | HSW_PWR_WELL_CTL_REQ(pw_idx));
> +}
> +
> +static void hsw_power_well_enable_complete(struct drm_i915_private *dev_priv,
> +					   struct i915_power_well *power_well)
> +{
> +	int pw_idx = power_well->desc->hsw.idx;
> +
>  	hsw_wait_for_power_well_enable(dev_priv, power_well);
>  
>  	/* Display WA #1178: cnl */
>  	if (IS_CANNONLAKE(dev_priv) &&
>  	    pw_idx >= GLK_PW_CTL_IDX_AUX_B &&
>  	    pw_idx <= CNL_PW_CTL_IDX_AUX_F) {
> +		u32 val;
> +
>  		val = intel_de_read(dev_priv, CNL_AUX_ANAOVRD1(pw_idx));
>  		val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS;
>  		intel_de_write(dev_priv, CNL_AUX_ANAOVRD1(pw_idx), val);
>  	}
>  
> -	if (wait_fuses)
> +	if (power_well->desc->hsw.has_fuses) {
> +		enum skl_power_gate pg;
> +
> +		pg = INTEL_GEN(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
> +						 SKL_PW_CTL_IDX_TO_PG(pw_idx);
>  		gen9_wait_for_power_well_fuses(dev_priv, pg);
> +	}
>  
>  	hsw_power_well_post_enable(dev_priv,
>  				   power_well->desc->hsw.irq_pipe_mask,
>  				   power_well->desc->hsw.has_vga);
>  }
>  
> +static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
> +				  struct i915_power_well *power_well)
> +{
> +	hsw_power_well_enable_prepare(dev_priv, power_well);
> +	hsw_power_well_enable_complete(dev_priv, power_well);
> +}
> +
>  static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
>  				   struct i915_power_well *power_well)
>  {
> @@ -570,7 +591,11 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
>  		val |= DP_AUX_CH_CTL_TBT_IO;
>  	intel_de_write(dev_priv, DP_AUX_CH_CTL(aux_ch), val);
>  
> -	hsw_power_well_enable(dev_priv, power_well);
> +	hsw_power_well_enable_prepare(dev_priv, power_well);
> +
> +	/* TODO ICL TC cold handling */
> +
> +	hsw_power_well_enable_complete(dev_priv, power_well);
>  
>  	if (INTEL_GEN(dev_priv) >= 12 && !power_well->desc->hsw.is_tc_tbt) {
>  		enum tc_port tc_port;
> -- 
> 2.26.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [Intel-gfx] [PATCH v2 4/8] drm/i915/tc/icl: Implement TC cold sequences
  2020-04-07  1:11 ` [Intel-gfx] [PATCH v2 4/8] drm/i915/tc/icl: Implement TC cold sequences José Roberto de Souza
@ 2020-04-07 15:42   ` Imre Deak
  2020-04-07 20:01     ` Souza, Jose
  0 siblings, 1 reply; 25+ messages in thread
From: Imre Deak @ 2020-04-07 15:42 UTC (permalink / raw)
  To: José Roberto de Souza; +Cc: Cooper Chiou, intel-gfx, Kai-Heng Feng

On Mon, Apr 06, 2020 at 06:11:53PM -0700, José Roberto de Souza wrote:
> This is required for legacy/static TC ports as IOM is not aware of
> the connection and will not trigger the TC cold exit.
> 
> Just request PCODE to exit TCCOLD is not enough as it could enter
> again before driver makes use of the port, to prevent it BSpec states
> that aux powerwell should be held.
> 
> So here embedding the TC cold exit sequence into ICL aux enable,
> it will enable aux and then request TC cold to exit.
> 
> The TC cold block(exit and aux hold) and unblock was added to some
> exported TC functions for the others and to access PHY registers,
> callers should enable and keep aux powerwell enabled during access.
> 
> Also adding TC cold check and warnig in tc_port_load_fia_params() as
> at this point of the driver initialization we can't request power
> wells, if we get this warning we will need to figure out how to handle
> it.
> 
> v2:
> - moved ICL TC cold exit function to intel_display_power
> - using dig_port->tc_legacy_port to only execute sequences for legacy
> ports, hopefully VBTs will have this right
> - fixed check to call _hsw_power_well_continue_enable()
> - calling _hsw_power_well_continue_enable() unconditionally in
> icl_tc_phy_aux_power_well_enable(), if needed we will surpress timeout
> warnings of TC legacy ports
> - only blocking TC cold around fia access
> 
> BSpec: 21750
> Fixes: https://gitlab.freedesktop.org/drm/intel/issues/1296
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Cooper Chiou <cooper.chiou@intel.com>
> Cc: Kai-Heng Feng <kai.heng.feng@canonical.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> 
> squash icl

Leftover.

> ---
>  .../drm/i915/display/intel_display_power.c    | 22 ++++++-
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_tc.c       | 64 +++++++++++++++++--
>  drivers/gpu/drm/i915/i915_reg.h               |  1 +
>  4 files changed, 80 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 62e49f06d467..1336247743c4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -575,6 +575,25 @@ static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
>  
>  #define TGL_AUX_PW_TO_TC_PORT(pw_idx)	((pw_idx) - TGL_PW_CTL_IDX_AUX_TC1)
>  
> +static void icl_tc_cold_exit(struct drm_i915_private *i915)
> +{
> +	int ret;
> +
> +	do {
> +		ret = sandybridge_pcode_write_timeout(i915,
> +						      ICL_PCODE_EXIT_TCCOLD,
> +						      0, 250, 1);
> +

Extra w/s.

> +	} while (ret == -EAGAIN);

Let's protect against an endless loop.

> +
> +	/* Spec states that TC cold exit can take up to 1ms to complete */
> +	if (!ret)
> +		msleep(1);
> +
> +	drm_dbg_kms(&i915->drm, "TC cold block %s\n", ret == 0 ? "succeeded" :
> +		    "failed");
> +}
> +
>  static void
>  icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
>  				 struct i915_power_well *power_well)
> @@ -593,7 +612,8 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
>  
>  	hsw_power_well_enable_prepare(dev_priv, power_well);
>  
> -	/* TODO ICL TC cold handling */
> +	if (INTEL_GEN(dev_priv) == 11 && dig_port->tc_legacy_port)
> +		icl_tc_cold_exit(dev_priv);
>  
>  	hsw_power_well_enable_complete(dev_priv, power_well);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 5a0adf14ebef..f7506ac40eb4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1400,6 +1400,7 @@ struct intel_digital_port {
>  	enum intel_display_power_domain ddi_io_power_domain;
>  	struct mutex tc_lock;	/* protects the TypeC port mode */
>  	intel_wakeref_t tc_lock_wakeref;
> +	intel_wakeref_t tc_cold_wakeref;

Not needed any more.

>  	int tc_link_refcount;
>  	bool tc_legacy_port:1;
>  	char tc_port_name[8];
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index 9b850c11aa78..7564259d677e 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -34,6 +34,7 @@ tc_port_load_fia_params(struct drm_i915_private *i915,
>  	if (INTEL_INFO(i915)->display.has_modular_fia) {
>  		modular_fia = intel_uncore_read(&i915->uncore,
>  						PORT_TX_DFLEXDPSP(FIA1));
> +		drm_WARN_ON(&i915->drm, modular_fia == 0xffffffff);
>  		modular_fia &= MODULAR_FIA_MASK;
>  	} else {
>  		modular_fia = 0;
> @@ -52,6 +53,37 @@ tc_port_load_fia_params(struct drm_i915_private *i915,
>  	}
>  }
>  
> +static intel_wakeref_t
> +tc_cold_block(struct intel_digital_port *dig_port)
> +{
> +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> +	enum intel_display_power_domain domain;
> +
> +	if (INTEL_GEN(i915) != 11 || !dig_port->tc_legacy_port)
> +		return 0;
> +
> +	domain = intel_legacy_aux_to_power_domain(dig_port->aux_ch);
> +	return intel_display_power_get(i915, domain);
> +}
> +
> +static void
> +tc_cold_unblock(struct intel_digital_port *dig_port, intel_wakeref_t wakeref)
> +{
> +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> +	enum intel_display_power_domain domain;
> +
> +	/*
> +	 * wakeref == -1, means some error happened saving save_depot_stack but
> +	 * power should still be put down and 0 is a invalid save_depot_stack
> +	 * id so can be used to skip it for non TC legacy ports.
> +	 */
> +	if (wakeref == 0)
> +		return;
> +
> +	domain = intel_legacy_aux_to_power_domain(dig_port->aux_ch);
> +	intel_display_power_put_async(i915, domain, wakeref);
> +}
> +
>  u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
>  {
>  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> @@ -415,9 +447,14 @@ static void intel_tc_port_reset_mode(struct intel_digital_port *dig_port,
>  	enum tc_port_mode old_tc_mode = dig_port->tc_mode;
>  
>  	intel_display_power_flush_work(i915);
> -	drm_WARN_ON(&i915->drm,
> -		    intel_display_power_is_enabled(i915,
> -					intel_aux_power_domain(dig_port)));
> +	if (INTEL_GEN(i915) != 11 || !dig_port->tc_legacy_port) {
> +		enum intel_display_power_domain aux_domain;
> +		bool aux_powered;
> +
> +		aux_domain = intel_aux_power_domain(dig_port);
> +		aux_powered = intel_display_power_is_enabled(i915, aux_domain);
> +		drm_WARN_ON(&i915->drm, aux_powered);
> +	}
>  
>  	icl_tc_phy_disconnect(dig_port);
>  	icl_tc_phy_connect(dig_port, required_lanes);
> @@ -439,9 +476,11 @@ intel_tc_port_link_init_refcount(struct intel_digital_port *dig_port,
>  void intel_tc_port_sanitize(struct intel_digital_port *dig_port)
>  {
>  	struct intel_encoder *encoder = &dig_port->base;
> +	intel_wakeref_t tc_cold_wref;
>  	int active_links = 0;
>  
>  	mutex_lock(&dig_port->tc_lock);
> +	tc_cold_wref = tc_cold_block(dig_port);
>  
>  	dig_port->tc_mode = intel_tc_port_get_current_mode(dig_port);
>  	if (dig_port->dp.is_mst)
> @@ -466,6 +505,7 @@ void intel_tc_port_sanitize(struct intel_digital_port *dig_port)
>  		      dig_port->tc_port_name,
>  		      tc_port_mode_name(dig_port->tc_mode));
>  
> +	tc_cold_unblock(dig_port, tc_cold_wref);
>  	mutex_unlock(&dig_port->tc_lock);
>  }
>  
> @@ -487,10 +527,15 @@ static bool intel_tc_port_needs_reset(struct intel_digital_port *dig_port)
>  bool intel_tc_port_connected(struct intel_digital_port *dig_port)
>  {
>  	bool is_connected;
> +	intel_wakeref_t tc_cold_wref;
>  
>  	intel_tc_port_lock(dig_port);
> +	tc_cold_wref = tc_cold_block(dig_port);
> +
>  	is_connected = tc_port_live_status_mask(dig_port) &
>  		       BIT(dig_port->tc_mode);
> +
> +	tc_cold_unblock(dig_port, tc_cold_wref);
>  	intel_tc_port_unlock(dig_port);
>  
>  	return is_connected;
> @@ -500,15 +545,20 @@ static void __intel_tc_port_lock(struct intel_digital_port *dig_port,
>  				 int required_lanes)
>  {
>  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> -	intel_wakeref_t wakeref;
> +	intel_wakeref_t wakeref, tc_cold_wref;

Could be moved into its scope.

>  
>  	wakeref = intel_display_power_get(i915, POWER_DOMAIN_DISPLAY_CORE);
>  
>  	mutex_lock(&dig_port->tc_lock);
>  
> -	if (!dig_port->tc_link_refcount &&
> -	    intel_tc_port_needs_reset(dig_port))
> -		intel_tc_port_reset_mode(dig_port, required_lanes);
> +	if (!dig_port->tc_link_refcount) {
> +		tc_cold_wref = tc_cold_block(dig_port);
> +
> +		if (intel_tc_port_needs_reset(dig_port))
> +			intel_tc_port_reset_mode(dig_port, required_lanes);
> +
> +		tc_cold_unblock(dig_port, tc_cold_wref);
> +	}
>  
>  	drm_WARN_ON(&i915->drm, dig_port->tc_lock_wakeref);
>  	dig_port->tc_lock_wakeref = wakeref;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8cebb7a86b8c..5cbcd01ac3d5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9107,6 +9107,7 @@ enum {
>  #define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)	(((point) << 16) | (0x1 << 8))
>  #define   GEN6_PCODE_READ_D_COMP		0x10
>  #define   GEN6_PCODE_WRITE_D_COMP		0x11
> +#define   ICL_PCODE_EXIT_TCCOLD			0x12
>  #define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
>  #define   DISPLAY_IPS_CONTROL			0x19
>              /* See also IPS_CTL */
> -- 
> 2.26.0
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [Intel-gfx] [PATCH v2 5/8] drm/i915/tc: Skip ref held check for TC legacy aux power wells
  2020-04-07  1:11 ` [Intel-gfx] [PATCH v2 5/8] drm/i915/tc: Skip ref held check for TC legacy aux power wells José Roberto de Souza
@ 2020-04-07 15:42   ` Imre Deak
  0 siblings, 0 replies; 25+ messages in thread
From: Imre Deak @ 2020-04-07 15:42 UTC (permalink / raw)
  To: José Roberto de Souza; +Cc: intel-gfx

On Mon, Apr 06, 2020 at 06:11:54PM -0700, José Roberto de Souza wrote:
> As part of ICL TC cold exit sequences we need to request aux power
> well before lock the access to TC ports, so skiping the
> intel_tc_port_ref_held() check for TC legacy ports.
> 
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display_power.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 1336247743c4..0383801a9acc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -560,6 +560,9 @@ static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
>  	if (drm_WARN_ON(&dev_priv->drm, !dig_port))
>  		return;
>  
> +	if (INTEL_GEN(dev_priv) == 11 && dig_port->tc_legacy_port)
> +		return;
> +
>  	drm_WARN_ON(&dev_priv->drm, !intel_tc_port_ref_held(dig_port));
>  }
>  
> -- 
> 2.26.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [Intel-gfx] [PATCH v2 6/8] drm/i915/tc/tgl: Implement TC cold sequences
  2020-04-07  1:11 ` [Intel-gfx] [PATCH v2 6/8] drm/i915/tc/tgl: Implement TC cold sequences José Roberto de Souza
@ 2020-04-07 16:02   ` Imre Deak
  2020-04-07 21:20     ` Souza, Jose
  0 siblings, 1 reply; 25+ messages in thread
From: Imre Deak @ 2020-04-07 16:02 UTC (permalink / raw)
  To: José Roberto de Souza; +Cc: Cooper Chiou, intel-gfx, Kai-Heng Feng

On Mon, Apr 06, 2020 at 06:11:55PM -0700, José Roberto de Souza wrote:
> TC ports can enter in TCCOLD to save power and is required to request
> to PCODE to exit this state before use or read to TC registers.
> 
> For TGL there is a new MBOX command to do that with a parameter to ask
> PCODE to exit and block TCCOLD entry or unblock TCCOLD entry.
> 
> So adding a new power domain to reuse the refcount and only allow
> TC cold when all TC ports are not in use.
> 
> v2:
> - fixed missing case in intel_display_power_domain_str()
> - moved tgl_tc_cold_request to intel_display_power.c
> - renamed TGL_TC_COLD_OFF to TGL_TC_COLD_OFF_POWER_DOMAINS
> - added all TC and TBT aux power domains to
> TGL_TC_COLD_OFF_POWER_DOMAINS
> 
> BSpec: 49294
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Cooper Chiou <cooper.chiou@intel.com>
> Cc: Kai-Heng Feng <kai.heng.feng@canonical.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  .../drm/i915/display/intel_display_power.c    | 98 +++++++++++++++++++
>  .../drm/i915/display/intel_display_power.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_tc.c       | 17 +++-
>  drivers/gpu/drm/i915/i915_reg.h               |  3 +
>  4 files changed, 116 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 0383801a9acc..5d33929f3724 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -151,6 +151,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
>  		return "GT_IRQ";
>  	case POWER_DOMAIN_DPLL_DC_OFF:
>  		return "DPLL_DC_OFF";
> +	case POWER_DOMAIN_TC_COLD_OFF:
> +		return "TC_COLD_OFF";
>  	default:
>  		MISSING_CASE(domain);
>  		return "?";
> @@ -2858,6 +2860,21 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
>  #define TGL_AUX_I_TBT6_IO_POWER_DOMAINS (	\
>  	BIT_ULL(POWER_DOMAIN_AUX_I_TBT))
>  
> +#define TGL_TC_COLD_OFF_POWER_DOMAINS (		\
> +	BIT_ULL(POWER_DOMAIN_AUX_D)	|	\
> +	BIT_ULL(POWER_DOMAIN_AUX_E)	|	\
> +	BIT_ULL(POWER_DOMAIN_AUX_F)	|	\
> +	BIT_ULL(POWER_DOMAIN_AUX_G)	|	\
> +	BIT_ULL(POWER_DOMAIN_AUX_H)	|	\
> +	BIT_ULL(POWER_DOMAIN_AUX_I)	|	\
> +	BIT_ULL(POWER_DOMAIN_AUX_D_TBT)	|	\
> +	BIT_ULL(POWER_DOMAIN_AUX_E_TBT)	|	\
> +	BIT_ULL(POWER_DOMAIN_AUX_F_TBT)	|	\
> +	BIT_ULL(POWER_DOMAIN_AUX_G_TBT)	|	\
> +	BIT_ULL(POWER_DOMAIN_AUX_H_TBT)	|	\
> +	BIT_ULL(POWER_DOMAIN_AUX_I_TBT)	|	\
> +	BIT_ULL(POWER_DOMAIN_TC_COLD_OFF))
> +
>  static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
>  	.sync_hw = i9xx_power_well_sync_hw_noop,
>  	.enable = i9xx_always_on_power_well_noop,
> @@ -3960,6 +3977,81 @@ static const struct i915_power_well_desc ehl_power_wells[] = {
>  	},
>  };
>  
> +static void
> +tgl_tc_cold_request(struct drm_i915_private *i915, bool block)
> +{
> +	u32 low_val, high_val;

Can be moved to their scope.

> +	u8 tries = 0;
> +	int ret;
> +
> +	do {
> +		low_val = 0;
> +		high_val = block ? 0 : TGL_PCODE_EXIT_TCCOLD_DATA_H_UNBLOCK_REQ;
> +
> +		/*
> +		 * Spec states that we should timeout the request after 200us
> +		 * but the function below will timeout after 500us
> +		 */
> +		ret = sandybridge_pcode_read(i915, TGL_PCODE_TCCOLD, &low_val,
> +					     &high_val);
> +		if (ret == 0) {
> +			if (block &&
> +			    (low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED))
> +				ret = -EIO;
> +			else
> +				break;
> +		}
> +
> +		if (ret != -EAGAIN)
> +			tries++;

-EAGAIN means that the PCODE run/busy flag didn't get cleared in the
previous iteration, and BSpec says to bail out and not to use the port
in that case. But we can't really do that, so let's give some slack to
PUNIT (and CPU), msleep(1) so the next iteration doesn't return
immediately and still protect against an endless loop?

> +	} while (tries < 3);
> +
> +	drm_dbg_kms(&i915->drm, "TC cold %sblock %s\n", block ? "" : "un",
> +		    ret == 0 ? "succeeded" : "failed");

Isn't the fail always a true error? (also on ICL)

> +}
> +
> +static void
> +tgl_tc_cold_off_power_well_enable(struct drm_i915_private *i915,
> +				  struct i915_power_well *power_well)
> +{
> +	tgl_tc_cold_request(i915, true);
> +}
> +
> +static void
> +tgl_tc_cold_off_power_well_disable(struct drm_i915_private *i915,
> +				   struct i915_power_well *power_well)
> +{
> +	tgl_tc_cold_request(i915, false);
> +}
> +
> +static void
> +tgl_tc_cold_off_power_well_sync_hw(struct drm_i915_private *i915,
> +				   struct i915_power_well *power_well)
> +{
> +	if (power_well->count > 0)
> +		tgl_tc_cold_off_power_well_enable(i915, power_well);
> +	else
> +		tgl_tc_cold_off_power_well_disable(i915, power_well);
> +}
> +
> +static bool
> +tgl_tc_cold_off_power_well_is_enabled(struct drm_i915_private *dev_priv,
> +				      struct i915_power_well *power_well)
> +{
> +	/*
> +	 * Not the correctly implementation but there is no way to just read it
> +	 * from PCODE, so returning count to avoid state mismatch errors
> +	 */
> +	return power_well->count;
> +}
> +
> +static const struct i915_power_well_ops tgl_tc_cold_off_ops = {
> +	.sync_hw = tgl_tc_cold_off_power_well_sync_hw,
> +	.enable = tgl_tc_cold_off_power_well_enable,
> +	.disable = tgl_tc_cold_off_power_well_disable,
> +	.is_enabled = tgl_tc_cold_off_power_well_is_enabled,
> +};
> +
>  static const struct i915_power_well_desc tgl_power_wells[] = {
>  	{
>  		.name = "always-on",
> @@ -4287,6 +4379,12 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
>  			.hsw.irq_pipe_mask = BIT(PIPE_D),
>  		},
>  	},
> +	{
> +		.name = "TC cold off",
> +		.domains = TGL_TC_COLD_OFF_POWER_DOMAINS,
> +		.ops = &tgl_tc_cold_off_ops,
> +		.id = DISP_PW_ID_NONE,
> +	},
>  };
>  
>  static int
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> index da64a5edae7a..070457e7b948 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -76,6 +76,7 @@ enum intel_display_power_domain {
>  	POWER_DOMAIN_MODESET,
>  	POWER_DOMAIN_GT_IRQ,
>  	POWER_DOMAIN_DPLL_DC_OFF,
> +	POWER_DOMAIN_TC_COLD_OFF,
>  	POWER_DOMAIN_INIT,
>  
>  	POWER_DOMAIN_NUM,
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index 7564259d677e..83861653768d 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -53,16 +53,27 @@ tc_port_load_fia_params(struct drm_i915_private *i915,
>  	}
>  }
>  
> +static enum intel_display_power_domain
> +tc_cold_get_power_domain(struct intel_digital_port *dig_port)
> +{
> +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> +
> +	if (INTEL_GEN(i915) == 11)
> +		return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
> +	else
> +		return POWER_DOMAIN_TC_COLD_OFF;
> +}
> +
>  static intel_wakeref_t
>  tc_cold_block(struct intel_digital_port *dig_port)
>  {
>  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
>  	enum intel_display_power_domain domain;
>  
> -	if (INTEL_GEN(i915) != 11 || !dig_port->tc_legacy_port)
> +	if (INTEL_GEN(i915) == 11 && !dig_port->tc_legacy_port)
>  		return 0;
>  
> -	domain = intel_legacy_aux_to_power_domain(dig_port->aux_ch);
> +	domain = tc_cold_get_power_domain(dig_port);
>  	return intel_display_power_get(i915, domain);
>  }
>  
> @@ -80,7 +91,7 @@ tc_cold_unblock(struct intel_digital_port *dig_port, intel_wakeref_t wakeref)
>  	if (wakeref == 0)
>  		return;
>  
> -	domain = intel_legacy_aux_to_power_domain(dig_port->aux_ch);
> +	domain = tc_cold_get_power_domain(dig_port);
>  	intel_display_power_put_async(i915, domain, wakeref);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5cbcd01ac3d5..e04eec003d4b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9110,6 +9110,9 @@ enum {
>  #define   ICL_PCODE_EXIT_TCCOLD			0x12
>  #define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
>  #define   DISPLAY_IPS_CONTROL			0x19
> +#define   TGL_PCODE_TCCOLD			0x26
> +#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED   REG_BIT(0)
> +#define     TGL_PCODE_EXIT_TCCOLD_DATA_H_UNBLOCK_REQ   REG_BIT(0)
>              /* See also IPS_CTL */
>  #define     IPS_PCODE_CONTROL			(1 << 30)
>  #define   HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
> -- 
> 2.26.0
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [Intel-gfx] [PATCH v2 7/8] drm/i915/tc: Catch TC users accessing FIA registers without enable aux
  2020-04-07  1:11 ` [Intel-gfx] [PATCH v2 7/8] drm/i915/tc: Catch TC users accessing FIA registers without enable aux José Roberto de Souza
@ 2020-04-07 16:04   ` Imre Deak
  2020-04-07 18:20     ` Imre Deak
  0 siblings, 1 reply; 25+ messages in thread
From: Imre Deak @ 2020-04-07 16:04 UTC (permalink / raw)
  To: José Roberto de Souza; +Cc: intel-gfx

On Mon, Apr 06, 2020 at 06:11:56PM -0700, José Roberto de Souza wrote:
> As described in "drm/i915/tc/icl: Implement TC cold sequences" users
> of TC functions should held aux power well during access to avoid
> read garbage due HW in TC cold state.
> 
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_tc.c | 22 ++++++++++++++++++++--
>  1 file changed, 20 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index 83861653768d..e473bb4a9b0b 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -95,6 +95,20 @@ tc_cold_unblock(struct intel_digital_port *dig_port, intel_wakeref_t wakeref)
>  	intel_display_power_put_async(i915, domain, wakeref);
>  }
>  
> +static void
> +is_tc_cold_blocked(struct intel_digital_port *dig_port)

assert_tc_cold_blocked()?

Reviewed-by: Imre Deak <imre.deak@intel.com>

> +{
> +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> +	bool enabled;
> +
> +	if (INTEL_GEN(i915) == 11 && !dig_port->tc_legacy_port)
> +		return;
> +
> +	enabled = intel_display_power_is_enabled(i915,
> +						 tc_cold_get_power_domain(dig_port));
> +	drm_WARN_ON(&i915->drm, !enabled);
> +}
> +
>  u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
>  {
>  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> @@ -104,7 +118,7 @@ u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
>  	lane_mask = intel_uncore_read(uncore,
>  				      PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
>  
> -	drm_WARN_ON(&i915->drm, lane_mask == 0xffffffff);
> +	is_tc_cold_blocked(dig_port);
>  
>  	lane_mask &= DP_LANE_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx);
>  	return lane_mask >> DP_LANE_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
> @@ -119,7 +133,7 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
>  	pin_mask = intel_uncore_read(uncore,
>  				     PORT_TX_DFLEXPA1(dig_port->tc_phy_fia));
>  
> -	drm_WARN_ON(&i915->drm, pin_mask == 0xffffffff);
> +	is_tc_cold_blocked(dig_port);
>  
>  	return (pin_mask & DP_PIN_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx)) >>
>  	       DP_PIN_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
> @@ -134,6 +148,8 @@ int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
>  	if (dig_port->tc_mode != TC_PORT_DP_ALT)
>  		return 4;
>  
> +	is_tc_cold_blocked(dig_port);
> +
>  	lane_mask = 0;
>  	with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
>  		lane_mask = intel_tc_port_get_lane_mask(dig_port);
> @@ -166,6 +182,8 @@ void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
>  	drm_WARN_ON(&i915->drm,
>  		    lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY);
>  
> +	is_tc_cold_blocked(dig_port);
> +
>  	val = intel_uncore_read(uncore,
>  				PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia));
>  	val &= ~DFLEXDPMLE1_DPMLETC_MASK(dig_port->tc_phy_fia_idx);
> -- 
> 2.26.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [Intel-gfx] [PATCH v2 8/8] drm/i915/tc: Do not warn when aux power well of static TC ports timeout
  2020-04-07  1:11 ` [Intel-gfx] [PATCH v2 8/8] drm/i915/tc: Do not warn when aux power well of static TC ports timeout José Roberto de Souza
@ 2020-04-07 16:18   ` Imre Deak
  0 siblings, 0 replies; 25+ messages in thread
From: Imre Deak @ 2020-04-07 16:18 UTC (permalink / raw)
  To: José Roberto de Souza; +Cc: intel-gfx

On Mon, Apr 06, 2020 at 06:11:57PM -0700, José Roberto de Souza wrote:
> This is a expected timeout of static TC ports not conneceted, so
> not throwing warnings that would taint CI.
> 
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  .../drm/i915/display/intel_display_power.c    | 37 +++++++++++--------
>  1 file changed, 21 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 5d33929f3724..50af5854658e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -284,6 +284,21 @@ static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
>  		gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
>  }
>  
> +#define ICL_AUX_PW_TO_CH(pw_idx)	\
> +	((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A)
> +
> +#define ICL_TBT_AUX_PW_TO_CH(pw_idx)	\
> +	((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C)
> +
> +static enum aux_ch icl_tc_phy_aux_ch(struct drm_i915_private *dev_priv,
> +				     struct i915_power_well *power_well)
> +{
> +	int pw_idx = power_well->desc->hsw.idx;
> +
> +	return power_well->desc->hsw.is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) :
> +						 ICL_AUX_PW_TO_CH(pw_idx);
> +}
> +
>  static struct intel_digital_port *
>  aux_ch_to_digital_port(struct drm_i915_private *dev_priv,
>  		       enum aux_ch aux_ch)
> @@ -320,11 +335,16 @@ static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
>  	/* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
>  	if (intel_de_wait_for_set(dev_priv, regs->driver,
>  				  HSW_PWR_WELL_CTL_STATE(pw_idx), 1)) {
> +		enum aux_ch aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);

This is only valid for ICL tc phy power wells. You could move the logic
for that to a tc_phy_aux_timeout_expected(pw_idx) helper.

> +		struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv, aux_ch);
> +
>  		drm_dbg_kms(&dev_priv->drm, "%s power well enable timeout\n",
>  			    power_well->desc->name);
>  
>  		/* An AUX timeout is expected if the TBT DP tunnel is down. */
> -		drm_WARN_ON(&dev_priv->drm, !power_well->desc->hsw.is_tc_tbt);
> +		drm_WARN_ON(&dev_priv->drm, !power_well->desc->hsw.is_tc_tbt &&
> +			    !(INTEL_GEN(dev_priv) == 11 && dig_port->tc_legacy_port));
> +
>  	}
>  }
>  
> @@ -520,21 +540,6 @@ icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
>  	hsw_wait_for_power_well_disable(dev_priv, power_well);
>  }
>  
> -#define ICL_AUX_PW_TO_CH(pw_idx)	\
> -	((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A)
> -
> -#define ICL_TBT_AUX_PW_TO_CH(pw_idx)	\
> -	((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C)
> -
> -static enum aux_ch icl_tc_phy_aux_ch(struct drm_i915_private *dev_priv,
> -				     struct i915_power_well *power_well)
> -{
> -	int pw_idx = power_well->desc->hsw.idx;
> -
> -	return power_well->desc->hsw.is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) :
> -						 ICL_AUX_PW_TO_CH(pw_idx);
> -}
> -
>  #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
>  
>  static u64 async_put_domains_mask(struct i915_power_domains *power_domains);
> -- 
> 2.26.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [Intel-gfx] [PATCH v2 7/8] drm/i915/tc: Catch TC users accessing FIA registers without enable aux
  2020-04-07 16:04   ` Imre Deak
@ 2020-04-07 18:20     ` Imre Deak
  0 siblings, 0 replies; 25+ messages in thread
From: Imre Deak @ 2020-04-07 18:20 UTC (permalink / raw)
  To: José Roberto de Souza; +Cc: intel-gfx

On Tue, Apr 07, 2020 at 07:04:55PM +0300, Imre Deak wrote:
> On Mon, Apr 06, 2020 at 06:11:56PM -0700, José Roberto de Souza wrote:
> > As described in "drm/i915/tc/icl: Implement TC cold sequences" users
> > of TC functions should held aux power well during access to avoid
> > read garbage due HW in TC cold state.
> > 
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_tc.c | 22 ++++++++++++++++++++--
> >  1 file changed, 20 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> > index 83861653768d..e473bb4a9b0b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_tc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> > @@ -95,6 +95,20 @@ tc_cold_unblock(struct intel_digital_port *dig_port, intel_wakeref_t wakeref)
> >  	intel_display_power_put_async(i915, domain, wakeref);
> >  }
> >  
> > +static void
> > +is_tc_cold_blocked(struct intel_digital_port *dig_port)
> 
> assert_tc_cold_blocked()?
> 
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> 
> > +{
> > +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > +	bool enabled;
> > +
> > +	if (INTEL_GEN(i915) == 11 && !dig_port->tc_legacy_port)
> > +		return;
> > +
> > +	enabled = intel_display_power_is_enabled(i915,
> > +						 tc_cold_get_power_domain(dig_port));
> > +	drm_WARN_ON(&i915->drm, !enabled);
> > +}
> > +
> >  u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
> >  {
> >  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > @@ -104,7 +118,7 @@ u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
> >  	lane_mask = intel_uncore_read(uncore,
> >  				      PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
> >  
> > -	drm_WARN_ON(&i915->drm, lane_mask == 0xffffffff);

You could also keep the checks like the above one, since reading all
0xff is still bogus.

> > +	is_tc_cold_blocked(dig_port);
> >  
> >  	lane_mask &= DP_LANE_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx);
> >  	return lane_mask >> DP_LANE_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
> > @@ -119,7 +133,7 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
> >  	pin_mask = intel_uncore_read(uncore,
> >  				     PORT_TX_DFLEXPA1(dig_port->tc_phy_fia));
> >  
> > -	drm_WARN_ON(&i915->drm, pin_mask == 0xffffffff);
> > +	is_tc_cold_blocked(dig_port);
> >  
> >  	return (pin_mask & DP_PIN_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx)) >>
> >  	       DP_PIN_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
> > @@ -134,6 +148,8 @@ int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
> >  	if (dig_port->tc_mode != TC_PORT_DP_ALT)
> >  		return 4;
> >  
> > +	is_tc_cold_blocked(dig_port);
> > +
> >  	lane_mask = 0;
> >  	with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
> >  		lane_mask = intel_tc_port_get_lane_mask(dig_port);
> > @@ -166,6 +182,8 @@ void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
> >  	drm_WARN_ON(&i915->drm,
> >  		    lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY);
> >  
> > +	is_tc_cold_blocked(dig_port);
> > +
> >  	val = intel_uncore_read(uncore,
> >  				PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia));
> >  	val &= ~DFLEXDPMLE1_DPMLETC_MASK(dig_port->tc_phy_fia_idx);
> > -- 
> > 2.26.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [Intel-gfx] [PATCH v2 4/8] drm/i915/tc/icl: Implement TC cold sequences
  2020-04-07 15:42   ` Imre Deak
@ 2020-04-07 20:01     ` Souza, Jose
  2020-04-07 21:52       ` Imre Deak
  0 siblings, 1 reply; 25+ messages in thread
From: Souza, Jose @ 2020-04-07 20:01 UTC (permalink / raw)
  To: Deak, Imre; +Cc: Chiou, Cooper, intel-gfx, kai.heng.feng

On Tue, 2020-04-07 at 18:42 +0300, Imre Deak wrote:
> On Mon, Apr 06, 2020 at 06:11:53PM -0700, José Roberto de Souza
> wrote:
> > This is required for legacy/static TC ports as IOM is not aware of
> > the connection and will not trigger the TC cold exit.
> > 
> > Just request PCODE to exit TCCOLD is not enough as it could enter
> > again before driver makes use of the port, to prevent it BSpec
> > states
> > that aux powerwell should be held.
> > 
> > So here embedding the TC cold exit sequence into ICL aux enable,
> > it will enable aux and then request TC cold to exit.
> > 
> > The TC cold block(exit and aux hold) and unblock was added to some
> > exported TC functions for the others and to access PHY registers,
> > callers should enable and keep aux powerwell enabled during access.
> > 
> > Also adding TC cold check and warnig in tc_port_load_fia_params()
> > as
> > at this point of the driver initialization we can't request power
> > wells, if we get this warning we will need to figure out how to
> > handle
> > it.
> > 
> > v2:
> > - moved ICL TC cold exit function to intel_display_power
> > - using dig_port->tc_legacy_port to only execute sequences for
> > legacy
> > ports, hopefully VBTs will have this right
> > - fixed check to call _hsw_power_well_continue_enable()
> > - calling _hsw_power_well_continue_enable() unconditionally in
> > icl_tc_phy_aux_power_well_enable(), if needed we will surpress
> > timeout
> > warnings of TC legacy ports
> > - only blocking TC cold around fia access
> > 
> > BSpec: 21750
> > Fixes: https://gitlab.freedesktop.org/drm/intel/issues/1296
> > Cc: Imre Deak <imre.deak@intel.com>
> > Cc: Cooper Chiou <cooper.chiou@intel.com>
> > Cc: Kai-Heng Feng <kai.heng.feng@canonical.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > 
> > squash icl
> 
> Leftover.

Ops, thanks

> 
> > ---
> >  .../drm/i915/display/intel_display_power.c    | 22 ++++++-
> >  .../drm/i915/display/intel_display_types.h    |  1 +
> >  drivers/gpu/drm/i915/display/intel_tc.c       | 64
> > +++++++++++++++++--
> >  drivers/gpu/drm/i915/i915_reg.h               |  1 +
> >  4 files changed, 80 insertions(+), 8 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 62e49f06d467..1336247743c4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -575,6 +575,25 @@ static void icl_tc_port_assert_ref_held(struct
> > drm_i915_private *dev_priv,
> >  
> >  #define TGL_AUX_PW_TO_TC_PORT(pw_idx)	((pw_idx) -
> > TGL_PW_CTL_IDX_AUX_TC1)
> >  
> > +static void icl_tc_cold_exit(struct drm_i915_private *i915)
> > +{
> > +	int ret;
> > +
> > +	do {
> > +		ret = sandybridge_pcode_write_timeout(i915,
> > +						      ICL_PCODE_EXIT_TC
> > COLD,
> > +						      0, 250, 1);
> > +
> 
> Extra w/s.

Removed

> 
> > +	} while (ret == -EAGAIN);
> 
> Let's protect against an endless loop.

const ktime_t timeout = ktime_add_ms(ktime_get_raw(), 3);
int ret;

do {
	ret = sandybridge_pcode_write_timeout(i915,
					      ICL_PCODE_EXIT_TCCOLD,
					      0, 250, 1);
} while (ret == -EAGAIN && ktime_compare(timeout, ktime_get_raw()) >
0);
Changing to:



> 
> > +
> > +	/* Spec states that TC cold exit can take up to 1ms to complete
> > */
> > +	if (!ret)
> > +		msleep(1);
> > +
> > +	drm_dbg_kms(&i915->drm, "TC cold block %s\n", ret == 0 ?
> > "succeeded" :
> > +		    "failed");
> > +}
> > +
> >  static void
> >  icl_tc_phy_aux_power_well_enable(struct drm_i915_private
> > *dev_priv,
> >  				 struct i915_power_well *power_well)
> > @@ -593,7 +612,8 @@ icl_tc_phy_aux_power_well_enable(struct
> > drm_i915_private *dev_priv,
> >  
> >  	hsw_power_well_enable_prepare(dev_priv, power_well);
> >  
> > -	/* TODO ICL TC cold handling */
> > +	if (INTEL_GEN(dev_priv) == 11 && dig_port->tc_legacy_port)
> > +		icl_tc_cold_exit(dev_priv);
> >  
> >  	hsw_power_well_enable_complete(dev_priv, power_well);
> >  
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 5a0adf14ebef..f7506ac40eb4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1400,6 +1400,7 @@ struct intel_digital_port {
> >  	enum intel_display_power_domain ddi_io_power_domain;
> >  	struct mutex tc_lock;	/* protects the TypeC port mode */
> >  	intel_wakeref_t tc_lock_wakeref;
> > +	intel_wakeref_t tc_cold_wakeref;
> 
> Not needed any more.

Ops, thanks

> 
> >  	int tc_link_refcount;
> >  	bool tc_legacy_port:1;
> >  	char tc_port_name[8];
> > diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
> > b/drivers/gpu/drm/i915/display/intel_tc.c
> > index 9b850c11aa78..7564259d677e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_tc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> > @@ -34,6 +34,7 @@ tc_port_load_fia_params(struct drm_i915_private
> > *i915,
> >  	if (INTEL_INFO(i915)->display.has_modular_fia) {
> >  		modular_fia = intel_uncore_read(&i915->uncore,
> >  						PORT_TX_DFLEXDPSP(FIA1)
> > );
> > +		drm_WARN_ON(&i915->drm, modular_fia == 0xffffffff);
> >  		modular_fia &= MODULAR_FIA_MASK;
> >  	} else {
> >  		modular_fia = 0;
> > @@ -52,6 +53,37 @@ tc_port_load_fia_params(struct drm_i915_private
> > *i915,
> >  	}
> >  }
> >  
> > +static intel_wakeref_t
> > +tc_cold_block(struct intel_digital_port *dig_port)
> > +{
> > +	struct drm_i915_private *i915 = to_i915(dig_port-
> > >base.base.dev);
> > +	enum intel_display_power_domain domain;
> > +
> > +	if (INTEL_GEN(i915) != 11 || !dig_port->tc_legacy_port)
> > +		return 0;
> > +
> > +	domain = intel_legacy_aux_to_power_domain(dig_port->aux_ch);
> > +	return intel_display_power_get(i915, domain);
> > +}
> > +
> > +static void
> > +tc_cold_unblock(struct intel_digital_port *dig_port,
> > intel_wakeref_t wakeref)
> > +{
> > +	struct drm_i915_private *i915 = to_i915(dig_port-
> > >base.base.dev);
> > +	enum intel_display_power_domain domain;
> > +
> > +	/*
> > +	 * wakeref == -1, means some error happened saving
> > save_depot_stack but
> > +	 * power should still be put down and 0 is a invalid
> > save_depot_stack
> > +	 * id so can be used to skip it for non TC legacy ports.
> > +	 */
> > +	if (wakeref == 0)
> > +		return;
> > +
> > +	domain = intel_legacy_aux_to_power_domain(dig_port->aux_ch);
> > +	intel_display_power_put_async(i915, domain, wakeref);
> > +}
> > +
> >  u32 intel_tc_port_get_lane_mask(struct intel_digital_port
> > *dig_port)
> >  {
> >  	struct drm_i915_private *i915 = to_i915(dig_port-
> > >base.base.dev);
> > @@ -415,9 +447,14 @@ static void intel_tc_port_reset_mode(struct
> > intel_digital_port *dig_port,
> >  	enum tc_port_mode old_tc_mode = dig_port->tc_mode;
> >  
> >  	intel_display_power_flush_work(i915);
> > -	drm_WARN_ON(&i915->drm,
> > -		    intel_display_power_is_enabled(i915,
> > -					intel_aux_power_domain(dig_port
> > )));
> > +	if (INTEL_GEN(i915) != 11 || !dig_port->tc_legacy_port) {
> > +		enum intel_display_power_domain aux_domain;
> > +		bool aux_powered;
> > +
> > +		aux_domain = intel_aux_power_domain(dig_port);
> > +		aux_powered = intel_display_power_is_enabled(i915,
> > aux_domain);
> > +		drm_WARN_ON(&i915->drm, aux_powered);
> > +	}
> >  
> >  	icl_tc_phy_disconnect(dig_port);
> >  	icl_tc_phy_connect(dig_port, required_lanes);
> > @@ -439,9 +476,11 @@ intel_tc_port_link_init_refcount(struct
> > intel_digital_port *dig_port,
> >  void intel_tc_port_sanitize(struct intel_digital_port *dig_port)
> >  {
> >  	struct intel_encoder *encoder = &dig_port->base;
> > +	intel_wakeref_t tc_cold_wref;
> >  	int active_links = 0;
> >  
> >  	mutex_lock(&dig_port->tc_lock);
> > +	tc_cold_wref = tc_cold_block(dig_port);
> >  
> >  	dig_port->tc_mode = intel_tc_port_get_current_mode(dig_port);
> >  	if (dig_port->dp.is_mst)
> > @@ -466,6 +505,7 @@ void intel_tc_port_sanitize(struct
> > intel_digital_port *dig_port)
> >  		      dig_port->tc_port_name,
> >  		      tc_port_mode_name(dig_port->tc_mode));
> >  
> > +	tc_cold_unblock(dig_port, tc_cold_wref);
> >  	mutex_unlock(&dig_port->tc_lock);
> >  }
> >  
> > @@ -487,10 +527,15 @@ static bool intel_tc_port_needs_reset(struct
> > intel_digital_port *dig_port)
> >  bool intel_tc_port_connected(struct intel_digital_port *dig_port)
> >  {
> >  	bool is_connected;
> > +	intel_wakeref_t tc_cold_wref;
> >  
> >  	intel_tc_port_lock(dig_port);
> > +	tc_cold_wref = tc_cold_block(dig_port);
> > +
> >  	is_connected = tc_port_live_status_mask(dig_port) &
> >  		       BIT(dig_port->tc_mode);
> > +
> > +	tc_cold_unblock(dig_port, tc_cold_wref);
> >  	intel_tc_port_unlock(dig_port);
> >  
> >  	return is_connected;
> > @@ -500,15 +545,20 @@ static void __intel_tc_port_lock(struct
> > intel_digital_port *dig_port,
> >  				 int required_lanes)
> >  {
> >  	struct drm_i915_private *i915 = to_i915(dig_port-
> > >base.base.dev);
> > -	intel_wakeref_t wakeref;
> > +	intel_wakeref_t wakeref, tc_cold_wref;
> 
> Could be moved into its scope.

Done

> 
> >  
> >  	wakeref = intel_display_power_get(i915,
> > POWER_DOMAIN_DISPLAY_CORE);
> >  
> >  	mutex_lock(&dig_port->tc_lock);
> >  
> > -	if (!dig_port->tc_link_refcount &&
> > -	    intel_tc_port_needs_reset(dig_port))
> > -		intel_tc_port_reset_mode(dig_port, required_lanes);
> > +	if (!dig_port->tc_link_refcount) {
> > +		tc_cold_wref = tc_cold_block(dig_port);
> > +
> > +		if (intel_tc_port_needs_reset(dig_port))
> > +			intel_tc_port_reset_mode(dig_port,
> > required_lanes);
> > +
> > +		tc_cold_unblock(dig_port, tc_cold_wref);
> > +	}
> >  
> >  	drm_WARN_ON(&i915->drm, dig_port->tc_lock_wakeref);
> >  	dig_port->tc_lock_wakeref = wakeref;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 8cebb7a86b8c..5cbcd01ac3d5 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -9107,6 +9107,7 @@ enum {
> >  #define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)	(((poin
> > t) << 16) | (0x1 << 8))
> >  #define   GEN6_PCODE_READ_D_COMP		0x10
> >  #define   GEN6_PCODE_WRITE_D_COMP		0x11
> > +#define   ICL_PCODE_EXIT_TCCOLD			0x12
> >  #define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
> >  #define   DISPLAY_IPS_CONTROL			0x19
> >              /* See also IPS_CTL */
> > -- 
> > 2.26.0
> > 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [Intel-gfx] [PATCH v2 6/8] drm/i915/tc/tgl: Implement TC cold sequences
  2020-04-07 16:02   ` Imre Deak
@ 2020-04-07 21:20     ` Souza, Jose
  0 siblings, 0 replies; 25+ messages in thread
From: Souza, Jose @ 2020-04-07 21:20 UTC (permalink / raw)
  To: Deak, Imre; +Cc: Chiou, Cooper, intel-gfx, kai.heng.feng

On Tue, 2020-04-07 at 19:02 +0300, Imre Deak wrote:
> On Mon, Apr 06, 2020 at 06:11:55PM -0700, José Roberto de Souza
> wrote:
> > TC ports can enter in TCCOLD to save power and is required to
> > request
> > to PCODE to exit this state before use or read to TC registers.
> > 
> > For TGL there is a new MBOX command to do that with a parameter to
> > ask
> > PCODE to exit and block TCCOLD entry or unblock TCCOLD entry.
> > 
> > So adding a new power domain to reuse the refcount and only allow
> > TC cold when all TC ports are not in use.
> > 
> > v2:
> > - fixed missing case in intel_display_power_domain_str()
> > - moved tgl_tc_cold_request to intel_display_power.c
> > - renamed TGL_TC_COLD_OFF to TGL_TC_COLD_OFF_POWER_DOMAINS
> > - added all TC and TBT aux power domains to
> > TGL_TC_COLD_OFF_POWER_DOMAINS
> > 
> > BSpec: 49294
> > Cc: Imre Deak <imre.deak@intel.com>
> > Cc: Cooper Chiou <cooper.chiou@intel.com>
> > Cc: Kai-Heng Feng <kai.heng.feng@canonical.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >  .../drm/i915/display/intel_display_power.c    | 98
> > +++++++++++++++++++
> >  .../drm/i915/display/intel_display_power.h    |  1 +
> >  drivers/gpu/drm/i915/display/intel_tc.c       | 17 +++-
> >  drivers/gpu/drm/i915/i915_reg.h               |  3 +
> >  4 files changed, 116 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 0383801a9acc..5d33929f3724 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -151,6 +151,8 @@ intel_display_power_domain_str(enum
> > intel_display_power_domain domain)
> >  		return "GT_IRQ";
> >  	case POWER_DOMAIN_DPLL_DC_OFF:
> >  		return "DPLL_DC_OFF";
> > +	case POWER_DOMAIN_TC_COLD_OFF:
> > +		return "TC_COLD_OFF";
> >  	default:
> >  		MISSING_CASE(domain);
> >  		return "?";
> > @@ -2858,6 +2860,21 @@ void intel_display_power_put(struct
> > drm_i915_private *dev_priv,
> >  #define TGL_AUX_I_TBT6_IO_POWER_DOMAINS (	\
> >  	BIT_ULL(POWER_DOMAIN_AUX_I_TBT))
> >  
> > +#define TGL_TC_COLD_OFF_POWER_DOMAINS (		\
> > +	BIT_ULL(POWER_DOMAIN_AUX_D)	|	\
> > +	BIT_ULL(POWER_DOMAIN_AUX_E)	|	\
> > +	BIT_ULL(POWER_DOMAIN_AUX_F)	|	\
> > +	BIT_ULL(POWER_DOMAIN_AUX_G)	|	\
> > +	BIT_ULL(POWER_DOMAIN_AUX_H)	|	\
> > +	BIT_ULL(POWER_DOMAIN_AUX_I)	|	\
> > +	BIT_ULL(POWER_DOMAIN_AUX_D_TBT)	|	\
> > +	BIT_ULL(POWER_DOMAIN_AUX_E_TBT)	|	\
> > +	BIT_ULL(POWER_DOMAIN_AUX_F_TBT)	|	\
> > +	BIT_ULL(POWER_DOMAIN_AUX_G_TBT)	|	\
> > +	BIT_ULL(POWER_DOMAIN_AUX_H_TBT)	|	\
> > +	BIT_ULL(POWER_DOMAIN_AUX_I_TBT)	|	\
> > +	BIT_ULL(POWER_DOMAIN_TC_COLD_OFF))
> > +
> >  static const struct i915_power_well_ops
> > i9xx_always_on_power_well_ops = {
> >  	.sync_hw = i9xx_power_well_sync_hw_noop,
> >  	.enable = i9xx_always_on_power_well_noop,
> > @@ -3960,6 +3977,81 @@ static const struct i915_power_well_desc
> > ehl_power_wells[] = {
> >  	},
> >  };
> >  
> > +static void
> > +tgl_tc_cold_request(struct drm_i915_private *i915, bool block)
> > +{
> > +	u32 low_val, high_val;
> 
> Can be moved to their scope.

Done

> 
> > +	u8 tries = 0;
> > +	int ret;
> > +
> > +	do {
> > +		low_val = 0;
> > +		high_val = block ? 0 :
> > TGL_PCODE_EXIT_TCCOLD_DATA_H_UNBLOCK_REQ;
> > +
> > +		/*
> > +		 * Spec states that we should timeout the request after
> > 200us
> > +		 * but the function below will timeout after 500us
> > +		 */
> > +		ret = sandybridge_pcode_read(i915, TGL_PCODE_TCCOLD,
> > &low_val,
> > +					     &high_val);
> > +		if (ret == 0) {
> > +			if (block &&
> > +			    (low_val &
> > TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED))
> > +				ret = -EIO;
> > +			else
> > +				break;
> > +		}
> > +
> > +		if (ret != -EAGAIN)
> > +			tries++;
> 
> -EAGAIN means that the PCODE run/busy flag didn't get cleared in the
> previous iteration, and BSpec says to bail out and not to use the
> port
> in that case. But we can't really do that, so let's give some slack
> to
> PUNIT (and CPU), msleep(1) so the next iteration doesn't return
> immediately and still protect against an endless loop?

Done

> 
> > +	} while (tries < 3);
> > +
> > +	drm_dbg_kms(&i915->drm, "TC cold %sblock %s\n", block ? "" :
> > "un",
> > +		    ret == 0 ? "succeeded" : "failed");
> 
> Isn't the fail always a true error? (also on ICL)

Done

> 
> > +}
> > +
> > +static void
> > +tgl_tc_cold_off_power_well_enable(struct drm_i915_private *i915,
> > +				  struct i915_power_well *power_well)
> > +{
> > +	tgl_tc_cold_request(i915, true);
> > +}
> > +
> > +static void
> > +tgl_tc_cold_off_power_well_disable(struct drm_i915_private *i915,
> > +				   struct i915_power_well *power_well)
> > +{
> > +	tgl_tc_cold_request(i915, false);
> > +}
> > +
> > +static void
> > +tgl_tc_cold_off_power_well_sync_hw(struct drm_i915_private *i915,
> > +				   struct i915_power_well *power_well)
> > +{
> > +	if (power_well->count > 0)
> > +		tgl_tc_cold_off_power_well_enable(i915, power_well);
> > +	else
> > +		tgl_tc_cold_off_power_well_disable(i915, power_well);
> > +}
> > +
> > +static bool
> > +tgl_tc_cold_off_power_well_is_enabled(struct drm_i915_private
> > *dev_priv,
> > +				      struct i915_power_well
> > *power_well)
> > +{
> > +	/*
> > +	 * Not the correctly implementation but there is no way to just
> > read it
> > +	 * from PCODE, so returning count to avoid state mismatch
> > errors
> > +	 */
> > +	return power_well->count;
> > +}
> > +
> > +static const struct i915_power_well_ops tgl_tc_cold_off_ops = {
> > +	.sync_hw = tgl_tc_cold_off_power_well_sync_hw,
> > +	.enable = tgl_tc_cold_off_power_well_enable,
> > +	.disable = tgl_tc_cold_off_power_well_disable,
> > +	.is_enabled = tgl_tc_cold_off_power_well_is_enabled,
> > +};
> > +
> >  static const struct i915_power_well_desc tgl_power_wells[] = {
> >  	{
> >  		.name = "always-on",
> > @@ -4287,6 +4379,12 @@ static const struct i915_power_well_desc
> > tgl_power_wells[] = {
> >  			.hsw.irq_pipe_mask = BIT(PIPE_D),
> >  		},
> >  	},
> > +	{
> > +		.name = "TC cold off",
> > +		.domains = TGL_TC_COLD_OFF_POWER_DOMAINS,
> > +		.ops = &tgl_tc_cold_off_ops,
> > +		.id = DISP_PW_ID_NONE,
> > +	},
> >  };
> >  
> >  static int
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
> > b/drivers/gpu/drm/i915/display/intel_display_power.h
> > index da64a5edae7a..070457e7b948 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> > @@ -76,6 +76,7 @@ enum intel_display_power_domain {
> >  	POWER_DOMAIN_MODESET,
> >  	POWER_DOMAIN_GT_IRQ,
> >  	POWER_DOMAIN_DPLL_DC_OFF,
> > +	POWER_DOMAIN_TC_COLD_OFF,
> >  	POWER_DOMAIN_INIT,
> >  
> >  	POWER_DOMAIN_NUM,
> > diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
> > b/drivers/gpu/drm/i915/display/intel_tc.c
> > index 7564259d677e..83861653768d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_tc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> > @@ -53,16 +53,27 @@ tc_port_load_fia_params(struct drm_i915_private
> > *i915,
> >  	}
> >  }
> >  
> > +static enum intel_display_power_domain
> > +tc_cold_get_power_domain(struct intel_digital_port *dig_port)
> > +{
> > +	struct drm_i915_private *i915 = to_i915(dig_port-
> > >base.base.dev);
> > +
> > +	if (INTEL_GEN(i915) == 11)
> > +		return intel_legacy_aux_to_power_domain(dig_port-
> > >aux_ch);
> > +	else
> > +		return POWER_DOMAIN_TC_COLD_OFF;
> > +}
> > +
> >  static intel_wakeref_t
> >  tc_cold_block(struct intel_digital_port *dig_port)
> >  {
> >  	struct drm_i915_private *i915 = to_i915(dig_port-
> > >base.base.dev);
> >  	enum intel_display_power_domain domain;
> >  
> > -	if (INTEL_GEN(i915) != 11 || !dig_port->tc_legacy_port)
> > +	if (INTEL_GEN(i915) == 11 && !dig_port->tc_legacy_port)
> >  		return 0;
> >  
> > -	domain = intel_legacy_aux_to_power_domain(dig_port->aux_ch);
> > +	domain = tc_cold_get_power_domain(dig_port);
> >  	return intel_display_power_get(i915, domain);
> >  }
> >  
> > @@ -80,7 +91,7 @@ tc_cold_unblock(struct intel_digital_port
> > *dig_port, intel_wakeref_t wakeref)
> >  	if (wakeref == 0)
> >  		return;
> >  
> > -	domain = intel_legacy_aux_to_power_domain(dig_port->aux_ch);
> > +	domain = tc_cold_get_power_domain(dig_port);
> >  	intel_display_power_put_async(i915, domain, wakeref);
> >  }
> >  
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 5cbcd01ac3d5..e04eec003d4b 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -9110,6 +9110,9 @@ enum {
> >  #define   ICL_PCODE_EXIT_TCCOLD			0x12
> >  #define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
> >  #define   DISPLAY_IPS_CONTROL			0x19
> > +#define   TGL_PCODE_TCCOLD			0x26
> > +#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED   REG_BIT(0)
> > +#define     TGL_PCODE_EXIT_TCCOLD_DATA_H_UNBLOCK_REQ   REG_BIT(0)
> >              /* See also IPS_CTL */
> >  #define     IPS_PCODE_CONTROL			(1 << 30)
> >  #define   HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
> > -- 
> > 2.26.0
> > 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [Intel-gfx] [PATCH v2 4/8] drm/i915/tc/icl: Implement TC cold sequences
  2020-04-07 20:01     ` Souza, Jose
@ 2020-04-07 21:52       ` Imre Deak
  0 siblings, 0 replies; 25+ messages in thread
From: Imre Deak @ 2020-04-07 21:52 UTC (permalink / raw)
  To: Souza, Jose; +Cc: Chiou, Cooper, intel-gfx, kai.heng.feng

On Tue, Apr 07, 2020 at 11:01:14PM +0300, Souza, Jose wrote:
> [...]
> > > +	} while (ret == -EAGAIN);
> > 
> > Let's protect against an endless loop.
> 
> const ktime_t timeout = ktime_add_ms(ktime_get_raw(), 3);
> int ret;
> 
> do {
> 	ret = sandybridge_pcode_write_timeout(i915,
> 					      ICL_PCODE_EXIT_TCCOLD,
> 					      0, 250, 1);
> } while (ret == -EAGAIN && ktime_compare(timeout, ktime_get_raw()) > 0);

Why not just a simple

	trial = 0;
	while (1) {
		ret = pcode_write();
		if (ret != -EAGAIN || ++trial == 3)
			break;
		msleep(1);
	}

with the msleep(1), as if the PCODE run/busy flag didn't get cleared after
the 1ms polling, it probably doesn't make sense to retry in a tight loop.

--Imre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [Intel-gfx]  ✗ Fi.CI.IGT: failure for series starting with [v2,1/8] drm/i915/display: Move out code to return the digital_port of the aux ch
  2020-04-07 10:28 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/8] " Patchwork
@ 2020-04-07 21:56   ` Souza, Jose
  0 siblings, 0 replies; 25+ messages in thread
From: Souza, Jose @ 2020-04-07 21:56 UTC (permalink / raw)
  To: intel-gfx

On Tue, 2020-04-07 at 10:28 +0000, Patchwork wrote:
> == Series Details ==
> 
> Series: series starting with [v2,1/8] drm/i915/display: Move out code
> to return the digital_port of the aux ch
> URL   : https://patchwork.freedesktop.org/series/75576/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_8264_full -> Patchwork_17226_full
> ====================================================
> 
> Summary
> -------
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_17226_full absolutely
> need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the
> changes
>   introduced in Patchwork_17226_full, please notify your bug team to
> allow them
>   to document this new failure mode, which will reduce false
> positives in CI.
> 
>   
> 
> Possible new issues
> -------------------
> 
>   Here are the unknown changes that may have been introduced in
> Patchwork_17226_full:
> 
> ### IGT changes ###
> 
> #### Possible regressions ####
> 
>   * igt@i915_module_load@reload-with-fault-injection:
>     - shard-tglb:         [PASS][1] -> [INCOMPLETE][2]
>    [1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-tglb5/igt@i915_module_load@reload-with-fault-injection.html
>    [2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-tglb3/igt@i915_module_load@reload-with-fault-injection.html
> 

Forgot to fix this one in v3, will do it.

>   
> Known issues
> ------------
> 
>   Here are the changes found in Patchwork_17226_full that come from
> known issues:
> 
> ### IGT changes ###
> 
> #### Issues hit ####
> 
>   * igt@i915_pm_rc6_residency@rc6-idle:
>     - shard-snb:          [PASS][3] -> [FAIL][4] ([i915#1066])
>    [3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-snb1/igt@i915_pm_rc6_residency@rc6-idle.html
>    [4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-snb2/igt@i915_pm_rc6_residency@rc6-idle.html
> 
>   * igt@i915_suspend@sysfs-reader:
>     - shard-apl:          [PASS][5] -> [DMESG-WARN][6] ([i915#180])
>    [5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-apl1/igt@i915_suspend@sysfs-reader.html
>    [6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-apl4/igt@i915_suspend@sysfs-reader.html
> 
>   * igt@kms_cursor_crc@pipe-a-cursor-256x256-sliding:
>     - shard-kbl:          [PASS][7] -> [FAIL][8] ([i915#54] /
> [i915#93] / [i915#95])
>    [7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-256x256-sliding.html
>    [8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-256x256-sliding.html
> 
>   * igt@kms_cursor_crc@pipe-a-cursor-64x21-onscreen:
>     - shard-apl:          [PASS][9] -> [FAIL][10] ([i915#54] /
> [i915#95])
>    [9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-apl3/igt@kms_cursor_crc@pipe-a-cursor-64x21-onscreen.html
>    [10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-apl3/igt@kms_cursor_crc@pipe-a-cursor-64x21-onscreen.html
> 
>   * igt@kms_cursor_crc@pipe-b-cursor-256x85-random:
>     - shard-skl:          [PASS][11] -> [FAIL][12] ([i915#54])
>    [11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-skl4/igt@kms_cursor_crc@pipe-b-cursor-256x85-random.html
>    [12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-skl5/igt@kms_cursor_crc@pipe-b-cursor-256x85-random.html
> 
>   * igt@kms_cursor_crc@pipe-c-cursor-suspend:
>     - shard-kbl:          [PASS][13] -> [DMESG-WARN][14] ([i915#180])
> +3 similar issues
>    [13]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-kbl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
>    [14]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
> 
>   * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
>     - shard-glk:          [PASS][15] -> [FAIL][16] ([i915#72])
>    [15]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-glk2/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
>    [16]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-glk1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
> 
>   * igt@kms_flip@flip-vs-absolute-wf_vblank:
>     - shard-kbl:          [PASS][17] -> [FAIL][18] ([i915#34])
>    [17]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-kbl6/igt@kms_flip@flip-vs-absolute-wf_vblank.html
>    [18]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-kbl7/igt@kms_flip@flip-vs-absolute-wf_vblank.html
> 
>   * igt@kms_flip@flip-vs-panning-interruptible:
>     - shard-hsw:          [PASS][19] -> [INCOMPLETE][20] ([i915#61])
>    [19]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-hsw8/igt@kms_flip@flip-vs-panning-interruptible.html
>    [20]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-hsw1/igt@kms_flip@flip-vs-panning-interruptible.html
> 
>   * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
>     - shard-iclb:         [PASS][21] -> [INCOMPLETE][22] ([i915#1185]
> / [i915#250])
>    [21]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-iclb4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
>    [22]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-iclb3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
> 
>   * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
>     - shard-skl:          [PASS][23] -> [FAIL][24] ([fdo#108145] /
> [i915#265]) +1 similar issue
>    [23]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
>    [24]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
> 
>   * igt@kms_psr@psr2_cursor_mmap_cpu:
>     - shard-iclb:         [PASS][25] -> [SKIP][26] ([fdo#109441]) +1
> similar issue
>    [25]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
>    [26]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-iclb8/igt@kms_psr@psr2_cursor_mmap_cpu.html
> 
>   
> #### Possible fixes ####
> 
>   * {igt@gem_ctx_isolation@preservation-s3@rcs0}:
>     - shard-apl:          [DMESG-WARN][27] ([i915#180]) -> [PASS][28]
> +4 similar issues
>    [27]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-apl6/igt@gem_ctx_isolation@preservation-s3@rcs0.html
>    [28]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-apl1/igt@gem_ctx_isolation@preservation-s3@rcs0.html
> 
>   * igt@gem_exec_balancer@hang:
>     - shard-tglb:         [FAIL][29] ([i915#1277]) -> [PASS][30]
>    [29]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-tglb6/igt@gem_exec_balancer@hang.html
>    [30]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-tglb2/igt@gem_exec_balancer@hang.html
> 
>   * igt@i915_pm_rc6_residency@rc6-idle:
>     - shard-hsw:          [FAIL][31] ([i915#1516]) -> [PASS][32]
>    [31]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-hsw1/igt@i915_pm_rc6_residency@rc6-idle.html
>    [32]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-hsw8/igt@i915_pm_rc6_residency@rc6-idle.html
> 
>   * igt@i915_pm_rpm@basic-pci-d3-state:
>     - shard-skl:          [FAIL][33] ([i915#138]) -> [PASS][34]
>    [33]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-skl5/igt@i915_pm_rpm@basic-pci-d3-state.html
>    [34]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-skl8/igt@i915_pm_rpm@basic-pci-d3-state.html
> 
>   * igt@i915_selftest@live@blt:
>     - shard-snb:          [DMESG-FAIL][35] ([i915#1409]) ->
> [PASS][36]
>    [35]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-snb4/igt@i915_selftest@live@blt.html
>    [36]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-snb5/igt@i915_selftest@live@blt.html
> 
>   * igt@i915_suspend@debugfs-reader:
>     - shard-kbl:          [DMESG-WARN][37] ([i915#180]) -> [PASS][38]
> +1 similar issue
>    [37]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-kbl2/igt@i915_suspend@debugfs-reader.html
>    [38]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-kbl6/igt@i915_suspend@debugfs-reader.html
> 
>   * igt@i915_suspend@fence-restore-tiled2untiled:
>     - shard-skl:          [INCOMPLETE][39] ([i915#69]) -> [PASS][40]
>    [39]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-skl3/igt@i915_suspend@fence-restore-tiled2untiled.html
>    [40]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-skl6/igt@i915_suspend@fence-restore-tiled2untiled.html
> 
>   * igt@kms_fbcon_fbt@fbc-suspend:
>     - shard-kbl:          [DMESG-WARN][41] ([i915#180] / [i915#93] /
> [i915#95]) -> [PASS][42]
>    [41]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html
>    [42]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-kbl2/igt@kms_fbcon_fbt@fbc-suspend.html
> 
>   * igt@kms_flip@2x-plain-flip-ts-check:
>     - shard-glk:          [FAIL][43] ([i915#34]) -> [PASS][44]
>    [43]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-glk5/igt@kms_flip@2x-plain-flip-ts-check.html
>    [44]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-glk9/igt@kms_flip@2x-plain-flip-ts-check.html
> 
>   * igt@kms_flip@flip-vs-expired-vblank:
>     - shard-apl:          [FAIL][45] ([i915#79]) -> [PASS][46]
>    [45]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-apl4/igt@kms_flip@flip-vs-expired-vblank.html
>    [46]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-apl6/igt@kms_flip@flip-vs-expired-vblank.html
> 
>   * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
>     - shard-snb:          [DMESG-WARN][47] ([i915#42]) -> [PASS][48]
>    [47]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-snb6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
>    [48]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-snb6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
> 
>   * igt@kms_plane_lowres@pipe-a-tiling-none:
>     - shard-kbl:          [DMESG-WARN][49] ([i915#165] / [i915#78])
> -> [PASS][50]
>    [49]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-kbl2/igt@kms_plane_lowres@pipe-a-tiling-none.html
>    [50]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-kbl6/igt@kms_plane_lowres@pipe-a-tiling-none.html
> 
>   * igt@kms_psr@psr2_cursor_plane_onoff:
>     - shard-iclb:         [SKIP][51] ([fdo#109441]) -> [PASS][52]
>    [51]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-iclb1/igt@kms_psr@psr2_cursor_plane_onoff.html
>    [52]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html
> 
>   * {igt@perf@blocking-parameterized}:
>     - shard-hsw:          [FAIL][53] ([i915#1542]) -> [PASS][54]
>    [53]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8264/shard-hsw6/igt@perf@blocking-parameterized.html
>    [54]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/shard-hsw4/igt@perf@blocking-parameterized.html
> 
>   
>   {name}: This element is suppressed. This means it is ignored when
> computing
>           the status of the difference (SUCCESS, WARNING, or
> FAILURE).
> 
>   [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
>   [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
>   [i915#1066]: https://gitlab.freedesktop.org/drm/intel/issues/1066
>   [i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185
>   [i915#1277]: https://gitlab.freedesktop.org/drm/intel/issues/1277
>   [i915#138]: https://gitlab.freedesktop.org/drm/intel/issues/138
>   [i915#1409]: https://gitlab.freedesktop.org/drm/intel/issues/1409
>   [i915#1516]: https://gitlab.freedesktop.org/drm/intel/issues/1516
>   [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
>   [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
>   [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
>   [i915#250]: https://gitlab.freedesktop.org/drm/intel/issues/250
>   [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
>   [i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
>   [i915#42]: https://gitlab.freedesktop.org/drm/intel/issues/42
>   [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
>   [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
>   [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
>   [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
>   [i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78
>   [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
>   [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
>   [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
> 
> 
> Participating hosts (10 -> 10)
> ------------------------------
> 
>   No changes in participating hosts
> 
> 
> Build changes
> -------------
> 
>   * CI: CI-20190529 -> None
>   * Linux: CI_DRM_8264 -> Patchwork_17226
> 
>   CI-20190529: 20190529
>   CI_DRM_8264: e0104585f880a64d4a9b40803cf4fb51ab499f7c @
> git://anongit.freedesktop.org/gfx-ci/linux
>   IGT_5573: 9c582425d6b4fc1de9fc2ffc8015cc6f0a0d3e98 @
> git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
>   Patchwork_17226: ba04f3ced69643939779e78860b0d7054875c784 @
> git://anongit.freedesktop.org/gfx-ci/linux
>   piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
> git://anongit.freedesktop.org/piglit
> 
> == Logs ==
> 
> For more details see: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17226/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

end of thread, other threads:[~2020-04-07 21:56 UTC | newest]

Thread overview: 25+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-04-07  1:11 [Intel-gfx] [PATCH v2 1/8] drm/i915/display: Move out code to return the digital_port of the aux ch José Roberto de Souza
2020-04-07  1:11 ` [Intel-gfx] [PATCH v2 2/8] drm/i915/display: Add intel_legacy_aux_to_power_domain() José Roberto de Souza
2020-04-07 15:15   ` Imre Deak
2020-04-07  1:11 ` [Intel-gfx] [PATCH v2 3/8] drm/i915/display: Split hsw_power_well_enable() into two José Roberto de Souza
2020-04-07 15:20   ` Imre Deak
2020-04-07  1:11 ` [Intel-gfx] [PATCH v2 4/8] drm/i915/tc/icl: Implement TC cold sequences José Roberto de Souza
2020-04-07 15:42   ` Imre Deak
2020-04-07 20:01     ` Souza, Jose
2020-04-07 21:52       ` Imre Deak
2020-04-07  1:11 ` [Intel-gfx] [PATCH v2 5/8] drm/i915/tc: Skip ref held check for TC legacy aux power wells José Roberto de Souza
2020-04-07 15:42   ` Imre Deak
2020-04-07  1:11 ` [Intel-gfx] [PATCH v2 6/8] drm/i915/tc/tgl: Implement TC cold sequences José Roberto de Souza
2020-04-07 16:02   ` Imre Deak
2020-04-07 21:20     ` Souza, Jose
2020-04-07  1:11 ` [Intel-gfx] [PATCH v2 7/8] drm/i915/tc: Catch TC users accessing FIA registers without enable aux José Roberto de Souza
2020-04-07 16:04   ` Imre Deak
2020-04-07 18:20     ` Imre Deak
2020-04-07  1:11 ` [Intel-gfx] [PATCH v2 8/8] drm/i915/tc: Do not warn when aux power well of static TC ports timeout José Roberto de Souza
2020-04-07 16:18   ` Imre Deak
2020-04-07  1:26 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/8] drm/i915/display: Move out code to return the digital_port of the aux ch Patchwork
2020-04-07  1:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-04-07  7:35 ` [Intel-gfx] [v2, 1/8] " You-Sheng Yang
2020-04-07 10:28 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/8] " Patchwork
2020-04-07 21:56   ` Souza, Jose
2020-04-07 15:13 ` [Intel-gfx] [PATCH v2 1/8] " Imre Deak

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