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From: Babu Moger <1856335@bugs.launchpad.net>
To: qemu-devel@nongnu.org
Subject: [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs
Date: Mon, 20 Apr 2020 22:58:26 -0000	[thread overview]
Message-ID: <158742350692.19878.6882586493225306144.malone@gac.canonical.com> (raw)
In-Reply-To: 157625616239.22064.10423897892496347105.malonedeb@gac.canonical.com

Damir, Example of how to use numa configuration.
-smp 16,maxcpus=16,cores=16,threads=1,sockets=1 -numa node,nodeid=0,cpus=0-7 -numa node,nodeid=1,cpus=8-15

This will help to put all the cores in correct L3 boundary. I strongly
suggest to use the latest qemu release.

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https://bugs.launchpad.net/bugs/1856335

Title:
  Cache Layout wrong on many Zen Arch CPUs

Status in QEMU:
  New

Bug description:
  AMD CPUs have L3 cache per 2, 3 or 4 cores. Currently, TOPOEXT seems
  to always map Cache ass if it was an 4-Core per CCX CPU, which is
  incorrect, and costs upwards 30% performance (more realistically 10%)
  in L3 Cache Layout aware applications.

  Example on a 4-CCX CPU (1950X /w 8 Cores and no SMT):

    <cpu mode='custom' match='exact' check='full'>
      <model fallback='forbid'>EPYC-IBPB</model>
      <vendor>AMD</vendor>
      <topology sockets='1' cores='8' threads='1'/>

  In windows, coreinfo reports correctly:

  ****----  Unified Cache 1, Level 3,    8 MB, Assoc  16, LineSize  64
  ----****  Unified Cache 6, Level 3,    8 MB, Assoc  16, LineSize  64

  On a 3-CCX CPU (3960X /w 6 cores and no SMT):

   <cpu mode='custom' match='exact' check='full'>
      <model fallback='forbid'>EPYC-IBPB</model>
      <vendor>AMD</vendor>
      <topology sockets='1' cores='6' threads='1'/>

  in windows, coreinfo reports incorrectly:

  ****--  Unified Cache  1, Level 3,    8 MB, Assoc  16, LineSize  64
  ----**  Unified Cache  6, Level 3,    8 MB, Assoc  16, LineSize  64

  Validated against 3.0, 3.1, 4.1 and 4.2 versions of qemu-kvm.

  With newer Qemu there is a fix (that does behave correctly) in using the dies parameter:
   <qemu:arg value='cores=3,threads=1,dies=2,sockets=1'/>

  The problem is that the dies are exposed differently than how AMD does
  it natively, they are exposed to Windows as sockets, which means, that
  if you are nto a business user, you can't ever have a machine with
  more than two CCX (6 cores) as consumer versions of Windows only
  supports two sockets. (Should this be reported as a separate bug?)

To manage notifications about this bug go to:
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  parent reply	other threads:[~2020-04-20 23:11 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-13 16:56 [Bug 1856335] [NEW] Cache Layout wrong on many Zen Arch CPUs Damir
2019-12-16 10:06 ` [Bug 1856335] " Damir
2019-12-22 10:09 ` Damir
2019-12-22 10:10 ` Damir
2019-12-23 15:41 ` Babu Moger
2020-04-15 20:46 ` Heiko Sieger
2020-04-15 21:34 ` Babu Moger
2020-04-20 22:58 ` Babu Moger [this message]
2020-04-26 10:43 ` Heiko Sieger
2020-05-03 18:32 ` Heiko Sieger
2020-05-03 18:38 ` Heiko Sieger
2020-05-05 22:18 ` Babu Moger
2020-05-07 12:06 ` Heiko Sieger
2020-05-07 14:38 ` Babu Moger
2020-05-10 17:47 ` Damir
2020-05-10 20:01 ` Heiko Sieger
2020-05-14 23:31 ` Jan Klos
2020-05-15  2:41 ` Jan Klos
2020-05-15 13:04 ` Jan Klos
2020-05-15 13:41 ` Damir
2020-05-15 17:34 ` Babu Moger
2020-05-17 11:15 ` Jan Klos
2020-05-17 11:25 ` Jan Klos
2020-05-18 17:32 ` Heiko Sieger
2020-05-18 18:21 ` Babu Moger
2020-05-18 19:19 ` Heiko Sieger
2020-05-19  9:34 ` Jan Klos
2020-05-19 20:35 ` Heiko Sieger
2020-05-20 21:47 ` Heiko Sieger
2020-05-20 23:28 ` Heiko Sieger
2020-05-21 12:45 ` Jan Klos
2020-05-24 10:34 ` Heiko Sieger
2020-05-29  6:31 ` Heiko Sieger
2020-06-12  8:53 ` Jan Klos
2020-07-10 14:41 ` Heiko Sieger
2020-07-10 19:54 ` Jan Klos
2020-07-26 15:11 ` Sanjay Basu
2020-07-26 17:30 ` Heiko Sieger
2020-07-26 22:20 ` Sanjay Basu
2020-07-29  2:23 ` Heiko Sieger
2021-05-02 18:14 ` Thomas Huth
2021-07-02  4:17 ` Launchpad Bug Tracker

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