From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=0.3 required=3.0 tests=DATE_IN_PAST_03_06, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83F80C54FCB for ; Sun, 26 Apr 2020 15:05:26 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 550FE206D4 for ; Sun, 26 Apr 2020 15:05:26 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 550FE206D4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bugs.launchpad.net Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:32874 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jSiqT-0001BA-BI for qemu-devel@archiver.kernel.org; Sun, 26 Apr 2020 11:05:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34034) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jSipg-0000cA-Bz for qemu-devel@nongnu.org; Sun, 26 Apr 2020 11:04:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jSipe-0006fv-Ad for qemu-devel@nongnu.org; Sun, 26 Apr 2020 11:04:36 -0400 Received: from indium.canonical.com ([91.189.90.7]:52830) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jSipd-0006fo-Sv for qemu-devel@nongnu.org; Sun, 26 Apr 2020 11:04:34 -0400 Received: from loganberry.canonical.com ([91.189.90.37]) by indium.canonical.com with esmtp (Exim 4.86_2 #2 (Debian)) id 1jSipX-0004xb-AC for ; Sun, 26 Apr 2020 15:04:27 +0000 Received: from loganberry.canonical.com (localhost [127.0.0.1]) by loganberry.canonical.com (Postfix) with ESMTP id 2AB8C2E8134 for ; Sun, 26 Apr 2020 15:03:30 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Date: Sun, 26 Apr 2020 10:43:45 -0000 From: Heiko Sieger <1856335@bugs.launchpad.net> To: qemu-devel@nongnu.org X-Launchpad-Notification-Type: bug X-Launchpad-Bug: product=qemu; status=New; importance=Undecided; assignee=None; X-Launchpad-Bug-Information-Type: Public X-Launchpad-Bug-Private: no X-Launchpad-Bug-Security-Vulnerability: no X-Launchpad-Bug-Commenters: babumoger djdatte h-sieger X-Launchpad-Bug-Reporter: Damir (djdatte) X-Launchpad-Bug-Modifier: Heiko Sieger (h-sieger) References: <157625616239.22064.10423897892496347105.malonedeb@gac.canonical.com> Message-Id: <158789782516.9219.12650443072841154748.malone@gac.canonical.com> Subject: [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs X-Launchpad-Message-Rationale: Subscriber (QEMU) @qemu-devel-ml X-Launchpad-Message-For: qemu-devel-ml Precedence: bulk X-Generated-By: Launchpad (canonical.com); Revision="486bbbd6cb608f8eb468ed0d08689a349dfabe49"; Instance="production-secrets-lazr.conf" X-Launchpad-Hash: e24542c9f664d2d7ec6b23fded907c71ec062403 Received-SPF: none client-ip=91.189.90.7; envelope-from=bounces@canonical.com; helo=indium.canonical.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/26 11:04:31 X-ACL-Warn: Detected OS = Linux 3.11 and newer X-Received-From: 91.189.90.7 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Bug 1856335 <1856335@bugs.launchpad.net> Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" It could be an issue of how the kernel presents the CPU topology. Hardware: AMD Ryzen 3900X 12 core 24 threads (SMT) Host: Kernel 5.6.6, QEMU 4.2 virsh capabilities | grep "cpu id" See how cpu id=3D3 gets core id=3D4, and cpu id=3D6 gets core id=3D8, etc. cat /sys/devices/system/cpu/cpu2/topology/core_id 2 cat /sys/devices/system/cpu/cpu3/topology/core_id 4 However, the association of CPU IDs to L3 caches seems to be correct: echo "Level CPU list";for file in /sys/devices/system/cpu/cpu*/cache/index= 3; do echo $(cat $file/id) " " $(cat $file/shared_cpu_list); done | sort= --version-sort Level CPU list 0 0-2,12-14 0 0-2,12-14 0 0-2,12-14 0 0-2,12-14 0 0-2,12-14 0 0-2,12-14 1 3-5,15-17 1 3-5,15-17 1 3-5,15-17 1 3-5,15-17 1 3-5,15-17 1 3-5,15-17 2 6-8,18-20 2 6-8,18-20 2 6-8,18-20 2 6-8,18-20 2 6-8,18-20 2 6-8,18-20 3 9-11,21-23 3 9-11,21-23 3 9-11,21-23 3 9-11,21-23 3 9-11,21-23 3 9-11,21-23 There are 4 L3 caches with the correct CPU lists (6 CPUs/threads each). Is it possible that this weird CPU ID enumeration is causing the confusion? Haven't had a chance to check out QEMU 5.0, but hope to do that today. -- = You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1856335 Title: Cache Layout wrong on many Zen Arch CPUs Status in QEMU: New Bug description: AMD CPUs have L3 cache per 2, 3 or 4 cores. Currently, TOPOEXT seems to always map Cache ass if it was an 4-Core per CCX CPU, which is incorrect, and costs upwards 30% performance (more realistically 10%) in L3 Cache Layout aware applications. Example on a 4-CCX CPU (1950X /w 8 Cores and no SMT): =C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0EPYC-IBPB =C2=A0=C2=A0=C2=A0=C2=A0AMD =C2=A0=C2=A0=C2=A0=C2=A0 In windows, coreinfo reports correctly: ****---- Unified Cache 1, Level 3, 8 MB, Assoc 16, LineSize 64 ----**** Unified Cache 6, Level 3, 8 MB, Assoc 16, LineSize 64 On a 3-CCX CPU (3960X /w 6 cores and no SMT): =C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0EPYC-IBPB =C2=A0=C2=A0=C2=A0=C2=A0AMD =C2=A0=C2=A0=C2=A0=C2=A0 in windows, coreinfo reports incorrectly: ****-- Unified Cache 1, Level 3, 8 MB, Assoc 16, LineSize 64 ----** Unified Cache 6, Level 3, 8 MB, Assoc 16, LineSize 64 Validated against 3.0, 3.1, 4.1 and 4.2 versions of qemu-kvm. With newer Qemu there is a fix (that does behave correctly) in using the = dies parameter: =C2=A0 The problem is that the dies are exposed differently than how AMD does it natively, they are exposed to Windows as sockets, which means, that if you are nto a business user, you can't ever have a machine with more than two CCX (6 cores) as consumer versions of Windows only supports two sockets. (Should this be reported as a separate bug?) To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1856335/+subscriptions