[PATCH v2 0/1] target/arm: Remove access_el3_aa32ns()

[PATCH v2 0/1] target/arm: Remove access_el3_aa32ns()

[Edgar E. Iglesias]

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Hi,

Laurent reported hitting the assert in access_el3_aa32ns()
when accessing 32-bit versions of some of the virtualization
regs when EL3 is 64-bit.

I think we got this wrong back then and it seems to me like
we should remove direct usage of access_el3_aa32ns() and
always call access_el3_aa32ns_aa64_any() to handle both
the aa32-only cases and the mixed aa32/aa64.

Cheers,
Edgar

ChangeLog:

v1 -> v2:
* Keep access_el3_aa32ns in favor of access_el3_aa32ns_aa64any
* Simplify description of access_el3_aa32ns
* Tweak secure aa32-el3 check in access_el3_aa32ns as suggested by Peter


Edgar E. Iglesias (1):
  target/arm: Drop access_el3_aa32ns()

 target/arm/helper.c | 30 +++++++-----------------------
 1 file changed, 7 insertions(+), 23 deletions(-)

-- 
2.20.1

[PATCH v2 1/1] target/arm: Drop access_el3_aa32ns()

[Edgar E. Iglesias]

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Calling access_el3_aa32ns() works for AArch32 only cores
but it does not handle 32-bit EL2 on top of 64-bit EL3
for mixed 32/64-bit cores.

Merge access_el3_aa32ns_aa64any() into access_el3_aa32ns()
and only use the latter.

Fixes: 68e9c2fe65 ("target-arm: Add VTCR_EL2")
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/arm/helper.c | 30 +++++++-----------------------
 1 file changed, 7 insertions(+), 23 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index dfefb9b3d9..7d21bf1cc7 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -502,35 +502,19 @@ void init_cpreg_list(ARMCPU *cpu)
 }
 
 /*
- * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
- * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
- *
- * access_el3_aa32ns: Used to check AArch32 register views.
- * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
+ * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0.
  */
 static CPAccessResult access_el3_aa32ns(CPUARMState *env,
                                         const ARMCPRegInfo *ri,
                                         bool isread)
 {
-    bool secure = arm_is_secure_below_el3(env);
-
-    assert(!arm_el_is_aa64(env, 3));
-    if (secure) {
+    if (!is_a64(env) && arm_current_el(env) == 3 &&
+        arm_is_secure_below_el3(env)) {
         return CP_ACCESS_TRAP_UNCATEGORIZED;
     }
     return CP_ACCESS_OK;
 }
 
-static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env,
-                                                const ARMCPRegInfo *ri,
-                                                bool isread)
-{
-    if (!arm_el_is_aa64(env, 3)) {
-        return access_el3_aa32ns(env, ri, isread);
-    }
-    return CP_ACCESS_OK;
-}
-
 /* Some secure-only AArch32 registers trap to EL3 if used from
  * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
  * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
@@ -5236,7 +5220,7 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
-      .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
+      .access = PL2_RW, .accessfn = access_el3_aa32ns,
       .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
       .cp = 15, .opc1 = 6, .crm = 2,
@@ -5284,7 +5268,7 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
       .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
-      .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
+      .access = PL2_RW, .accessfn = access_el3_aa32ns,
       .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
@@ -7626,12 +7610,12 @@ void register_cp_regs_for_features(ARMCPU *cpu)
             ARMCPRegInfo vpidr_regs[] = {
                 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
                   .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
-                  .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
+                  .access = PL2_RW, .accessfn = access_el3_aa32ns,
                   .type = ARM_CP_CONST, .resetvalue = cpu->midr,
                   .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
                 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
                   .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
-                  .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
+                  .access = PL2_RW, .accessfn = access_el3_aa32ns,
                   .type = ARM_CP_NO_RAW,
                   .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
                 REGINFO_SENTINEL
-- 
2.20.1

Re: [PATCH v2 1/1] target/arm: Drop access_el3_aa32ns()

[Edgar E. Iglesias]

On Mon, May 04, 2020 at 04:21:25PM +0200, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> 
> Calling access_el3_aa32ns() works for AArch32 only cores
> but it does not handle 32-bit EL2 on top of 64-bit EL3
> for mixed 32/64-bit cores.
> 
> Merge access_el3_aa32ns_aa64any() into access_el3_aa32ns()
> and only use the latter.


Forgot to update the Subject/Summary to reflect that
access_el3_aa32ns_aa64any() is now being removed.

Will fix in v3...




> 
> Fixes: 68e9c2fe65 ("target-arm: Add VTCR_EL2")
> Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
>  target/arm/helper.c | 30 +++++++-----------------------
>  1 file changed, 7 insertions(+), 23 deletions(-)
> 
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index dfefb9b3d9..7d21bf1cc7 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -502,35 +502,19 @@ void init_cpreg_list(ARMCPU *cpu)
>  }
>  
>  /*
> - * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
> - * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
> - *
> - * access_el3_aa32ns: Used to check AArch32 register views.
> - * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
> + * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0.
>   */
>  static CPAccessResult access_el3_aa32ns(CPUARMState *env,
>                                          const ARMCPRegInfo *ri,
>                                          bool isread)
>  {
> -    bool secure = arm_is_secure_below_el3(env);
> -
> -    assert(!arm_el_is_aa64(env, 3));
> -    if (secure) {
> +    if (!is_a64(env) && arm_current_el(env) == 3 &&
> +        arm_is_secure_below_el3(env)) {
>          return CP_ACCESS_TRAP_UNCATEGORIZED;
>      }
>      return CP_ACCESS_OK;
>  }
>  
> -static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env,
> -                                                const ARMCPRegInfo *ri,
> -                                                bool isread)
> -{
> -    if (!arm_el_is_aa64(env, 3)) {
> -        return access_el3_aa32ns(env, ri, isread);
> -    }
> -    return CP_ACCESS_OK;
> -}
> -
>  /* Some secure-only AArch32 registers trap to EL3 if used from
>   * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
>   * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
> @@ -5236,7 +5220,7 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
>        .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
>      { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
>        .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
> -      .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
> +      .access = PL2_RW, .accessfn = access_el3_aa32ns,
>        .type = ARM_CP_CONST, .resetvalue = 0 },
>      { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
>        .cp = 15, .opc1 = 6, .crm = 2,
> @@ -5284,7 +5268,7 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
>        .type = ARM_CP_CONST, .resetvalue = 0 },
>      { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
>        .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
> -      .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
> +      .access = PL2_RW, .accessfn = access_el3_aa32ns,
>        .type = ARM_CP_CONST, .resetvalue = 0 },
>      { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
>        .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
> @@ -7626,12 +7610,12 @@ void register_cp_regs_for_features(ARMCPU *cpu)
>              ARMCPRegInfo vpidr_regs[] = {
>                  { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
>                    .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
> -                  .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
> +                  .access = PL2_RW, .accessfn = access_el3_aa32ns,
>                    .type = ARM_CP_CONST, .resetvalue = cpu->midr,
>                    .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
>                  { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
>                    .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
> -                  .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
> +                  .access = PL2_RW, .accessfn = access_el3_aa32ns,
>                    .type = ARM_CP_NO_RAW,
>                    .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
>                  REGINFO_SENTINEL
> -- 
> 2.20.1
> 

Re: [PATCH v2 0/1] target/arm: Remove access_el3_aa32ns()

[no-reply]

Patchew URL: https://patchew.org/QEMU/20200504142125.31180-1-edgar.iglesias@gmail.com/



Hi,

This series failed the docker-mingw@fedora build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.

=== TEST SCRIPT BEGIN ===
#! /bin/bash
export ARCH=x86_64
make docker-image-fedora V=1 NETWORK=1
time make docker-test-mingw@fedora J=14 NETWORK=1
=== TEST SCRIPT END ===




The full log is available at
http://patchew.org/logs/20200504142125.31180-1-edgar.iglesias@gmail.com/testing.docker-mingw@fedora/?type=message.
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Re: [PATCH v2 0/1] target/arm: Remove access_el3_aa32ns()

[no-reply]

Patchew URL: https://patchew.org/QEMU/20200504142125.31180-1-edgar.iglesias@gmail.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Message-id: 20200504142125.31180-1-edgar.iglesias@gmail.com
Subject: [PATCH v2 0/1] target/arm: Remove access_el3_aa32ns()
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
fatal: unable to write new index file
warning: Clone succeeded, but checkout failed.
You can inspect what was checked out with 'git status'
and retry the checkout with 'git checkout -f HEAD'

Traceback (most recent call last):
  File "patchew-tester/src/patchew-cli", line 521, in test_one
    git_clone_repo(clone, r["repo"], r["head"], logf, True)
  File "patchew-tester/src/patchew-cli", line 53, in git_clone_repo
    subprocess.check_call(clone_cmd, stderr=logf, stdout=logf)
  File "/opt/rh/rh-python36/root/usr/lib64/python3.6/subprocess.py", line 291, in check_call
    raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['git', 'clone', '-q', '/home/patchew/.cache/patchew-git-cache/httpsgithubcompatchewprojectqemu-3c8cf5a9c21ff8782164d1def7f44bd888713384', '/var/tmp/patchew-tester-tmp-jts7e35j/src']' returned non-zero exit status 128.



The full log is available at
http://patchew.org/logs/20200504142125.31180-1-edgar.iglesias@gmail.com/testing.checkpatch/?type=message.
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