[PATCH RFC 3/8] clk: actions: Add MMC clock-register reset bits

From: Amit Singh Tomar <amittomer25@gmail.com>
To: andre.przywara@arm.com, afaerber@suse.de,
	manivannan.sadhasivam@linaro.org, sboyd@kernel.org
Cc: linux-actions@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org,
	cristian.ciocaltea@gmail.com
Subject: [PATCH RFC 3/8] clk: actions: Add MMC clock-register reset bits
Date: Wed,  6 May 2020 16:06:05 +0530	[thread overview]
Message-ID: <1588761371-9078-4-git-send-email-amittomer25@gmail.com> (raw)
In-Reply-To: <1588761371-9078-1-git-send-email-amittomer25@gmail.com>

This commit adds reset bits needed for MMC clock registers present
on Actions S700 SoC.

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
---
 drivers/clk/actions/owl-s700.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/actions/owl-s700.c b/drivers/clk/actions/owl-s700.c
index a2f34d13fb54..cd60eca7727d 100644
--- a/drivers/clk/actions/owl-s700.c
+++ b/drivers/clk/actions/owl-s700.c
@@ -577,6 +577,9 @@ static const struct owl_reset_map s700_resets[] = {
 	[RESET_DSI]	= { CMU_DEVRST0, BIT(2) },
 	[RESET_CSI]	= { CMU_DEVRST0, BIT(13) },
 	[RESET_SI]	= { CMU_DEVRST0, BIT(14) },
+	[RESET_SD0]     = { CMU_DEVRST0, BIT(22) },
+	[RESET_SD1]     = { CMU_DEVRST0, BIT(23) },
+	[RESET_SD2]     = { CMU_DEVRST0, BIT(24) },
 	[RESET_I2C0]	= { CMU_DEVRST1, BIT(0) },
 	[RESET_I2C1]	= { CMU_DEVRST1, BIT(1) },
 	[RESET_I2C2]	= { CMU_DEVRST1, BIT(2) },
-- 
2.7.4


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