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From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
To: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	"Alistair Francis" <Alistair.Francis@wdc.com>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Jason Wang" <jasowang@redhat.com>,
	"Markus Armbruster" <armbru@redhat.com>,
	"Philippe Mathieu-Daudé" <philmd@redhat.com>,
	"Tong Ho" <tong.ho@xilinx.com>,
	"Ramon Fried" <rfried.dev@gmail.com>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: [PATCH v5 10/12] net: cadence_gem: Update the reset value for interrupt mask register
Date: Tue, 12 May 2020 20:24:52 +0530	[thread overview]
Message-ID: <1589295294-26466-11-git-send-email-sai.pavan.boddu@xilinx.com> (raw)
In-Reply-To: <1589295294-26466-1-git-send-email-sai.pavan.boddu@xilinx.com>

Mask all interrupt on reset.

Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 hw/net/cadence_gem.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 3e7b32f..ddb8938 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -1375,6 +1375,7 @@ static void gem_reset(DeviceState *d)
     s->regs[GEM_DESCONF2] = 0x2ab10000 | s->jumbo_max_len;
     s->regs[GEM_DESCONF5] = 0x002f2045;
     s->regs[GEM_DESCONF6] = GEM_DESCONF6_64B_MASK;
+    s->regs[GEM_INT_Q1_MASK] = 0x00000CE6;
     s->regs[GEM_JUMBO_MAX_LEN] = s->jumbo_max_len;
 
     if (s->num_priority_queues > 1) {
-- 
2.7.4



  parent reply	other threads:[~2020-05-12 15:26 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-12 14:54 [PATCH v5 00/12] Cadence GEM Fixes Sai Pavan Boddu
2020-05-12 14:54 ` [PATCH v5 01/12] net: cadence_gem: Fix debug statements Sai Pavan Boddu
2020-05-12 14:54 ` [PATCH v5 02/12] net: cadence_gem: Fix the queue address update during wrap around Sai Pavan Boddu
2020-05-12 14:54 ` [PATCH v5 03/12] net: cadence_gem: Fix irq update w.r.t queue Sai Pavan Boddu
2020-05-12 14:54 ` [PATCH v5 04/12] net: cadence_gem: Define access permission for interrupt registers Sai Pavan Boddu
2020-05-12 14:54 ` [PATCH v5 05/12] net: cadence_gem: Set ISR according to queue in use Sai Pavan Boddu
2020-05-12 14:54 ` [PATCH v5 06/12] net: cadence_gem: Move tx/rx packet buffert to CadenceGEMState Sai Pavan Boddu
2020-05-12 14:54 ` [PATCH v5 07/12] net: cadence_gem: Fix up code style Sai Pavan Boddu
2020-05-12 15:19   ` Edgar E. Iglesias
2020-05-12 14:54 ` [PATCH v5 08/12] net: cadence_gem: Add support for jumbo frames Sai Pavan Boddu
2020-05-12 15:19   ` Edgar E. Iglesias
2020-05-13  5:15     ` Sai Pavan Boddu
2020-05-12 14:54 ` [PATCH v5 09/12] net: cadnece_gem: Update irq_read_clear field of designcfg_debug1 reg Sai Pavan Boddu
2020-05-12 14:54 ` Sai Pavan Boddu [this message]
2020-05-12 14:54 ` [PATCH v5 11/12] net: cadence_gem: TX_LAST bit should be set by guest Sai Pavan Boddu
2020-05-12 14:54 ` [PATCH v5 12/12] net: cadence_gem: Fix RX address filtering Sai Pavan Boddu
2020-05-14  6:47 ` [PATCH v5 00/12] Cadence GEM Fixes Jason Wang

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