From: Jacob Pan <jacob.jun.pan@linux.intel.com> To: "Lu Baolu" <baolu.lu@linux.intel.com>, iommu@lists.linux-foundation.org, LKML <linux-kernel@vger.kernel.org>, Joerg Roedel <joro@8bytes.org>, David Woodhouse <dwmw2@infradead.org>, Jean-Philippe Brucker <jean-philippe@linaro.com>, Eric Auger <eric.auger@redhat.com> Cc: Yi Liu <yi.l.liu@intel.com>, "Tian, Kevin" <kevin.tian@intel.com>, Raj Ashok <ashok.raj@intel.com>, Alex Williamson <alex.williamson@redhat.com>, "Christoph Hellwig" <hch@infradead.org>, Jonathan Cameron <jic23@kernel.org>, Jacob Pan <jacob.jun.pan@linux.intel.com> Subject: [PATCH v13 2/8] iommu/vt-d: Use a helper function to skip agaw for SL Date: Wed, 13 May 2020 16:01:43 -0700 [thread overview] Message-ID: <1589410909-38925-3-git-send-email-jacob.jun.pan@linux.intel.com> (raw) In-Reply-To: <1589410909-38925-1-git-send-email-jacob.jun.pan@linux.intel.com> An Intel iommu domain uses 5-level page table by default. If the iommu that the domain tries to attach supports less page levels, the top level page tables should be skipped. Add a helper to do this so that it could be used in other places. Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Kevin Tian <kevin.tian@intel.com> --- drivers/iommu/intel-pasid.c | 33 +++++++++++++++++++++++---------- 1 file changed, 23 insertions(+), 10 deletions(-) diff --git a/drivers/iommu/intel-pasid.c b/drivers/iommu/intel-pasid.c index 22b30f10b396..d9cea3011b58 100644 --- a/drivers/iommu/intel-pasid.c +++ b/drivers/iommu/intel-pasid.c @@ -500,6 +500,25 @@ int intel_pasid_setup_first_level(struct intel_iommu *iommu, } /* + * Skip top levels of page tables for iommu which has less agaw + * than default. Unnecessary for PT mode. + */ +static inline int iommu_skip_agaw(struct dmar_domain *domain, + struct intel_iommu *iommu, + struct dma_pte **pgd) +{ + int agaw; + + for (agaw = domain->agaw; agaw > iommu->agaw; agaw--) { + *pgd = phys_to_virt(dma_pte_addr(*pgd)); + if (!dma_pte_present(*pgd)) + return -EINVAL; + } + + return agaw; +} + +/* * Set up the scalable mode pasid entry for second only translation type. */ int intel_pasid_setup_second_level(struct intel_iommu *iommu, @@ -522,17 +541,11 @@ int intel_pasid_setup_second_level(struct intel_iommu *iommu, return -EINVAL; } - /* - * Skip top levels of page tables for iommu which has less agaw - * than default. Unnecessary for PT mode. - */ pgd = domain->pgd; - for (agaw = domain->agaw; agaw > iommu->agaw; agaw--) { - pgd = phys_to_virt(dma_pte_addr(pgd)); - if (!dma_pte_present(pgd)) { - dev_err(dev, "Invalid domain page table\n"); - return -EINVAL; - } + agaw = iommu_skip_agaw(domain, iommu, &pgd); + if (agaw < 0) { + dev_err(dev, "Invalid domain page table\n"); + return -EINVAL; } pgd_val = virt_to_phys(pgd); -- 2.7.4
WARNING: multiple messages have this Message-ID
From: Jacob Pan <jacob.jun.pan@linux.intel.com> To: "Lu Baolu" <baolu.lu@linux.intel.com>, iommu@lists.linux-foundation.org, LKML <linux-kernel@vger.kernel.org>, Joerg Roedel <joro@8bytes.org>, David Woodhouse <dwmw2@infradead.org>, Jean-Philippe Brucker <jean-philippe@linaro.com>, Eric Auger <eric.auger@redhat.com> Cc: "Tian, Kevin" <kevin.tian@intel.com>, Raj Ashok <ashok.raj@intel.com>, Christoph Hellwig <hch@infradead.org>, Alex Williamson <alex.williamson@redhat.com>, Jonathan Cameron <jic23@kernel.org> Subject: [PATCH v13 2/8] iommu/vt-d: Use a helper function to skip agaw for SL Date: Wed, 13 May 2020 16:01:43 -0700 [thread overview] Message-ID: <1589410909-38925-3-git-send-email-jacob.jun.pan@linux.intel.com> (raw) In-Reply-To: <1589410909-38925-1-git-send-email-jacob.jun.pan@linux.intel.com> An Intel iommu domain uses 5-level page table by default. If the iommu that the domain tries to attach supports less page levels, the top level page tables should be skipped. Add a helper to do this so that it could be used in other places. Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Kevin Tian <kevin.tian@intel.com> --- drivers/iommu/intel-pasid.c | 33 +++++++++++++++++++++++---------- 1 file changed, 23 insertions(+), 10 deletions(-) diff --git a/drivers/iommu/intel-pasid.c b/drivers/iommu/intel-pasid.c index 22b30f10b396..d9cea3011b58 100644 --- a/drivers/iommu/intel-pasid.c +++ b/drivers/iommu/intel-pasid.c @@ -500,6 +500,25 @@ int intel_pasid_setup_first_level(struct intel_iommu *iommu, } /* + * Skip top levels of page tables for iommu which has less agaw + * than default. Unnecessary for PT mode. + */ +static inline int iommu_skip_agaw(struct dmar_domain *domain, + struct intel_iommu *iommu, + struct dma_pte **pgd) +{ + int agaw; + + for (agaw = domain->agaw; agaw > iommu->agaw; agaw--) { + *pgd = phys_to_virt(dma_pte_addr(*pgd)); + if (!dma_pte_present(*pgd)) + return -EINVAL; + } + + return agaw; +} + +/* * Set up the scalable mode pasid entry for second only translation type. */ int intel_pasid_setup_second_level(struct intel_iommu *iommu, @@ -522,17 +541,11 @@ int intel_pasid_setup_second_level(struct intel_iommu *iommu, return -EINVAL; } - /* - * Skip top levels of page tables for iommu which has less agaw - * than default. Unnecessary for PT mode. - */ pgd = domain->pgd; - for (agaw = domain->agaw; agaw > iommu->agaw; agaw--) { - pgd = phys_to_virt(dma_pte_addr(pgd)); - if (!dma_pte_present(pgd)) { - dev_err(dev, "Invalid domain page table\n"); - return -EINVAL; - } + agaw = iommu_skip_agaw(domain, iommu, &pgd); + if (agaw < 0) { + dev_err(dev, "Invalid domain page table\n"); + return -EINVAL; } pgd_val = virt_to_phys(pgd); -- 2.7.4 _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
next prev parent reply other threads:[~2020-05-13 22:55 UTC|newest] Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-05-13 23:01 [PATCH v13 0/8] Nested Shared Virtual Address (SVA) VT-d support Jacob Pan 2020-05-13 23:01 ` Jacob Pan 2020-05-13 23:01 ` [PATCH v13 1/8] iommu/vt-d: Move domain helper to header Jacob Pan 2020-05-13 23:01 ` Jacob Pan 2020-05-13 23:01 ` Jacob Pan [this message] 2020-05-13 23:01 ` [PATCH v13 2/8] iommu/vt-d: Use a helper function to skip agaw for SL Jacob Pan 2020-05-14 5:51 ` Christoph Hellwig 2020-05-14 5:51 ` Christoph Hellwig 2020-05-14 15:20 ` Jacob Pan 2020-05-14 15:20 ` Jacob Pan 2020-05-13 23:01 ` [PATCH v13 3/8] iommu/vt-d: Add nested translation helper function Jacob Pan 2020-05-13 23:01 ` Jacob Pan 2020-05-14 5:54 ` Christoph Hellwig 2020-05-14 5:54 ` Christoph Hellwig 2020-05-14 15:31 ` Jacob Pan 2020-05-14 15:31 ` Jacob Pan 2020-05-13 23:01 ` [PATCH v13 4/8] iommu/vt-d: Add bind guest PASID support Jacob Pan 2020-05-13 23:01 ` Jacob Pan 2020-05-14 5:59 ` Christoph Hellwig 2020-05-14 5:59 ` Christoph Hellwig 2020-05-14 15:57 ` Jacob Pan 2020-05-14 15:57 ` Jacob Pan 2020-05-15 1:01 ` Lu Baolu 2020-05-15 1:01 ` Lu Baolu 2020-05-16 6:02 ` Lu Baolu 2020-05-16 6:02 ` Lu Baolu 2020-05-13 23:01 ` [PATCH v13 5/8] iommu/vt-d: Support flushing more translation cache types Jacob Pan 2020-05-13 23:01 ` Jacob Pan 2020-05-13 23:01 ` [PATCH v13 6/8] iommu/vt-d: Add svm/sva invalidate function Jacob Pan 2020-05-13 23:01 ` Jacob Pan 2020-05-13 23:01 ` [PATCH v13 7/8] iommu/vt-d: Enlightened PASID allocation Jacob Pan 2020-05-13 23:01 ` Jacob Pan 2020-05-13 23:01 ` [PATCH v13 8/8] iommu/vt-d: Add custom allocator for IOASID Jacob Pan 2020-05-13 23:01 ` Jacob Pan 2020-05-16 6:31 ` [PATCH v13 0/8] Nested Shared Virtual Address (SVA) VT-d support Lu Baolu 2020-05-16 6:31 ` Lu Baolu
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