[Intel-gfx] [PATCH] drm/i915: Fix dbuf slice mask when turning off all the pipes

[Intel-gfx] [PATCH] drm/i915: Fix dbuf slice mask when turning off all the pipes

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The current dbuf slice computation only happens when there are
active pipes. If we are turning off all the pipes we just leave
the dbuf slice mask at it's previous value, which may be something
other that BIT(S1). If runtime PM will kick in it will however
turn off everything but S1. Then on the next atomic commit (if
the new dbuf slice mask matches the stale value we left behind)
the code will not turn on the other slices we now need. This will
lead to underruns as the planes are trying to use a dbuf slice
that's not powered up.

To work around let's just just explicitly set the dbuf slice mask
to BIT(S1) when we are turning off all the pipes. Really the code
should just calculate this stuff the same way regardless whether
the pipes are on or off, but we're not quite there yet (need a
bit more work on the dbuf state for that).

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Fixes: 3cf43cdc63fb ("drm/i915: Introduce proper dbuf state")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a21e36ed1a77..4a523d8b881f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4071,6 +4071,22 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
 	*num_active = hweight8(active_pipes);
 
 	if (!crtc_state->hw.active) {
+		/*
+		 * FIXME hack to make sure we compute this sensibly when
+		 * turning off all the pipes. Otherwise we leave it at
+		 * whatever we had previously, and then runtime PM will
+		 * mess it up by turning off all but S1. Remove this
+		 * once the dbuf state computation flow becomes sane.
+		 */
+		if (active_pipes == 0) {
+			new_dbuf_state->enabled_slices = BIT(DBUF_S1);
+
+			if (old_dbuf_state->enabled_slices != new_dbuf_state->enabled_slices) {
+				ret = intel_atomic_serialize_global_state(&new_dbuf_state->base);
+				if (ret)
+					return ret;
+			}
+		}
 		alloc->start = 0;
 		alloc->end = 0;
 		return 0;
-- 
2.26.2

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Re: [Intel-gfx] [PATCH] drm/i915: Fix dbuf slice mask when turning off all the pipes

[Chris Wilson]

Quoting Ville Syrjala (2020-05-16 17:15:42)
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The current dbuf slice computation only happens when there are
> active pipes. If we are turning off all the pipes we just leave
> the dbuf slice mask at it's previous value, which may be something
> other that BIT(S1). If runtime PM will kick in it will however
> turn off everything but S1. Then on the next atomic commit (if
> the new dbuf slice mask matches the stale value we left behind)
> the code will not turn on the other slices we now need. This will
> lead to underruns as the planes are trying to use a dbuf slice
> that's not powered up.
> 
> To work around let's just just explicitly set the dbuf slice mask
> to BIT(S1) when we are turning off all the pipes. Really the code
> should just calculate this stuff the same way regardless whether
> the pipes are on or off, but we're not quite there yet (need a
> bit more work on the dbuf state for that).
> 
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Fixes: 3cf43cdc63fb ("drm/i915: Introduce proper dbuf state")
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index a21e36ed1a77..4a523d8b881f 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4071,6 +4071,22 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
>         *num_active = hweight8(active_pipes);
>  
>         if (!crtc_state->hw.active) {
> +               /*
> +                * FIXME hack to make sure we compute this sensibly when
> +                * turning off all the pipes. Otherwise we leave it at
> +                * whatever we had previously, and then runtime PM will
> +                * mess it up by turning off all but S1. Remove this
> +                * once the dbuf state computation flow becomes sane.
> +                */
> +               if (active_pipes == 0) {
> +                       new_dbuf_state->enabled_slices = BIT(DBUF_S1);
> +
> +                       if (old_dbuf_state->enabled_slices != new_dbuf_state->enabled_slices) {
> +                               ret = intel_atomic_serialize_global_state(&new_dbuf_state->base);
> +                               if (ret)
> +                                       return ret;
> +                       }

Ok, that's equivalent to the tail of the function if no planes were
enabled.

Acked-by: Chris Wilson <chris@chris-wilson.co.uk>

I can't comment on the interaction with rpm, and was waiting for CI to
see if it cheers tgl up, but CI looks to be waiting for some tlc itself.
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: Fix dbuf slice mask when turning off all the pipes

[Lisovskiy, Stanislav]

On Sat, May 16, 2020 at 07:15:42PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The current dbuf slice computation only happens when there are
> active pipes. If we are turning off all the pipes we just leave
> the dbuf slice mask at it's previous value, which may be something
> other that BIT(S1). If runtime PM will kick in it will however
> turn off everything but S1. Then on the next atomic commit (if
> the new dbuf slice mask matches the stale value we left behind)
> the code will not turn on the other slices we now need. This will
> lead to underruns as the planes are trying to use a dbuf slice
> that's not powered up.
> 
> To work around let's just just explicitly set the dbuf slice mask
> to BIT(S1) when we are turning off all the pipes. Really the code
> should just calculate this stuff the same way regardless whether
> the pipes are on or off, but we're not quite there yet (need a
> bit more work on the dbuf state for that).
> 
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Fixes: 3cf43cdc63fb ("drm/i915: Introduce proper dbuf state")
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index a21e36ed1a77..4a523d8b881f 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4071,6 +4071,22 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
>  	*num_active = hweight8(active_pipes);
>  
>  	if (!crtc_state->hw.active) {
> +		/*
> +		 * FIXME hack to make sure we compute this sensibly when
> +		 * turning off all the pipes. Otherwise we leave it at
> +		 * whatever we had previously, and then runtime PM will
> +		 * mess it up by turning off all but S1. Remove this
> +		 * once the dbuf state computation flow becomes sane.
> +		 */
> +		if (active_pipes == 0) {
> +			new_dbuf_state->enabled_slices = BIT(DBUF_S1);
> +
> +			if (old_dbuf_state->enabled_slices != new_dbuf_state->enabled_slices) {
> +				ret = intel_atomic_serialize_global_state(&new_dbuf_state->base);
> +				if (ret)
> +					return ret;
> +			}
> +		}

Rather weird, why we didnt have that issue before..
Just trying to figure out what's the reason - aren't we recovering the last
state of enabled slices from hw in gen9_dbuf_enable?

As I understand you modify enabled_slices in dbuf global object recovering
the actual hw state there. 

Also from your patches I don't see the actual logic difference with what 
was happening before dbuf_state in that sense.
I.e we were also bailing out in skl_get_pipe_alloc_limits, without modifying
dbuf_state before, however there was no issue.

So the reason for regression should be somewhere else? Or am I missing something?

Also I guess would be really cute if we use a single way to get
slice configuration, i.e those tables from BSpec and functionality around it,
i.e we have skl_compute_dbuf_slices(crtc_state, active_pipes) call, which is supposed
to return dbuf slice config correspondent to active_pipes.

I guess by scattering those kind of assignments, here and there we just increasing 
the probability of more issues happening.

Stan


>  		alloc->start = 0;
>  		alloc->end = 0;
>  		return 0;
> -- 
> 2.26.2
> 
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Re: [Intel-gfx] [PATCH] drm/i915: Fix dbuf slice mask when turning off all the pipes

[Ville Syrjälä]

On Sun, May 17, 2020 at 03:12:49PM +0300, Lisovskiy, Stanislav wrote:
> On Sat, May 16, 2020 at 07:15:42PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > The current dbuf slice computation only happens when there are
> > active pipes. If we are turning off all the pipes we just leave
> > the dbuf slice mask at it's previous value, which may be something
> > other that BIT(S1). If runtime PM will kick in it will however
> > turn off everything but S1. Then on the next atomic commit (if
> > the new dbuf slice mask matches the stale value we left behind)
> > the code will not turn on the other slices we now need. This will
> > lead to underruns as the planes are trying to use a dbuf slice
> > that's not powered up.
> > 
> > To work around let's just just explicitly set the dbuf slice mask
> > to BIT(S1) when we are turning off all the pipes. Really the code
> > should just calculate this stuff the same way regardless whether
> > the pipes are on or off, but we're not quite there yet (need a
> > bit more work on the dbuf state for that).
> > 
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Fixes: 3cf43cdc63fb ("drm/i915: Introduce proper dbuf state")
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++++++++
> >  1 file changed, 16 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index a21e36ed1a77..4a523d8b881f 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4071,6 +4071,22 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
> >  	*num_active = hweight8(active_pipes);
> >  
> >  	if (!crtc_state->hw.active) {
> > +		/*
> > +		 * FIXME hack to make sure we compute this sensibly when
> > +		 * turning off all the pipes. Otherwise we leave it at
> > +		 * whatever we had previously, and then runtime PM will
> > +		 * mess it up by turning off all but S1. Remove this
> > +		 * once the dbuf state computation flow becomes sane.
> > +		 */
> > +		if (active_pipes == 0) {
> > +			new_dbuf_state->enabled_slices = BIT(DBUF_S1);
> > +
> > +			if (old_dbuf_state->enabled_slices != new_dbuf_state->enabled_slices) {
> > +				ret = intel_atomic_serialize_global_state(&new_dbuf_state->base);
> > +				if (ret)
> > +					return ret;
> > +			}
> > +		}
> 
> Rather weird, why we didnt have that issue before..
> Just trying to figure out what's the reason - aren't we recovering the last
> state of enabled slices from hw in gen9_dbuf_enable?
> 
> As I understand you modify enabled_slices in dbuf global object recovering
> the actual hw state there. 
> 
> Also from your patches I don't see the actual logic difference with what 
> was happening before dbuf_state in that sense.
> I.e we were also bailing out in skl_get_pipe_alloc_limits, without modifying
> dbuf_state before, however there was no issue.

We didn't have the old state so the pre/post update hooks were comparing
the new value against the value that was mangled by the display core init
to match the actual hw state.

The reason why it bit tgl so hard is that we tend to use two slices
on tgl all the time, whereas on icl we use just the first slice most
of the time.

-- 
Ville Syrjälä
Intel
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix dbuf slice mask when turning off all the pipes

[Patchwork]

== Series Details ==

Series: drm/i915: Fix dbuf slice mask when turning off all the pipes
URL   : https://patchwork.freedesktop.org/series/77322/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8493 -> Patchwork_17680
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/index.html

Known issues
------------

  Here are the changes found in Patchwork_17680 that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@i915_selftest@live@execlists:
    - fi-tgl-y:           [INCOMPLETE][1] ([i915#1803]) -> [PASS][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/fi-tgl-y/igt@i915_selftest@live@execlists.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/fi-tgl-y/igt@i915_selftest@live@execlists.html

  
#### Warnings ####

  * igt@i915_pm_rpm@module-reload:
    - fi-kbl-x1275:       [SKIP][3] ([fdo#109271]) -> [FAIL][4] ([i915#62] / [i915#95])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1803]: https://gitlab.freedesktop.org/drm/intel/issues/1803
  [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (51 -> 45)
------------------------------

  Additional (1): fi-kbl-7560u 
  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_8493 -> Patchwork_17680

  CI-20190529: 20190529
  CI_DRM_8493: 47e0097b33017be45f6826ef82a1f535b81ab9a3 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5657: 649eae5c905a7460b44305800f95db83a6dd47cb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17680: 7b2bb13994737b6fb1c5e52d8d1227622ccd9d36 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

7b2bb1399473 drm/i915: Fix dbuf slice mask when turning off all the pipes

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/index.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix dbuf slice mask when turning off all the pipes

[Patchwork]

== Series Details ==

Series: drm/i915: Fix dbuf slice mask when turning off all the pipes
URL   : https://patchwork.freedesktop.org/series/77322/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8493_full -> Patchwork_17680_full
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with Patchwork_17680_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_17680_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_17680_full:

### IGT changes ###

#### Warnings ####

  * igt@kms_cursor_edge_walk@pipe-c-64x64-left-edge:
    - shard-tglb:         [FAIL][1] ([i915#402]) -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb5/igt@kms_cursor_edge_walk@pipe-c-64x64-left-edge.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/shard-tglb5/igt@kms_cursor_edge_walk@pipe-c-64x64-left-edge.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-iclb:         [FAIL][3] ([i915#1757]) -> [FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-iclb3/igt@kms_panel_fitting@atomic-fastset.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/shard-iclb1/igt@kms_panel_fitting@atomic-fastset.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb}:
    - shard-tglb:         [FAIL][5] ([i915#402]) -> [FAIL][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb1/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/shard-tglb8/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html

  
Known issues
------------

  Here are the changes found in Patchwork_17680_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_workarounds@suspend-resume:
    - shard-apl:          [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-apl6/igt@gem_workarounds@suspend-resume.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/shard-apl1/igt@gem_workarounds@suspend-resume.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-apl:          [PASS][9] -> [DMESG-WARN][10] ([i915#1436] / [i915#716])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-apl4/igt@gen9_exec_parse@allowed-all.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/shard-apl1/igt@gen9_exec_parse@allowed-all.html

  * igt@kms_cursor_crc@pipe-a-cursor-dpms:
    - shard-skl:          [PASS][11] -> [FAIL][12] ([i915#54])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-skl3/igt@kms_cursor_crc@pipe-a-cursor-dpms.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/shard-skl2/igt@kms_cursor_crc@pipe-a-cursor-dpms.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-kbl:          [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +1 similar issue
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-kbl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/shard-kbl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-skl:          [PASS][15] -> [FAIL][16] ([IGT#5])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-kbl:          [PASS][17] -> [DMESG-WARN][18] ([i915#165] / [i915#180])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [PASS][19] -> [FAIL][20] ([fdo#108145] / [i915#265])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_psr@psr2_primary_render:
    - shard-iclb:         [PASS][21] -> [SKIP][22] ([fdo#109441])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-iclb2/igt@kms_psr@psr2_primary_render.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/shard-iclb6/igt@kms_psr@psr2_primary_render.html

  
#### Possible fixes ####

  * {igt@gem_ctx_isolation@preservation-s3@rcs0}:
    - shard-kbl:          [DMESG-WARN][23] ([i915#180]) -> [PASS][24] +2 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-kbl4/igt@gem_ctx_isolation@preservation-s3@rcs0.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/shard-kbl2/igt@gem_ctx_isolation@preservation-s3@rcs0.html

  * igt@kms_cursor_crc@pipe-b-cursor-128x42-offscreen:
    - shard-tglb:         [FAIL][25] ([i915#1897]) -> [PASS][26] +4 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb5/igt@kms_cursor_crc@pipe-b-cursor-128x42-offscreen.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/shard-tglb1/igt@kms_cursor_crc@pipe-b-cursor-128x42-offscreen.html

  * igt@kms_cursor_crc@pipe-b-cursor-suspend:
    - shard-apl:          [DMESG-WARN][27] ([i915#180]) -> [PASS][28] +3 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-apl8/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/shard-apl3/igt@kms_cursor_crc@pipe-b-cursor-suspend.html

  * igt@kms_dp_dsc@basic-dsc-enable-edp:
    - shard-iclb:         [SKIP][29] ([fdo#109349]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-iclb3/igt@kms_dp_dsc@basic-dsc-enable-edp.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html

  * igt@kms_draw_crc@draw-method-rgb565-render-xtiled:
    - shard-snb:          [SKIP][31] ([fdo#109271]) -> [PASS][32] +3 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-snb4/igt@kms_draw_crc@draw-method-rgb565-render-xtiled.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/shard-snb6/igt@kms_draw_crc@draw-method-rgb565-render-xtiled.html

  * {igt@kms_flip@flip-vs-suspend@b-edp1}:
    - shard-skl:          [INCOMPLETE][33] ([i915#198]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-skl3/igt@kms_flip@flip-vs-suspend@b-edp1.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/shard-skl2/igt@kms_flip@flip-vs-suspend@b-edp1.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu:
    - shard-tglb:         [FAIL][35] ([i915#402]) -> [PASS][36] +3 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw:
    - shard-skl:          [FAIL][37] ([i915#49]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-skl8/igt@kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/shard-skl2/igt@kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html

  * igt@kms_plane@plane-position-hole-dpms-pipe-d-planes:
    - shard-tglb:         [FAIL][39] ([i915#1897] / [i915#402]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb7/igt@kms_plane@plane-position-hole-dpms-pipe-d-planes.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/shard-tglb5/igt@kms_plane@plane-position-hole-dpms-pipe-d-planes.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          [FAIL][41] ([fdo#108145] / [i915#265]) -> [PASS][42] +2 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_plane_cursor@pipe-a-primary-size-256:
    - shard-glk:          [FAIL][43] ([i915#1559]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-glk9/igt@kms_plane_cursor@pipe-a-primary-size-256.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/shard-glk7/igt@kms_plane_cursor@pipe-a-primary-size-256.html

  * igt@kms_psr@psr2_cursor_plane_onoff:
    - shard-iclb:         [SKIP][45] ([fdo#109441]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-iclb3/igt@kms_psr@psr2_cursor_plane_onoff.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html

  * igt@kms_setmode@basic:
    - shard-skl:          [FAIL][47] ([i915#31]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-skl5/igt@kms_setmode@basic.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/shard-skl7/igt@kms_setmode@basic.html

  
#### Warnings ####

  * igt@i915_pm_dc@dc6-psr:
    - shard-tglb:         [SKIP][49] ([i915#468]) -> [SKIP][50] ([i915#668])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb2/igt@i915_pm_dc@dc6-psr.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/shard-tglb7/igt@i915_pm_dc@dc6-psr.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-0:
    - shard-tglb:         [FAIL][51] ([i915#1172] / [i915#402]) -> [FAIL][52] ([i915#1172])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb5/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/shard-tglb1/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html

  * igt@kms_color@pipe-c-gamma:
    - shard-tglb:         [FAIL][53] ([i915#1149]) -> [FAIL][54] ([i915#1149] / [i915#402])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb6/igt@kms_color@pipe-c-gamma.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/shard-tglb8/igt@kms_color@pipe-c-gamma.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-apl:          [FAIL][55] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][56] ([i915#1319])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-apl8/igt@kms_content_protection@atomic-dpms.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/shard-apl3/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@lic:
    - shard-apl:          [FAIL][57] ([fdo#110321]) -> [TIMEOUT][58] ([i915#1319])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-apl8/igt@kms_content_protection@lic.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/shard-apl3/igt@kms_content_protection@lic.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-gtt:
    - shard-tglb:         [FAIL][59] ([i915#1897]) -> [FAIL][60] ([i915#1897] / [i915#402]) +2 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-gtt.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-gtt.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
    - shard-tglb:         [FAIL][61] -> [FAIL][62] ([i915#402]) +1 similar issue
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/shard-tglb5/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html

  * igt@kms_plane@plane-panning-top-left-pipe-d-planes:
    - shard-tglb:         [FAIL][63] ([i915#1897] / [i915#402]) -> [FAIL][64] ([i915#1897]) +3 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/shard-tglb6/igt@kms_plane@plane-panning-top-left-pipe-d-planes.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/shard-tglb5/igt@kms_plane@plane-panning-top-left-pipe-d-planes.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
  [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336
  [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
  [i915#1172]: https://gitlab.freedesktop.org/drm/intel/issues/1172
  [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1559]: https://gitlab.freedesktop.org/drm/intel/issues/1559
  [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
  [i915#1757]: https://gitlab.freedesktop.org/drm/intel/issues/1757
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1883]: https://gitlab.freedesktop.org/drm/intel/issues/1883
  [i915#1897]: https://gitlab.freedesktop.org/drm/intel/issues/1897
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
  [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_8493 -> Patchwork_17680

  CI-20190529: 20190529
  CI_DRM_8493: 47e0097b33017be45f6826ef82a1f535b81ab9a3 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5657: 649eae5c905a7460b44305800f95db83a6dd47cb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17680: 7b2bb13994737b6fb1c5e52d8d1227622ccd9d36 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17680/index.html
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[Intel-gfx] [PATCH v2] drm/i915: Fix dbuf slice mask when turning off all the pipes

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The current dbuf slice computation only happens when there are
active pipes. If we are turning off all the pipes we just leave
the dbuf slice mask at it's previous value, which may be something
other that BIT(S1). If runtime PM will kick in it will however
turn off everything but S1. Then on the next atomic commit (if
the new dbuf slice mask matches the stale value we left behind)
the code will not turn on the other slices we now need. This will
lead to underruns as the planes are trying to use a dbuf slice
that's not powered up.

To work around let's just just explicitly set the dbuf slice mask
to BIT(S1) when we are turning off all the pipes. Really the code
should just calculate this stuff the same way regardless whether
the pipes are on or off, but we're not quite there yet (need a
bit more work on the dbuf state for that).

v2: Let's not put the fix into dead code

Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk> #v1
Fixes: 3cf43cdc63fb ("drm/i915: Introduce proper dbuf state")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a21e36ed1a77..0082582d8352 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4764,6 +4764,30 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 	memset(crtc_state->wm.skl.plane_ddb_uv, 0, sizeof(crtc_state->wm.skl.plane_ddb_uv));
 
 	if (!crtc_state->hw.active) {
+		struct intel_atomic_state *state =
+			to_intel_atomic_state(crtc_state->uapi.state);
+		struct intel_dbuf_state *new_dbuf_state =
+			intel_atomic_get_new_dbuf_state(state);
+		const struct intel_dbuf_state *old_dbuf_state =
+			intel_atomic_get_old_dbuf_state(state);
+
+		/*
+		 * FIXME hack to make sure we compute this sensibly when
+		 * turning off all the pipes. Otherwise we leave it at
+		 * whatever we had previously, and then runtime PM will
+		 * mess it up by turning off all but S1. Remove this
+		 * once the dbuf state computation flow becomes sane.
+		 */
+		if (new_dbuf_state->active_pipes == 0) {
+			new_dbuf_state->enabled_slices = BIT(DBUF_S1);
+
+			if (old_dbuf_state->enabled_slices != new_dbuf_state->enabled_slices) {
+				ret = intel_atomic_serialize_global_state(&new_dbuf_state->base);
+				if (ret)
+					return ret;
+			}
+		}
+
 		alloc->start = alloc->end = 0;
 		return 0;
 	}
-- 
2.26.2

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Re: [Intel-gfx] [PATCH v2] drm/i915: Fix dbuf slice mask when turning off all the pipes

[Chris Wilson]

Quoting Ville Syrjala (2020-05-18 13:13:54)
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The current dbuf slice computation only happens when there are
> active pipes. If we are turning off all the pipes we just leave
> the dbuf slice mask at it's previous value, which may be something
> other that BIT(S1). If runtime PM will kick in it will however
> turn off everything but S1. Then on the next atomic commit (if
> the new dbuf slice mask matches the stale value we left behind)
> the code will not turn on the other slices we now need. This will
> lead to underruns as the planes are trying to use a dbuf slice
> that's not powered up.
> 
> To work around let's just just explicitly set the dbuf slice mask
> to BIT(S1) when we are turning off all the pipes. Really the code
> should just calculate this stuff the same way regardless whether
> the pipes are on or off, but we're not quite there yet (need a
> bit more work on the dbuf state for that).
> 
> v2: Let's not put the fix into dead code
> 
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> #v1
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
> Fixes: 3cf43cdc63fb ("drm/i915: Introduce proper dbuf state")
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: Fix dbuf slice mask when turning off all the pipes

[Lisovskiy, Stanislav]

On Mon, May 18, 2020 at 09:33:29AM +0300, Ville Syrjälä wrote:
> On Sun, May 17, 2020 at 03:12:49PM +0300, Lisovskiy, Stanislav wrote:
> > On Sat, May 16, 2020 at 07:15:42PM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > The current dbuf slice computation only happens when there are
> > > active pipes. If we are turning off all the pipes we just leave
> > > the dbuf slice mask at it's previous value, which may be something
> > > other that BIT(S1). If runtime PM will kick in it will however
> > > turn off everything but S1. Then on the next atomic commit (if
> > > the new dbuf slice mask matches the stale value we left behind)
> > > the code will not turn on the other slices we now need. This will
> > > lead to underruns as the planes are trying to use a dbuf slice
> > > that's not powered up.
> > > 
> > > To work around let's just just explicitly set the dbuf slice mask
> > > to BIT(S1) when we are turning off all the pipes. Really the code
> > > should just calculate this stuff the same way regardless whether
> > > the pipes are on or off, but we're not quite there yet (need a
> > > bit more work on the dbuf state for that).
> > > 
> > > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > > Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > Fixes: 3cf43cdc63fb ("drm/i915: Introduce proper dbuf state")
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++++++++
> > >  1 file changed, 16 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index a21e36ed1a77..4a523d8b881f 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -4071,6 +4071,22 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
> > >  	*num_active = hweight8(active_pipes);
> > >  
> > >  	if (!crtc_state->hw.active) {
> > > +		/*
> > > +		 * FIXME hack to make sure we compute this sensibly when
> > > +		 * turning off all the pipes. Otherwise we leave it at
> > > +		 * whatever we had previously, and then runtime PM will
> > > +		 * mess it up by turning off all but S1. Remove this
> > > +		 * once the dbuf state computation flow becomes sane.
> > > +		 */
> > > +		if (active_pipes == 0) {
> > > +			new_dbuf_state->enabled_slices = BIT(DBUF_S1);
> > > +
> > > +			if (old_dbuf_state->enabled_slices != new_dbuf_state->enabled_slices) {
> > > +				ret = intel_atomic_serialize_global_state(&new_dbuf_state->base);
> > > +				if (ret)
> > > +					return ret;
> > > +			}
> > > +		}
> > 
> > Rather weird, why we didnt have that issue before..
> > Just trying to figure out what's the reason - aren't we recovering the last
> > state of enabled slices from hw in gen9_dbuf_enable?
> > 
> > As I understand you modify enabled_slices in dbuf global object recovering
> > the actual hw state there. 
> > 
> > Also from your patches I don't see the actual logic difference with what 
> > was happening before dbuf_state in that sense.
> > I.e we were also bailing out in skl_get_pipe_alloc_limits, without modifying
> > dbuf_state before, however there was no issue.
> 
> We didn't have the old state so the pre/post update hooks were comparing
> the new value against the value that was mangled by the display core init
> to match the actual hw state.
> 
> The reason why it bit tgl so hard is that we tend to use two slices
> on tgl all the time, whereas on icl we use just the first slice most
> of the time.

Ah yep, so previously we were comparing it against value fetched from hw
right away and now we compare aginst previous dbuf_state.

However I agree that of course we should modify the new dbuf state properly
in case if active_pipe == 0 however the only thing I would vote for is
doing all enabled_slices assignment in a same place, using that table
magic func.

Stan
> 
> -- 
> Ville Syrjälä
> Intel
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix dbuf slice mask when turning off all the pipes (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Fix dbuf slice mask when turning off all the pipes (rev2)
URL   : https://patchwork.freedesktop.org/series/77322/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8494 -> Patchwork_17690
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/index.html

Known issues
------------

  Here are the changes found in Patchwork_17690 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@active:
    - fi-bsw-nick:        [PASS][1] -> [DMESG-FAIL][2] ([i915#541])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-bsw-nick/igt@i915_selftest@live@active.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/fi-bsw-nick/igt@i915_selftest@live@active.html

  * igt@i915_selftest@live@execlists:
    - fi-kbl-r:           [PASS][3] -> [INCOMPLETE][4] ([i915#656])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-kbl-r/igt@i915_selftest@live@execlists.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/fi-kbl-r/igt@i915_selftest@live@execlists.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@execlists:
    - fi-whl-u:           [INCOMPLETE][5] ([i915#656]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-whl-u/igt@i915_selftest@live@execlists.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/fi-whl-u/igt@i915_selftest@live@execlists.html

  
  [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
  [i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656


Participating hosts (51 -> 43)
------------------------------

  Missing    (8): fi-cml-u2 fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_8494 -> Patchwork_17690

  CI-20190529: 20190529
  CI_DRM_8494: 3d15348fde9b998e754da0b0655baf02b98e7f17 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5657: 649eae5c905a7460b44305800f95db83a6dd47cb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17690: fed553859a0fa75b2dac63ac5738561c2094e1ed @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

fed553859a0f drm/i915: Fix dbuf slice mask when turning off all the pipes

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Fix dbuf slice mask when turning off all the pipes (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Fix dbuf slice mask when turning off all the pipes (rev2)
URL   : https://patchwork.freedesktop.org/series/77322/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_8494_full -> Patchwork_17690_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_17690_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_17690_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_17690_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-tglb:         [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-tglb2/igt@kms_panel_fitting@atomic-fastset.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-tglb5/igt@kms_panel_fitting@atomic-fastset.html

  
#### Warnings ####

  * igt@i915_pm_dc@dc6-psr:
    - shard-tglb:         [SKIP][3] ([i915#668]) -> [FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-tglb7/igt@i915_pm_dc@dc6-psr.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-tglb1/igt@i915_pm_dc@dc6-psr.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-iclb:         [FAIL][5] ([i915#1757]) -> [FAIL][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-iclb6/igt@kms_panel_fitting@atomic-fastset.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-iclb1/igt@kms_panel_fitting@atomic-fastset.html

  
Known issues
------------

  Here are the changes found in Patchwork_17690_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gen9_exec_parse@allowed-all:
    - shard-kbl:          [PASS][7] -> [DMESG-WARN][8] ([i915#1436] / [i915#716])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-kbl3/igt@gen9_exec_parse@allowed-all.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-kbl7/igt@gen9_exec_parse@allowed-all.html

  * igt@i915_suspend@debugfs-reader:
    - shard-apl:          [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-apl6/igt@i915_suspend@debugfs-reader.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-apl1/igt@i915_suspend@debugfs-reader.html

  * igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen:
    - shard-skl:          [PASS][11] -> [FAIL][12] ([i915#54])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-skl1/igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-skl8/igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-skl:          [PASS][13] -> [INCOMPLETE][14] ([i915#300])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-skl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-skl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-apl:          [PASS][15] -> [DMESG-WARN][16] ([i915#180] / [i915#95])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-apl8/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-apl1/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
    - shard-kbl:          [PASS][17] -> [DMESG-WARN][18] ([i915#180])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-kbl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-kbl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
    - shard-skl:          [PASS][19] -> [FAIL][20] ([fdo#108145] / [i915#265])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html

  * igt@kms_psr@psr2_sprite_blt:
    - shard-iclb:         [PASS][21] -> [SKIP][22] ([fdo#109441])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-iclb6/igt@kms_psr@psr2_sprite_blt.html

  
#### Possible fixes ####

  * {igt@gem_exec_schedule@pi-shared-iova@rcs0}:
    - shard-tglb:         [INCOMPLETE][23] ([i915#1193]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-tglb2/igt@gem_exec_schedule@pi-shared-iova@rcs0.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-tglb5/igt@gem_exec_schedule@pi-shared-iova@rcs0.html

  * {igt@kms_atomic_transition@plane-all-transition-nonblocking@pipe-b}:
    - shard-kbl:          [DMESG-WARN][25] ([i915#78]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-kbl2/igt@kms_atomic_transition@plane-all-transition-nonblocking@pipe-b.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-kbl2/igt@kms_atomic_transition@plane-all-transition-nonblocking@pipe-b.html

  * igt@kms_available_modes_crc@available_mode_test_crc:
    - shard-tglb:         [FAIL][27] ([i915#1537]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-tglb7/igt@kms_available_modes_crc@available_mode_test_crc.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-tglb1/igt@kms_available_modes_crc@available_mode_test_crc.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-0:
    - shard-tglb:         [FAIL][29] ([i915#1172] / [i915#1897] / [i915#402]) -> [PASS][30] +4 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-tglb8/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-tglb5/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-180:
    - shard-tglb:         [FAIL][31] ([i915#1172] / [i915#1897]) -> [PASS][32] +2 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-tglb6/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-tglb7/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html

  * igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
    - shard-tglb:         [FAIL][33] ([i915#1483] / [i915#1897] / [i915#402]) -> [PASS][34] +1 similar issue
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-tglb7/igt@kms_ccs@pipe-a-crc-sprite-planes-basic.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-tglb1/igt@kms_ccs@pipe-a-crc-sprite-planes-basic.html

  * igt@kms_color@pipe-a-ctm-blue-to-red:
    - shard-tglb:         [FAIL][35] ([i915#1149] / [i915#402]) -> [PASS][36] +5 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-tglb6/igt@kms_color@pipe-a-ctm-blue-to-red.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-tglb2/igt@kms_color@pipe-a-ctm-blue-to-red.html

  * igt@kms_color@pipe-b-gamma:
    - shard-tglb:         [FAIL][37] ([i915#1149] / [i915#1897] / [i915#402]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-tglb6/igt@kms_color@pipe-b-gamma.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-tglb7/igt@kms_color@pipe-b-gamma.html

  * igt@kms_color@pipe-c-gamma:
    - shard-tglb:         [FAIL][39] ([i915#1149] / [i915#1897]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-tglb7/igt@kms_color@pipe-c-gamma.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-tglb2/igt@kms_color@pipe-c-gamma.html

  * igt@kms_color@pipe-d-ctm-max:
    - shard-tglb:         [FAIL][41] ([i915#1149]) -> [PASS][42] +4 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-tglb7/igt@kms_color@pipe-d-ctm-max.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-tglb1/igt@kms_color@pipe-d-ctm-max.html

  * igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen:
    - shard-skl:          [FAIL][43] ([i915#54]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-skl4/igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-skl7/igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen.html

  * igt@kms_cursor_crc@pipe-d-cursor-alpha-opaque:
    - shard-tglb:         [FAIL][45] ([i915#1897]) -> [PASS][46] +109 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-tglb3/igt@kms_cursor_crc@pipe-d-cursor-alpha-opaque.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-tglb8/igt@kms_cursor_crc@pipe-d-cursor-alpha-opaque.html

  * igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
    - shard-tglb:         [FAIL][47] ([IGT#5] / [i915#402]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-tglb6/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-tglb7/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-tglb:         [FAIL][49] ([i915#64]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-tglb7/igt@kms_fbcon_fbt@fbc-suspend.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-tglb2/igt@kms_fbcon_fbt@fbc-suspend.html

  * {igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1}:
    - shard-skl:          [FAIL][51] ([i915#79]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * {igt@kms_flip@flip-vs-suspend-interruptible@c-dp1}:
    - shard-apl:          [DMESG-WARN][53] ([i915#180]) -> [PASS][54] +2 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html

  * igt@kms_flip_tiling@flip-changes-tiling-y:
    - shard-apl:          [FAIL][55] ([i915#95]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-apl8/igt@kms_flip_tiling@flip-changes-tiling-y.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-apl1/igt@kms_flip_tiling@flip-changes-tiling-y.html

  * igt@kms_flip_tiling@flip-to-y-tiled:
    - shard-tglb:         [FAIL][57] ([i915#1897] / [i915#402] / [i915#699]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-tglb2/igt@kms_flip_tiling@flip-to-y-tiled.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-tglb2/igt@kms_flip_tiling@flip-to-y-tiled.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt:
    - shard-tglb:         [FAIL][59] ([i915#1897] / [i915#402]) -> [PASS][60] +120 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw:
    - shard-skl:          [FAIL][61] ([i915#49]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite:
    - shard-tglb:         [SKIP][63] ([i915#668]) -> [PASS][64] +51 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-tglb8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-tglb5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite.html

  * igt@kms_hdr@bpc-switch:
    - shard-skl:          [FAIL][65] ([i915#1188]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-skl9/igt@kms_hdr@bpc-switch.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-skl4/igt@kms_hdr@bpc-switch.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-kbl:          [DMESG-WARN][67] ([i915#180]) -> [PASS][68] +8 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-kbl2/igt@kms_hdr@bpc-switch-suspend.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-kbl2/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_mmap_write_crc@main:
    - shard-tglb:         [FAIL][69] ([i915#1180] / [i915#1897] / [i915#402]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-tglb1/igt@kms_mmap_write_crc@main.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-tglb6/igt@kms_mmap_write_crc@main.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
    - shard-kbl:          [INCOMPLETE][71] ([i915#155]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-kbl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [FAIL][73] ([fdo#108145] / [i915#265]) -> [PASS][74] +2 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_plane_lowres@pipe-c-tiling-none:
    - shard-tglb:         [FAIL][75] ([i915#1897] / [i915#899]) -> [PASS][76] +3 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-tglb6/igt@kms_plane_lowres@pipe-c-tiling-none.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-tglb2/igt@kms_plane_lowres@pipe-c-tiling-none.html

  * igt@kms_psr@psr2_suspend:
    - shard-iclb:         [SKIP][77] ([fdo#109441]) -> [PASS][78] +2 similar issues
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-iclb4/igt@kms_psr@psr2_suspend.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-iclb2/igt@kms_psr@psr2_suspend.html

  
#### Warnings ####

  * igt@kms_content_protection@atomic:
    - shard-apl:          [TIMEOUT][79] ([i915#1319]) -> [FAIL][80] ([fdo#110321] / [fdo#110336])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-apl6/igt@kms_content_protection@atomic.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-apl8/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@lic:
    - shard-apl:          [DMESG-FAIL][81] ([fdo#110321]) -> [FAIL][82] ([fdo#110321])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-apl8/igt@kms_content_protection@lic.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-apl3/igt@kms_content_protection@lic.html

  * igt@kms_psr2_su@page_flip:
    - shard-tglb:         [SKIP][83] ([i915#668]) -> [FAIL][84] ([i915#608])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-tglb3/igt@kms_psr2_su@page_flip.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-tglb8/igt@kms_psr2_su@page_flip.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
  [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336
  [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
  [i915#1172]: https://gitlab.freedesktop.org/drm/intel/issues/1172
  [i915#1180]: https://gitlab.freedesktop.org/drm/intel/issues/1180
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1193]: https://gitlab.freedesktop.org/drm/intel/issues/1193
  [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1483]: https://gitlab.freedesktop.org/drm/intel/issues/1483
  [i915#1537]: https://gitlab.freedesktop.org/drm/intel/issues/1537
  [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
  [i915#1757]: https://gitlab.freedesktop.org/drm/intel/issues/1757
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1883]: https://gitlab.freedesktop.org/drm/intel/issues/1883
  [i915#1897]: https://gitlab.freedesktop.org/drm/intel/issues/1897
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#608]: https://gitlab.freedesktop.org/drm/intel/issues/608
  [i915#64]: https://gitlab.freedesktop.org/drm/intel/issues/64
  [i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668
  [i915#699]: https://gitlab.freedesktop.org/drm/intel/issues/699
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
  [i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_8494 -> Patchwork_17690

  CI-20190529: 20190529
  CI_DRM_8494: 3d15348fde9b998e754da0b0655baf02b98e7f17 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5657: 649eae5c905a7460b44305800f95db83a6dd47cb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17690: fed553859a0fa75b2dac63ac5738561c2094e1ed @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/index.html
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Re: [Intel-gfx] [PATCH v2] drm/i915: Fix dbuf slice mask when turning off all the pipes

[Ville Syrjälä]

On Mon, May 18, 2020 at 02:14:15PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2020-05-18 13:13:54)
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > The current dbuf slice computation only happens when there are
> > active pipes. If we are turning off all the pipes we just leave
> > the dbuf slice mask at it's previous value, which may be something
> > other that BIT(S1). If runtime PM will kick in it will however
> > turn off everything but S1. Then on the next atomic commit (if
> > the new dbuf slice mask matches the stale value we left behind)
> > the code will not turn on the other slices we now need. This will
> > lead to underruns as the planes are trying to use a dbuf slice
> > that's not powered up.
> > 
> > To work around let's just just explicitly set the dbuf slice mask
> > to BIT(S1) when we are turning off all the pipes. Really the code
> > should just calculate this stuff the same way regardless whether
> > the pipes are on or off, but we're not quite there yet (need a
> > bit more work on the dbuf state for that).
> > 
> > v2: Let's not put the fix into dead code
> > 
> > Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Acked-by: Chris Wilson <chris@chris-wilson.co.uk> #v1
> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Fixes: 3cf43cdc63fb ("drm/i915: Introduce proper dbuf state")
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> -Chris

v2 seems to have done the trick. CI gave up on the reverts anyway so
let's go with this one then. Pushed along with Chris's smatch fix.

Apologies for the massive cockup.

-- 
Ville Syrjälä
Intel
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