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status=New; importance=Undecided; assignee=None; X-Launchpad-Bug-Information-Type: Public X-Launchpad-Bug-Private: no X-Launchpad-Bug-Security-Vulnerability: no X-Launchpad-Bug-Commenters: babumoger djdatte h-sieger janklos X-Launchpad-Bug-Reporter: Damir (djdatte) X-Launchpad-Bug-Modifier: Heiko Sieger (h-sieger) References: <157625616239.22064.10423897892496347105.malonedeb@gac.canonical.com> Message-Id: <159001732338.19840.6413596738980744971.malone@soybean.canonical.com> Subject: [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs X-Launchpad-Message-Rationale: Subscriber (QEMU) @qemu-devel-ml X-Launchpad-Message-For: qemu-devel-ml Precedence: bulk X-Generated-By: Launchpad (canonical.com); Revision="1f7bc749b40714a4cc10f5e4d787118a78037035"; Instance="production-secrets-lazr.conf" X-Launchpad-Hash: 079046ef53b245e410feb415b9974e39f6d8fd9a Received-SPF: none client-ip=91.189.90.7; envelope-from=bounces@canonical.com; helo=indium.canonical.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/20 17:55:46 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -65 X-Spam_score: -6.6 X-Spam_bar: ------ X-Spam_report: (-6.6 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Bug 1856335 <1856335@bugs.launchpad.net> Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This is the CPU cache layout as shown by lscpu -a -e CPU NODE SOCKET CORE L1d:L1i:L2:L3 ONLINE MAXMHZ MINMHZ 0 0 0 0 0:0:0:0 yes 3800.0000 2200.0000 1 0 0 1 1:1:1:0 yes 3800.0000 2200.0000 2 0 0 2 2:2:2:0 yes 3800.0000 2200.0000 3 0 0 3 3:3:3:1 yes 3800.0000 2200.0000 4 0 0 4 4:4:4:1 yes 3800.0000 2200.0000 5 0 0 5 5:5:5:1 yes 3800.0000 2200.0000 6 0 0 6 6:6:6:2 yes 3800.0000 2200.0000 7 0 0 7 7:7:7:2 yes 3800.0000 2200.0000 8 0 0 8 8:8:8:2 yes 3800.0000 2200.0000 9 0 0 9 9:9:9:3 yes 3800.0000 2200.0000 10 0 0 10 10:10:10:3 yes 3800.0000 2200.0000 11 0 0 11 11:11:11:3 yes 3800.0000 2200.0000 12 0 0 0 0:0:0:0 yes 3800.0000 2200.0000 13 0 0 1 1:1:1:0 yes 3800.0000 2200.0000 14 0 0 2 2:2:2:0 yes 3800.0000 2200.0000 15 0 0 3 3:3:3:1 yes 3800.0000 2200.0000 16 0 0 4 4:4:4:1 yes 3800.0000 2200.0000 17 0 0 5 5:5:5:1 yes 3800.0000 2200.0000 18 0 0 6 6:6:6:2 yes 3800.0000 2200.0000 19 0 0 7 7:7:7:2 yes 3800.0000 2200.0000 20 0 0 8 8:8:8:2 yes 3800.0000 2200.0000 21 0 0 9 9:9:9:3 yes 3800.0000 2200.0000 22 0 0 10 10:10:10:3 yes 3800.0000 2200.0000 23 0 0 11 11:11:11:3 yes 3800.0000 2200.0000 I was trying to allocate cache using the cachetune feature in libvirt, but it turns out to be either misleading or much too complicated to be usable. Here is what I tried: 24 Unfortunately it gives the following error when I try to start the VM: Error starting domain: internal error: Missing or inconsistent resctrl info for memory bandwidth allocation I have resctrl mounted like this: mount -t resctrl resctrl /sys/fs/resctrl This error leads to the following description on how to allocate memory bandwith: https://software.intel.com/content/www/us/en/develop/articles /use-intel-resource-director-technology-to-allocate-memory- bandwidth.html I think this is over the top and perhaps I'm trying the wrong approach. All I can say is that every suggestion I've seen and tried so far has led me to one conclusion: QEMU does NOT support the L3 cache layout of the new ZEN 2 arch CPUs such as the Ryzen 9 3900X. -- = You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1856335 Title: Cache Layout wrong on many Zen Arch CPUs Status in QEMU: New Bug description: AMD CPUs have L3 cache per 2, 3 or 4 cores. Currently, TOPOEXT seems to always map Cache ass if it was an 4-Core per CCX CPU, which is incorrect, and costs upwards 30% performance (more realistically 10%) in L3 Cache Layout aware applications. Example on a 4-CCX CPU (1950X /w 8 Cores and no SMT): =C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0EPYC-IBPB =C2=A0=C2=A0=C2=A0=C2=A0AMD =C2=A0=C2=A0=C2=A0=C2=A0 In windows, coreinfo reports correctly: ****---- Unified Cache 1, Level 3, 8 MB, Assoc 16, LineSize 64 ----**** Unified Cache 6, Level 3, 8 MB, Assoc 16, LineSize 64 On a 3-CCX CPU (3960X /w 6 cores and no SMT): =C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0EPYC-IBPB =C2=A0=C2=A0=C2=A0=C2=A0AMD =C2=A0=C2=A0=C2=A0=C2=A0 in windows, coreinfo reports incorrectly: ****-- Unified Cache 1, Level 3, 8 MB, Assoc 16, LineSize 64 ----** Unified Cache 6, Level 3, 8 MB, Assoc 16, LineSize 64 Validated against 3.0, 3.1, 4.1 and 4.2 versions of qemu-kvm. With newer Qemu there is a fix (that does behave correctly) in using the = dies parameter: =C2=A0 The problem is that the dies are exposed differently than how AMD does it natively, they are exposed to Windows as sockets, which means, that if you are nto a business user, you can't ever have a machine with more than two CCX (6 cores) as consumer versions of Windows only supports two sockets. (Should this be reported as a separate bug?) To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1856335/+subscriptions