From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0287BC433E1 for ; Tue, 26 May 2020 09:12:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D241D20776 for ; Tue, 26 May 2020 09:12:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="MBjQ0qLo" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731785AbgEZJMV (ORCPT ); Tue, 26 May 2020 05:12:21 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:47073 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728682AbgEZJMT (ORCPT ); Tue, 26 May 2020 05:12:19 -0400 X-UUID: 21e65f87b913463a9cf005196ef70e69-20200526 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=gLvWi1nqtTxrY8+10s7N7a3KehB3j++1xRvGDtVazhY=; b=MBjQ0qLolyW2Q4K12Tlc8hqfr9f6mrv8+BPCD0mZdMkeJ1VDDxlj9iOEb1kX5O+QxtSEuwfsscljw8zPe2Xc5wjkI1Et/8c+FPjPFDFhZBtSe6bfm50hp6DL2ZdalWqS9TtEYPgvYNNRwOSq5dr+CY2ID4JK9PepFOHcgeKHa0o=; X-UUID: 21e65f87b913463a9cf005196ef70e69-20200526 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 858423237; Tue, 26 May 2020 17:12:09 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 26 May 2020 17:12:06 +0800 Received: from [172.21.77.4] (172.21.77.4) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 26 May 2020 17:12:06 +0800 Message-ID: <1590484328.4392.44.camel@mtksdaap41> Subject: Re: [PATCH v8 3/3] PM / AVS: SVS: Introduce SVS engine From: Roger Lu To: Matthias Brugger CC: Enric Balletbo Serra , Kevin Hilman , Rob Herring , Nicolas Boichat , Stephen Boyd , Mark Rutland , Nishanth Menon , Angus Lin , "devicetree@vger.kernel.org" , Linux PM list , linux-kernel , Xiaoqing Liu , YT Lee , Fan Chen , "moderated list:ARM/Mediatek SoC support" , HenryC Chen , Charles Yang , "Linux ARM" Date: Tue, 26 May 2020 17:12:08 +0800 In-Reply-To: <3b810588-ac4a-7fec-2163-38555dd83928@gmail.com> References: <20200518092403.22647-1-roger.lu@mediatek.com> <20200518092403.22647-4-roger.lu@mediatek.com> <1590140434.4392.22.camel@mtksdaap41> <3b810588-ac4a-7fec-2163-38555dd83928@gmail.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: base64 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org SGkgTWF0dGhpYXMsDQoNClRoYW5rcyBmb3IgdGhlIGZlZWRiYWNrLg0KDQpPbiBGcmksIDIwMjAt MDUtMjIgYXQgMTc6MzggKzAyMDAsIE1hdHRoaWFzIEJydWdnZXIgd3JvdGU6DQo+IA0KPiBPbiAy Mi8wNS8yMDIwIDExOjQwLCBSb2dlciBMdSB3cm90ZToNCj4gPiANCj4gPiBIaSBFbnJpYywNCj4g PiANCj4gPiBPbiBUdWUsIDIwMjAtMDUtMTkgYXQgMTc6MzAgKzAyMDAsIEVucmljIEJhbGxldGJv IFNlcnJhIHdyb3RlOg0KPiA+PiBIaSBSb2dlciwNCj4gPj4NCj4gPj4gVGhhbmsgeW91IGZvciB5 b3VyIHBhdGNoLiBJIGhhdmUgdGhlIGZlZWxpbmcgdGhhdCB0aGlzIGRyaXZlciBpcw0KPiA+PiBj b21wbGV4IGFuZCBkaWZmaWN1bHQgdG8gZm9sbG93IGFuZCBJIGFtIHdvbmRlcmluZyBpZiBpdCB3 b3VsZG4ndCBiZQ0KPiA+PiBiZXR0ZXIgaWYgeW91IGNhbiBzZW5kIGEgdmVyc2lvbiB0aGF0IHNp bXBseSBhZGRzIGJhc2ljIGZ1bmN0aW9uYWxpdHkNCj4gPj4gZm9yIG5vdy4gU29tZSBjb21tZW50 cyBiZWxvdy4NCj4gPiANCj4gPiBUaGFua3MgZm9yIHRoZSBhZHZpY2VzLiBJJ2xsIHN1Ym1pdCBT VlMgdjkgd2l0aCBiYXNpYyBmdW5jdGlvbmFsaXR5DQo+ID4gcGF0Y2ggKyBzdGVwIGJ5IHN0ZXAg ZnVuY3Rpb25hbGl0aWVzJyBwYXRjaGVzLiANCj4gPiANCj4gPj4NCj4gPj4gTWlzc2F0Z2UgZGUg Um9nZXIgTHUgPHJvZ2VyLmx1QG1lZGlhdGVrLmNvbT4gZGVsIGRpYSBkbC4sIDE4IGRlIG1haWcN Cj4gPj4gMjAyMCBhIGxlcyAxMToyNToNCj4gPj4+DQo+ID4+PiBUaGUgU1ZTIChTbWFydCBWb2x0 YWdlIFNjYWxpbmcpIGVuZ2luZSBpcyBhIHBpZWNlDQo+ID4+PiBvZiBoYXJkd2FyZSB3aGljaCBp cyB1c2VkIHRvIGNhbGN1bGF0ZSBvcHRpbWl6ZWQNCj4gPj4+IHZvbHRhZ2UgdmFsdWVzIG9mIHNl dmVyYWwgcG93ZXIgZG9tYWlucywNCj4gPj4+IGUuZy4gQ1BVL0dQVS9DQ0ksIGFjY29yZGluZyB0 byBjaGlwIHByb2Nlc3MgY29ybmVyLA0KPiA+Pj4gdGVtcGVyYXR1cmVzLCBhbmQgb3RoZXIgZmFj dG9ycy4gVGhlbiBEVkZTIGRyaXZlcg0KPiA+Pj4gY291bGQgYXBwbHkgdGhvc2Ugb3B0aW1pemVk IHZvbHRhZ2UgdmFsdWVzIHRvIHJlZHVjZQ0KPiA+Pj4gcG93ZXIgY29uc3VtcHRpb24uDQo+ID4+ Pg0KPiA+Pj4gU2lnbmVkLW9mZi1ieTogUm9nZXIgTHUgPHJvZ2VyLmx1QG1lZGlhdGVrLmNvbT4N Cj4gPj4+IC0tLQ0KPiA+Pj4gIGRyaXZlcnMvcG93ZXIvYXZzL0tjb25maWcgICAgIHwgICAxMCAr DQo+ID4+PiAgZHJpdmVycy9wb3dlci9hdnMvTWFrZWZpbGUgICAgfCAgICAxICsNCj4gPj4+ICBk cml2ZXJzL3Bvd2VyL2F2cy9tdGtfc3ZzLmMgICB8IDIxMTkgKysrKysrKysrKysrKysrKysrKysr KysrKysrKysrKysrDQo+ID4+PiAgaW5jbHVkZS9saW51eC9wb3dlci9tdGtfc3ZzLmggfCAgIDIz ICsNCj4gPj4+ICA0IGZpbGVzIGNoYW5nZWQsIDIxNTMgaW5zZXJ0aW9ucygrKQ0KPiA+Pj4gIGNy ZWF0ZSBtb2RlIDEwMDY0NCBkcml2ZXJzL3Bvd2VyL2F2cy9tdGtfc3ZzLmMNCj4gPj4+ICBjcmVh dGUgbW9kZSAxMDA2NDQgaW5jbHVkZS9saW51eC9wb3dlci9tdGtfc3ZzLmgNCj4gPj4+DQo+ID4+ PiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9wb3dlci9hdnMvS2NvbmZpZyBiL2RyaXZlcnMvcG93ZXIv YXZzL0tjb25maWcNCj4gPj4+IGluZGV4IGNkYjQyMzdiZmQwMi4uNjcwODlhYzYwNDBlIDEwMDY0 NA0KPiA+Pj4gLS0tIGEvZHJpdmVycy9wb3dlci9hdnMvS2NvbmZpZw0KPiA+Pj4gKysrIGIvZHJp dmVycy9wb3dlci9hdnMvS2NvbmZpZw0KPiA+Pj4gQEAgLTM1LDMgKzM1LDEzIEBAIGNvbmZpZyBS T0NLQ0hJUF9JT0RPTUFJTg0KPiA+Pj4gICAgICAgICAgIFNheSB5IGhlcmUgdG8gZW5hYmxlIHN1 cHBvcnQgaW8gZG9tYWlucyBvbiBSb2NrY2hpcCBTb0NzLiBJdCBpcw0KPiA+Pj4gICAgICAgICAg IG5lY2Vzc2FyeSBmb3IgdGhlIGlvIGRvbWFpbiBzZXR0aW5nIG9mIHRoZSBTb0MgdG8gbWF0Y2gg dGhlDQo+ID4+PiAgICAgICAgICAgdm9sdGFnZSBzdXBwbGllZCBieSB0aGUgcmVndWxhdG9ycy4N Cj4gPj4+ICsNCj4gPj4+ICtjb25maWcgTVRLX1NWUw0KPiA+Pj4gKyAgICAgICBib29sICJNZWRp YVRlayBTbWFydCBWb2x0YWdlIFNjYWxpbmcoU1ZTKSINCj4gPj4NCj4gPj4gQ2FuJ3QgYmUgdGhp cyBhIG1vZHVsZT8gV2h5PyBJbiBzdWNoIGNhc2UsIHlvdSBzaG91bGQgdXNlIHRyaXN0YXRlIG9w dGlvbg0KPiA+IA0KPiA+IEdlbmVyYWxseSwgTVRLX1NWUyBpcyBuZWVkZWQgaW4gTVRLIFNvQyht dDgxeHgpIHByb2R1Y3RzLiBTbywgd2UgZG9uJ3QgcHJvdmlkZQ0KPiA+IG1vZHVsZSBvcHRpb24g aW4gY29uZmlnLiBJZiwgc29tZWhvdywgU1ZTIGlzbid0IG5lZWRlZCwgd2Ugc3VnZ2VzdA0KPiA+ IENPTkZJR19NVEtfU1ZTPW4gdG8gYmUgc2V0Lg0KPiA+IA0KPiANCj4gVGhlIHF1ZXN0aW9uIGhl cmUgaXMgaWYgaXQgbmVlZHMgdG8gYmUgcHJvYmVkIGJlZm9yZSB3ZSBwcm9iZSB0aGUgbW9kdWxl cy4gSWYNCj4gbm90LCB3ZSBzaG91bGQgYWRkIGEgS2NvbmZpZyBvcHRpb24gZm9yIE1UODF4eCBT b0NzIHRvIHNlbGVjdCBNVEtfU1ZTLg0KDQpFeGN1c2UgbWUgdG8gbWFrZSB5b3UgY29uZnVzZS4g TVQ4MXh4IFNvQ3MgaXMgdGhlIHN1YnNldCBNVEsgSUNzIHRoYXQNCndpbGwgdXNlIENPTkZJR19N VEtfU1ZTLiBJbiBvdGhlciB3b3JkcywgQ09ORklHX01US19TVlMgd2lsbCBiZSB1c2VkDQp3aXRo IG90aGVyIE1USyBJQ3MgYXMgd2VsbC4gU28sIE1US19TVlMgaXMgdGhlIGdlbmVyYWwgbmFtaW5n IGZvciBNVEsgSUMNCnRvIGVuYWJsZSBTVlMgcG93ZXIgZmVhdHVyZS4gQW55d2F5LCBiYWNrIHRv IEVucmljJ3MgcXVlc3Rpb24sIEknbGwgbWFrZQ0KTVRLX1NWUyBiZWNvbWUgYSB0cmlzdGF0ZSBm ZWF0dXJlIGluIHRoZSBuZXh0IHBhdGNoLiBUaGFua3MuDQoNCj4gDQo+ID4+DQo+ID4+PiArICAg ICAgIGRlcGVuZHMgb24gUE9XRVJfQVZTICYmIE1US19FRlVTRSAmJiBOVk1FTQ0KPiA+Pj4gKyAg ICAgICBoZWxwDQo+ID4+PiArICAgICAgICAgVGhlIFNWUyBlbmdpbmUgaXMgYSBwaWVjZSBvZiBo YXJkd2FyZSB3aGljaCBpcyB1c2VkIHRvIGNhbGN1bGF0ZQ0KPiA+Pj4gKyAgICAgICAgIG9wdGlt aXplZCB2b2x0YWdlIHZhbHVlcyBvZiBzZXZlcmFsIHBvd2VyIGRvbWFpbnMsIGUuZy4NCj4gPj4+ ICsgICAgICAgICBDUFUgY2x1c3RlcnMvR1BVL0NDSSwgYWNjb3JkaW5nIHRvIGNoaXAgcHJvY2Vz cyBjb3JuZXIsIHRlbXBlcmF0dXJlcywNCj4gPj4+ICsgICAgICAgICBhbmQgb3RoZXIgZmFjdG9y cy4gVGhlbiBEVkZTIGRyaXZlciBjb3VsZCBhcHBseSB0aG9zZSBvcHRpbWl6ZWQgdm9sdGFnZQ0K PiA+Pj4gKyAgICAgICAgIHZhbHVlcyB0byByZWR1Y2UgcG93ZXIgY29uc3VtcHRpb24uDQo+ID4+ PiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9wb3dlci9hdnMvTWFrZWZpbGUgYi9kcml2ZXJzL3Bvd2Vy L2F2cy9NYWtlZmlsZQ0KPiA+Pj4gaW5kZXggOTAwN2QwNTg1M2UyLi4yMzFhZGYwNzg1ODIgMTAw NjQ0DQo+ID4+PiAtLS0gYS9kcml2ZXJzL3Bvd2VyL2F2cy9NYWtlZmlsZQ0KPiA+Pj4gKysrIGIv ZHJpdmVycy9wb3dlci9hdnMvTWFrZWZpbGUNCj4gPj4+IEBAIC0yLDMgKzIsNCBAQA0KPiA+Pj4g IG9iai0kKENPTkZJR19QT1dFUl9BVlNfT01BUCkgICAgICAgICAgICs9IHNtYXJ0cmVmbGV4Lm8N Cj4gPj4+ICBvYmotJChDT05GSUdfUUNPTV9DUFIpICAgICAgICAgICAgICAgICArPSBxY29tLWNw ci5vDQo+ID4+PiAgb2JqLSQoQ09ORklHX1JPQ0tDSElQX0lPRE9NQUlOKSAgICAgICAgICAgICAg ICArPSByb2NrY2hpcC1pby1kb21haW4ubw0KPiA+Pj4gK29iai0kKENPTkZJR19NVEtfU1ZTKSAg ICAgICAgICAgICAgICAgICs9IG10a19zdnMubw0KPiA+Pg0KPiA+PiBXaWxsIHRoaXMgZHJpdmVy IGJlIFNvQyBzcGVjaWZpYyBvciB0aGUgaWRlYSBpcyB0byBzdXBwb3J0IGRpZmZlcmVudA0KPiA+ PiBTb0NzPyBJZiB0aGUgYW5zd2VyIHRvIHRoZSBmaXJzdCBxdWVzdGlvbiBpcyB5ZXMsIHBsZWFz ZSBuYW1lIHRoZSBmaWxlDQo+ID4+IHdpdGggdGhlIFNvQyBwcmVmaXggKGkuZSBtdDgxODNfc3Zz KS4gSG93ZXZlciwgSWYgdGhlIGFuc3dlciB0byB0aGUNCj4gPj4gc2Vjb25kIHF1ZXN0aW9uIGlz IHllcywgbWFrZSBzdXJlIHlvdSBwcmVmaXggY29tbW9uDQo+ID4+IGZ1bmN0aW9ucy9zdHJ1Y3Rz L2RlZmluZXMgd2l0aCBhIGdlbmVyaWMgcHJlZml4IG10a19zdnMgYnV0IHVzZSB0aGUNCj4gPj4g U29DIHByZWZpeCBmb3IgdGhlIG9uZXMgeW91IGV4cGVjdCB3aWxsIGJlIGRpZmZlcmVudCBiZXR3 ZWVuIFNvQywgaS5lDQo+ID4+IG10ODE4M19zdnNfLiBUaGlzIGhlbHBzIHRoZSByZWFkYWJpbGl0 eSBvZiB0aGUgZHJpdmVyLiBBbHNvLCB0cnkgdG8NCj4gPj4gYXZvaWQgdG9vIGdlbmVyaWMgbmFt ZXMuDQo+ID4gDQo+ID4gTVRLX1NWUyBpcyBkZXNpZ25lZCBmb3Igc3VwcG9ydGluZyBkaWZmZXJl bnQgTVRLIFNvQ3MuVGhlcmVmb3JlLCB0aGUgYW5zd2VyIGlzIHNlY29uZA0KPiA+IHF1ZXN0aW9u IGFuZCB0aGFua3MgZm9yIHRoZSBoZWFkcy11cC4NCj4gPiANCj4gPj4NCj4gPj4+IGRpZmYgLS1n aXQgYS9kcml2ZXJzL3Bvd2VyL2F2cy9tdGtfc3ZzLmMgYi9kcml2ZXJzL3Bvd2VyL2F2cy9tdGtf c3ZzLmMNCj4gPj4+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0DQo+ID4+PiBpbmRleCAwMDAwMDAwMDAw MDAuLmE0MDgzYjNlZjE3NQ0KPiA+Pj4gLS0tIC9kZXYvbnVsbA0KPiA+Pj4gKysrIGIvZHJpdmVy cy9wb3dlci9hdnMvbXRrX3N2cy5jDQo+ID4+PiBAQCAtMCwwICsxLDIxMTkgQEANCj4gPj4+ICsv LyBTUERYLUxpY2Vuc2UtSWRlbnRpZmllcjogR1BMLTIuMA0KPiA+Pg0KPiA+PiBJIHN1c3BlY3Qg eW91IHdhbnQgdGhpcyBvbmx5IEdQTHYyIGNvbXBsaWFudC4gVXNlIEdQTC0yLjAtb25seQ0KPiA+ IA0KPiA+IE9LLiBJJ2xsIHVzZSBHUEwtMi4wLW9ubHkuVGhhbmtzLg0KPiA+IA0KPiA+Pg0KPiA+ Pj4gKy8qDQo+ID4+PiArICogQ29weXJpZ2h0IChDKSAyMDIwIE1lZGlhVGVrIEluYy4NCj4gPj4+ ICsgKi8NCj4gPj4+ICsNCj4gPj4+ICsjZGVmaW5lIHByX2ZtdChmbXQpICAgICJbbXRrX3N2c10g IiBmbXQNCj4gPj4NCj4gPj4gSSBkb24ndCBzZWUgYW55IHJlYXNvbiB0byB1c2UgcHJfZm10IGlu IHRoaXMgZHJpdmVyLiBVc2UgZGV2XyoNCj4gPj4gZnVuY3Rpb25zIGluc3RlYWQgYW5kIHJlbW92 ZSB0aGUgYWJvdmUuDQo+ID4gDQo+ID4gT2suIEkgd2lsbCByZW1vdmUgaXQuIFRoYW5rcy4NCj4g PiANCj4gPj4NCj4gPj4+ICsNCj4gPj4+ICsjaW5jbHVkZSA8bGludXgvYml0cy5oPg0KPiA+Pj4g KyNpbmNsdWRlIDxsaW51eC9jbGsuaD4NCj4gPj4+ICsjaW5jbHVkZSA8bGludXgvY29tcGxldGlv bi5oPg0KPiA+Pj4gKyNpbmNsdWRlIDxsaW51eC9pbml0Lmg+DQo+ID4+PiArI2luY2x1ZGUgPGxp bnV4L2ludGVycnVwdC5oPg0KPiA+Pj4gKyNpbmNsdWRlIDxsaW51eC9rZXJuZWwuaD4NCj4gPj4+ ICsjaW5jbHVkZSA8bGludXgva3RocmVhZC5oPg0KPiA+Pj4gKyNpbmNsdWRlIDxsaW51eC9tb2R1 bGUuaD4NCj4gPj4+ICsjaW5jbHVkZSA8bGludXgvbXV0ZXguaD4NCj4gPj4+ICsjaW5jbHVkZSA8 bGludXgvbnZtZW0tY29uc3VtZXIuaD4NCj4gPj4+ICsjaW5jbHVkZSA8bGludXgvb2ZfYWRkcmVz cy5oPg0KPiA+Pj4gKyNpbmNsdWRlIDxsaW51eC9vZl9pcnEuaD4NCj4gPj4+ICsjaW5jbHVkZSA8 bGludXgvb2ZfcGxhdGZvcm0uaD4NCj4gPj4+ICsjaW5jbHVkZSA8bGludXgvcGxhdGZvcm1fZGV2 aWNlLmg+DQo+ID4+PiArI2luY2x1ZGUgPGxpbnV4L3BtX2RvbWFpbi5oPg0KPiA+Pj4gKyNpbmNs dWRlIDxsaW51eC9wbV9vcHAuaD4NCj4gPj4+ICsjaW5jbHVkZSA8bGludXgvcG1fcW9zLmg+DQo+ ID4+PiArI2luY2x1ZGUgPGxpbnV4L3BtX3J1bnRpbWUuaD4NCj4gPj4+ICsjaW5jbHVkZSA8bGlu dXgvcG93ZXIvbXRrX3N2cy5oPg0KPiA+Pj4gKyNpbmNsdWRlIDxsaW51eC9wcm9jX2ZzLmg+DQo+ ID4+PiArI2luY2x1ZGUgPGxpbnV4L3JlZ3VsYXRvci9jb25zdW1lci5oPg0KPiA+Pj4gKyNpbmNs dWRlIDxsaW51eC9yZXNldC5oPg0KPiA+Pj4gKyNpbmNsdWRlIDxsaW51eC9zZXFfZmlsZS5oPg0K PiA+Pj4gKyNpbmNsdWRlIDxsaW51eC9zbGFiLmg+DQo+ID4+PiArI2luY2x1ZGUgPGxpbnV4L3Nw aW5sb2NrLmg+DQo+ID4+PiArI2luY2x1ZGUgPGxpbnV4L3RoZXJtYWwuaD4NCj4gPj4+ICsjaW5j bHVkZSA8bGludXgvdWFjY2Vzcy5oPg0KPiA+Pj4gKw0KPiA+Pj4gKy8qIHN2cyAxLWxpbmUgc3cg aWQgKi8NCj4gPj4+ICsjZGVmaW5lIFNWU19DUFVfTElUVExFICAgICAgICAgICAgICAgICBCSVQo MCkNCj4gPj4+ICsjZGVmaW5lIFNWU19DUFVfQklHICAgICAgICAgICAgICAgICAgICBCSVQoMSkN Cj4gPj4+ICsjZGVmaW5lIFNWU19DQ0kgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIEJJ VCgyKQ0KPiA+Pj4gKyNkZWZpbmUgU1ZTX0dQVSAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgQklUKDMpDQo+ID4+PiArDQo+ID4+PiArLyogc3ZzIGJhbmsgbW9kZSBzdXBwb3J0ICovDQo+ ID4+PiArI2RlZmluZSBTVlNCX01PREVfQUxMX0RJU0FCTEUgICAgICAgICAgKDApDQo+ID4+DQo+ ID4+IG5pdDogU1ZTX0JNT0RFXz8NCj4gPiANCj4gPiBPaC4gSWYgd2UgYWRkIGJhbmsgd29yZGlu ZyBsaWtlIFNWU19CeHh4LCBpdCBtaWdodCBjYXVzZSBzb21lIGNvbmZ1c2lvbiB3aGVuIEIgY29t YmluZXMNCj4gPiB3aXRoIG90aGVyIHdvcmRzLiBTbywgSSdsbCBrZWVwIFNWU0IgZm9yIFNWUyBC YW5rIHJlcHJlc2VudGF0aW9uLg0KPiA+IEUuZzogU1ZTX0JEQ19TSUdORURfQklUIG1pZ2h0IGxl YWQgdG8gYmUgZXhwbGFpbmVkIGRpZmZlcmVudGx5ICgiU1ZTIGJhbmsgKyBEQ19TSUdORURfQklU IiBvciAiU1ZTICsgQkRDX1NJR05FRF9CSVQiKQ0KPiA+ICAgICAgLSAiU1ZTIGJhbmsgKyBEQ19T SUdORURfQklUIiBpcyB3aGF0IHdlIHdhbnQgZm9yIG5hbWluZyBTVlNfQkRDX1NJR05FRF9CSVQg YnV0IGl0IG1pZ2h0IGJlIG1pc3VuZGVyc3Rvb2QuDQo+ID4gDQo+ID4+DQo+ID4+PiArI2RlZmlu ZSBTVlNCX01PREVfSU5JVDAxICAgICAgICAgICAgICAgQklUKDEpDQo+ID4+PiArI2RlZmluZSBT VlNCX01PREVfSU5JVDAyICAgICAgICAgICAgICAgQklUKDIpDQo+ID4+PiArI2RlZmluZSBTVlNC X01PREVfTU9OICAgICAgICAgICAgICAgICAgQklUKDMpDQo+ID4+PiArDQo+ID4+PiArLyogc3Zz IGJhbmsgaW5pdDAxIGNvbmRpdGlvbiAqLw0KPiA+Pj4gKyNkZWZpbmUgU1ZTQl9JTklUMDFfVk9M VF9JR05PUkUgICAgICAgICAgICAgICAgQklUKDEpDQo+ID4+PiArI2RlZmluZSBTVlNCX0lOSVQw MV9WT0xUX0lOQ19PTkxZICAgICAgQklUKDIpDQo+ID4+PiArDQo+ID4+PiArLyogc3ZzIGJhbmsg Y29tbW9uIHNldHRpbmcgKi8NCj4gPj4+ICsjZGVmaW5lIEhJR0hfVEVNUF9NQVggICAgICAgICAg ICAgICAgICAoVTMyX01BWCkNCj4gPj4NCj4gPj4gbml0OiBTVlNfKg0KPiA+IA0KPiA+IG9rLiBJ IHdpbGwgYWRkIFNWUyBvciBTVlNCIHdoZW4gaXQgcmVmZXJzIHRvIFNWUyBCQU5LLg0KPiA+IA0K PiA+Pg0KPiA+Pj4gKyNkZWZpbmUgUlVOQ09ORklHX0RFRkFVTFQgICAgICAgICAgICAgICgweDgw MDAwMDAwKQ0KPiA+Pg0KPiA+PiBCdHcsIHRoZXJlIGlzIGFueSBwdWJsaWMgZGF0YXNoZWV0IHdo ZXJlIEkgY2FuIHNlZSB0aG9zZSBhZGRyZXNzZXMgYW5kDQo+ID4+IHJlZ2lzdGVycyBhbmQgYml0 IGZpZWxkcz8NCj4gPiANCj4gPiBFeGN1c2UgdXMsIHRoZXJlIGlzIG5vIHB1YmxpYyBkYXRhc2hl ZXQuIFdlIGNhbiByZXBseSBpdCBvbiBwYXRjaHdvcmsuIFRoYW5rcy4NCj4gPiANCj4gPj4NCj4g Pj4+ICsjZGVmaW5lIERDX1NJR05FRF9CSVQgICAgICAgICAgICAgICAgICAoMHg4MDAwKQ0KPiA+ Pj4gKyNkZWZpbmUgSU5URU5fSU5JVDB4ICAgICAgICAgICAgICAgICAgICgweDAwMDA1ZjAxKQ0K PiA+Pj4gKyNkZWZpbmUgSU5URU5fTU9OVk9QRU4gICAgICAgICAgICAgICAgICgweDAwZmYwMDAw KQ0KPiA+Pj4gKyNkZWZpbmUgU1ZTRU5fT0ZGICAgICAgICAgICAgICAgICAgICAgICgweDApDQo+ ID4+PiArI2RlZmluZSBTVlNFTl9NQVNLICAgICAgICAgICAgICAgICAgICAgKDB4NykNCj4gPj4+ ICsjZGVmaW5lIFNWU0VOX0lOSVQwMSAgICAgICAgICAgICAgICAgICAoMHgxKQ0KPiA+Pj4gKyNk ZWZpbmUgU1ZTRU5fSU5JVDAyICAgICAgICAgICAgICAgICAgICgweDUpDQo+ID4+PiArI2RlZmlu ZSBTVlNFTl9NT04gICAgICAgICAgICAgICAgICAgICAgKDB4MikNCj4gPj4+ICsjZGVmaW5lIElO VFNUU19NT05WT1AgICAgICAgICAgICAgICAgICAoMHgwMGZmMDAwMCkNCj4gPj4+ICsjZGVmaW5l IElOVFNUU19DT01QTEVURSAgICAgICAgICAgICAgICAgICAgICAgICgweDEpDQo+ID4+PiArI2Rl ZmluZSBJTlRTVFNfQ0xFQU4gICAgICAgICAgICAgICAgICAgKDB4MDBmZmZmZmYpDQo+ID4+PiAr DQo+ID4+PiArI2RlZmluZSBwcm9jX2ZvcHNfcncobmFtZSkgXA0KPiA+Pj4gKyAgICAgICBzdGF0 aWMgaW50IG5hbWUgIyMgX3Byb2Nfb3BlbihzdHJ1Y3QgaW5vZGUgKmlub2RlLCAgICAgIFwNCj4g Pj4+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgc3RydWN0IGZpbGUgKmZp bGUpICAgICAgICBcDQo+ID4+PiArICAgICAgIHsgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgXA0KPiA+Pj4gKyAgICAgICAgICAgICAgIHJldHVy biBzaW5nbGVfb3BlbihmaWxlLCBuYW1lICMjIF9wcm9jX3Nob3csICAgIFwNCj4gPj4+ICsgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgUERFX0RBVEEoaW5vZGUpKTsgICAgICAgICAg ICBcDQo+ID4+PiArICAgICAgIH0gICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgXA0KPiA+Pj4gKyAgICAgICBzdGF0aWMgY29uc3Qgc3RydWN0IHBy b2Nfb3BzIG5hbWUgIyMgX3Byb2NfZm9wcyA9IHsgICAgIFwNCj4gPj4+ICsgICAgICAgICAgICAg ICAucHJvY19vcGVuICAgICAgPSBuYW1lICMjIF9wcm9jX29wZW4sICAgICAgICAgICBcDQo+ID4+ PiArICAgICAgICAgICAgICAgLnByb2NfcmVhZCAgICAgID0gc2VxX3JlYWQsICAgICAgICAgICAg ICAgICAgICAgXA0KPiA+Pj4gKyAgICAgICAgICAgICAgIC5wcm9jX2xzZWVrICAgICA9IHNlcV9s c2VlaywgICAgICAgICAgICAgICAgICAgIFwNCj4gPj4+ICsgICAgICAgICAgICAgICAucHJvY19y ZWxlYXNlICAgPSBzaW5nbGVfcmVsZWFzZSwgICAgICAgICAgICAgICBcDQo+ID4+PiArICAgICAg ICAgICAgICAgLnByb2Nfd3JpdGUgICAgID0gbmFtZSAjIyBfcHJvY193cml0ZSwgICAgICAgICAg XA0KPiA+Pj4gKyAgICAgICB9DQo+ID4+PiArDQo+ID4+PiArI2RlZmluZSBwcm9jX2ZvcHNfcm8o bmFtZSkgXA0KPiA+Pj4gKyAgICAgICBzdGF0aWMgaW50IG5hbWUgIyMgX3Byb2Nfb3BlbihzdHJ1 Y3QgaW5vZGUgKmlub2RlLCAgICAgIFwNCj4gPj4+ICsgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgc3RydWN0IGZpbGUgKmZpbGUpICAgICAgICBcDQo+ID4+PiArICAgICAgIHsg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgXA0K PiA+Pj4gKyAgICAgICAgICAgICAgIHJldHVybiBzaW5nbGVfb3BlbihmaWxlLCBuYW1lICMjIF9w cm9jX3Nob3csICAgIFwNCj4gPj4+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg UERFX0RBVEEoaW5vZGUpKTsgICAgICAgICAgICBcDQo+ID4+PiArICAgICAgIH0gICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgXA0KPiA+Pj4gKyAg ICAgICBzdGF0aWMgY29uc3Qgc3RydWN0IHByb2Nfb3BzIG5hbWUgIyMgX3Byb2NfZm9wcyA9IHsg ICAgIFwNCj4gPj4+ICsgICAgICAgICAgICAgICAucHJvY19vcGVuICAgICAgPSBuYW1lICMjIF9w cm9jX29wZW4sICAgICAgICAgICBcDQo+ID4+PiArICAgICAgICAgICAgICAgLnByb2NfcmVhZCAg ICAgID0gc2VxX3JlYWQsICAgICAgICAgICAgICAgICAgICAgXA0KPiA+Pj4gKyAgICAgICAgICAg ICAgIC5wcm9jX2xzZWVrICAgICA9IHNlcV9sc2VlaywgICAgICAgICAgICAgICAgICAgIFwNCj4g Pj4+ICsgICAgICAgICAgICAgICAucHJvY19yZWxlYXNlICAgPSBzaW5nbGVfcmVsZWFzZSwgICAg ICAgICAgICAgICBcDQo+ID4+PiArICAgICAgIH0NCj4gPj4+ICsNCj4gPj4+ICsjZGVmaW5lIHBy b2NfZW50cnkobmFtZSkgICAgICAge19fc3RyaW5naWZ5KG5hbWUpLCAmbmFtZSAjIyBfcHJvY19m b3BzfQ0KPiA+Pj4gKw0KPiA+Pg0KPiA+PiAvcHJvYyBpcyB1c3VhbGx5IHRoZSBvbGQgd2F5IG9m IGV4cG9ydGluZyBmaWxlcyB0byB1c2Vyc3BhY2UsIHNvDQo+ID4+IHVubGVzcyB5b3UgaGF2ZSBh IHJlYWxseSBnb29kIHJlYXNvbiB1c2Ugc3lzZnMgaW5zdGVhZCwgb3IgZXZlbg0KPiA+PiBiZXR0 ZXIsIGlmIGl0IGlzIG9ubHkgZm9yIGRlYnVnIHB1cnBvc2VzIHVzZSBkZWJ1Z2ZzLiBBbHNvLCB5 b3Ugc2hvdWxkDQo+ID4+IGRvY3VtZW50IHRoZSBlbnRyaWVzIGluIERvY3VtZW50YXRpb24uDQo+ ID4gDQo+ID4gT2suIEknbGwgY2hhbmdlIGl0IHRvIGRlYnVnZnMgYW5kIGNvdWxkIHlvdSBnaXZl IHVzIGFuIGV4YW1wbGUgYWJvdXQgZW50cmllcyBpbiBkb2N1bWVudGF0aW9uPw0KPiA+IFdlIGNh biBmb2xsb3cgdGhlbS4gVGhhbmtzLg0KPiA+IA0KPiA+Pg0KPiA+Pj4gK3N0YXRpYyBERUZJTkVf U1BJTkxPQ0sobXRrX3N2c19sb2NrKTsNCj4gPj4+ICtzdHJ1Y3QgbXRrX3N2czsNCj4gPj4+ICsN Cj4gPj4+ICtlbnVtIHN2c2JfcGhhc2Ugew0KPiA+Pg0KPiA+PiBuaXQ6IG10a19zdnNfYnBoYXNl Pw0KPiA+IA0KPiA+IGRpdHRvDQo+ID4gDQo+ID4+DQo+ID4+PiArICAgICAgIFNWU0JfUEhBU0Vf SU5JVDAxID0gMCwNCj4gPj4NCj4gPj4gbml0OiBTVlNfQlBIQVNFXz8NCj4gPiANCj4gPiBkaXR0 bw0KPiA+IA0KPiA+Pg0KPiA+Pj4gKyAgICAgICBTVlNCX1BIQVNFX0lOSVQwMiwNCj4gPj4+ICsg ICAgICAgU1ZTQl9QSEFTRV9NT04sDQo+ID4+PiArICAgICAgIFNWU0JfUEhBU0VfRVJST1IsDQo+ ID4+PiArfTsNCj4gPj4+ICsNCj4gPj4+ICtlbnVtIHJlZ19pbmRleCB7DQo+ID4+DQo+ID4+IG5p dDogc3ZzX3JlZ19pbmRleD8NCj4gPiANCj4gPiBPSy4gVGhhbmtzLg0KPiA+IA0KPiA+Pg0KPiA+ Pj4gKyAgICAgICBURU1QTU9OQ1RMMCA9IDAsDQo+ID4+PiArICAgICAgIFRFTVBNT05DVEwxLA0K PiA+Pj4gKyAgICAgICBURU1QTU9OQ1RMMiwNCj4gPj4+ICsgICAgICAgVEVNUE1PTklOVCwNCj4g Pj4+ICsgICAgICAgVEVNUE1PTklOVFNUUywNCj4gPj4+ICsgICAgICAgVEVNUE1PTklERVQwLA0K PiA+Pj4gKyAgICAgICBURU1QTU9OSURFVDEsDQo+ID4+PiArICAgICAgIFRFTVBNT05JREVUMiwN Cj4gPj4+ICsgICAgICAgVEVNUEgyTlRIUkUsDQo+ID4+PiArICAgICAgIFRFTVBIVEhSRSwNCj4g Pj4+ICsgICAgICAgVEVNUENUSFJFLA0KPiA+Pj4gKyAgICAgICBURU1QT0ZGU0VUSCwNCj4gPj4+ ICsgICAgICAgVEVNUE9GRlNFVEwsDQo+ID4+PiArICAgICAgIFRFTVBNU1JDVEwwLA0KPiA+Pj4g KyAgICAgICBURU1QTVNSQ1RMMSwNCj4gPj4+ICsgICAgICAgVEVNUEFIQlBPTEwsDQo+ID4+PiAr ICAgICAgIFRFTVBBSEJUTywNCj4gPj4+ICsgICAgICAgVEVNUEFEQ1BOUDAsDQo+ID4+PiArICAg ICAgIFRFTVBBRENQTlAxLA0KPiA+Pj4gKyAgICAgICBURU1QQURDUE5QMiwNCj4gPj4+ICsgICAg ICAgVEVNUEFEQ01VWCwNCj4gPj4+ICsgICAgICAgVEVNUEFEQ0VYVCwNCj4gPj4+ICsgICAgICAg VEVNUEFEQ0VYVDEsDQo+ID4+PiArICAgICAgIFRFTVBBRENFTiwNCj4gPj4+ICsgICAgICAgVEVN UFBOUE1VWEFERFIsDQo+ID4+PiArICAgICAgIFRFTVBBRENNVVhBRERSLA0KPiA+Pj4gKyAgICAg ICBURU1QQURDRVhUQUREUiwNCj4gPj4+ICsgICAgICAgVEVNUEFEQ0VYVDFBRERSLA0KPiA+Pj4g KyAgICAgICBURU1QQURDRU5BRERSLA0KPiA+Pj4gKyAgICAgICBURU1QQURDVkFMSURBRERSLA0K PiA+Pj4gKyAgICAgICBURU1QQURDVk9MVEFERFIsDQo+ID4+PiArICAgICAgIFRFTVBSRENUUkws DQo+ID4+PiArICAgICAgIFRFTVBBRENWQUxJRE1BU0ssDQo+ID4+PiArICAgICAgIFRFTVBBRENW T0xUQUdFU0hJRlQsDQo+ID4+PiArICAgICAgIFRFTVBBRENXUklURUNUUkwsDQo+ID4+PiArICAg ICAgIFRFTVBNU1IwLA0KPiA+Pj4gKyAgICAgICBURU1QTVNSMSwNCj4gPj4+ICsgICAgICAgVEVN UE1TUjIsDQo+ID4+PiArICAgICAgIFRFTVBBRENIQUREUiwNCj4gPj4+ICsgICAgICAgVEVNUElN TUQwLA0KPiA+Pj4gKyAgICAgICBURU1QSU1NRDEsDQo+ID4+PiArICAgICAgIFRFTVBJTU1EMiwN Cj4gPj4+ICsgICAgICAgVEVNUE1PTklERVQzLA0KPiA+Pj4gKyAgICAgICBURU1QQURDUE5QMywN Cj4gPj4+ICsgICAgICAgVEVNUE1TUjMsDQo+ID4+PiArICAgICAgIFRFTVBJTU1EMywNCj4gPj4+ ICsgICAgICAgVEVNUFBST1RDVEwsDQo+ID4+PiArICAgICAgIFRFTVBQUk9UVEEsDQo+ID4+PiAr ICAgICAgIFRFTVBQUk9UVEIsDQo+ID4+PiArICAgICAgIFRFTVBQUk9UVEMsDQo+ID4+PiArICAg ICAgIFRFTVBTUEFSRTAsDQo+ID4+PiArICAgICAgIFRFTVBTUEFSRTEsDQo+ID4+PiArICAgICAg IFRFTVBTUEFSRTIsDQo+ID4+PiArICAgICAgIFRFTVBTUEFSRTMsDQo+ID4+PiArICAgICAgIFRF TVBNU1IwXzEsDQo+ID4+PiArICAgICAgIFRFTVBNU1IxXzEsDQo+ID4+PiArICAgICAgIFRFTVBN U1IyXzEsDQo+ID4+PiArICAgICAgIFRFTVBNU1IzXzEsDQo+ID4+PiArICAgICAgIERFU0NIQVIs DQo+ID4+PiArICAgICAgIFRFTVBDSEFSLA0KPiA+Pj4gKyAgICAgICBERVRDSEFSLA0KPiA+Pj4g KyAgICAgICBBR0VDSEFSLA0KPiA+Pj4gKyAgICAgICBEQ0NPTkZJRywNCj4gPj4+ICsgICAgICAg QUdFQ09ORklHLA0KPiA+Pj4gKyAgICAgICBGUkVRUENUMzAsDQo+ID4+PiArICAgICAgIEZSRVFQ Q1Q3NCwNCj4gPj4+ICsgICAgICAgTElNSVRWQUxTLA0KPiA+Pj4gKyAgICAgICBWQk9PVCwNCj4g Pj4+ICsgICAgICAgREVUV0lORE9XLA0KPiA+Pj4gKyAgICAgICBDT05GSUcsDQo+ID4+PiArICAg ICAgIFRTQ0FMQ1MsDQo+ID4+PiArICAgICAgIFJVTkNPTkZJRywNCj4gPj4+ICsgICAgICAgU1ZT RU4sDQo+ID4+PiArICAgICAgIElOSVQyVkFMUywNCj4gPj4+ICsgICAgICAgRENWQUxVRVMsDQo+ ID4+PiArICAgICAgIEFHRVZBTFVFUywNCj4gPj4+ICsgICAgICAgVk9QMzAsDQo+ID4+PiArICAg ICAgIFZPUDc0LA0KPiA+Pj4gKyAgICAgICBURU1QLA0KPiA+Pj4gKyAgICAgICBJTlRTVFMsDQo+ ID4+PiArICAgICAgIElOVFNUU1JBVywNCj4gPj4+ICsgICAgICAgSU5URU4sDQo+ID4+PiArICAg ICAgIENIS0lOVCwNCj4gPj4+ICsgICAgICAgQ0hLU0hJRlQsDQo+ID4+PiArICAgICAgIFNUQVRV UywNCj4gPj4+ICsgICAgICAgVkRFU0lHTjMwLA0KPiA+Pj4gKyAgICAgICBWREVTSUdONzQsDQo+ ID4+PiArICAgICAgIERWVDMwLA0KPiA+Pj4gKyAgICAgICBEVlQ3NCwNCj4gPj4+ICsgICAgICAg QUdFQ09VTlQsDQo+ID4+PiArICAgICAgIFNNU1RBVEUwLA0KPiA+Pj4gKyAgICAgICBTTVNUQVRF MSwNCj4gPj4+ICsgICAgICAgQ1RMMCwNCj4gPj4+ICsgICAgICAgREVTREVUU0VDLA0KPiA+Pj4g KyAgICAgICBURU1QQUdFU0VDLA0KPiA+Pj4gKyAgICAgICBDVFJMU1BBUkUwLA0KPiA+Pj4gKyAg ICAgICBDVFJMU1BBUkUxLA0KPiA+Pj4gKyAgICAgICBDVFJMU1BBUkUyLA0KPiA+Pj4gKyAgICAg ICBDVFJMU1BBUkUzLA0KPiA+Pj4gKyAgICAgICBDT1JFU0VMLA0KPiA+Pj4gKyAgICAgICBUSEVS TUlOVFNULA0KPiA+Pj4gKyAgICAgICBJTlRTVCwNCj4gPj4+ICsgICAgICAgVEhTVEFHRTBTVCwN Cj4gPj4+ICsgICAgICAgVEhTVEFHRTFTVCwNCj4gPj4+ICsgICAgICAgVEhTVEFHRTJTVCwNCj4g Pj4+ICsgICAgICAgVEhBSEJTVDAsDQo+ID4+PiArICAgICAgIFRIQUhCU1QxLA0KPiA+Pj4gKyAg ICAgICBTUEFSRTAsDQo+ID4+PiArICAgICAgIFNQQVJFMSwNCj4gPj4+ICsgICAgICAgU1BBUkUy LA0KPiA+Pj4gKyAgICAgICBTUEFSRTMsDQo+ID4+PiArICAgICAgIFRIU0xQRVZFQiwNCj4gPj4+ ICsgICAgICAgcmVnX251bSwNCj4gPj4+ICt9Ow0KPiA+Pj4gKw0KPiA+Pj4gK3N0YXRpYyBjb25z dCB1MzIgc3ZzX3JlZ3NfdjJbXSA9IHsNCj4gPj4NCj4gPj4gSXMgdGhpcyBTb0Mgc3BlY2lmaWMg b3Igc2hhcmVkIGJldHdlZW4gU29Dcz8NCj4gPiANCj4gPiBTaGFyZWQgYmV0d2VlbiBTb0NzLiBT b21lIFNWUyBpbiBNVEsgU29DcyB1c2UgdjIgcmVnaXN0ZXIgbWFwLg0KPiA+IA0KPiANCj4gQW5k IHdoaWNoIHNpbGljb24gdXNlcyB2MSB0aGVuPyBJcyB2MiBhIE1lZGlhVGVrIGludGVybmFsIG5h bWluZyB5b3Ugd2FudCB0byBrZWVwPw0KDQoxLiBNVDgxNzMgSUMgdXNlcyB2MSByZWdpc3RlciBt YXAuIA0KMi4gWWVzLCBJJ2xsIGtlZXAgdjIgcG9zdGZpeC4NCg0KPiANCj4gPj4NCj4gPj4+ICsg ICAgICAgW1RFTVBNT05DVEwwXSAgICAgICAgICAgPSAweDAwMCwNCj4gPj4+ICsgICAgICAgW1RF TVBNT05DVEwxXSAgICAgICAgICAgPSAweDAwNCwNCj4gPj4+ICsgICAgICAgW1RFTVBNT05DVEwy XSAgICAgICAgICAgPSAweDAwOCwNCj4gPj4+ICsgICAgICAgW1RFTVBNT05JTlRdICAgICAgICAg ICAgPSAweDAwYywNCj4gPj4+ICsgICAgICAgW1RFTVBNT05JTlRTVFNdICAgICAgICAgPSAweDAx MCwNCj4gPj4+ICsgICAgICAgW1RFTVBNT05JREVUMF0gICAgICAgICAgPSAweDAxNCwNCj4gPj4+ ICsgICAgICAgW1RFTVBNT05JREVUMV0gICAgICAgICAgPSAweDAxOCwNCj4gPj4+ICsgICAgICAg W1RFTVBNT05JREVUMl0gICAgICAgICAgPSAweDAxYywNCj4gPj4+ICsgICAgICAgW1RFTVBIMk5U SFJFXSAgICAgICAgICAgPSAweDAyNCwNCj4gPj4+ICsgICAgICAgW1RFTVBIVEhSRV0gICAgICAg ICAgICAgPSAweDAyOCwNCj4gPj4+ICsgICAgICAgW1RFTVBDVEhSRV0gICAgICAgICAgICAgPSAw eDAyYywNCj4gPj4+ICsgICAgICAgW1RFTVBPRkZTRVRIXSAgICAgICAgICAgPSAweDAzMCwNCj4g Pj4+ICsgICAgICAgW1RFTVBPRkZTRVRMXSAgICAgICAgICAgPSAweDAzNCwNCj4gPj4+ICsgICAg ICAgW1RFTVBNU1JDVEwwXSAgICAgICAgICAgPSAweDAzOCwNCj4gPj4+ICsgICAgICAgW1RFTVBN U1JDVEwxXSAgICAgICAgICAgPSAweDAzYywNCj4gPj4+ICsgICAgICAgW1RFTVBBSEJQT0xMXSAg ICAgICAgICAgPSAweDA0MCwNCj4gPj4+ICsgICAgICAgW1RFTVBBSEJUT10gICAgICAgICAgICAg PSAweDA0NCwNCj4gPj4+ICsgICAgICAgW1RFTVBBRENQTlAwXSAgICAgICAgICAgPSAweDA0OCwN Cj4gPj4+ICsgICAgICAgW1RFTVBBRENQTlAxXSAgICAgICAgICAgPSAweDA0YywNCj4gPj4+ICsg ICAgICAgW1RFTVBBRENQTlAyXSAgICAgICAgICAgPSAweDA1MCwNCj4gPj4+ICsgICAgICAgW1RF TVBBRENNVVhdICAgICAgICAgICAgPSAweDA1NCwNCj4gPj4+ICsgICAgICAgW1RFTVBBRENFWFRd ICAgICAgICAgICAgPSAweDA1OCwNCj4gPj4+ICsgICAgICAgW1RFTVBBRENFWFQxXSAgICAgICAg ICAgPSAweDA1YywNCj4gPj4+ICsgICAgICAgW1RFTVBBRENFTl0gICAgICAgICAgICAgPSAweDA2 MCwNCj4gPj4+ICsgICAgICAgW1RFTVBQTlBNVVhBRERSXSAgICAgICAgPSAweDA2NCwNCj4gPj4+ ICsgICAgICAgW1RFTVBBRENNVVhBRERSXSAgICAgICAgPSAweDA2OCwNCj4gPj4+ICsgICAgICAg W1RFTVBBRENFWFRBRERSXSAgICAgICAgPSAweDA2YywNCj4gPj4+ICsgICAgICAgW1RFTVBBRENF WFQxQUREUl0gICAgICAgPSAweDA3MCwNCj4gPj4+ICsgICAgICAgW1RFTVBBRENFTkFERFJdICAg ICAgICAgPSAweDA3NCwNCj4gPj4+ICsgICAgICAgW1RFTVBBRENWQUxJREFERFJdICAgICAgPSAw eDA3OCwNCj4gPj4+ICsgICAgICAgW1RFTVBBRENWT0xUQUREUl0gICAgICAgPSAweDA3YywNCj4g Pj4+ICsgICAgICAgW1RFTVBSRENUUkxdICAgICAgICAgICAgPSAweDA4MCwNCj4gPj4+ICsgICAg ICAgW1RFTVBBRENWQUxJRE1BU0tdICAgICAgPSAweDA4NCwNCj4gPj4+ICsgICAgICAgW1RFTVBB RENWT0xUQUdFU0hJRlRdICAgPSAweDA4OCwNCj4gPj4+ICsgICAgICAgW1RFTVBBRENXUklURUNU UkxdICAgICAgPSAweDA4YywNCj4gPj4+ICsgICAgICAgW1RFTVBNU1IwXSAgICAgICAgICAgICAg PSAweDA5MCwNCj4gPj4+ICsgICAgICAgW1RFTVBNU1IxXSAgICAgICAgICAgICAgPSAweDA5NCwN Cj4gPj4+ICsgICAgICAgW1RFTVBNU1IyXSAgICAgICAgICAgICAgPSAweDA5OCwNCj4gPj4+ICsg ICAgICAgW1RFTVBBRENIQUREUl0gICAgICAgICAgPSAweDA5YywNCj4gPj4+ICsgICAgICAgW1RF TVBJTU1EMF0gICAgICAgICAgICAgPSAweDBhMCwNCj4gPj4+ICsgICAgICAgW1RFTVBJTU1EMV0g ICAgICAgICAgICAgPSAweDBhNCwNCj4gPj4+ICsgICAgICAgW1RFTVBJTU1EMl0gICAgICAgICAg ICAgPSAweDBhOCwNCj4gPj4+ICsgICAgICAgW1RFTVBNT05JREVUM10gICAgICAgICAgPSAweDBi MCwNCj4gPj4+ICsgICAgICAgW1RFTVBBRENQTlAzXSAgICAgICAgICAgPSAweDBiNCwNCj4gPj4+ ICsgICAgICAgW1RFTVBNU1IzXSAgICAgICAgICAgICAgPSAweDBiOCwNCj4gPj4+ICsgICAgICAg W1RFTVBJTU1EM10gICAgICAgICAgICAgPSAweDBiYywNCj4gPj4+ICsgICAgICAgW1RFTVBQUk9U Q1RMXSAgICAgICAgICAgPSAweDBjMCwNCj4gPj4+ICsgICAgICAgW1RFTVBQUk9UVEFdICAgICAg ICAgICAgPSAweDBjNCwNCj4gPj4+ICsgICAgICAgW1RFTVBQUk9UVEJdICAgICAgICAgICAgPSAw eDBjOCwNCj4gPj4+ICsgICAgICAgW1RFTVBQUk9UVENdICAgICAgICAgICAgPSAweDBjYywNCj4g Pj4+ICsgICAgICAgW1RFTVBTUEFSRTBdICAgICAgICAgICAgPSAweDBmMCwNCj4gPj4+ICsgICAg ICAgW1RFTVBTUEFSRTFdICAgICAgICAgICAgPSAweDBmNCwNCj4gPj4+ICsgICAgICAgW1RFTVBT UEFSRTJdICAgICAgICAgICAgPSAweDBmOCwNCj4gPj4+ICsgICAgICAgW1RFTVBTUEFSRTNdICAg ICAgICAgICAgPSAweDBmYywNCj4gPj4+ICsgICAgICAgW1RFTVBNU1IwXzFdICAgICAgICAgICAg PSAweDE5MCwNCj4gPj4+ICsgICAgICAgW1RFTVBNU1IxXzFdICAgICAgICAgICAgPSAweDE5NCwN Cj4gPj4+ICsgICAgICAgW1RFTVBNU1IyXzFdICAgICAgICAgICAgPSAweDE5OCwNCj4gPj4+ICsg ICAgICAgW1RFTVBNU1IzXzFdICAgICAgICAgICAgPSAweDFiOCwNCj4gPj4+ICsgICAgICAgW0RF U0NIQVJdICAgICAgICAgICAgICAgPSAweGMwMCwNCj4gPj4+ICsgICAgICAgW1RFTVBDSEFSXSAg ICAgICAgICAgICAgPSAweGMwNCwNCj4gPj4+ICsgICAgICAgW0RFVENIQVJdICAgICAgICAgICAg ICAgPSAweGMwOCwNCj4gPj4+ICsgICAgICAgW0FHRUNIQVJdICAgICAgICAgICAgICAgPSAweGMw YywNCj4gPj4+ICsgICAgICAgW0RDQ09ORklHXSAgICAgICAgICAgICAgPSAweGMxMCwNCj4gPj4+ ICsgICAgICAgW0FHRUNPTkZJR10gICAgICAgICAgICAgPSAweGMxNCwNCj4gPj4+ICsgICAgICAg W0ZSRVFQQ1QzMF0gICAgICAgICAgICAgPSAweGMxOCwNCj4gPj4+ICsgICAgICAgW0ZSRVFQQ1Q3 NF0gICAgICAgICAgICAgPSAweGMxYywNCj4gPj4+ICsgICAgICAgW0xJTUlUVkFMU10gICAgICAg ICAgICAgPSAweGMyMCwNCj4gPj4+ICsgICAgICAgW1ZCT09UXSAgICAgICAgICAgICAgICAgPSAw eGMyNCwNCj4gPj4+ICsgICAgICAgW0RFVFdJTkRPV10gICAgICAgICAgICAgPSAweGMyOCwNCj4g Pj4+ICsgICAgICAgW0NPTkZJR10gICAgICAgICAgICAgICAgPSAweGMyYywNCj4gPj4+ICsgICAg ICAgW1RTQ0FMQ1NdICAgICAgICAgICAgICAgPSAweGMzMCwNCj4gPj4+ICsgICAgICAgW1JVTkNP TkZJR10gICAgICAgICAgICAgPSAweGMzNCwNCj4gPj4+ICsgICAgICAgW1NWU0VOXSAgICAgICAg ICAgICAgICAgPSAweGMzOCwNCj4gPj4+ICsgICAgICAgW0lOSVQyVkFMU10gICAgICAgICAgICAg PSAweGMzYywNCj4gPj4+ICsgICAgICAgW0RDVkFMVUVTXSAgICAgICAgICAgICAgPSAweGM0MCwN Cj4gPj4+ICsgICAgICAgW0FHRVZBTFVFU10gICAgICAgICAgICAgPSAweGM0NCwNCj4gPj4+ICsg ICAgICAgW1ZPUDMwXSAgICAgICAgICAgICAgICAgPSAweGM0OCwNCj4gPj4+ICsgICAgICAgW1ZP UDc0XSAgICAgICAgICAgICAgICAgPSAweGM0YywNCj4gPj4+ICsgICAgICAgW1RFTVBdICAgICAg ICAgICAgICAgICAgPSAweGM1MCwNCj4gPj4+ICsgICAgICAgW0lOVFNUU10gICAgICAgICAgICAg ICAgPSAweGM1NCwNCj4gPj4+ICsgICAgICAgW0lOVFNUU1JBV10gICAgICAgICAgICAgPSAweGM1 OCwNCj4gPj4+ICsgICAgICAgW0lOVEVOXSAgICAgICAgICAgICAgICAgPSAweGM1YywNCj4gPj4+ ICsgICAgICAgW0NIS0lOVF0gICAgICAgICAgICAgICAgPSAweGM2MCwNCj4gPj4+ICsgICAgICAg W0NIS1NISUZUXSAgICAgICAgICAgICAgPSAweGM2NCwNCj4gPj4+ICsgICAgICAgW1NUQVRVU10g ICAgICAgICAgICAgICAgPSAweGM2OCwNCj4gPj4+ICsgICAgICAgW1ZERVNJR04zMF0gICAgICAg ICAgICAgPSAweGM2YywNCj4gPj4+ICsgICAgICAgW1ZERVNJR043NF0gICAgICAgICAgICAgPSAw eGM3MCwNCj4gPj4+ICsgICAgICAgW0RWVDMwXSAgICAgICAgICAgICAgICAgPSAweGM3NCwNCj4g Pj4+ICsgICAgICAgW0RWVDc0XSAgICAgICAgICAgICAgICAgPSAweGM3OCwNCj4gPj4+ICsgICAg ICAgW0FHRUNPVU5UXSAgICAgICAgICAgICAgPSAweGM3YywNCj4gPj4+ICsgICAgICAgW1NNU1RB VEUwXSAgICAgICAgICAgICAgPSAweGM4MCwNCj4gPj4+ICsgICAgICAgW1NNU1RBVEUxXSAgICAg ICAgICAgICAgPSAweGM4NCwNCj4gPj4+ICsgICAgICAgW0NUTDBdICAgICAgICAgICAgICAgICAg PSAweGM4OCwNCj4gPj4+ICsgICAgICAgW0RFU0RFVFNFQ10gICAgICAgICAgICAgPSAweGNlMCwN Cj4gPj4+ICsgICAgICAgW1RFTVBBR0VTRUNdICAgICAgICAgICAgPSAweGNlNCwNCj4gPj4+ICsg ICAgICAgW0NUUkxTUEFSRTBdICAgICAgICAgICAgPSAweGNmMCwNCj4gPj4+ICsgICAgICAgW0NU UkxTUEFSRTFdICAgICAgICAgICAgPSAweGNmNCwNCj4gPj4+ICsgICAgICAgW0NUUkxTUEFSRTJd ICAgICAgICAgICAgPSAweGNmOCwNCj4gPj4+ICsgICAgICAgW0NUUkxTUEFSRTNdICAgICAgICAg ICAgPSAweGNmYywNCj4gPj4+ICsgICAgICAgW0NPUkVTRUxdICAgICAgICAgICAgICAgPSAweGYw MCwNCj4gPj4+ICsgICAgICAgW1RIRVJNSU5UU1RdICAgICAgICAgICAgPSAweGYwNCwNCj4gPj4+ ICsgICAgICAgW0lOVFNUXSAgICAgICAgICAgICAgICAgPSAweGYwOCwNCj4gPj4+ICsgICAgICAg W1RIU1RBR0UwU1RdICAgICAgICAgICAgPSAweGYwYywNCj4gPj4+ICsgICAgICAgW1RIU1RBR0Ux U1RdICAgICAgICAgICAgPSAweGYxMCwNCj4gPj4+ICsgICAgICAgW1RIU1RBR0UyU1RdICAgICAg ICAgICAgPSAweGYxNCwNCj4gPj4+ICsgICAgICAgW1RIQUhCU1QwXSAgICAgICAgICAgICAgPSAw eGYxOCwNCj4gPj4+ICsgICAgICAgW1RIQUhCU1QxXSAgICAgICAgICAgICAgPSAweGYxYywNCj4g Pj4+ICsgICAgICAgW1NQQVJFMF0gICAgICAgICAgICAgICAgPSAweGYyMCwNCj4gPj4+ICsgICAg ICAgW1NQQVJFMV0gICAgICAgICAgICAgICAgPSAweGYyNCwNCj4gPj4+ICsgICAgICAgW1NQQVJF Ml0gICAgICAgICAgICAgICAgPSAweGYyOCwNCj4gPj4+ICsgICAgICAgW1NQQVJFM10gICAgICAg ICAgICAgICAgPSAweGYyYywNCj4gPj4+ICsgICAgICAgW1RIU0xQRVZFQl0gICAgICAgICAgICAg PSAweGYzMCwNCj4gPj4+ICt9Ow0KPiA+Pj4gKw0KPiA+Pj4gK3N0cnVjdCB0aGVybWFsX3BhcmFt ZXRlciB7DQo+ID4+DQo+ID4+IEluIGdlbmVyYWwsIG5vdCBvbmx5IGluIHRoaXMgc3RydWN0LCB3 b3VsZCBiZSBnb29kIGhhdmUgc29tZQ0KPiA+PiBkb2N1bWVudGF0aW9uIHRvIGhhdmUgYSBiZXR0 ZXIgdW5kZXN0YW5kaW5nIG9mIHRoZSBmaWVsZHMuIFRoYXQgbWFrZXMNCj4gPj4gdGhlIGpvYiBv ZiB0aGUgcmV2aWV3ZXIgYSBiaXQgZWFzaWVyLg0KPiA+IA0KPiA+IE9rLiBDb3VsZCB5b3Ugc2hh cmUgYSBkb2N1bWVudGF0aW9uIGV4YW1wbGUgdG8gdXM/IFdlJ2xsIHNoYXJlIHRoZQ0KPiA+IGlu Zm9ybWF0aW9uIGFzIG11Y2ggYXMgd2UgY2FuLiBUaGFua3MgYSBsb3QuDQo+ID4gDQo+IA0KPiB5 b3Ugc2hvdWxkIGZpbmQgdGhhdCBpbiBhbGwgZHJpdmVycywgZWc6DQo+IGh0dHBzOi8vZWxpeGly LmJvb3RsaW4uY29tL2xpbnV4L2xhdGVzdC9zb3VyY2UvZHJpdmVycy9zb2MvbWVkaWF0ZWsvbXRr LXNjcHN5cy5jI0wxMTENCg0KTm8gcHJvYmxlbSBTaXIuIFRoYW5rcyBmb3Igc2hvd2luZyBhIGRp cmVjdGlvbiB0byBtZS4gSSdsbCB0YWtlIGEgbG9vaw0KYXQgaXQuDQoNCj4gDQo+IFJlZ2FyZHMs DQo+IE1hdHRoaWFzDQoNCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26F41C433DF for ; Tue, 26 May 2020 09:22:47 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E5028207ED for ; Tue, 26 May 2020 09:22:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Q4teJ5wY"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Rb2GH9Ew" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E5028207ED Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Date:To:From:Subject:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=CAi00OjnxVAWsVSNgbN475JNWymoqc7pgU/1ZMmKius=; b=Q4teJ5wY9fPYqm xvGAmGF2G7NE93wkg4aK8C4ZTtdpMfwmmHXUEXPUiZcyl7UMSCVqBVU8+bLyXJ1fwGrLEhKIjp1E1 th7/4e0CFg25JIliasdCMd3NVAkpCC36qpcNFeNJJlKMNUUlxsXB7DkkApCx4TdLIVColqTrChfNY IiA07hbLKO6od5LPHx6794ZiIRZIWmJT7ZLxb+H78wQabJ4nsGSVMPpfV27+A2X6e/rvdXOuYNEyh sEW6+UWmdhJEcoYn4FCm4wAxn4f6ThB1AOW9aRrp/Xg9vtsjO+yG0xHsvDYEycG9E4I6fFajVwBjP 8xN4+xWwGFAFJL3naLmg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jdVnA-0002OI-CJ; Tue, 26 May 2020 09:22:36 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jdVmt-0002BB-BM; Tue, 26 May 2020 09:22:21 +0000 X-UUID: 9e4c3c98654c4f0e968ec73826e05b18-20200526 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=gLvWi1nqtTxrY8+10s7N7a3KehB3j++1xRvGDtVazhY=; b=Rb2GH9EwZK3ETfLusjirYtuSWnmALYnlgFzpgoWXcsyyR58eT+ve6O3szIotCeTWYpK6doHc0I1gDwApu+g3qA+RokdWteEIqTQukoq0s+9bJ5pYMuFGbxpkTbkIqlUR3zMJUIHfHJ4JbISW3D6SsXVlO/4mSLCqh6u5NedDldM=; X-UUID: 9e4c3c98654c4f0e968ec73826e05b18-20200526 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1637176630; Tue, 26 May 2020 01:22:02 -0800 Received: from mtkmbs05n2.mediatek.inc (172.21.101.140) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 26 May 2020 02:12:07 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 26 May 2020 17:12:06 +0800 Received: from [172.21.77.4] (172.21.77.4) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 26 May 2020 17:12:06 +0800 Message-ID: <1590484328.4392.44.camel@mtksdaap41> Subject: Re: [PATCH v8 3/3] PM / AVS: SVS: Introduce SVS engine From: Roger Lu To: Matthias Brugger Date: Tue, 26 May 2020 17:12:08 +0800 In-Reply-To: <3b810588-ac4a-7fec-2163-38555dd83928@gmail.com> References: <20200518092403.22647-1-roger.lu@mediatek.com> <20200518092403.22647-4-roger.lu@mediatek.com> <1590140434.4392.22.camel@mtksdaap41> <3b810588-ac4a-7fec-2163-38555dd83928@gmail.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200526_022219_415497_0E4A28E1 X-CRM114-Status: GOOD ( 33.16 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Nicolas Boichat , Nishanth Menon , Kevin Hilman , Enric Balletbo Serra , Linux PM list , Angus Lin , Xiaoqing Liu , linux-kernel , Stephen Boyd , "devicetree@vger.kernel.org" , Rob Herring , "moderated list:ARM/Mediatek SoC support" , HenryC Chen , Charles Yang , YT Lee , Fan Chen , Linux ARM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Hi Matthias, Thanks for the feedback. On Fri, 2020-05-22 at 17:38 +0200, Matthias Brugger wrote: > > On 22/05/2020 11:40, Roger Lu wrote: > > > > Hi Enric, > > > > On Tue, 2020-05-19 at 17:30 +0200, Enric Balletbo Serra wrote: > >> Hi Roger, > >> > >> Thank you for your patch. I have the feeling that this driver is > >> complex and difficult to follow and I am wondering if it wouldn't be > >> better if you can send a version that simply adds basic functionality > >> for now. Some comments below. > > > > Thanks for the advices. I'll submit SVS v9 with basic functionality > > patch + step by step functionalities' patches. > > > >> > >> Missatge de Roger Lu del dia dl., 18 de maig > >> 2020 a les 11:25: > >>> > >>> The SVS (Smart Voltage Scaling) engine is a piece > >>> of hardware which is used to calculate optimized > >>> voltage values of several power domains, > >>> e.g. CPU/GPU/CCI, according to chip process corner, > >>> temperatures, and other factors. Then DVFS driver > >>> could apply those optimized voltage values to reduce > >>> power consumption. > >>> > >>> Signed-off-by: Roger Lu > >>> --- > >>> drivers/power/avs/Kconfig | 10 + > >>> drivers/power/avs/Makefile | 1 + > >>> drivers/power/avs/mtk_svs.c | 2119 +++++++++++++++++++++++++++++++++ > >>> include/linux/power/mtk_svs.h | 23 + > >>> 4 files changed, 2153 insertions(+) > >>> create mode 100644 drivers/power/avs/mtk_svs.c > >>> create mode 100644 include/linux/power/mtk_svs.h > >>> > >>> diff --git a/drivers/power/avs/Kconfig b/drivers/power/avs/Kconfig > >>> index cdb4237bfd02..67089ac6040e 100644 > >>> --- a/drivers/power/avs/Kconfig > >>> +++ b/drivers/power/avs/Kconfig > >>> @@ -35,3 +35,13 @@ config ROCKCHIP_IODOMAIN > >>> Say y here to enable support io domains on Rockchip SoCs. It is > >>> necessary for the io domain setting of the SoC to match the > >>> voltage supplied by the regulators. > >>> + > >>> +config MTK_SVS > >>> + bool "MediaTek Smart Voltage Scaling(SVS)" > >> > >> Can't be this a module? Why? In such case, you should use tristate option > > > > Generally, MTK_SVS is needed in MTK SoC(mt81xx) products. So, we don't provide > > module option in config. If, somehow, SVS isn't needed, we suggest > > CONFIG_MTK_SVS=n to be set. > > > > The question here is if it needs to be probed before we probe the modules. If > not, we should add a Kconfig option for MT81xx SoCs to select MTK_SVS. Excuse me to make you confuse. MT81xx SoCs is the subset MTK ICs that will use CONFIG_MTK_SVS. In other words, CONFIG_MTK_SVS will be used with other MTK ICs as well. So, MTK_SVS is the general naming for MTK IC to enable SVS power feature. Anyway, back to Enric's question, I'll make MTK_SVS become a tristate feature in the next patch. Thanks. > > >> > >>> + depends on POWER_AVS && MTK_EFUSE && NVMEM > >>> + help > >>> + The SVS engine is a piece of hardware which is used to calculate > >>> + optimized voltage values of several power domains, e.g. > >>> + CPU clusters/GPU/CCI, according to chip process corner, temperatures, > >>> + and other factors. Then DVFS driver could apply those optimized voltage > >>> + values to reduce power consumption. > >>> diff --git a/drivers/power/avs/Makefile b/drivers/power/avs/Makefile > >>> index 9007d05853e2..231adf078582 100644 > >>> --- a/drivers/power/avs/Makefile > >>> +++ b/drivers/power/avs/Makefile > >>> @@ -2,3 +2,4 @@ > >>> obj-$(CONFIG_POWER_AVS_OMAP) += smartreflex.o > >>> obj-$(CONFIG_QCOM_CPR) += qcom-cpr.o > >>> obj-$(CONFIG_ROCKCHIP_IODOMAIN) += rockchip-io-domain.o > >>> +obj-$(CONFIG_MTK_SVS) += mtk_svs.o > >> > >> Will this driver be SoC specific or the idea is to support different > >> SoCs? If the answer to the first question is yes, please name the file > >> with the SoC prefix (i.e mt8183_svs). However, If the answer to the > >> second question is yes, make sure you prefix common > >> functions/structs/defines with a generic prefix mtk_svs but use the > >> SoC prefix for the ones you expect will be different between SoC, i.e > >> mt8183_svs_. This helps the readability of the driver. Also, try to > >> avoid too generic names. > > > > MTK_SVS is designed for supporting different MTK SoCs.Therefore, the answer is second > > question and thanks for the heads-up. > > > >> > >>> diff --git a/drivers/power/avs/mtk_svs.c b/drivers/power/avs/mtk_svs.c > >>> new file mode 100644 > >>> index 000000000000..a4083b3ef175 > >>> --- /dev/null > >>> +++ b/drivers/power/avs/mtk_svs.c > >>> @@ -0,0 +1,2119 @@ > >>> +// SPDX-License-Identifier: GPL-2.0 > >> > >> I suspect you want this only GPLv2 compliant. Use GPL-2.0-only > > > > OK. I'll use GPL-2.0-only.Thanks. > > > >> > >>> +/* > >>> + * Copyright (C) 2020 MediaTek Inc. > >>> + */ > >>> + > >>> +#define pr_fmt(fmt) "[mtk_svs] " fmt > >> > >> I don't see any reason to use pr_fmt in this driver. Use dev_* > >> functions instead and remove the above. > > > > Ok. I will remove it. Thanks. > > > >> > >>> + > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> + > >>> +/* svs 1-line sw id */ > >>> +#define SVS_CPU_LITTLE BIT(0) > >>> +#define SVS_CPU_BIG BIT(1) > >>> +#define SVS_CCI BIT(2) > >>> +#define SVS_GPU BIT(3) > >>> + > >>> +/* svs bank mode support */ > >>> +#define SVSB_MODE_ALL_DISABLE (0) > >> > >> nit: SVS_BMODE_? > > > > Oh. If we add bank wording like SVS_Bxxx, it might cause some confusion when B combines > > with other words. So, I'll keep SVSB for SVS Bank representation. > > E.g: SVS_BDC_SIGNED_BIT might lead to be explained differently ("SVS bank + DC_SIGNED_BIT" or "SVS + BDC_SIGNED_BIT") > > - "SVS bank + DC_SIGNED_BIT" is what we want for naming SVS_BDC_SIGNED_BIT but it might be misunderstood. > > > >> > >>> +#define SVSB_MODE_INIT01 BIT(1) > >>> +#define SVSB_MODE_INIT02 BIT(2) > >>> +#define SVSB_MODE_MON BIT(3) > >>> + > >>> +/* svs bank init01 condition */ > >>> +#define SVSB_INIT01_VOLT_IGNORE BIT(1) > >>> +#define SVSB_INIT01_VOLT_INC_ONLY BIT(2) > >>> + > >>> +/* svs bank common setting */ > >>> +#define HIGH_TEMP_MAX (U32_MAX) > >> > >> nit: SVS_* > > > > ok. I will add SVS or SVSB when it refers to SVS BANK. > > > >> > >>> +#define RUNCONFIG_DEFAULT (0x80000000) > >> > >> Btw, there is any public datasheet where I can see those addresses and > >> registers and bit fields? > > > > Excuse us, there is no public datasheet. We can reply it on patchwork. Thanks. > > > >> > >>> +#define DC_SIGNED_BIT (0x8000) > >>> +#define INTEN_INIT0x (0x00005f01) > >>> +#define INTEN_MONVOPEN (0x00ff0000) > >>> +#define SVSEN_OFF (0x0) > >>> +#define SVSEN_MASK (0x7) > >>> +#define SVSEN_INIT01 (0x1) > >>> +#define SVSEN_INIT02 (0x5) > >>> +#define SVSEN_MON (0x2) > >>> +#define INTSTS_MONVOP (0x00ff0000) > >>> +#define INTSTS_COMPLETE (0x1) > >>> +#define INTSTS_CLEAN (0x00ffffff) > >>> + > >>> +#define proc_fops_rw(name) \ > >>> + static int name ## _proc_open(struct inode *inode, \ > >>> + struct file *file) \ > >>> + { \ > >>> + return single_open(file, name ## _proc_show, \ > >>> + PDE_DATA(inode)); \ > >>> + } \ > >>> + static const struct proc_ops name ## _proc_fops = { \ > >>> + .proc_open = name ## _proc_open, \ > >>> + .proc_read = seq_read, \ > >>> + .proc_lseek = seq_lseek, \ > >>> + .proc_release = single_release, \ > >>> + .proc_write = name ## _proc_write, \ > >>> + } > >>> + > >>> +#define proc_fops_ro(name) \ > >>> + static int name ## _proc_open(struct inode *inode, \ > >>> + struct file *file) \ > >>> + { \ > >>> + return single_open(file, name ## _proc_show, \ > >>> + PDE_DATA(inode)); \ > >>> + } \ > >>> + static const struct proc_ops name ## _proc_fops = { \ > >>> + .proc_open = name ## _proc_open, \ > >>> + .proc_read = seq_read, \ > >>> + .proc_lseek = seq_lseek, \ > >>> + .proc_release = single_release, \ > >>> + } > >>> + > >>> +#define proc_entry(name) {__stringify(name), &name ## _proc_fops} > >>> + > >> > >> /proc is usually the old way of exporting files to userspace, so > >> unless you have a really good reason use sysfs instead, or even > >> better, if it is only for debug purposes use debugfs. Also, you should > >> document the entries in Documentation. > > > > Ok. I'll change it to debugfs and could you give us an example about entries in documentation? > > We can follow them. Thanks. > > > >> > >>> +static DEFINE_SPINLOCK(mtk_svs_lock); > >>> +struct mtk_svs; > >>> + > >>> +enum svsb_phase { > >> > >> nit: mtk_svs_bphase? > > > > ditto > > > >> > >>> + SVSB_PHASE_INIT01 = 0, > >> > >> nit: SVS_BPHASE_? > > > > ditto > > > >> > >>> + SVSB_PHASE_INIT02, > >>> + SVSB_PHASE_MON, > >>> + SVSB_PHASE_ERROR, > >>> +}; > >>> + > >>> +enum reg_index { > >> > >> nit: svs_reg_index? > > > > OK. Thanks. > > > >> > >>> + TEMPMONCTL0 = 0, > >>> + TEMPMONCTL1, > >>> + TEMPMONCTL2, > >>> + TEMPMONINT, > >>> + TEMPMONINTSTS, > >>> + TEMPMONIDET0, > >>> + TEMPMONIDET1, > >>> + TEMPMONIDET2, > >>> + TEMPH2NTHRE, > >>> + TEMPHTHRE, > >>> + TEMPCTHRE, > >>> + TEMPOFFSETH, > >>> + TEMPOFFSETL, > >>> + TEMPMSRCTL0, > >>> + TEMPMSRCTL1, > >>> + TEMPAHBPOLL, > >>> + TEMPAHBTO, > >>> + TEMPADCPNP0, > >>> + TEMPADCPNP1, > >>> + TEMPADCPNP2, > >>> + TEMPADCMUX, > >>> + TEMPADCEXT, > >>> + TEMPADCEXT1, > >>> + TEMPADCEN, > >>> + TEMPPNPMUXADDR, > >>> + TEMPADCMUXADDR, > >>> + TEMPADCEXTADDR, > >>> + TEMPADCEXT1ADDR, > >>> + TEMPADCENADDR, > >>> + TEMPADCVALIDADDR, > >>> + TEMPADCVOLTADDR, > >>> + TEMPRDCTRL, > >>> + TEMPADCVALIDMASK, > >>> + TEMPADCVOLTAGESHIFT, > >>> + TEMPADCWRITECTRL, > >>> + TEMPMSR0, > >>> + TEMPMSR1, > >>> + TEMPMSR2, > >>> + TEMPADCHADDR, > >>> + TEMPIMMD0, > >>> + TEMPIMMD1, > >>> + TEMPIMMD2, > >>> + TEMPMONIDET3, > >>> + TEMPADCPNP3, > >>> + TEMPMSR3, > >>> + TEMPIMMD3, > >>> + TEMPPROTCTL, > >>> + TEMPPROTTA, > >>> + TEMPPROTTB, > >>> + TEMPPROTTC, > >>> + TEMPSPARE0, > >>> + TEMPSPARE1, > >>> + TEMPSPARE2, > >>> + TEMPSPARE3, > >>> + TEMPMSR0_1, > >>> + TEMPMSR1_1, > >>> + TEMPMSR2_1, > >>> + TEMPMSR3_1, > >>> + DESCHAR, > >>> + TEMPCHAR, > >>> + DETCHAR, > >>> + AGECHAR, > >>> + DCCONFIG, > >>> + AGECONFIG, > >>> + FREQPCT30, > >>> + FREQPCT74, > >>> + LIMITVALS, > >>> + VBOOT, > >>> + DETWINDOW, > >>> + CONFIG, > >>> + TSCALCS, > >>> + RUNCONFIG, > >>> + SVSEN, > >>> + INIT2VALS, > >>> + DCVALUES, > >>> + AGEVALUES, > >>> + VOP30, > >>> + VOP74, > >>> + TEMP, > >>> + INTSTS, > >>> + INTSTSRAW, > >>> + INTEN, > >>> + CHKINT, > >>> + CHKSHIFT, > >>> + STATUS, > >>> + VDESIGN30, > >>> + VDESIGN74, > >>> + DVT30, > >>> + DVT74, > >>> + AGECOUNT, > >>> + SMSTATE0, > >>> + SMSTATE1, > >>> + CTL0, > >>> + DESDETSEC, > >>> + TEMPAGESEC, > >>> + CTRLSPARE0, > >>> + CTRLSPARE1, > >>> + CTRLSPARE2, > >>> + CTRLSPARE3, > >>> + CORESEL, > >>> + THERMINTST, > >>> + INTST, > >>> + THSTAGE0ST, > >>> + THSTAGE1ST, > >>> + THSTAGE2ST, > >>> + THAHBST0, > >>> + THAHBST1, > >>> + SPARE0, > >>> + SPARE1, > >>> + SPARE2, > >>> + SPARE3, > >>> + THSLPEVEB, > >>> + reg_num, > >>> +}; > >>> + > >>> +static const u32 svs_regs_v2[] = { > >> > >> Is this SoC specific or shared between SoCs? > > > > Shared between SoCs. Some SVS in MTK SoCs use v2 register map. > > > > And which silicon uses v1 then? Is v2 a MediaTek internal naming you want to keep? 1. MT8173 IC uses v1 register map. 2. Yes, I'll keep v2 postfix. > > >> > >>> + [TEMPMONCTL0] = 0x000, > >>> + [TEMPMONCTL1] = 0x004, > >>> + [TEMPMONCTL2] = 0x008, > >>> + [TEMPMONINT] = 0x00c, > >>> + [TEMPMONINTSTS] = 0x010, > >>> + [TEMPMONIDET0] = 0x014, > >>> + [TEMPMONIDET1] = 0x018, > >>> + [TEMPMONIDET2] = 0x01c, > >>> + [TEMPH2NTHRE] = 0x024, > >>> + [TEMPHTHRE] = 0x028, > >>> + [TEMPCTHRE] = 0x02c, > >>> + [TEMPOFFSETH] = 0x030, > >>> + [TEMPOFFSETL] = 0x034, > >>> + [TEMPMSRCTL0] = 0x038, > >>> + [TEMPMSRCTL1] = 0x03c, > >>> + [TEMPAHBPOLL] = 0x040, > >>> + [TEMPAHBTO] = 0x044, > >>> + [TEMPADCPNP0] = 0x048, > >>> + [TEMPADCPNP1] = 0x04c, > >>> + [TEMPADCPNP2] = 0x050, > >>> + [TEMPADCMUX] = 0x054, > >>> + [TEMPADCEXT] = 0x058, > >>> + [TEMPADCEXT1] = 0x05c, > >>> + [TEMPADCEN] = 0x060, > >>> + [TEMPPNPMUXADDR] = 0x064, > >>> + [TEMPADCMUXADDR] = 0x068, > >>> + [TEMPADCEXTADDR] = 0x06c, > >>> + [TEMPADCEXT1ADDR] = 0x070, > >>> + [TEMPADCENADDR] = 0x074, > >>> + [TEMPADCVALIDADDR] = 0x078, > >>> + [TEMPADCVOLTADDR] = 0x07c, > >>> + [TEMPRDCTRL] = 0x080, > >>> + [TEMPADCVALIDMASK] = 0x084, > >>> + [TEMPADCVOLTAGESHIFT] = 0x088, > >>> + [TEMPADCWRITECTRL] = 0x08c, > >>> + [TEMPMSR0] = 0x090, > >>> + [TEMPMSR1] = 0x094, > >>> + [TEMPMSR2] = 0x098, > >>> + [TEMPADCHADDR] = 0x09c, > >>> + [TEMPIMMD0] = 0x0a0, > >>> + [TEMPIMMD1] = 0x0a4, > >>> + [TEMPIMMD2] = 0x0a8, > >>> + [TEMPMONIDET3] = 0x0b0, > >>> + [TEMPADCPNP3] = 0x0b4, > >>> + [TEMPMSR3] = 0x0b8, > >>> + [TEMPIMMD3] = 0x0bc, > >>> + [TEMPPROTCTL] = 0x0c0, > >>> + [TEMPPROTTA] = 0x0c4, > >>> + [TEMPPROTTB] = 0x0c8, > >>> + [TEMPPROTTC] = 0x0cc, > >>> + [TEMPSPARE0] = 0x0f0, > >>> + [TEMPSPARE1] = 0x0f4, > >>> + [TEMPSPARE2] = 0x0f8, > >>> + [TEMPSPARE3] = 0x0fc, > >>> + [TEMPMSR0_1] = 0x190, > >>> + [TEMPMSR1_1] = 0x194, > >>> + [TEMPMSR2_1] = 0x198, > >>> + [TEMPMSR3_1] = 0x1b8, > >>> + [DESCHAR] = 0xc00, > >>> + [TEMPCHAR] = 0xc04, > >>> + [DETCHAR] = 0xc08, > >>> + [AGECHAR] = 0xc0c, > >>> + [DCCONFIG] = 0xc10, > >>> + [AGECONFIG] = 0xc14, > >>> + [FREQPCT30] = 0xc18, > >>> + [FREQPCT74] = 0xc1c, > >>> + [LIMITVALS] = 0xc20, > >>> + [VBOOT] = 0xc24, > >>> + [DETWINDOW] = 0xc28, > >>> + [CONFIG] = 0xc2c, > >>> + [TSCALCS] = 0xc30, > >>> + [RUNCONFIG] = 0xc34, > >>> + [SVSEN] = 0xc38, > >>> + [INIT2VALS] = 0xc3c, > >>> + [DCVALUES] = 0xc40, > >>> + [AGEVALUES] = 0xc44, > >>> + [VOP30] = 0xc48, > >>> + [VOP74] = 0xc4c, > >>> + [TEMP] = 0xc50, > >>> + [INTSTS] = 0xc54, > >>> + [INTSTSRAW] = 0xc58, > >>> + [INTEN] = 0xc5c, > >>> + [CHKINT] = 0xc60, > >>> + [CHKSHIFT] = 0xc64, > >>> + [STATUS] = 0xc68, > >>> + [VDESIGN30] = 0xc6c, > >>> + [VDESIGN74] = 0xc70, > >>> + [DVT30] = 0xc74, > >>> + [DVT74] = 0xc78, > >>> + [AGECOUNT] = 0xc7c, > >>> + [SMSTATE0] = 0xc80, > >>> + [SMSTATE1] = 0xc84, > >>> + [CTL0] = 0xc88, > >>> + [DESDETSEC] = 0xce0, > >>> + [TEMPAGESEC] = 0xce4, > >>> + [CTRLSPARE0] = 0xcf0, > >>> + [CTRLSPARE1] = 0xcf4, > >>> + [CTRLSPARE2] = 0xcf8, > >>> + [CTRLSPARE3] = 0xcfc, > >>> + [CORESEL] = 0xf00, > >>> + [THERMINTST] = 0xf04, > >>> + [INTST] = 0xf08, > >>> + [THSTAGE0ST] = 0xf0c, > >>> + [THSTAGE1ST] = 0xf10, > >>> + [THSTAGE2ST] = 0xf14, > >>> + [THAHBST0] = 0xf18, > >>> + [THAHBST1] = 0xf1c, > >>> + [SPARE0] = 0xf20, > >>> + [SPARE1] = 0xf24, > >>> + [SPARE2] = 0xf28, > >>> + [SPARE3] = 0xf2c, > >>> + [THSLPEVEB] = 0xf30, > >>> +}; > >>> + > >>> +struct thermal_parameter { > >> > >> In general, not only in this struct, would be good have some > >> documentation to have a better undestanding of the fields. That makes > >> the job of the reviewer a bit easier. > > > > Ok. Could you share a documentation example to us? We'll share the > > information as much as we can. Thanks a lot. > > > > you should find that in all drivers, eg: > https://elixir.bootlin.com/linux/latest/source/drivers/soc/mediatek/mtk-scpsys.c#L111 No problem Sir. Thanks for showing a direction to me. I'll take a look at it. > > Regards, > Matthias _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34E8FC433E0 for ; Tue, 26 May 2020 09:22:24 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D2C79207CB for ; Tue, 26 May 2020 09:22:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="YSJcElmk"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Rb2GH9Ew" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D2C79207CB Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Date:To:From:Subject:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=A7wdHymu7CK/TLmtq1csLL0wzhxLC3Hj69tLpjpMVqI=; b=YSJcElmkryp5HL eDMV9gF38EVkXdr1jxi421XrP3kWIvBT4++hzW1M/r7DytLfL+VH5UFpPCpkGwxkMQy3DBkhR4Sjq NuS1iRPE7/uLpIR1IUN7RYgIpyVudrMjMGHLziwfJjYmVcYR5XgrXYvgNkc5jvqGm1EROjcX/BLqN 3DY9ynNJxKgcfUwCKm5w028FyacbbQC97rChHnkD85VNY9a2IeXdTBe1QUaK7qPDi5ddbb03onTLL sNRKeRNjjo0rqGxxkjgnaz9CSpQaeJwZUWKQFkuZ0IZMSxmghqoau/dGY6+Xg+I/IVZDM31Aam35N MapTD7leBj0y2ZQj3tgg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jdVmx-0002Co-Gp; Tue, 26 May 2020 09:22:23 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jdVmt-0002BB-BM; Tue, 26 May 2020 09:22:21 +0000 X-UUID: 9e4c3c98654c4f0e968ec73826e05b18-20200526 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=gLvWi1nqtTxrY8+10s7N7a3KehB3j++1xRvGDtVazhY=; b=Rb2GH9EwZK3ETfLusjirYtuSWnmALYnlgFzpgoWXcsyyR58eT+ve6O3szIotCeTWYpK6doHc0I1gDwApu+g3qA+RokdWteEIqTQukoq0s+9bJ5pYMuFGbxpkTbkIqlUR3zMJUIHfHJ4JbISW3D6SsXVlO/4mSLCqh6u5NedDldM=; X-UUID: 9e4c3c98654c4f0e968ec73826e05b18-20200526 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1637176630; Tue, 26 May 2020 01:22:02 -0800 Received: from mtkmbs05n2.mediatek.inc (172.21.101.140) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 26 May 2020 02:12:07 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 26 May 2020 17:12:06 +0800 Received: from [172.21.77.4] (172.21.77.4) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 26 May 2020 17:12:06 +0800 Message-ID: <1590484328.4392.44.camel@mtksdaap41> Subject: Re: [PATCH v8 3/3] PM / AVS: SVS: Introduce SVS engine From: Roger Lu To: Matthias Brugger Date: Tue, 26 May 2020 17:12:08 +0800 In-Reply-To: <3b810588-ac4a-7fec-2163-38555dd83928@gmail.com> References: <20200518092403.22647-1-roger.lu@mediatek.com> <20200518092403.22647-4-roger.lu@mediatek.com> <1590140434.4392.22.camel@mtksdaap41> <3b810588-ac4a-7fec-2163-38555dd83928@gmail.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200526_022219_415497_0E4A28E1 X-CRM114-Status: GOOD ( 33.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Nicolas Boichat , Nishanth Menon , Kevin Hilman , Enric Balletbo Serra , Linux PM list , Angus Lin , Xiaoqing Liu , linux-kernel , Stephen Boyd , "devicetree@vger.kernel.org" , Rob Herring , "moderated list:ARM/Mediatek SoC support" , HenryC Chen , Charles Yang , YT Lee , Fan Chen , Linux ARM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Matthias, Thanks for the feedback. On Fri, 2020-05-22 at 17:38 +0200, Matthias Brugger wrote: > > On 22/05/2020 11:40, Roger Lu wrote: > > > > Hi Enric, > > > > On Tue, 2020-05-19 at 17:30 +0200, Enric Balletbo Serra wrote: > >> Hi Roger, > >> > >> Thank you for your patch. I have the feeling that this driver is > >> complex and difficult to follow and I am wondering if it wouldn't be > >> better if you can send a version that simply adds basic functionality > >> for now. Some comments below. > > > > Thanks for the advices. I'll submit SVS v9 with basic functionality > > patch + step by step functionalities' patches. > > > >> > >> Missatge de Roger Lu del dia dl., 18 de maig > >> 2020 a les 11:25: > >>> > >>> The SVS (Smart Voltage Scaling) engine is a piece > >>> of hardware which is used to calculate optimized > >>> voltage values of several power domains, > >>> e.g. CPU/GPU/CCI, according to chip process corner, > >>> temperatures, and other factors. Then DVFS driver > >>> could apply those optimized voltage values to reduce > >>> power consumption. > >>> > >>> Signed-off-by: Roger Lu > >>> --- > >>> drivers/power/avs/Kconfig | 10 + > >>> drivers/power/avs/Makefile | 1 + > >>> drivers/power/avs/mtk_svs.c | 2119 +++++++++++++++++++++++++++++++++ > >>> include/linux/power/mtk_svs.h | 23 + > >>> 4 files changed, 2153 insertions(+) > >>> create mode 100644 drivers/power/avs/mtk_svs.c > >>> create mode 100644 include/linux/power/mtk_svs.h > >>> > >>> diff --git a/drivers/power/avs/Kconfig b/drivers/power/avs/Kconfig > >>> index cdb4237bfd02..67089ac6040e 100644 > >>> --- a/drivers/power/avs/Kconfig > >>> +++ b/drivers/power/avs/Kconfig > >>> @@ -35,3 +35,13 @@ config ROCKCHIP_IODOMAIN > >>> Say y here to enable support io domains on Rockchip SoCs. It is > >>> necessary for the io domain setting of the SoC to match the > >>> voltage supplied by the regulators. > >>> + > >>> +config MTK_SVS > >>> + bool "MediaTek Smart Voltage Scaling(SVS)" > >> > >> Can't be this a module? Why? In such case, you should use tristate option > > > > Generally, MTK_SVS is needed in MTK SoC(mt81xx) products. So, we don't provide > > module option in config. If, somehow, SVS isn't needed, we suggest > > CONFIG_MTK_SVS=n to be set. > > > > The question here is if it needs to be probed before we probe the modules. If > not, we should add a Kconfig option for MT81xx SoCs to select MTK_SVS. Excuse me to make you confuse. MT81xx SoCs is the subset MTK ICs that will use CONFIG_MTK_SVS. In other words, CONFIG_MTK_SVS will be used with other MTK ICs as well. So, MTK_SVS is the general naming for MTK IC to enable SVS power feature. Anyway, back to Enric's question, I'll make MTK_SVS become a tristate feature in the next patch. Thanks. > > >> > >>> + depends on POWER_AVS && MTK_EFUSE && NVMEM > >>> + help > >>> + The SVS engine is a piece of hardware which is used to calculate > >>> + optimized voltage values of several power domains, e.g. > >>> + CPU clusters/GPU/CCI, according to chip process corner, temperatures, > >>> + and other factors. Then DVFS driver could apply those optimized voltage > >>> + values to reduce power consumption. > >>> diff --git a/drivers/power/avs/Makefile b/drivers/power/avs/Makefile > >>> index 9007d05853e2..231adf078582 100644 > >>> --- a/drivers/power/avs/Makefile > >>> +++ b/drivers/power/avs/Makefile > >>> @@ -2,3 +2,4 @@ > >>> obj-$(CONFIG_POWER_AVS_OMAP) += smartreflex.o > >>> obj-$(CONFIG_QCOM_CPR) += qcom-cpr.o > >>> obj-$(CONFIG_ROCKCHIP_IODOMAIN) += rockchip-io-domain.o > >>> +obj-$(CONFIG_MTK_SVS) += mtk_svs.o > >> > >> Will this driver be SoC specific or the idea is to support different > >> SoCs? If the answer to the first question is yes, please name the file > >> with the SoC prefix (i.e mt8183_svs). However, If the answer to the > >> second question is yes, make sure you prefix common > >> functions/structs/defines with a generic prefix mtk_svs but use the > >> SoC prefix for the ones you expect will be different between SoC, i.e > >> mt8183_svs_. This helps the readability of the driver. Also, try to > >> avoid too generic names. > > > > MTK_SVS is designed for supporting different MTK SoCs.Therefore, the answer is second > > question and thanks for the heads-up. > > > >> > >>> diff --git a/drivers/power/avs/mtk_svs.c b/drivers/power/avs/mtk_svs.c > >>> new file mode 100644 > >>> index 000000000000..a4083b3ef175 > >>> --- /dev/null > >>> +++ b/drivers/power/avs/mtk_svs.c > >>> @@ -0,0 +1,2119 @@ > >>> +// SPDX-License-Identifier: GPL-2.0 > >> > >> I suspect you want this only GPLv2 compliant. Use GPL-2.0-only > > > > OK. I'll use GPL-2.0-only.Thanks. > > > >> > >>> +/* > >>> + * Copyright (C) 2020 MediaTek Inc. > >>> + */ > >>> + > >>> +#define pr_fmt(fmt) "[mtk_svs] " fmt > >> > >> I don't see any reason to use pr_fmt in this driver. Use dev_* > >> functions instead and remove the above. > > > > Ok. I will remove it. Thanks. > > > >> > >>> + > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> + > >>> +/* svs 1-line sw id */ > >>> +#define SVS_CPU_LITTLE BIT(0) > >>> +#define SVS_CPU_BIG BIT(1) > >>> +#define SVS_CCI BIT(2) > >>> +#define SVS_GPU BIT(3) > >>> + > >>> +/* svs bank mode support */ > >>> +#define SVSB_MODE_ALL_DISABLE (0) > >> > >> nit: SVS_BMODE_? > > > > Oh. If we add bank wording like SVS_Bxxx, it might cause some confusion when B combines > > with other words. So, I'll keep SVSB for SVS Bank representation. > > E.g: SVS_BDC_SIGNED_BIT might lead to be explained differently ("SVS bank + DC_SIGNED_BIT" or "SVS + BDC_SIGNED_BIT") > > - "SVS bank + DC_SIGNED_BIT" is what we want for naming SVS_BDC_SIGNED_BIT but it might be misunderstood. > > > >> > >>> +#define SVSB_MODE_INIT01 BIT(1) > >>> +#define SVSB_MODE_INIT02 BIT(2) > >>> +#define SVSB_MODE_MON BIT(3) > >>> + > >>> +/* svs bank init01 condition */ > >>> +#define SVSB_INIT01_VOLT_IGNORE BIT(1) > >>> +#define SVSB_INIT01_VOLT_INC_ONLY BIT(2) > >>> + > >>> +/* svs bank common setting */ > >>> +#define HIGH_TEMP_MAX (U32_MAX) > >> > >> nit: SVS_* > > > > ok. I will add SVS or SVSB when it refers to SVS BANK. > > > >> > >>> +#define RUNCONFIG_DEFAULT (0x80000000) > >> > >> Btw, there is any public datasheet where I can see those addresses and > >> registers and bit fields? > > > > Excuse us, there is no public datasheet. We can reply it on patchwork. Thanks. > > > >> > >>> +#define DC_SIGNED_BIT (0x8000) > >>> +#define INTEN_INIT0x (0x00005f01) > >>> +#define INTEN_MONVOPEN (0x00ff0000) > >>> +#define SVSEN_OFF (0x0) > >>> +#define SVSEN_MASK (0x7) > >>> +#define SVSEN_INIT01 (0x1) > >>> +#define SVSEN_INIT02 (0x5) > >>> +#define SVSEN_MON (0x2) > >>> +#define INTSTS_MONVOP (0x00ff0000) > >>> +#define INTSTS_COMPLETE (0x1) > >>> +#define INTSTS_CLEAN (0x00ffffff) > >>> + > >>> +#define proc_fops_rw(name) \ > >>> + static int name ## _proc_open(struct inode *inode, \ > >>> + struct file *file) \ > >>> + { \ > >>> + return single_open(file, name ## _proc_show, \ > >>> + PDE_DATA(inode)); \ > >>> + } \ > >>> + static const struct proc_ops name ## _proc_fops = { \ > >>> + .proc_open = name ## _proc_open, \ > >>> + .proc_read = seq_read, \ > >>> + .proc_lseek = seq_lseek, \ > >>> + .proc_release = single_release, \ > >>> + .proc_write = name ## _proc_write, \ > >>> + } > >>> + > >>> +#define proc_fops_ro(name) \ > >>> + static int name ## _proc_open(struct inode *inode, \ > >>> + struct file *file) \ > >>> + { \ > >>> + return single_open(file, name ## _proc_show, \ > >>> + PDE_DATA(inode)); \ > >>> + } \ > >>> + static const struct proc_ops name ## _proc_fops = { \ > >>> + .proc_open = name ## _proc_open, \ > >>> + .proc_read = seq_read, \ > >>> + .proc_lseek = seq_lseek, \ > >>> + .proc_release = single_release, \ > >>> + } > >>> + > >>> +#define proc_entry(name) {__stringify(name), &name ## _proc_fops} > >>> + > >> > >> /proc is usually the old way of exporting files to userspace, so > >> unless you have a really good reason use sysfs instead, or even > >> better, if it is only for debug purposes use debugfs. Also, you should > >> document the entries in Documentation. > > > > Ok. I'll change it to debugfs and could you give us an example about entries in documentation? > > We can follow them. Thanks. > > > >> > >>> +static DEFINE_SPINLOCK(mtk_svs_lock); > >>> +struct mtk_svs; > >>> + > >>> +enum svsb_phase { > >> > >> nit: mtk_svs_bphase? > > > > ditto > > > >> > >>> + SVSB_PHASE_INIT01 = 0, > >> > >> nit: SVS_BPHASE_? > > > > ditto > > > >> > >>> + SVSB_PHASE_INIT02, > >>> + SVSB_PHASE_MON, > >>> + SVSB_PHASE_ERROR, > >>> +}; > >>> + > >>> +enum reg_index { > >> > >> nit: svs_reg_index? > > > > OK. Thanks. > > > >> > >>> + TEMPMONCTL0 = 0, > >>> + TEMPMONCTL1, > >>> + TEMPMONCTL2, > >>> + TEMPMONINT, > >>> + TEMPMONINTSTS, > >>> + TEMPMONIDET0, > >>> + TEMPMONIDET1, > >>> + TEMPMONIDET2, > >>> + TEMPH2NTHRE, > >>> + TEMPHTHRE, > >>> + TEMPCTHRE, > >>> + TEMPOFFSETH, > >>> + TEMPOFFSETL, > >>> + TEMPMSRCTL0, > >>> + TEMPMSRCTL1, > >>> + TEMPAHBPOLL, > >>> + TEMPAHBTO, > >>> + TEMPADCPNP0, > >>> + TEMPADCPNP1, > >>> + TEMPADCPNP2, > >>> + TEMPADCMUX, > >>> + TEMPADCEXT, > >>> + TEMPADCEXT1, > >>> + TEMPADCEN, > >>> + TEMPPNPMUXADDR, > >>> + TEMPADCMUXADDR, > >>> + TEMPADCEXTADDR, > >>> + TEMPADCEXT1ADDR, > >>> + TEMPADCENADDR, > >>> + TEMPADCVALIDADDR, > >>> + TEMPADCVOLTADDR, > >>> + TEMPRDCTRL, > >>> + TEMPADCVALIDMASK, > >>> + TEMPADCVOLTAGESHIFT, > >>> + TEMPADCWRITECTRL, > >>> + TEMPMSR0, > >>> + TEMPMSR1, > >>> + TEMPMSR2, > >>> + TEMPADCHADDR, > >>> + TEMPIMMD0, > >>> + TEMPIMMD1, > >>> + TEMPIMMD2, > >>> + TEMPMONIDET3, > >>> + TEMPADCPNP3, > >>> + TEMPMSR3, > >>> + TEMPIMMD3, > >>> + TEMPPROTCTL, > >>> + TEMPPROTTA, > >>> + TEMPPROTTB, > >>> + TEMPPROTTC, > >>> + TEMPSPARE0, > >>> + TEMPSPARE1, > >>> + TEMPSPARE2, > >>> + TEMPSPARE3, > >>> + TEMPMSR0_1, > >>> + TEMPMSR1_1, > >>> + TEMPMSR2_1, > >>> + TEMPMSR3_1, > >>> + DESCHAR, > >>> + TEMPCHAR, > >>> + DETCHAR, > >>> + AGECHAR, > >>> + DCCONFIG, > >>> + AGECONFIG, > >>> + FREQPCT30, > >>> + FREQPCT74, > >>> + LIMITVALS, > >>> + VBOOT, > >>> + DETWINDOW, > >>> + CONFIG, > >>> + TSCALCS, > >>> + RUNCONFIG, > >>> + SVSEN, > >>> + INIT2VALS, > >>> + DCVALUES, > >>> + AGEVALUES, > >>> + VOP30, > >>> + VOP74, > >>> + TEMP, > >>> + INTSTS, > >>> + INTSTSRAW, > >>> + INTEN, > >>> + CHKINT, > >>> + CHKSHIFT, > >>> + STATUS, > >>> + VDESIGN30, > >>> + VDESIGN74, > >>> + DVT30, > >>> + DVT74, > >>> + AGECOUNT, > >>> + SMSTATE0, > >>> + SMSTATE1, > >>> + CTL0, > >>> + DESDETSEC, > >>> + TEMPAGESEC, > >>> + CTRLSPARE0, > >>> + CTRLSPARE1, > >>> + CTRLSPARE2, > >>> + CTRLSPARE3, > >>> + CORESEL, > >>> + THERMINTST, > >>> + INTST, > >>> + THSTAGE0ST, > >>> + THSTAGE1ST, > >>> + THSTAGE2ST, > >>> + THAHBST0, > >>> + THAHBST1, > >>> + SPARE0, > >>> + SPARE1, > >>> + SPARE2, > >>> + SPARE3, > >>> + THSLPEVEB, > >>> + reg_num, > >>> +}; > >>> + > >>> +static const u32 svs_regs_v2[] = { > >> > >> Is this SoC specific or shared between SoCs? > > > > Shared between SoCs. Some SVS in MTK SoCs use v2 register map. > > > > And which silicon uses v1 then? Is v2 a MediaTek internal naming you want to keep? 1. MT8173 IC uses v1 register map. 2. Yes, I'll keep v2 postfix. > > >> > >>> + [TEMPMONCTL0] = 0x000, > >>> + [TEMPMONCTL1] = 0x004, > >>> + [TEMPMONCTL2] = 0x008, > >>> + [TEMPMONINT] = 0x00c, > >>> + [TEMPMONINTSTS] = 0x010, > >>> + [TEMPMONIDET0] = 0x014, > >>> + [TEMPMONIDET1] = 0x018, > >>> + [TEMPMONIDET2] = 0x01c, > >>> + [TEMPH2NTHRE] = 0x024, > >>> + [TEMPHTHRE] = 0x028, > >>> + [TEMPCTHRE] = 0x02c, > >>> + [TEMPOFFSETH] = 0x030, > >>> + [TEMPOFFSETL] = 0x034, > >>> + [TEMPMSRCTL0] = 0x038, > >>> + [TEMPMSRCTL1] = 0x03c, > >>> + [TEMPAHBPOLL] = 0x040, > >>> + [TEMPAHBTO] = 0x044, > >>> + [TEMPADCPNP0] = 0x048, > >>> + [TEMPADCPNP1] = 0x04c, > >>> + [TEMPADCPNP2] = 0x050, > >>> + [TEMPADCMUX] = 0x054, > >>> + [TEMPADCEXT] = 0x058, > >>> + [TEMPADCEXT1] = 0x05c, > >>> + [TEMPADCEN] = 0x060, > >>> + [TEMPPNPMUXADDR] = 0x064, > >>> + [TEMPADCMUXADDR] = 0x068, > >>> + [TEMPADCEXTADDR] = 0x06c, > >>> + [TEMPADCEXT1ADDR] = 0x070, > >>> + [TEMPADCENADDR] = 0x074, > >>> + [TEMPADCVALIDADDR] = 0x078, > >>> + [TEMPADCVOLTADDR] = 0x07c, > >>> + [TEMPRDCTRL] = 0x080, > >>> + [TEMPADCVALIDMASK] = 0x084, > >>> + [TEMPADCVOLTAGESHIFT] = 0x088, > >>> + [TEMPADCWRITECTRL] = 0x08c, > >>> + [TEMPMSR0] = 0x090, > >>> + [TEMPMSR1] = 0x094, > >>> + [TEMPMSR2] = 0x098, > >>> + [TEMPADCHADDR] = 0x09c, > >>> + [TEMPIMMD0] = 0x0a0, > >>> + [TEMPIMMD1] = 0x0a4, > >>> + [TEMPIMMD2] = 0x0a8, > >>> + [TEMPMONIDET3] = 0x0b0, > >>> + [TEMPADCPNP3] = 0x0b4, > >>> + [TEMPMSR3] = 0x0b8, > >>> + [TEMPIMMD3] = 0x0bc, > >>> + [TEMPPROTCTL] = 0x0c0, > >>> + [TEMPPROTTA] = 0x0c4, > >>> + [TEMPPROTTB] = 0x0c8, > >>> + [TEMPPROTTC] = 0x0cc, > >>> + [TEMPSPARE0] = 0x0f0, > >>> + [TEMPSPARE1] = 0x0f4, > >>> + [TEMPSPARE2] = 0x0f8, > >>> + [TEMPSPARE3] = 0x0fc, > >>> + [TEMPMSR0_1] = 0x190, > >>> + [TEMPMSR1_1] = 0x194, > >>> + [TEMPMSR2_1] = 0x198, > >>> + [TEMPMSR3_1] = 0x1b8, > >>> + [DESCHAR] = 0xc00, > >>> + [TEMPCHAR] = 0xc04, > >>> + [DETCHAR] = 0xc08, > >>> + [AGECHAR] = 0xc0c, > >>> + [DCCONFIG] = 0xc10, > >>> + [AGECONFIG] = 0xc14, > >>> + [FREQPCT30] = 0xc18, > >>> + [FREQPCT74] = 0xc1c, > >>> + [LIMITVALS] = 0xc20, > >>> + [VBOOT] = 0xc24, > >>> + [DETWINDOW] = 0xc28, > >>> + [CONFIG] = 0xc2c, > >>> + [TSCALCS] = 0xc30, > >>> + [RUNCONFIG] = 0xc34, > >>> + [SVSEN] = 0xc38, > >>> + [INIT2VALS] = 0xc3c, > >>> + [DCVALUES] = 0xc40, > >>> + [AGEVALUES] = 0xc44, > >>> + [VOP30] = 0xc48, > >>> + [VOP74] = 0xc4c, > >>> + [TEMP] = 0xc50, > >>> + [INTSTS] = 0xc54, > >>> + [INTSTSRAW] = 0xc58, > >>> + [INTEN] = 0xc5c, > >>> + [CHKINT] = 0xc60, > >>> + [CHKSHIFT] = 0xc64, > >>> + [STATUS] = 0xc68, > >>> + [VDESIGN30] = 0xc6c, > >>> + [VDESIGN74] = 0xc70, > >>> + [DVT30] = 0xc74, > >>> + [DVT74] = 0xc78, > >>> + [AGECOUNT] = 0xc7c, > >>> + [SMSTATE0] = 0xc80, > >>> + [SMSTATE1] = 0xc84, > >>> + [CTL0] = 0xc88, > >>> + [DESDETSEC] = 0xce0, > >>> + [TEMPAGESEC] = 0xce4, > >>> + [CTRLSPARE0] = 0xcf0, > >>> + [CTRLSPARE1] = 0xcf4, > >>> + [CTRLSPARE2] = 0xcf8, > >>> + [CTRLSPARE3] = 0xcfc, > >>> + [CORESEL] = 0xf00, > >>> + [THERMINTST] = 0xf04, > >>> + [INTST] = 0xf08, > >>> + [THSTAGE0ST] = 0xf0c, > >>> + [THSTAGE1ST] = 0xf10, > >>> + [THSTAGE2ST] = 0xf14, > >>> + [THAHBST0] = 0xf18, > >>> + [THAHBST1] = 0xf1c, > >>> + [SPARE0] = 0xf20, > >>> + [SPARE1] = 0xf24, > >>> + [SPARE2] = 0xf28, > >>> + [SPARE3] = 0xf2c, > >>> + [THSLPEVEB] = 0xf30, > >>> +}; > >>> + > >>> +struct thermal_parameter { > >> > >> In general, not only in this struct, would be good have some > >> documentation to have a better undestanding of the fields. That makes > >> the job of the reviewer a bit easier. > > > > Ok. Could you share a documentation example to us? We'll share the > > information as much as we can. Thanks a lot. > > > > you should find that in all drivers, eg: > https://elixir.bootlin.com/linux/latest/source/drivers/soc/mediatek/mtk-scpsys.c#L111 No problem Sir. Thanks for showing a direction to me. I'll take a look at it. > > Regards, > Matthias _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel