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From: "tip-bot2 for Stephane Eranian" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: Stephane Eranian <eranian@google.com>,
	Ingo Molnar <mingo@kernel.org>, x86 <x86@kernel.org>,
	LKML <linux-kernel@vger.kernel.org>
Subject: [tip: perf/core] perf/x86/rapl: Make perf_probe_msr() more robust and flexible
Date: Thu, 28 May 2020 06:49:01 -0000	[thread overview]
Message-ID: <159064854124.17951.10750193374892124205.tip-bot2@tip-bot2> (raw)
In-Reply-To: <20200527224659.206129-5-eranian@google.com>

The following commit has been merged into the perf/core branch of tip:

Commit-ID:     4c953f879460bf65ea3c119354026b126fe8ee57
Gitweb:        https://git.kernel.org/tip/4c953f879460bf65ea3c119354026b126fe8ee57
Author:        Stephane Eranian <eranian@google.com>
AuthorDate:    Wed, 27 May 2020 15:46:58 -07:00
Committer:     Ingo Molnar <mingo@kernel.org>
CommitterDate: Thu, 28 May 2020 07:58:55 +02:00

perf/x86/rapl: Make perf_probe_msr() more robust and flexible

This patch modifies perf_probe_msr() by allowing passing of
struct perf_msr array where some entries are not populated, i.e.,
they have either an msr address of 0 or no attribute_group pointer.
This helps with certain call paths, e.g., RAPL.

In case the grp is NULL, the default sysfs visibility rule
applies which is to make the group visible. Without the patch,
you would get a kernel crash with a NULL group.

Signed-off-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/r/20200527224659.206129-5-eranian@google.com
---
 arch/x86/events/probe.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/x86/events/probe.c b/arch/x86/events/probe.c
index c2ede2f..136a1e8 100644
--- a/arch/x86/events/probe.c
+++ b/arch/x86/events/probe.c
@@ -10,6 +10,11 @@ not_visible(struct kobject *kobj, struct attribute *attr, int i)
 	return 0;
 }
 
+/*
+ * Accepts msr[] array with non populated entries as long as either
+ * msr[i].msr is 0 or msr[i].grp is NULL. Note that the default sysfs
+ * visibility is visible when group->is_visible callback is set.
+ */
 unsigned long
 perf_msr_probe(struct perf_msr *msr, int cnt, bool zero, void *data)
 {
@@ -24,8 +29,16 @@ perf_msr_probe(struct perf_msr *msr, int cnt, bool zero, void *data)
 		if (!msr[bit].no_check) {
 			struct attribute_group *grp = msr[bit].grp;
 
+			/* skip entry with no group */
+			if (!grp)
+				continue;
+
 			grp->is_visible = not_visible;
 
+			/* skip unpopulated entry */
+			if (!msr[bit].msr)
+				continue;
+
 			if (msr[bit].test && !msr[bit].test(bit, data))
 				continue;
 			/* Virt sucks; you cannot tell if a R/O MSR is present :/ */

  reply	other threads:[~2020-05-28  6:49 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-27 22:46 [PATCH v2 0/5] perf/x86/rapl: Enable RAPL for AMD Fam17h Stephane Eranian
2020-05-27 22:46 ` [PATCH v2 1/5] perf/x86/rapl: move RAPL support to common x86 code Stephane Eranian
2020-05-28  6:49   ` [tip: perf/core] perf/x86/rapl: Move " tip-bot2 for Stephane Eranian
2020-06-01 12:38   ` [PATCH v2 1/5] perf/x86/rapl: move " Johannes Hirte
2020-06-01 19:46     ` Stephane Eranian
2020-06-04 13:11       ` Johannes Hirte
2020-06-04 15:32         ` Stephane Eranian
2020-05-27 22:46 ` [PATCH v2 2/5] perf/x86/rapl: refactor code for Intel/AMD sharing Stephane Eranian
2020-05-28  6:49   ` [tip: perf/core] perf/x86/rapl: Refactor to share the RAPL code between Intel and AMD CPUs tip-bot2 for Stephane Eranian
2020-05-27 22:46 ` [PATCH v2 3/5] perf/x86/rapl: flip logic on default events visibility Stephane Eranian
2020-05-28  6:49   ` [tip: perf/core] perf/x86/rapl: Flip " tip-bot2 for Stephane Eranian
2020-05-27 22:46 ` [PATCH v2 4/5] perf/x86/rapl: make perf_probe_msr() more robust and flexible Stephane Eranian
2020-05-28  6:49   ` tip-bot2 for Stephane Eranian [this message]
2020-05-27 22:46 ` [PATCH v2 5/5] perf/x86/rapl: add AMD Fam17h RAPL support Stephane Eranian
2020-05-28  6:49   ` [tip: perf/core] perf/x86/rapl: Add " tip-bot2 for Stephane Eranian

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