From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_SANE_2 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 997AFC433DF for ; Thu, 28 May 2020 08:06:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6626E20B80 for ; Thu, 28 May 2020 08:06:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="IDMRoK7f" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726330AbgE1IGm (ORCPT ); Thu, 28 May 2020 04:06:42 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<20200523084103.31276-1-dongchun.zhu@mediatek.com> <20200523084103.31276-2-dongchun.zhu@mediatek.com> <20200526182847.GA92449@bogus> <1590569355.8804.448.camel@mhfsdcap03> <20200527211628.GT7618@paasikivi.fi.intel.com> <1590636882.8804.474.camel@mhfsdcap03> <20200528072332.GW7618@paasikivi.fi.intel.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 40A29D3792692DD8CE5B51233948BE224921176E99DFDF64883FC26B2B3119662000:8 X-MTK: N Content-Transfer-Encoding: base64 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org SGkgU2FrYXJpLA0KDQpPbiBUaHUsIDIwMjAtMDUtMjggYXQgMTA6MjMgKzAzMDAsIFNha2FyaSBB aWx1cyB3cm90ZToNCj4gSGkgRG9uZ2NodW4sDQo+IA0KPiBPbiBUaHUsIE1heSAyOCwgMjAyMCBh dCAxMTozNDo0MkFNICswODAwLCBEb25nY2h1biBaaHUgd3JvdGU6DQo+ID4gSGkgU2FrYXJpLCBS b2IsDQo+ID4gDQo+ID4gT24gVGh1LCAyMDIwLTA1LTI4IGF0IDAwOjE2ICswMzAwLCBTYWthcmkg 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<1590653082.8804.517.camel@mhfsdcap03> Subject: Re: [V9, 1/2] media: dt-bindings: media: i2c: Document OV02A10 bindings From: Dongchun Zhu To: Sakari Ailus Date: Thu, 28 May 2020 16:04:42 +0800 In-Reply-To: <20200528072332.GW7618@paasikivi.fi.intel.com> References: <20200523084103.31276-1-dongchun.zhu@mediatek.com> <20200523084103.31276-2-dongchun.zhu@mediatek.com> <20200526182847.GA92449@bogus> <1590569355.8804.448.camel@mhfsdcap03> <20200527211628.GT7618@paasikivi.fi.intel.com> <1590636882.8804.474.camel@mhfsdcap03> <20200528072332.GW7618@paasikivi.fi.intel.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 40A29D3792692DD8CE5B51233948BE224921176E99DFDF64883FC26B2B3119662000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200528_011255_249854_F4934AFD X-CRM114-Status: GOOD ( 23.40 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Rob Herring , Andy Shevchenko , srv_heupstream , devicetree@vger.kernel.org, Linus Walleij , Shengnan Wang =?UTF-8?Q?=28=E7=8E=8B=E5=9C=A3=E7=94=B7=29?= , Tomasz Figa , Bartosz Golaszewski , Sj Huang , Nicolas Boichat , "moderated list:ARM/Mediatek SoC support" , Louis Kuo , Matthias Brugger , Cao Bing Bu , Mauro Carvalho Chehab , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , Linux Media Mailing List Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Hi Sakari, On Thu, 2020-05-28 at 10:23 +0300, Sakari Ailus wrote: > Hi Dongchun, > > On Thu, May 28, 2020 at 11:34:42AM +0800, Dongchun Zhu wrote: > > Hi Sakari, Rob, > > > > On Thu, 2020-05-28 at 00:16 +0300, Sakari Ailus wrote: > > > Hi Rob, Dongchun, > > > > > > On Wed, May 27, 2020 at 09:27:22AM -0600, Rob Herring wrote: > > > > > > > + properties: > > > > > > > + endpoint: > > > > > > > + type: object > > > > > > > + additionalProperties: false > > > > > > > + > > > > > > > + properties: > > > > > > > > > > Actually I wonder whether we need to declare 'clock-lanes' here? > > > > > > > > Yes, if you are using it. > > > > > > Dongchun, can you confirm the chip has a single data and a single clock > > > lane and that it does not support lane reordering? > > > > > > > From the datasheet, 'MIPI inside the OV02A10 provides one single > > uni-directional clock lane and one bi-directional data lane solution for > > communication links between components inside a mobile device. > > The data lane has full support for HS(uni-directional) and > > LP(bi-directional) data transfer mode.' > > > > The sensor doesn't support lane reordering, so 'clock-lanes' property > > would not be added in next release. > > > > > So if there's nothing to convey to the driver, also the data-lanes should > > > be removed IMO. > > > > > > > However, 'data-lanes' property may still be required. > > It is known that either data-lanes or clock-lanes is an array of > > physical data lane indexes. Position of an entry determines the logical > > lane number, while the value of an entry indicates physical lane, e.g., > > for 1-lane MIPI CSI-2 bus we could have "data-lanes = <1>;", assuming > > the clock lane is on hardware lane 0. > > > > As mentioned earlier, the OV02A10 sensor supports only 1C1D and does not > > support lane reordering, so here we shall use 'data-lanes = <1>' as > > there is only a clock lane for OV02A10. > > > > Reminder: > > If 'data-lanes' property is not present, the driver would assume > > four-lane operation. This means for one-lane or two-lane operation, this > > property must be present and set to the right physical lane indexes. > > If the hardware does not support lane reordering, monotonically > > incremented values shall be used from 0 or 1 onwards, depending on > > whether or not there is also a clock lane. > > How can the driver use four lanes, considering the device only supports a > single lane?? > I understood your meaning. If we omit the property 'data-lanes', the sensor should work still. But then what's the meaning of the existence of 'data-lanes'? If this property 'data-lanes' is always optional, then why dt-bindings provide the interface? In the meantime, if omitting 'data-lanes' for one sensor(transmitter) that has only one physical data lane, MIPI receiver(e.g., MIPI CSI-2) shall enable four-lane configuration, which may increase consumption of both power and resource in the process of IIC communication. _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D676FC433DF for ; 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Thu, 28 May 2020 16:06:29 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 May 2020 16:06:30 +0800 Message-ID: <1590653082.8804.517.camel@mhfsdcap03> Subject: Re: [V9, 1/2] media: dt-bindings: media: i2c: Document OV02A10 bindings From: Dongchun Zhu To: Sakari Ailus Date: Thu, 28 May 2020 16:04:42 +0800 In-Reply-To: <20200528072332.GW7618@paasikivi.fi.intel.com> References: <20200523084103.31276-1-dongchun.zhu@mediatek.com> <20200523084103.31276-2-dongchun.zhu@mediatek.com> <20200526182847.GA92449@bogus> <1590569355.8804.448.camel@mhfsdcap03> <20200527211628.GT7618@paasikivi.fi.intel.com> <1590636882.8804.474.camel@mhfsdcap03> <20200528072332.GW7618@paasikivi.fi.intel.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 40A29D3792692DD8CE5B51233948BE224921176E99DFDF64883FC26B2B3119662000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200528_011255_249854_F4934AFD X-CRM114-Status: GOOD ( 23.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Rob Herring , Andy Shevchenko , srv_heupstream , devicetree@vger.kernel.org, Linus Walleij , Shengnan Wang =?UTF-8?Q?=28=E7=8E=8B=E5=9C=A3=E7=94=B7=29?= , Tomasz Figa , Bartosz Golaszewski , Sj Huang , Nicolas Boichat , "moderated list:ARM/Mediatek SoC support" , Louis Kuo , Matthias Brugger , Cao Bing Bu , Mauro Carvalho Chehab , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , Linux Media Mailing List Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Sakari, On Thu, 2020-05-28 at 10:23 +0300, Sakari Ailus wrote: > Hi Dongchun, > > On Thu, May 28, 2020 at 11:34:42AM +0800, Dongchun Zhu wrote: > > Hi Sakari, Rob, > > > > On Thu, 2020-05-28 at 00:16 +0300, Sakari Ailus wrote: > > > Hi Rob, Dongchun, > > > > > > On Wed, May 27, 2020 at 09:27:22AM -0600, Rob Herring wrote: > > > > > > > + properties: > > > > > > > + endpoint: > > > > > > > + type: object > > > > > > > + additionalProperties: false > > > > > > > + > > > > > > > + properties: > > > > > > > > > > Actually I wonder whether we need to declare 'clock-lanes' here? > > > > > > > > Yes, if you are using it. > > > > > > Dongchun, can you confirm the chip has a single data and a single clock > > > lane and that it does not support lane reordering? > > > > > > > From the datasheet, 'MIPI inside the OV02A10 provides one single > > uni-directional clock lane and one bi-directional data lane solution for > > communication links between components inside a mobile device. > > The data lane has full support for HS(uni-directional) and > > LP(bi-directional) data transfer mode.' > > > > The sensor doesn't support lane reordering, so 'clock-lanes' property > > would not be added in next release. > > > > > So if there's nothing to convey to the driver, also the data-lanes should > > > be removed IMO. > > > > > > > However, 'data-lanes' property may still be required. > > It is known that either data-lanes or clock-lanes is an array of > > physical data lane indexes. Position of an entry determines the logical > > lane number, while the value of an entry indicates physical lane, e.g., > > for 1-lane MIPI CSI-2 bus we could have "data-lanes = <1>;", assuming > > the clock lane is on hardware lane 0. > > > > As mentioned earlier, the OV02A10 sensor supports only 1C1D and does not > > support lane reordering, so here we shall use 'data-lanes = <1>' as > > there is only a clock lane for OV02A10. > > > > Reminder: > > If 'data-lanes' property is not present, the driver would assume > > four-lane operation. This means for one-lane or two-lane operation, this > > property must be present and set to the right physical lane indexes. > > If the hardware does not support lane reordering, monotonically > > incremented values shall be used from 0 or 1 onwards, depending on > > whether or not there is also a clock lane. > > How can the driver use four lanes, considering the device only supports a > single lane?? > I understood your meaning. If we omit the property 'data-lanes', the sensor should work still. But then what's the meaning of the existence of 'data-lanes'? If this property 'data-lanes' is always optional, then why dt-bindings provide the interface? In the meantime, if omitting 'data-lanes' for one sensor(transmitter) that has only one physical data lane, MIPI receiver(e.g., MIPI CSI-2) shall enable four-lane configuration, which may increase consumption of both power and resource in the process of IIC communication. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel