* [Intel-gfx] [PATCH 0/7] Move some device capabilities under intel_gt
@ 2020-06-25 23:42 Daniele Ceraolo Spurio
2020-06-25 23:42 ` [Intel-gfx] [PATCH 1/7] drm/i915: Convert device_info to uncore/de_read Daniele Ceraolo Spurio
` (8 more replies)
0 siblings, 9 replies; 26+ messages in thread
From: Daniele Ceraolo Spurio @ 2020-06-25 23:42 UTC (permalink / raw)
To: intel-gfx
Continuing our grouping of GT-related code under intel_gt, this series
moves some of the runtime-detected device capabilities. In particular,
the engine_mask and the sseu_info are placed under the gt structure,
inside a newly added struct intel_gt_info.
Error capture and info print at the intel_gt_info level have also been
added.
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Andi Shyti <andi.shyti@intel.com>
Cc: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
Daniele Ceraolo Spurio (6):
drm/i915: Convert device_info to uncore/de_read
drm/i915: Use the gt in HAS_ENGINE
drm/i915: Move engine-related mmio init to engines_init_mmio
drm/i915: Move the engine mask to intel_gt_info
drm/i915: Introduce gt_init_mmio
drm/i915/sseu: Move sseu detection and dump to intel_sseu
Venkata Sandeep Dhanalakota (1):
drm/i915/sseu: Move sseu_info under gt_info
drivers/gpu/drm/i915/gem/i915_gem_context.c | 7 +-
drivers/gpu/drm/i915/gem/i915_gem_context.h | 2 +-
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 3 +-
.../drm/i915/gem/selftests/i915_gem_context.c | 5 +-
drivers/gpu/drm/i915/gt/intel_context_sseu.c | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 87 ++-
drivers/gpu/drm/i915/gt/intel_gt.c | 16 +
drivers/gpu/drm/i915/gt/intel_gt.h | 5 +
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt_types.h | 11 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 6 +-
.../gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
drivers/gpu/drm/i915/gt/intel_rps.c | 3 +-
drivers/gpu/drm/i915/gt/intel_sseu.c | 592 +++++++++++++++-
drivers/gpu/drm/i915/gt/intel_sseu.h | 10 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 +-
drivers/gpu/drm/i915/gt/selftest_lrc.c | 8 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 10 +-
drivers/gpu/drm/i915/gvt/handlers.c | 4 +-
drivers/gpu/drm/i915/gvt/interrupt.c | 2 +-
drivers/gpu/drm/i915/gvt/mmio_context.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 12 +-
drivers/gpu/drm/i915/i915_drv.c | 9 +-
drivers/gpu/drm/i915/i915_drv.h | 17 +-
drivers/gpu/drm/i915/i915_getparam.c | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 25 +-
drivers/gpu/drm/i915/i915_gpu_error.h | 3 +
drivers/gpu/drm/i915/i915_pci.c | 42 +-
drivers/gpu/drm/i915/i915_perf.c | 9 +-
drivers/gpu/drm/i915/i915_query.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 652 +-----------------
drivers/gpu/drm/i915/intel_device_info.h | 14 +-
drivers/gpu/drm/i915/intel_pm.c | 2 +-
drivers/gpu/drm/i915/intel_uncore.c | 16 +-
drivers/gpu/drm/i915/intel_uncore.h | 4 +-
drivers/gpu/drm/i915/selftests/i915_request.c | 2 +-
.../gpu/drm/i915/selftests/mock_gem_device.c | 3 +-
38 files changed, 835 insertions(+), 768 deletions(-)
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH 1/7] drm/i915: Convert device_info to uncore/de_read
2020-06-25 23:42 [Intel-gfx] [PATCH 0/7] Move some device capabilities under intel_gt Daniele Ceraolo Spurio
@ 2020-06-25 23:42 ` Daniele Ceraolo Spurio
2020-06-26 14:18 ` Tvrtko Ursulin
2020-06-25 23:42 ` [Intel-gfx] [PATCH 2/7] drm/i915: Use the gt in HAS_ENGINE Daniele Ceraolo Spurio
` (7 subsequent siblings)
8 siblings, 1 reply; 26+ messages in thread
From: Daniele Ceraolo Spurio @ 2020-06-25 23:42 UTC (permalink / raw)
To: intel-gfx
Use intel_<uncore/de>_read instead of I915_READ to read the
informational registers.
Extended from an original sseu-only patch by Sandeep.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Andi Shyti <andi.shyti@intel.com>
Cc: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
---
drivers/gpu/drm/i915/intel_device_info.c | 77 +++++++++++++++---------
1 file changed, 47 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 544ac61fbc36..c27a56aff5de 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -26,6 +26,7 @@
#include <drm/i915_pciids.h>
#include "display/intel_cdclk.h"
+#include "display/intel_de.h"
#include "intel_device_info.h"
#include "i915_drv.h"
@@ -237,6 +238,7 @@ static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
static void gen12_sseu_info_init(struct drm_i915_private *dev_priv)
{
struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
+ struct intel_uncore *uncore = &dev_priv->uncore;
u8 s_en;
u32 dss_en;
u16 eu_en = 0;
@@ -250,12 +252,14 @@ static void gen12_sseu_info_init(struct drm_i915_private *dev_priv)
*/
intel_sseu_set_info(sseu, 1, 6, 16);
- s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
+ s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
+ GEN11_GT_S_ENA_MASK;
- dss_en = I915_READ(GEN12_GT_DSS_ENABLE);
+ dss_en = intel_uncore_read(uncore, GEN12_GT_DSS_ENABLE);
/* one bit per pair of EUs */
- eu_en_fuse = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK);
+ eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
+ GEN11_EU_DIS_MASK);
for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
if (eu_en_fuse & BIT(eu))
eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
@@ -269,6 +273,7 @@ static void gen12_sseu_info_init(struct drm_i915_private *dev_priv)
static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
{
struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
+ struct intel_uncore *uncore = &dev_priv->uncore;
u8 s_en;
u32 ss_en;
u8 eu_en;
@@ -278,9 +283,12 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
else
intel_sseu_set_info(sseu, 1, 8, 8);
- s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
- ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
- eu_en = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK);
+ s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
+ GEN11_GT_S_ENA_MASK;
+ ss_en = ~intel_uncore_read(uncore, GEN11_GT_SUBSLICE_DISABLE);
+
+ eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
+ GEN11_EU_DIS_MASK);
gen11_compute_sseu_info(sseu, s_en, ss_en, eu_en);
@@ -292,8 +300,9 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
{
+ struct intel_uncore *uncore = &dev_priv->uncore;
struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
- const u32 fuse2 = I915_READ(GEN8_FUSE2);
+ const u32 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
int s, ss;
const int eu_mask = 0xff;
u32 subslice_mask, eu_en;
@@ -304,26 +313,26 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
GEN10_F2_S_ENA_SHIFT;
/* Slice0 */
- eu_en = ~I915_READ(GEN8_EU_DISABLE0);
+ eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE0);
for (ss = 0; ss < sseu->max_subslices; ss++)
sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask);
/* Slice1 */
sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask);
- eu_en = ~I915_READ(GEN8_EU_DISABLE1);
+ eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE1);
sseu_set_eus(sseu, 1, 1, eu_en & eu_mask);
/* Slice2 */
sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask);
sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask);
/* Slice3 */
sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask);
- eu_en = ~I915_READ(GEN8_EU_DISABLE2);
+ eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE2);
sseu_set_eus(sseu, 3, 1, eu_en & eu_mask);
/* Slice4 */
sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask);
sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask);
/* Slice5 */
sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask);
- eu_en = ~I915_READ(GEN10_EU_DISABLE3);
+ eu_en = ~intel_uncore_read(uncore, GEN10_EU_DISABLE3);
sseu_set_eus(sseu, 5, 1, eu_en & eu_mask);
subslice_mask = (1 << 4) - 1;
@@ -372,7 +381,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
u32 fuse;
u8 subslice_mask = 0;
- fuse = I915_READ(CHV_FUSE_GT);
+ fuse = intel_uncore_read(&dev_priv->uncore, CHV_FUSE_GT);
sseu->slice_mask = BIT(0);
intel_sseu_set_info(sseu, 1, 2, 8);
@@ -425,11 +434,12 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
{
struct intel_device_info *info = mkwrite_device_info(dev_priv);
struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
+ struct intel_uncore *uncore = &dev_priv->uncore;
int s, ss;
u32 fuse2, eu_disable, subslice_mask;
const u8 eu_mask = 0xff;
- fuse2 = I915_READ(GEN8_FUSE2);
+ fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
/* BXT has a single slice and at most 3 subslices. */
@@ -455,7 +465,7 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
intel_sseu_set_subslices(sseu, s, subslice_mask);
- eu_disable = I915_READ(GEN9_EU_DISABLE(s));
+ eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s));
for (ss = 0; ss < sseu->max_subslices; ss++) {
int eu_per_ss;
u8 eu_disabled_mask;
@@ -528,10 +538,12 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
static void bdw_sseu_info_init(struct drm_i915_private *dev_priv)
{
struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
+ struct intel_uncore *uncore = &dev_priv->uncore;
int s, ss;
u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */
+ u32 eu_disable0, eu_disable1, eu_disable2;
- fuse2 = I915_READ(GEN8_FUSE2);
+ fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
intel_sseu_set_info(sseu, 3, 3, 8);
@@ -542,13 +554,15 @@ static void bdw_sseu_info_init(struct drm_i915_private *dev_priv)
subslice_mask = GENMASK(sseu->max_subslices - 1, 0);
subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >>
GEN8_F2_SS_DIS_SHIFT);
-
- eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
- eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
- ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
+ eu_disable0 = intel_uncore_read(uncore, GEN8_EU_DISABLE0);
+ eu_disable1 = intel_uncore_read(uncore, GEN8_EU_DISABLE1);
+ eu_disable2 = intel_uncore_read(uncore, GEN8_EU_DISABLE2);
+ eu_disable[0] = eu_disable0 & GEN8_EU_DIS0_S0_MASK;
+ eu_disable[1] = (eu_disable0 >> GEN8_EU_DIS0_S1_SHIFT) |
+ ((eu_disable1 & GEN8_EU_DIS1_S1_MASK) <<
(32 - GEN8_EU_DIS0_S1_SHIFT));
- eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
- ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
+ eu_disable[2] = (eu_disable1 >> GEN8_EU_DIS1_S2_SHIFT) |
+ ((eu_disable2 & GEN8_EU_DIS2_S2_MASK) <<
(32 - GEN8_EU_DIS1_S2_SHIFT));
/*
@@ -635,7 +649,7 @@ static void hsw_sseu_info_init(struct drm_i915_private *dev_priv)
break;
}
- fuse1 = I915_READ(HSW_PAVP_FUSE1);
+ fuse1 = intel_uncore_read(&dev_priv->uncore, HSW_PAVP_FUSE1);
switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) {
default:
MISSING_CASE((fuse1 & HSW_F1_EU_DIS_MASK) >>
@@ -675,7 +689,8 @@ static void hsw_sseu_info_init(struct drm_i915_private *dev_priv)
static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv)
{
- u32 ts_override = I915_READ(GEN9_TIMESTAMP_OVERRIDE);
+ u32 ts_override = intel_uncore_read(&dev_priv->uncore,
+ GEN9_TIMESTAMP_OVERRIDE);
u32 base_freq, frac_freq;
base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >>
@@ -738,6 +753,7 @@ static u32 gen11_get_crystal_clock_freq(struct drm_i915_private *dev_priv,
static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
{
+ struct intel_uncore *uncore = &dev_priv->uncore;
u32 f12_5_mhz = 12500000;
u32 f19_2_mhz = 19200000;
u32 f24_mhz = 24000000;
@@ -759,7 +775,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
*/
return f12_5_mhz;
} else if (INTEL_GEN(dev_priv) <= 9) {
- u32 ctc_reg = I915_READ(CTC_MODE);
+ u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
u32 freq = 0;
if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
@@ -777,7 +793,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
return freq;
} else if (INTEL_GEN(dev_priv) <= 12) {
- u32 ctc_reg = I915_READ(CTC_MODE);
+ u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
u32 freq = 0;
/* First figure out the reference frequency. There are 2 ways
@@ -788,7 +804,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
freq = read_reference_ts_freq(dev_priv);
} else {
- u32 rpm_config_reg = I915_READ(RPM_CONFIG0);
+ u32 rpm_config_reg = intel_uncore_read(uncore, RPM_CONFIG0);
if (INTEL_GEN(dev_priv) <= 10)
freq = gen10_get_crystal_clock_freq(dev_priv,
@@ -967,8 +983,8 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
if (HAS_DISPLAY(dev_priv) && IS_GEN_RANGE(dev_priv, 7, 8) &&
HAS_PCH_SPLIT(dev_priv)) {
- u32 fuse_strap = I915_READ(FUSE_STRAP);
- u32 sfuse_strap = I915_READ(SFUSE_STRAP);
+ u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
+ u32 sfuse_strap = intel_de_read(dev_priv, SFUSE_STRAP);
/*
* SFUSE_STRAP is supposed to have a bit signalling the display
@@ -993,7 +1009,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
}
} else if (HAS_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 9) {
- u32 dfsm = I915_READ(SKL_DFSM);
+ u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);
if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
info->pipe_mask &= ~BIT(PIPE_A);
@@ -1083,6 +1099,7 @@ void intel_driver_caps_print(const struct intel_driver_caps *caps,
void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
{
struct intel_device_info *info = mkwrite_device_info(dev_priv);
+ struct intel_uncore *uncore = &dev_priv->uncore;
unsigned int logical_vdbox = 0;
unsigned int i;
u32 media_fuse;
@@ -1092,7 +1109,7 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
if (INTEL_GEN(dev_priv) < 11)
return;
- media_fuse = ~I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE);
+ media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH 2/7] drm/i915: Use the gt in HAS_ENGINE
2020-06-25 23:42 [Intel-gfx] [PATCH 0/7] Move some device capabilities under intel_gt Daniele Ceraolo Spurio
2020-06-25 23:42 ` [Intel-gfx] [PATCH 1/7] drm/i915: Convert device_info to uncore/de_read Daniele Ceraolo Spurio
@ 2020-06-25 23:42 ` Daniele Ceraolo Spurio
2020-06-26 14:20 ` Tvrtko Ursulin
2020-06-26 14:35 ` Chris Wilson
2020-06-25 23:42 ` [Intel-gfx] [PATCH 3/7] drm/i915: Move engine-related mmio init to engines_init_mmio Daniele Ceraolo Spurio
` (6 subsequent siblings)
8 siblings, 2 replies; 26+ messages in thread
From: Daniele Ceraolo Spurio @ 2020-06-25 23:42 UTC (permalink / raw)
To: intel-gfx
A follow up patch will move the engine mask under the gt structure,
so get ready for that.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Andi Shyti <andi.shyti@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 7 ++++---
drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
drivers/gpu/drm/i915/gvt/interrupt.c | 2 +-
drivers/gpu/drm/i915/gvt/mmio_context.c | 2 +-
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 15 ++++++++-------
drivers/gpu/drm/i915/intel_device_info.c | 13 +++++++------
drivers/gpu/drm/i915/intel_pm.c | 2 +-
drivers/gpu/drm/i915/intel_uncore.c | 16 +++++++++-------
drivers/gpu/drm/i915/intel_uncore.h | 4 +++-
12 files changed, 38 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 7bf2f76212f0..be92d1ef9aa9 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -473,7 +473,7 @@ int intel_engines_init_mmio(struct intel_gt *gt)
return -ENODEV;
for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
- if (!HAS_ENGINE(i915, i))
+ if (!HAS_ENGINE(gt, i))
continue;
err = intel_engine_setup(gt, i);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 0cc7dd54f4f9..e1964cf40fd6 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -457,7 +457,7 @@ void gen5_gt_irq_postinstall(struct intel_gt *gt)
* RPS interrupts will get enabled/disabled on demand when RPS
* itself is enabled/disabled.
*/
- if (HAS_ENGINE(gt->i915, VECS0)) {
+ if (HAS_ENGINE(gt, VECS0)) {
pm_irqs |= PM_VEBOX_USER_INTERRUPT;
gt->pm_ier |= PM_VEBOX_USER_INTERRUPT;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 101728006ae9..fbdd6b0677db 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -67,7 +67,8 @@ struct __guc_ads_blob {
static void __guc_ads_init(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
+ struct intel_gt *gt = guc_to_gt(guc);
+ struct drm_i915_private *dev_priv = gt->i915;
struct __guc_ads_blob *blob = guc->ads_blob;
const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;
u32 base;
@@ -103,8 +104,8 @@ static void __guc_ads_init(struct intel_guc *guc)
blob->system_info.rcs_enabled = 1;
blob->system_info.bcs_enabled = 1;
- blob->system_info.vdbox_enable_mask = VDBOX_MASK(dev_priv);
- blob->system_info.vebox_enable_mask = VEBOX_MASK(dev_priv);
+ blob->system_info.vdbox_enable_mask = VDBOX_MASK(gt);
+ blob->system_info.vebox_enable_mask = VEBOX_MASK(gt);
blob->system_info.vdbox_sfc_support_mask = RUNTIME_INFO(dev_priv)->vdbox_sfc_access;
base = intel_guc_ggtt_offset(guc, guc->ads_vma);
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 26cae4846c82..ddefc52f6e09 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1867,7 +1867,7 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
- if (HAS_ENGINE(dev_priv, VCS1)) \
+ if (HAS_ENGINE(&dev_priv->gt, VCS1)) \
MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
} while (0)
diff --git a/drivers/gpu/drm/i915/gvt/interrupt.c b/drivers/gpu/drm/i915/gvt/interrupt.c
index 540017fed908..7498878e6289 100644
--- a/drivers/gpu/drm/i915/gvt/interrupt.c
+++ b/drivers/gpu/drm/i915/gvt/interrupt.c
@@ -540,7 +540,7 @@ static void gen8_init_irq(
SET_BIT_INFO(irq, 4, VCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT1);
SET_BIT_INFO(irq, 8, VCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT1);
- if (HAS_ENGINE(gvt->gt->i915, VCS1)) {
+ if (HAS_ENGINE(gvt->gt, VCS1)) {
SET_BIT_INFO(irq, 16, VCS2_MI_USER_INTERRUPT,
INTEL_GVT_IRQ_INFO_GT1);
SET_BIT_INFO(irq, 20, VCS2_MI_FLUSH_DW,
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index 2ccaf78f96e8..86a60bdf0818 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -171,7 +171,7 @@ static void load_render_mocs(const struct intel_engine_cs *engine)
return;
for (ring_id = 0; ring_id < cnt; ring_id++) {
- if (!HAS_ENGINE(engine->i915, ring_id))
+ if (!HAS_ENGINE(engine->gt, ring_id))
continue;
offset.reg = regs[ring_id];
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 67102dc26fce..1f9c40cf10ae 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -533,7 +533,7 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
intel_device_info_init_mmio(dev_priv);
- intel_uncore_prune_mmio_domains(&dev_priv->uncore);
+ intel_uncore_prune_engine_fw_domains(&dev_priv->uncore, &dev_priv->gt);
intel_uc_init_mmio(&dev_priv->gt.uc);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9aad3ec979bd..17cad4e2cb9c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1560,18 +1560,19 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
#define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
-#define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id))
+#define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
+#define HAS_ENGINE(gt, id) __HAS_ENGINE(INTEL_INFO((gt)->i915)->engine_mask, id)
-#define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({ \
+#define ENGINE_INSTANCES_MASK(gt, first, count) ({ \
unsigned int first__ = (first); \
unsigned int count__ = (count); \
- (INTEL_INFO(dev_priv)->engine_mask & \
+ (INTEL_INFO((gt)->i915)->engine_mask & \
GENMASK(first__ + count__ - 1, first__)) >> first__; \
})
-#define VDBOX_MASK(dev_priv) \
- ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS)
-#define VEBOX_MASK(dev_priv) \
- ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS)
+#define VDBOX_MASK(gt) \
+ ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
+#define VEBOX_MASK(gt) \
+ ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
/*
* The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index c27a56aff5de..c0443afa12b9 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -1100,6 +1100,7 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
{
struct intel_device_info *info = mkwrite_device_info(dev_priv);
struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_gt *gt = &dev_priv->gt;
unsigned int logical_vdbox = 0;
unsigned int i;
u32 media_fuse;
@@ -1116,7 +1117,7 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
GEN11_GT_VEBOX_DISABLE_SHIFT;
for (i = 0; i < I915_MAX_VCS; i++) {
- if (!HAS_ENGINE(dev_priv, _VCS(i))) {
+ if (!HAS_ENGINE(gt, _VCS(i))) {
vdbox_mask &= ~BIT(i);
continue;
}
@@ -1136,11 +1137,11 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
RUNTIME_INFO(dev_priv)->vdbox_sfc_access |= BIT(i);
}
drm_dbg(&dev_priv->drm, "vdbox enable: %04x, instances: %04lx\n",
- vdbox_mask, VDBOX_MASK(dev_priv));
- GEM_BUG_ON(vdbox_mask != VDBOX_MASK(dev_priv));
+ vdbox_mask, VDBOX_MASK(gt));
+ GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
for (i = 0; i < I915_MAX_VECS; i++) {
- if (!HAS_ENGINE(dev_priv, _VECS(i))) {
+ if (!HAS_ENGINE(gt, _VECS(i))) {
vebox_mask &= ~BIT(i);
continue;
}
@@ -1151,6 +1152,6 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
}
}
drm_dbg(&dev_priv->drm, "vebox enable: %04x, instances: %04lx\n",
- vebox_mask, VEBOX_MASK(dev_priv));
- GEM_BUG_ON(vebox_mask != VEBOX_MASK(dev_priv));
+ vebox_mask, VEBOX_MASK(gt));
+ GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
}
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2a32d6230795..40f6fe69b70a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7105,7 +7105,7 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
/* This is not a WA. Enable VD HCP & MFX_ENC powergate */
for (i = 0; i < I915_MAX_VCS; i++) {
- if (HAS_ENGINE(dev_priv, _VCS(i)))
+ if (HAS_ENGINE(&dev_priv->gt, _VCS(i)))
vd_pg_enable |= VDN_HCP_POWERGATE_ENABLE(i) |
VDN_MFX_POWERGATE_ENABLE(i);
}
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 592364aed2da..bd4b45191f7b 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1529,6 +1529,8 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
(ret ?: (ret = __fw_domain_init((uncore__), (id__), (set__), (ack__))))
if (INTEL_GEN(i915) >= 11) {
+ /* we'll prune the domains of missing engines later */
+ intel_engine_mask_t emask = INTEL_INFO(i915)->engine_mask;
int i;
uncore->funcs.force_wake_get = fw_domains_get_with_fallback;
@@ -1541,7 +1543,7 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
FORCEWAKE_ACK_BLITTER_GEN9);
for (i = 0; i < I915_MAX_VCS; i++) {
- if (!HAS_ENGINE(i915, _VCS(i)))
+ if (!__HAS_ENGINE(emask, _VCS(i)))
continue;
fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VDBOX0 + i,
@@ -1549,7 +1551,7 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(i));
}
for (i = 0; i < I915_MAX_VECS; i++) {
- if (!HAS_ENGINE(i915, _VECS(i)))
+ if (!__HAS_ENGINE(emask, _VECS(i)))
continue;
fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VEBOX0 + i,
@@ -1844,20 +1846,20 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore)
* the forcewake domains. Prune them, to make sure they only reference existing
* engines.
*/
-void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore)
+void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
+ struct intel_gt *gt)
{
- struct drm_i915_private *i915 = uncore->i915;
enum forcewake_domains fw_domains = uncore->fw_domains;
enum forcewake_domain_id domain_id;
int i;
- if (!intel_uncore_has_forcewake(uncore) || INTEL_GEN(i915) < 11)
+ if (!intel_uncore_has_forcewake(uncore) || INTEL_GEN(uncore->i915) < 11)
return;
for (i = 0; i < I915_MAX_VCS; i++) {
domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i;
- if (HAS_ENGINE(i915, _VCS(i)))
+ if (HAS_ENGINE(gt, _VCS(i)))
continue;
if (fw_domains & BIT(domain_id))
@@ -1867,7 +1869,7 @@ void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore)
for (i = 0; i < I915_MAX_VECS; i++) {
domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i;
- if (HAS_ENGINE(i915, _VECS(i)))
+ if (HAS_ENGINE(gt, _VECS(i)))
continue;
if (fw_domains & BIT(domain_id))
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index 8d3aa8b9acf9..c4b22d9d0b45 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -35,6 +35,7 @@
struct drm_i915_private;
struct intel_runtime_pm;
struct intel_uncore;
+struct intel_gt;
struct intel_uncore_mmio_debug {
spinlock_t lock; /** lock is also taken in irq contexts. */
@@ -186,7 +187,8 @@ intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug);
void intel_uncore_init_early(struct intel_uncore *uncore,
struct drm_i915_private *i915);
int intel_uncore_init_mmio(struct intel_uncore *uncore);
-void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore);
+void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
+ struct intel_gt *gt);
bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore);
bool intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore);
void intel_uncore_fini_mmio(struct intel_uncore *uncore);
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH 3/7] drm/i915: Move engine-related mmio init to engines_init_mmio
2020-06-25 23:42 [Intel-gfx] [PATCH 0/7] Move some device capabilities under intel_gt Daniele Ceraolo Spurio
2020-06-25 23:42 ` [Intel-gfx] [PATCH 1/7] drm/i915: Convert device_info to uncore/de_read Daniele Ceraolo Spurio
2020-06-25 23:42 ` [Intel-gfx] [PATCH 2/7] drm/i915: Use the gt in HAS_ENGINE Daniele Ceraolo Spurio
@ 2020-06-25 23:42 ` Daniele Ceraolo Spurio
2020-06-26 14:38 ` Tvrtko Ursulin
2020-06-26 14:38 ` Chris Wilson
2020-06-25 23:42 ` [Intel-gfx] [PATCH 4/7] drm/i915: Move the engine mask to intel_gt_info Daniele Ceraolo Spurio
` (5 subsequent siblings)
8 siblings, 2 replies; 26+ messages in thread
From: Daniele Ceraolo Spurio @ 2020-06-25 23:42 UTC (permalink / raw)
To: intel-gfx
All the info we read in intel_device_info_init_mmio are engine-related
and since we already have an engine_init_mmio function we can just
perform the operations from there.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Andi Shyti <andi.shyti@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 72 ++++++++++++++++++++++-
drivers/gpu/drm/i915/i915_drv.c | 4 --
drivers/gpu/drm/i915/intel_device_info.c | 66 ---------------------
drivers/gpu/drm/i915/intel_device_info.h | 2 -
4 files changed, 71 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index be92d1ef9aa9..8497106eb3a6 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -450,6 +450,74 @@ void intel_engines_free(struct intel_gt *gt)
}
}
+/*
+ * Determine which engines are fused off in our particular hardware. Since the
+ * fuse register is in the blitter powerwell, we need forcewake to be ready at
+ * this point (but later we need to prune the forcewake domains for engines that
+ * are indeed fused off).
+ */
+static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
+{
+ struct drm_i915_private *i915 = gt->i915;
+ struct intel_device_info *info = mkwrite_device_info(i915);
+ struct intel_uncore *uncore = gt->uncore;
+ unsigned int logical_vdbox = 0;
+ unsigned int i;
+ u32 media_fuse;
+ u16 vdbox_mask;
+ u16 vebox_mask;
+
+ if (INTEL_GEN(i915) < 11)
+ return info->engine_mask;
+
+ media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
+
+ vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
+ vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
+ GEN11_GT_VEBOX_DISABLE_SHIFT;
+
+ for (i = 0; i < I915_MAX_VCS; i++) {
+ if (!HAS_ENGINE(gt, _VCS(i))) {
+ vdbox_mask &= ~BIT(i);
+ continue;
+ }
+
+ if (!(BIT(i) & vdbox_mask)) {
+ info->engine_mask &= ~BIT(_VCS(i));
+ drm_dbg(&i915->drm, "vcs%u fused off\n", i);
+ continue;
+ }
+
+ /*
+ * In Gen11, only even numbered logical VDBOXes are
+ * hooked up to an SFC (Scaler & Format Converter) unit.
+ * In TGL each VDBOX has access to an SFC.
+ */
+ if (INTEL_GEN(i915) >= 12 || logical_vdbox++ % 2 == 0)
+ RUNTIME_INFO(i915)->vdbox_sfc_access |= BIT(i);
+ }
+ drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
+ vdbox_mask, VDBOX_MASK(gt));
+ GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
+
+ for (i = 0; i < I915_MAX_VECS; i++) {
+ if (!HAS_ENGINE(gt, _VECS(i))) {
+ vebox_mask &= ~BIT(i);
+ continue;
+ }
+
+ if (!(BIT(i) & vebox_mask)) {
+ info->engine_mask &= ~BIT(_VECS(i));
+ drm_dbg(&i915->drm, "vecs%u fused off\n", i);
+ }
+ }
+ drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n",
+ vebox_mask, VEBOX_MASK(gt));
+ GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
+
+ return info->engine_mask;
+}
+
/**
* intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers
* @gt: pointer to struct intel_gt
@@ -460,7 +528,7 @@ int intel_engines_init_mmio(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
struct intel_device_info *device_info = mkwrite_device_info(i915);
- const unsigned int engine_mask = INTEL_INFO(i915)->engine_mask;
+ const unsigned int engine_mask = init_engine_mask(gt);
unsigned int mask = 0;
unsigned int i;
int err;
@@ -497,6 +565,8 @@ int intel_engines_init_mmio(struct intel_gt *gt)
intel_setup_engine_capabilities(gt);
+ intel_uncore_prune_engine_fw_domains(gt->uncore, gt);
+
return 0;
cleanup:
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1f9c40cf10ae..611287353420 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -531,10 +531,6 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
/* Try to make sure MCHBAR is enabled before poking at it */
intel_setup_mchbar(dev_priv);
- intel_device_info_init_mmio(dev_priv);
-
- intel_uncore_prune_engine_fw_domains(&dev_priv->uncore, &dev_priv->gt);
-
intel_uc_init_mmio(&dev_priv->gt.uc);
ret = intel_engines_init_mmio(&dev_priv->gt);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index c0443afa12b9..92ebea35c752 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -1089,69 +1089,3 @@ void intel_driver_caps_print(const struct intel_driver_caps *caps,
yesno(caps->has_logical_contexts));
drm_printf(p, "scheduler: %x\n", caps->scheduler);
}
-
-/*
- * Determine which engines are fused off in our particular hardware. Since the
- * fuse register is in the blitter powerwell, we need forcewake to be ready at
- * this point (but later we need to prune the forcewake domains for engines that
- * are indeed fused off).
- */
-void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
-{
- struct intel_device_info *info = mkwrite_device_info(dev_priv);
- struct intel_uncore *uncore = &dev_priv->uncore;
- struct intel_gt *gt = &dev_priv->gt;
- unsigned int logical_vdbox = 0;
- unsigned int i;
- u32 media_fuse;
- u16 vdbox_mask;
- u16 vebox_mask;
-
- if (INTEL_GEN(dev_priv) < 11)
- return;
-
- media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
-
- vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
- vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
- GEN11_GT_VEBOX_DISABLE_SHIFT;
-
- for (i = 0; i < I915_MAX_VCS; i++) {
- if (!HAS_ENGINE(gt, _VCS(i))) {
- vdbox_mask &= ~BIT(i);
- continue;
- }
-
- if (!(BIT(i) & vdbox_mask)) {
- info->engine_mask &= ~BIT(_VCS(i));
- drm_dbg(&dev_priv->drm, "vcs%u fused off\n", i);
- continue;
- }
-
- /*
- * In Gen11, only even numbered logical VDBOXes are
- * hooked up to an SFC (Scaler & Format Converter) unit.
- * In TGL each VDBOX has access to an SFC.
- */
- if (INTEL_GEN(dev_priv) >= 12 || logical_vdbox++ % 2 == 0)
- RUNTIME_INFO(dev_priv)->vdbox_sfc_access |= BIT(i);
- }
- drm_dbg(&dev_priv->drm, "vdbox enable: %04x, instances: %04lx\n",
- vdbox_mask, VDBOX_MASK(gt));
- GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
-
- for (i = 0; i < I915_MAX_VECS; i++) {
- if (!HAS_ENGINE(gt, _VECS(i))) {
- vebox_mask &= ~BIT(i);
- continue;
- }
-
- if (!(BIT(i) & vebox_mask)) {
- info->engine_mask &= ~BIT(_VECS(i));
- drm_dbg(&dev_priv->drm, "vecs%u fused off\n", i);
- }
- }
- drm_dbg(&dev_priv->drm, "vebox enable: %04x, instances: %04lx\n",
- vebox_mask, VEBOX_MASK(gt));
- GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
-}
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 8d62b8538585..fa60fdc1d75a 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -250,8 +250,6 @@ void intel_device_info_print_runtime(const struct intel_runtime_info *info,
void intel_device_info_print_topology(const struct sseu_dev_info *sseu,
struct drm_printer *p);
-void intel_device_info_init_mmio(struct drm_i915_private *dev_priv);
-
void intel_driver_caps_print(const struct intel_driver_caps *caps,
struct drm_printer *p);
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH 4/7] drm/i915: Move the engine mask to intel_gt_info
2020-06-25 23:42 [Intel-gfx] [PATCH 0/7] Move some device capabilities under intel_gt Daniele Ceraolo Spurio
` (2 preceding siblings ...)
2020-06-25 23:42 ` [Intel-gfx] [PATCH 3/7] drm/i915: Move engine-related mmio init to engines_init_mmio Daniele Ceraolo Spurio
@ 2020-06-25 23:42 ` Daniele Ceraolo Spurio
2020-06-26 14:45 ` Tvrtko Ursulin
2020-06-25 23:42 ` [Intel-gfx] [PATCH 5/7] drm/i915: Introduce gt_init_mmio Daniele Ceraolo Spurio
` (4 subsequent siblings)
8 siblings, 1 reply; 26+ messages in thread
From: Daniele Ceraolo Spurio @ 2020-06-25 23:42 UTC (permalink / raw)
To: intel-gfx
Since the engines belong to the GT, move the runtime-updated list of
available engines to the intel_gt struct. The original mask has been
renamed to indicate it contains the maximum engine list that can be
found on a matching device.
In preparation for other info being moved to the gt in follow up patches
(sseu), introduce an intel_gt_info structure to group all gt-related
runtime info.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Andi Shyti <andi.shyti@intel.com>
Cc: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 3 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 13 +++---
drivers/gpu/drm/i915/gt/intel_gt.c | 6 +++
drivers/gpu/drm/i915/gt/intel_gt.h | 4 ++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 8 ++++
drivers/gpu/drm/i915/gt/intel_reset.c | 6 +--
.../gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_lrc.c | 8 ++--
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 2 +-
drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 2 +
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 6 +--
drivers/gpu/drm/i915/i915_gpu_error.c | 23 ++++++----
drivers/gpu/drm/i915/i915_gpu_error.h | 3 ++
drivers/gpu/drm/i915/i915_pci.c | 42 +++++++++----------
drivers/gpu/drm/i915/intel_device_info.c | 1 -
drivers/gpu/drm/i915/intel_device_info.h | 7 +---
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
drivers/gpu/drm/i915/selftests/i915_request.c | 2 +-
.../gpu/drm/i915/selftests/mock_gem_device.c | 3 +-
21 files changed, 84 insertions(+), 62 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index c38ab51e82f0..7ffac711e4b4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1973,8 +1973,7 @@ static int eb_submit(struct i915_execbuffer *eb, struct i915_vma *batch)
static int num_vcs_engines(const struct drm_i915_private *i915)
{
- return hweight64(INTEL_INFO(i915)->engine_mask &
- GENMASK_ULL(VCS0 + I915_MAX_VCS - 1, VCS0));
+ return hweight64(VDBOX_MASK(&i915->gt));
}
/*
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 8497106eb3a6..3af58df3b13e 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -370,7 +370,7 @@ static void __setup_engine_capabilities(struct intel_engine_cs *engine)
* instances.
*/
if ((INTEL_GEN(i915) >= 11 &&
- RUNTIME_INFO(i915)->vdbox_sfc_access & engine->mask) ||
+ engine->gt->info.vdbox_sfc_access & engine->mask) ||
(INTEL_GEN(i915) >= 9 && engine->instance == 0))
engine->uabi_capabilities |=
I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
@@ -459,7 +459,7 @@ void intel_engines_free(struct intel_gt *gt)
static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
- struct intel_device_info *info = mkwrite_device_info(i915);
+ struct intel_gt_info *info = >->info;
struct intel_uncore *uncore = gt->uncore;
unsigned int logical_vdbox = 0;
unsigned int i;
@@ -467,6 +467,8 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
u16 vdbox_mask;
u16 vebox_mask;
+ info->engine_mask = INTEL_INFO(i915)->max_engine_mask;
+
if (INTEL_GEN(i915) < 11)
return info->engine_mask;
@@ -494,7 +496,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
* In TGL each VDBOX has access to an SFC.
*/
if (INTEL_GEN(i915) >= 12 || logical_vdbox++ % 2 == 0)
- RUNTIME_INFO(i915)->vdbox_sfc_access |= BIT(i);
+ gt->info.vdbox_sfc_access |= BIT(i);
}
drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
vdbox_mask, VDBOX_MASK(gt));
@@ -527,7 +529,6 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
int intel_engines_init_mmio(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
- struct intel_device_info *device_info = mkwrite_device_info(i915);
const unsigned int engine_mask = init_engine_mask(gt);
unsigned int mask = 0;
unsigned int i;
@@ -557,9 +558,9 @@ int intel_engines_init_mmio(struct intel_gt *gt)
* engines.
*/
if (drm_WARN_ON(&i915->drm, mask != engine_mask))
- device_info->engine_mask = mask;
+ gt->info.engine_mask = mask;
- RUNTIME_INFO(i915)->num_engines = hweight32(mask);
+ gt->info.num_engines = hweight32(mask);
intel_gt_check_and_clear_faults(gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index ebc29b6ee86c..d0ae1cb5c7c9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -642,3 +642,9 @@ void intel_gt_driver_late_release(struct intel_gt *gt)
intel_gt_fini_timelines(gt);
intel_engines_free(gt);
}
+
+void intel_gt_info_print(const struct intel_gt_info *info,
+ struct drm_printer *p)
+{
+ drm_printf(p, "available engines: %x\n", info->engine_mask);
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index 4fac043750aa..15142e2a3b22 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -11,6 +11,7 @@
#include "intel_reset.h"
struct drm_i915_private;
+struct drm_printer;
#define GT_TRACE(gt, fmt, ...) do { \
const struct intel_gt *gt__ __maybe_unused = (gt); \
@@ -68,4 +69,7 @@ static inline bool intel_gt_has_init_error(const struct intel_gt *gt)
return test_bit(I915_WEDGED_ON_INIT, >->reset.flags);
}
+void intel_gt_info_print(const struct intel_gt_info *info,
+ struct drm_printer *p);
+
#endif /* __INTEL_GT_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 0cc1d6b185dc..bb7551867c00 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -109,6 +109,14 @@ struct intel_gt {
struct intel_gt_buffer_pool buffer_pool;
struct i915_vma *scratch;
+
+ struct intel_gt_info {
+ intel_engine_mask_t engine_mask;
+ u8 num_engines;
+
+ /* Media engine access to SFC per instance */
+ u8 vdbox_sfc_access;
+ } info;
};
enum intel_gt_scratch_field {
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 0156f1f5c736..952cd6e9b88e 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -342,7 +342,7 @@ static int gen6_reset_engines(struct intel_gt *gt,
static int gen11_lock_sfc(struct intel_engine_cs *engine, u32 *hw_mask)
{
struct intel_uncore *uncore = engine->uncore;
- u8 vdbox_sfc_access = RUNTIME_INFO(engine->i915)->vdbox_sfc_access;
+ u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;
i915_reg_t sfc_forced_lock, sfc_forced_lock_ack;
u32 sfc_forced_lock_bit, sfc_forced_lock_ack_bit;
i915_reg_t sfc_usage;
@@ -417,7 +417,7 @@ static int gen11_lock_sfc(struct intel_engine_cs *engine, u32 *hw_mask)
static void gen11_unlock_sfc(struct intel_engine_cs *engine)
{
struct intel_uncore *uncore = engine->uncore;
- u8 vdbox_sfc_access = RUNTIME_INFO(engine->i915)->vdbox_sfc_access;
+ u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;
i915_reg_t sfc_forced_lock;
u32 sfc_forced_lock_bit;
@@ -1246,7 +1246,7 @@ void intel_gt_handle_error(struct intel_gt *gt,
*/
wakeref = intel_runtime_pm_get(gt->uncore->rpm);
- engine_mask &= INTEL_INFO(gt->i915)->engine_mask;
+ engine_mask &= gt->info.engine_mask;
if (flags & I915_ERROR_CAPTURE) {
i915_capture_error_state(gt->i915);
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 68a08486fc87..b09b83deecef 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -649,7 +649,7 @@ static inline int mi_set_context(struct i915_request *rq,
struct drm_i915_private *i915 = engine->i915;
enum intel_engine_id id;
const int num_engines =
- IS_HASWELL(i915) ? RUNTIME_INFO(i915)->num_engines - 1 : 0;
+ IS_HASWELL(i915) ? engine->gt->info.num_engines - 1 : 0;
bool force_restore = false;
int len;
u32 *cs;
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index daa4aabab9a7..b3678b5f9655 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -963,7 +963,7 @@ slice_semaphore_queue(struct intel_engine_cs *outer,
goto out;
if (i915_request_wait(head, 0,
- 2 * RUNTIME_INFO(outer->i915)->num_engines * (count + 2) * (count + 3)) < 0) {
+ 2 * engine->gt->info.num_engines * (count + 2) * (count + 3)) < 0) {
pr_err("Failed to slice along semaphore chain of length (%d, %d)!\n",
count, n);
GEM_TRACE_DUMP();
@@ -3569,8 +3569,7 @@ static int smoke_crescendo(struct preempt_smoke *smoke, unsigned int flags)
}
pr_info("Submitted %lu crescendo:%x requests across %d engines and %d contexts\n",
- count, flags,
- RUNTIME_INFO(smoke->gt->i915)->num_engines, smoke->ncontext);
+ count, flags, smoke->gt->info.num_engines, smoke->ncontext);
return 0;
}
@@ -3597,8 +3596,7 @@ static int smoke_random(struct preempt_smoke *smoke, unsigned int flags)
} while (count < smoke->ncontext && !__igt_timeout(end_time, NULL));
pr_info("Submitted %lu random:%x requests across %d engines and %d contexts\n",
- count, flags,
- RUNTIME_INFO(smoke->gt->i915)->num_engines, smoke->ncontext);
+ count, flags, smoke->gt->info.num_engines, smoke->ncontext);
return 0;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index fbdd6b0677db..c10ae1660e53 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -106,7 +106,7 @@ static void __guc_ads_init(struct intel_guc *guc)
blob->system_info.vdbox_enable_mask = VDBOX_MASK(gt);
blob->system_info.vebox_enable_mask = VEBOX_MASK(gt);
- blob->system_info.vdbox_sfc_support_mask = RUNTIME_INFO(dev_priv)->vdbox_sfc_access;
+ blob->system_info.vdbox_sfc_support_mask = gt->info.vdbox_sfc_access;
base = intel_guc_ggtt_offset(guc, guc->ads_vma);
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index ddefc52f6e09..e047a4950f5f 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -347,7 +347,7 @@ static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
gvt_dbg_mmio("vgpu%d: request GUC Reset\n", vgpu->id);
vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET;
}
- engine_mask &= INTEL_INFO(vgpu->gvt->gt->i915)->engine_mask;
+ engine_mask &= vgpu->gvt->gt->info.engine_mask;
}
/* vgpu_lock already hold by emulate mmio r/w */
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 8594a8ef08ce..cad1620d2a7e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -34,6 +34,7 @@
#include "gem/i915_gem_context.h"
#include "gt/intel_gt_buffer_pool.h"
#include "gt/intel_gt_clock_utils.h"
+#include "gt/intel_gt.h"
#include "gt/intel_gt_pm.h"
#include "gt/intel_gt_requests.h"
#include "gt/intel_reset.h"
@@ -61,6 +62,7 @@ static int i915_capabilities(struct seq_file *m, void *data)
intel_device_info_print_static(INTEL_INFO(i915), &p);
intel_device_info_print_runtime(RUNTIME_INFO(i915), &p);
+ intel_gt_info_print(&i915->gt.info, &p);
intel_driver_caps_print(&i915->caps, &p);
kernel_param_lock(THIS_MODULE);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 611287353420..67789df42be8 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -886,6 +886,7 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv)
intel_device_info_print_static(INTEL_INFO(dev_priv), &p);
intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p);
+ intel_gt_info_print(&dev_priv->gt.info, &p);
}
if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 17cad4e2cb9c..fa01bf0929e0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1254,7 +1254,7 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
/* Iterator over subset of engines selected by mask */
#define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
- for ((tmp__) = (mask__) & INTEL_INFO((gt__)->i915)->engine_mask; \
+ for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
(tmp__) ? \
((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
0;)
@@ -1561,12 +1561,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
#define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
-#define HAS_ENGINE(gt, id) __HAS_ENGINE(INTEL_INFO((gt)->i915)->engine_mask, id)
+#define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
#define ENGINE_INSTANCES_MASK(gt, first, count) ({ \
unsigned int first__ = (first); \
unsigned int count__ = (count); \
- (INTEL_INFO((gt)->i915)->engine_mask & \
+ ((gt)->info.engine_mask & \
GENMASK(first__ + count__ - 1, first__)) >> first__; \
})
#define VDBOX_MASK(gt) \
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 866166ada10e..9cb9aa39c33d 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -42,6 +42,7 @@
#include "gem/i915_gem_context.h"
#include "gem/i915_gem_lmem.h"
+#include "gt/intel_gt.h"
#include "gt/intel_gt_pm.h"
#include "i915_drv.h"
@@ -619,16 +620,15 @@ static void print_error_vma(struct drm_i915_error_state_buf *m,
}
static void err_print_capabilities(struct drm_i915_error_state_buf *m,
- const struct intel_device_info *info,
- const struct intel_runtime_info *runtime,
- const struct intel_driver_caps *caps)
+ struct i915_gpu_coredump *error)
{
struct drm_printer p = i915_error_printer(m);
- intel_device_info_print_static(info, &p);
- intel_device_info_print_runtime(runtime, &p);
- intel_device_info_print_topology(&runtime->sseu, &p);
- intel_driver_caps_print(caps, &p);
+ intel_device_info_print_static(&error->device_info, &p);
+ intel_device_info_print_runtime(&error->runtime_info, &p);
+ intel_device_info_print_topology(&error->runtime_info.sseu, &p);
+ intel_gt_info_print(&error->gt->info, &p);
+ intel_driver_caps_print(&error->driver_caps, &p);
}
static void err_print_params(struct drm_i915_error_state_buf *m,
@@ -798,8 +798,7 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
if (error->display)
intel_display_print_error_state(m, error->display);
- err_print_capabilities(m, &error->device_info, &error->runtime_info,
- &error->driver_caps);
+ err_print_capabilities(m, error);
err_print_params(m, &error->params);
}
@@ -1630,6 +1629,11 @@ static void gt_record_regs(struct intel_gt_coredump *gt)
gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER);
}
+static void gt_record_info(struct intel_gt_coredump *gt)
+{
+ memcpy(>->info, >->_gt->info, sizeof(struct intel_gt_info));
+}
+
/*
* Generate a semi-unique error code. The code is not meant to have meaning, The
* code's only purpose is to try to prevent false duplicated bug reports by
@@ -1808,6 +1812,7 @@ struct i915_gpu_coredump *i915_gpu_coredump(struct drm_i915_private *i915)
return ERR_PTR(-ENOMEM);
}
+ gt_record_info(error->gt);
gt_record_engines(error->gt, compress);
if (INTEL_INFO(i915)->has_gt_uc)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h b/drivers/gpu/drm/i915/i915_gpu_error.h
index 76b80fbfb7e9..0220b0992808 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.h
+++ b/drivers/gpu/drm/i915/i915_gpu_error.h
@@ -15,6 +15,7 @@
#include <drm/drm_mm.h>
#include "gt/intel_engine.h"
+#include "gt/intel_gt_types.h"
#include "gt/uc/intel_uc_fw.h"
#include "intel_device_info.h"
@@ -118,6 +119,8 @@ struct intel_gt_coredump {
bool awake;
bool simulated;
+ struct intel_gt_info info;
+
/* Generic register state */
u32 eir;
u32 pgtbl_er;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index e5fdf17cd9cd..7658025a791f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -168,7 +168,7 @@
.gpu_reset_clobbers_display = true, \
.hws_needs_physical = 1, \
.unfenced_needs_alignment = 1, \
- .engine_mask = BIT(RCS0), \
+ .max_engine_mask = BIT(RCS0), \
.has_snoop = true, \
.has_coherent_ggtt = false, \
.dma_mask_size = 32, \
@@ -188,7 +188,7 @@
.gpu_reset_clobbers_display = true, \
.hws_needs_physical = 1, \
.unfenced_needs_alignment = 1, \
- .engine_mask = BIT(RCS0), \
+ .max_engine_mask = BIT(RCS0), \
.has_snoop = true, \
.has_coherent_ggtt = false, \
.dma_mask_size = 32, \
@@ -225,7 +225,7 @@ static const struct intel_device_info i865g_info = {
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
.display.has_gmch = 1, \
.gpu_reset_clobbers_display = true, \
- .engine_mask = BIT(RCS0), \
+ .max_engine_mask = BIT(RCS0), \
.has_snoop = true, \
.has_coherent_ggtt = true, \
.dma_mask_size = 32, \
@@ -316,7 +316,7 @@ static const struct intel_device_info pnv_m_info = {
.display.has_hotplug = 1, \
.display.has_gmch = 1, \
.gpu_reset_clobbers_display = true, \
- .engine_mask = BIT(RCS0), \
+ .max_engine_mask = BIT(RCS0), \
.has_snoop = true, \
.has_coherent_ggtt = true, \
.dma_mask_size = 36, \
@@ -348,7 +348,7 @@ static const struct intel_device_info i965gm_info = {
static const struct intel_device_info g45_info = {
GEN4_FEATURES,
PLATFORM(INTEL_G45),
- .engine_mask = BIT(RCS0) | BIT(VCS0),
+ .max_engine_mask = BIT(RCS0) | BIT(VCS0),
.gpu_reset_clobbers_display = false,
};
@@ -358,7 +358,7 @@ static const struct intel_device_info gm45_info = {
.is_mobile = 1,
.display.has_fbc = 1,
.display.supports_tv = 1,
- .engine_mask = BIT(RCS0) | BIT(VCS0),
+ .max_engine_mask = BIT(RCS0) | BIT(VCS0),
.gpu_reset_clobbers_display = false,
};
@@ -367,7 +367,7 @@ static const struct intel_device_info gm45_info = {
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
.display.has_hotplug = 1, \
- .engine_mask = BIT(RCS0) | BIT(VCS0), \
+ .max_engine_mask = BIT(RCS0) | BIT(VCS0), \
.has_snoop = true, \
.has_coherent_ggtt = true, \
/* ilk does support rc6, but we do not implement [power] contexts */ \
@@ -397,7 +397,7 @@ static const struct intel_device_info ilk_m_info = {
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
.display.has_hotplug = 1, \
.display.has_fbc = 1, \
- .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
+ .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
.has_coherent_ggtt = true, \
.has_llc = 1, \
.has_rc6 = 1, \
@@ -448,7 +448,7 @@ static const struct intel_device_info snb_m_gt2_info = {
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
.display.has_hotplug = 1, \
.display.has_fbc = 1, \
- .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
+ .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
.has_coherent_ggtt = true, \
.has_llc = 1, \
.has_rc6 = 1, \
@@ -519,7 +519,7 @@ static const struct intel_device_info vlv_info = {
.ppgtt_size = 31,
.has_snoop = true,
.has_coherent_ggtt = false,
- .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
+ .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
.display_mmio_offset = VLV_DISPLAY_BASE,
I9XX_PIPE_OFFSETS,
I9XX_CURSOR_OFFSETS,
@@ -530,7 +530,7 @@ static const struct intel_device_info vlv_info = {
#define G75_FEATURES \
GEN7_FEATURES, \
- .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
+ .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
.display.has_ddi = 1, \
@@ -597,7 +597,7 @@ static const struct intel_device_info bdw_rsvd_info = {
static const struct intel_device_info bdw_gt3_info = {
BDW_PLATFORM,
.gt = 3,
- .engine_mask =
+ .max_engine_mask =
BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
};
@@ -608,7 +608,7 @@ static const struct intel_device_info chv_info = {
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
.display.has_hotplug = 1,
.is_lp = 1,
- .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
+ .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
.has_64bit_reloc = 1,
.has_runtime_pm = 1,
.has_rc6 = 1,
@@ -661,7 +661,7 @@ static const struct intel_device_info skl_gt2_info = {
#define SKL_GT3_PLUS_PLATFORM \
SKL_PLATFORM, \
- .engine_mask = \
+ .max_engine_mask = \
BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
@@ -680,7 +680,7 @@ static const struct intel_device_info skl_gt4_info = {
.is_lp = 1, \
.num_supported_dbuf_slices = 1, \
.display.has_hotplug = 1, \
- .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
+ .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
@@ -743,7 +743,7 @@ static const struct intel_device_info kbl_gt2_info = {
static const struct intel_device_info kbl_gt3_info = {
KBL_PLATFORM,
.gt = 3,
- .engine_mask =
+ .max_engine_mask =
BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
};
@@ -764,7 +764,7 @@ static const struct intel_device_info cfl_gt2_info = {
static const struct intel_device_info cfl_gt3_info = {
CFL_PLATFORM,
.gt = 3,
- .engine_mask =
+ .max_engine_mask =
BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
};
@@ -833,7 +833,7 @@ static const struct intel_device_info cnl_info = {
static const struct intel_device_info icl_info = {
GEN11_FEATURES,
PLATFORM(INTEL_ICELAKE),
- .engine_mask =
+ .max_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
};
@@ -841,7 +841,7 @@ static const struct intel_device_info ehl_info = {
GEN11_FEATURES,
PLATFORM(INTEL_ELKHARTLAKE),
.require_force_probe = 1,
- .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
+ .max_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
.ppgtt_size = 36,
};
@@ -877,7 +877,7 @@ static const struct intel_device_info tgl_info = {
GEN12_FEATURES,
PLATFORM(INTEL_TIGERLAKE),
.display.has_modular_fia = 1,
- .engine_mask =
+ .max_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
};
@@ -890,7 +890,7 @@ static const struct intel_device_info rkl_info = {
BIT(TRANSCODER_C),
.require_force_probe = 1,
.display.has_psr_hw_tracking = 0,
- .engine_mask =
+ .max_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
};
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 92ebea35c752..a362a66fce11 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -92,7 +92,6 @@ static const char *iommu_name(void)
void intel_device_info_print_static(const struct intel_device_info *info,
struct drm_printer *p)
{
- drm_printf(p, "engines: %x\n", info->engine_mask);
drm_printf(p, "gen: %d\n", info->gen);
drm_printf(p, "gt: %d\n", info->gt);
drm_printf(p, "iommu: %s\n", iommu_name());
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index fa60fdc1d75a..f03ed95af190 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -157,7 +157,7 @@ struct intel_device_info {
u8 gen;
u8 gt; /* GT number, 0 if undefined */
- intel_engine_mask_t engine_mask; /* Engines supported by the HW */
+ intel_engine_mask_t max_engine_mask; /* Engines supported by the HW */
enum intel_platform platform;
@@ -219,8 +219,6 @@ struct intel_runtime_info {
u8 num_sprites[I915_MAX_PIPES];
u8 num_scalers[I915_MAX_PIPES];
- u8 num_engines;
-
/* Slice/subslice/EU info */
struct sseu_dev_info sseu;
@@ -228,9 +226,6 @@ struct intel_runtime_info {
u32 cs_timestamp_frequency_hz;
u32 cs_timestamp_period_ns;
-
- /* Media engine access to SFC per instance */
- u8 vdbox_sfc_access;
};
struct intel_driver_caps {
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index bd4b45191f7b..f5548875836c 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1530,7 +1530,7 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
if (INTEL_GEN(i915) >= 11) {
/* we'll prune the domains of missing engines later */
- intel_engine_mask_t emask = INTEL_INFO(i915)->engine_mask;
+ intel_engine_mask_t emask = INTEL_INFO(i915)->max_engine_mask;
int i;
uncore->funcs.force_wake_get = fw_domains_get_with_fallback;
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c
index 9271aad7f779..57dd6f5122ee 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -1454,7 +1454,7 @@ static int live_breadcrumbs_smoketest(void *arg)
idx++;
}
pr_info("Completed %lu waits for %lu fences across %d engines and %d cpus\n",
- num_waits, num_fences, RUNTIME_INFO(i915)->num_engines, ncpus);
+ num_waits, num_fences, idx, ncpus);
ret = igt_live_test_end(&live) ?: ret;
out_contexts:
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 9b105b811f1f..0916efa31889 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -190,7 +190,8 @@ struct drm_i915_private *mock_gem_device(void)
mock_init_ggtt(i915, &i915->ggtt);
i915->gt.vm = i915_vm_get(&i915->ggtt.vm);
- mkwrite_device_info(i915)->engine_mask = BIT(0);
+ mkwrite_device_info(i915)->max_engine_mask = BIT(0);
+ i915->gt.info.engine_mask = BIT(0);
i915->gt.engine[RCS0] = mock_engine(i915, "mock", RCS0);
if (!i915->gt.engine[RCS0])
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH 5/7] drm/i915: Introduce gt_init_mmio
2020-06-25 23:42 [Intel-gfx] [PATCH 0/7] Move some device capabilities under intel_gt Daniele Ceraolo Spurio
` (3 preceding siblings ...)
2020-06-25 23:42 ` [Intel-gfx] [PATCH 4/7] drm/i915: Move the engine mask to intel_gt_info Daniele Ceraolo Spurio
@ 2020-06-25 23:42 ` Daniele Ceraolo Spurio
2020-06-26 14:46 ` Tvrtko Ursulin
2020-06-25 23:42 ` [Intel-gfx] [PATCH 6/7] drm/i915/sseu: Move sseu detection and dump to intel_sseu Daniele Ceraolo Spurio
` (3 subsequent siblings)
8 siblings, 1 reply; 26+ messages in thread
From: Daniele Ceraolo Spurio @ 2020-06-25 23:42 UTC (permalink / raw)
To: intel-gfx
We already call 2 gt-related init_mmio functions in driver_mmio_probe
and a 3rd one will be added by a follow-up patch, so pre-emptively
introduce a gt_init_mmio function to group them.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Andi Shyti <andi.shyti@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt.c | 7 +++++++
drivers/gpu/drm/i915/gt/intel_gt.h | 1 +
drivers/gpu/drm/i915/i915_drv.c | 4 +---
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index d0ae1cb5c7c9..949114f09b82 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -44,6 +44,13 @@ void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt)
gt->ggtt = ggtt;
}
+int intel_gt_init_mmio(struct intel_gt *gt)
+{
+ intel_uc_init_mmio(>->uc);
+
+ return intel_engines_init_mmio(gt);
+}
+
static void init_unused_ring(struct intel_gt *gt, u32 base)
{
struct intel_uncore *uncore = gt->uncore;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index 15142e2a3b22..4bd64ab2b686 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -36,6 +36,7 @@ static inline struct intel_gt *huc_to_gt(struct intel_huc *huc)
void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt);
+int intel_gt_init_mmio(struct intel_gt *gt);
int __must_check intel_gt_init_hw(struct intel_gt *gt);
int intel_gt_init(struct intel_gt *gt);
void intel_gt_driver_register(struct intel_gt *gt);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 67789df42be8..5fd5af4bc855 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -531,9 +531,7 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
/* Try to make sure MCHBAR is enabled before poking at it */
intel_setup_mchbar(dev_priv);
- intel_uc_init_mmio(&dev_priv->gt.uc);
-
- ret = intel_engines_init_mmio(&dev_priv->gt);
+ ret = intel_gt_init_mmio(&dev_priv->gt);
if (ret)
goto err_uncore;
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH 6/7] drm/i915/sseu: Move sseu detection and dump to intel_sseu
2020-06-25 23:42 [Intel-gfx] [PATCH 0/7] Move some device capabilities under intel_gt Daniele Ceraolo Spurio
` (4 preceding siblings ...)
2020-06-25 23:42 ` [Intel-gfx] [PATCH 5/7] drm/i915: Introduce gt_init_mmio Daniele Ceraolo Spurio
@ 2020-06-25 23:42 ` Daniele Ceraolo Spurio
2020-06-26 15:00 ` Tvrtko Ursulin
2020-06-25 23:42 ` [Intel-gfx] [PATCH 7/7] drm/i915/sseu: Move sseu_info under gt_info Daniele Ceraolo Spurio
` (2 subsequent siblings)
8 siblings, 1 reply; 26+ messages in thread
From: Daniele Ceraolo Spurio @ 2020-06-25 23:42 UTC (permalink / raw)
To: intel-gfx
Keep all the SSEU code in the relevant file. The code has also been
updated to use intel_gt instead of dev_priv.
Based on an original patch by Sandeep.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Andi Shyti <andi.shyti@intel.com>
Cc: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
drivers/gpu/drm/i915/gt/intel_sseu.c | 587 +++++++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_sseu.h | 8 +
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 584 +---------------------
drivers/gpu/drm/i915/intel_device_info.h | 2 -
7 files changed, 600 insertions(+), 586 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 949114f09b82..de95930f8627 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -47,6 +47,7 @@ void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt)
int intel_gt_init_mmio(struct intel_gt *gt)
{
intel_uc_init_mmio(>->uc);
+ intel_sseu_info_init(gt);
return intel_engines_init_mmio(gt);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index d173271c7397..006f9118b319 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -60,6 +60,548 @@ intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
return hweight32(intel_sseu_get_subslices(sseu, slice));
}
+static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice,
+ int subslice)
+{
+ int slice_stride = sseu->max_subslices * sseu->eu_stride;
+
+ return slice * slice_stride + subslice * sseu->eu_stride;
+}
+
+static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
+ int subslice)
+{
+ int i, offset = sseu_eu_idx(sseu, slice, subslice);
+ u16 eu_mask = 0;
+
+ for (i = 0; i < sseu->eu_stride; i++) {
+ eu_mask |= ((u16)sseu->eu_mask[offset + i]) <<
+ (i * BITS_PER_BYTE);
+ }
+
+ return eu_mask;
+}
+
+static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice,
+ u16 eu_mask)
+{
+ int i, offset = sseu_eu_idx(sseu, slice, subslice);
+
+ for (i = 0; i < sseu->eu_stride; i++) {
+ sseu->eu_mask[offset + i] =
+ (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
+ }
+}
+
+static u16 compute_eu_total(const struct sseu_dev_info *sseu)
+{
+ u16 i, total = 0;
+
+ for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++)
+ total += hweight8(sseu->eu_mask[i]);
+
+ return total;
+}
+
+static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
+ u8 s_en, u32 ss_en, u16 eu_en)
+{
+ int s, ss;
+
+ /* ss_en represents entire subslice mask across all slices */
+ GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
+ sizeof(ss_en) * BITS_PER_BYTE);
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ if ((s_en & BIT(s)) == 0)
+ continue;
+
+ sseu->slice_mask |= BIT(s);
+
+ intel_sseu_set_subslices(sseu, s, ss_en);
+
+ for (ss = 0; ss < sseu->max_subslices; ss++)
+ if (intel_sseu_has_subslice(sseu, s, ss))
+ sseu_set_eus(sseu, s, ss, eu_en);
+ }
+ sseu->eu_per_subslice = hweight16(eu_en);
+ sseu->eu_total = compute_eu_total(sseu);
+}
+
+static void gen12_sseu_info_init(struct intel_gt *gt)
+{
+ struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
+ struct intel_uncore *uncore = gt->uncore;
+ u8 s_en;
+ u32 dss_en;
+ u16 eu_en = 0;
+ u8 eu_en_fuse;
+ int eu;
+
+ /*
+ * Gen12 has Dual-Subslices, which behave similarly to 2 gen11 SS.
+ * Instead of splitting these, provide userspace with an array
+ * of DSS to more closely represent the hardware resource.
+ */
+ intel_sseu_set_info(sseu, 1, 6, 16);
+
+ s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
+ GEN11_GT_S_ENA_MASK;
+
+ dss_en = intel_uncore_read(uncore, GEN12_GT_DSS_ENABLE);
+
+ /* one bit per pair of EUs */
+ eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
+ GEN11_EU_DIS_MASK);
+ for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
+ if (eu_en_fuse & BIT(eu))
+ eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
+
+ gen11_compute_sseu_info(sseu, s_en, dss_en, eu_en);
+
+ /* TGL only supports slice-level power gating */
+ sseu->has_slice_pg = 1;
+}
+
+static void gen11_sseu_info_init(struct intel_gt *gt)
+{
+ struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
+ struct intel_uncore *uncore = gt->uncore;
+ u8 s_en;
+ u32 ss_en;
+ u8 eu_en;
+
+ if (IS_ELKHARTLAKE(gt->i915))
+ intel_sseu_set_info(sseu, 1, 4, 8);
+ else
+ intel_sseu_set_info(sseu, 1, 8, 8);
+
+ s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
+ GEN11_GT_S_ENA_MASK;
+ ss_en = ~intel_uncore_read(uncore, GEN11_GT_SUBSLICE_DISABLE);
+
+ eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
+ GEN11_EU_DIS_MASK);
+
+ gen11_compute_sseu_info(sseu, s_en, ss_en, eu_en);
+
+ /* ICL has no power gating restrictions. */
+ sseu->has_slice_pg = 1;
+ sseu->has_subslice_pg = 1;
+ sseu->has_eu_pg = 1;
+}
+
+static void gen10_sseu_info_init(struct intel_gt *gt)
+{
+ struct intel_uncore *uncore = gt->uncore;
+ struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
+ const u32 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
+ int s, ss;
+ const int eu_mask = 0xff;
+ u32 subslice_mask, eu_en;
+
+ intel_sseu_set_info(sseu, 6, 4, 8);
+
+ sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
+ GEN10_F2_S_ENA_SHIFT;
+
+ /* Slice0 */
+ eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE0);
+ for (ss = 0; ss < sseu->max_subslices; ss++)
+ sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask);
+ /* Slice1 */
+ sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask);
+ eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE1);
+ sseu_set_eus(sseu, 1, 1, eu_en & eu_mask);
+ /* Slice2 */
+ sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask);
+ sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask);
+ /* Slice3 */
+ sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask);
+ eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE2);
+ sseu_set_eus(sseu, 3, 1, eu_en & eu_mask);
+ /* Slice4 */
+ sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask);
+ sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask);
+ /* Slice5 */
+ sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask);
+ eu_en = ~intel_uncore_read(uncore, GEN10_EU_DISABLE3);
+ sseu_set_eus(sseu, 5, 1, eu_en & eu_mask);
+
+ subslice_mask = (1 << 4) - 1;
+ subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
+ GEN10_F2_SS_DIS_SHIFT);
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ u32 subslice_mask_with_eus = subslice_mask;
+
+ for (ss = 0; ss < sseu->max_subslices; ss++) {
+ if (sseu_get_eus(sseu, s, ss) == 0)
+ subslice_mask_with_eus &= ~BIT(ss);
+ }
+
+ /*
+ * Slice0 can have up to 3 subslices, but there are only 2 in
+ * slice1/2.
+ */
+ intel_sseu_set_subslices(sseu, s, s == 0 ?
+ subslice_mask_with_eus :
+ subslice_mask_with_eus & 0x3);
+ }
+
+ sseu->eu_total = compute_eu_total(sseu);
+
+ /*
+ * CNL is expected to always have a uniform distribution
+ * of EU across subslices with the exception that any one
+ * EU in any one subslice may be fused off for die
+ * recovery.
+ */
+ sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ?
+ DIV_ROUND_UP(sseu->eu_total,
+ intel_sseu_subslice_total(sseu)) :
+ 0;
+
+ /* No restrictions on Power Gating */
+ sseu->has_slice_pg = 1;
+ sseu->has_subslice_pg = 1;
+ sseu->has_eu_pg = 1;
+}
+
+static void cherryview_sseu_info_init(struct intel_gt *gt)
+{
+ struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
+ u32 fuse;
+ u8 subslice_mask = 0;
+
+ fuse = intel_uncore_read(gt->uncore, CHV_FUSE_GT);
+
+ sseu->slice_mask = BIT(0);
+ intel_sseu_set_info(sseu, 1, 2, 8);
+
+ if (!(fuse & CHV_FGT_DISABLE_SS0)) {
+ u8 disabled_mask =
+ ((fuse & CHV_FGT_EU_DIS_SS0_R0_MASK) >>
+ CHV_FGT_EU_DIS_SS0_R0_SHIFT) |
+ (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
+ CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
+
+ subslice_mask |= BIT(0);
+ sseu_set_eus(sseu, 0, 0, ~disabled_mask);
+ }
+
+ if (!(fuse & CHV_FGT_DISABLE_SS1)) {
+ u8 disabled_mask =
+ ((fuse & CHV_FGT_EU_DIS_SS1_R0_MASK) >>
+ CHV_FGT_EU_DIS_SS1_R0_SHIFT) |
+ (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
+ CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
+
+ subslice_mask |= BIT(1);
+ sseu_set_eus(sseu, 0, 1, ~disabled_mask);
+ }
+
+ intel_sseu_set_subslices(sseu, 0, subslice_mask);
+
+ sseu->eu_total = compute_eu_total(sseu);
+
+ /*
+ * CHV expected to always have a uniform distribution of EU
+ * across subslices.
+ */
+ sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ?
+ sseu->eu_total /
+ intel_sseu_subslice_total(sseu) :
+ 0;
+ /*
+ * CHV supports subslice power gating on devices with more than
+ * one subslice, and supports EU power gating on devices with
+ * more than one EU pair per subslice.
+ */
+ sseu->has_slice_pg = 0;
+ sseu->has_subslice_pg = intel_sseu_subslice_total(sseu) > 1;
+ sseu->has_eu_pg = (sseu->eu_per_subslice > 2);
+}
+
+static void gen9_sseu_info_init(struct intel_gt *gt)
+{
+ struct drm_i915_private *i915 = gt->i915;
+ struct intel_device_info *info = mkwrite_device_info(i915);
+ struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
+ struct intel_uncore *uncore = gt->uncore;
+ int s, ss;
+ u32 fuse2, eu_disable, subslice_mask;
+ const u8 eu_mask = 0xff;
+
+ fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
+ sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
+
+ /* BXT has a single slice and at most 3 subslices. */
+ intel_sseu_set_info(sseu, IS_GEN9_LP(i915) ? 1 : 3,
+ IS_GEN9_LP(i915) ? 3 : 4, 8);
+
+ /*
+ * The subslice disable field is global, i.e. it applies
+ * to each of the enabled slices.
+ */
+ subslice_mask = (1 << sseu->max_subslices) - 1;
+ subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >>
+ GEN9_F2_SS_DIS_SHIFT);
+
+ /*
+ * Iterate through enabled slices and subslices to
+ * count the total enabled EU.
+ */
+ for (s = 0; s < sseu->max_slices; s++) {
+ if (!(sseu->slice_mask & BIT(s)))
+ /* skip disabled slice */
+ continue;
+
+ intel_sseu_set_subslices(sseu, s, subslice_mask);
+
+ eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s));
+ for (ss = 0; ss < sseu->max_subslices; ss++) {
+ int eu_per_ss;
+ u8 eu_disabled_mask;
+
+ if (!intel_sseu_has_subslice(sseu, s, ss))
+ /* skip disabled subslice */
+ continue;
+
+ eu_disabled_mask = (eu_disable >> (ss * 8)) & eu_mask;
+
+ sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
+
+ eu_per_ss = sseu->max_eus_per_subslice -
+ hweight8(eu_disabled_mask);
+
+ /*
+ * Record which subslice(s) has(have) 7 EUs. we
+ * can tune the hash used to spread work among
+ * subslices if they are unbalanced.
+ */
+ if (eu_per_ss == 7)
+ sseu->subslice_7eu[s] |= BIT(ss);
+ }
+ }
+
+ sseu->eu_total = compute_eu_total(sseu);
+
+ /*
+ * SKL is expected to always have a uniform distribution
+ * of EU across subslices with the exception that any one
+ * EU in any one subslice may be fused off for die
+ * recovery. BXT is expected to be perfectly uniform in EU
+ * distribution.
+ */
+ sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ?
+ DIV_ROUND_UP(sseu->eu_total,
+ intel_sseu_subslice_total(sseu)) :
+ 0;
+ /*
+ * SKL+ supports slice power gating on devices with more than
+ * one slice, and supports EU power gating on devices with
+ * more than one EU pair per subslice. BXT+ supports subslice
+ * power gating on devices with more than one subslice, and
+ * supports EU power gating on devices with more than one EU
+ * pair per subslice.
+ */
+ sseu->has_slice_pg =
+ !IS_GEN9_LP(i915) && hweight8(sseu->slice_mask) > 1;
+ sseu->has_subslice_pg =
+ IS_GEN9_LP(i915) && intel_sseu_subslice_total(sseu) > 1;
+ sseu->has_eu_pg = sseu->eu_per_subslice > 2;
+
+ if (IS_GEN9_LP(i915)) {
+#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss)))
+ info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3;
+
+ sseu->min_eu_in_pool = 0;
+ if (info->has_pooled_eu) {
+ if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0))
+ sseu->min_eu_in_pool = 3;
+ else if (IS_SS_DISABLED(1))
+ sseu->min_eu_in_pool = 6;
+ else
+ sseu->min_eu_in_pool = 9;
+ }
+#undef IS_SS_DISABLED
+ }
+}
+
+static void bdw_sseu_info_init(struct intel_gt *gt)
+{
+ struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
+ struct intel_uncore *uncore = gt->uncore;
+ int s, ss;
+ u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */
+ u32 eu_disable0, eu_disable1, eu_disable2;
+
+ fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
+ sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
+ intel_sseu_set_info(sseu, 3, 3, 8);
+
+ /*
+ * The subslice disable field is global, i.e. it applies
+ * to each of the enabled slices.
+ */
+ subslice_mask = GENMASK(sseu->max_subslices - 1, 0);
+ subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >>
+ GEN8_F2_SS_DIS_SHIFT);
+ eu_disable0 = intel_uncore_read(uncore, GEN8_EU_DISABLE0);
+ eu_disable1 = intel_uncore_read(uncore, GEN8_EU_DISABLE1);
+ eu_disable2 = intel_uncore_read(uncore, GEN8_EU_DISABLE2);
+ eu_disable[0] = eu_disable0 & GEN8_EU_DIS0_S0_MASK;
+ eu_disable[1] = (eu_disable0 >> GEN8_EU_DIS0_S1_SHIFT) |
+ ((eu_disable1 & GEN8_EU_DIS1_S1_MASK) <<
+ (32 - GEN8_EU_DIS0_S1_SHIFT));
+ eu_disable[2] = (eu_disable1 >> GEN8_EU_DIS1_S2_SHIFT) |
+ ((eu_disable2 & GEN8_EU_DIS2_S2_MASK) <<
+ (32 - GEN8_EU_DIS1_S2_SHIFT));
+
+ /*
+ * Iterate through enabled slices and subslices to
+ * count the total enabled EU.
+ */
+ for (s = 0; s < sseu->max_slices; s++) {
+ if (!(sseu->slice_mask & BIT(s)))
+ /* skip disabled slice */
+ continue;
+
+ intel_sseu_set_subslices(sseu, s, subslice_mask);
+
+ for (ss = 0; ss < sseu->max_subslices; ss++) {
+ u8 eu_disabled_mask;
+ u32 n_disabled;
+
+ if (!intel_sseu_has_subslice(sseu, s, ss))
+ /* skip disabled subslice */
+ continue;
+
+ eu_disabled_mask =
+ eu_disable[s] >> (ss * sseu->max_eus_per_subslice);
+
+ sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
+
+ n_disabled = hweight8(eu_disabled_mask);
+
+ /*
+ * Record which subslices have 7 EUs.
+ */
+ if (sseu->max_eus_per_subslice - n_disabled == 7)
+ sseu->subslice_7eu[s] |= 1 << ss;
+ }
+ }
+
+ sseu->eu_total = compute_eu_total(sseu);
+
+ /*
+ * BDW is expected to always have a uniform distribution of EU across
+ * subslices with the exception that any one EU in any one subslice may
+ * be fused off for die recovery.
+ */
+ sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ?
+ DIV_ROUND_UP(sseu->eu_total,
+ intel_sseu_subslice_total(sseu)) :
+ 0;
+
+ /*
+ * BDW supports slice power gating on devices with more than
+ * one slice.
+ */
+ sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1;
+ sseu->has_subslice_pg = 0;
+ sseu->has_eu_pg = 0;
+}
+
+static void hsw_sseu_info_init(struct intel_gt *gt)
+{
+ struct drm_i915_private *i915 = gt->i915;
+ struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
+ u32 fuse1;
+ u8 subslice_mask = 0;
+ int s, ss;
+
+ /*
+ * There isn't a register to tell us how many slices/subslices. We
+ * work off the PCI-ids here.
+ */
+ switch (INTEL_INFO(i915)->gt) {
+ default:
+ MISSING_CASE(INTEL_INFO(i915)->gt);
+ /* fall through */
+ case 1:
+ sseu->slice_mask = BIT(0);
+ subslice_mask = BIT(0);
+ break;
+ case 2:
+ sseu->slice_mask = BIT(0);
+ subslice_mask = BIT(0) | BIT(1);
+ break;
+ case 3:
+ sseu->slice_mask = BIT(0) | BIT(1);
+ subslice_mask = BIT(0) | BIT(1);
+ break;
+ }
+
+ fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);
+ switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) {
+ default:
+ MISSING_CASE((fuse1 & HSW_F1_EU_DIS_MASK) >>
+ HSW_F1_EU_DIS_SHIFT);
+ /* fall through */
+ case HSW_F1_EU_DIS_10EUS:
+ sseu->eu_per_subslice = 10;
+ break;
+ case HSW_F1_EU_DIS_8EUS:
+ sseu->eu_per_subslice = 8;
+ break;
+ case HSW_F1_EU_DIS_6EUS:
+ sseu->eu_per_subslice = 6;
+ break;
+ }
+
+ intel_sseu_set_info(sseu, hweight8(sseu->slice_mask),
+ hweight8(subslice_mask),
+ sseu->eu_per_subslice);
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ intel_sseu_set_subslices(sseu, s, subslice_mask);
+
+ for (ss = 0; ss < sseu->max_subslices; ss++) {
+ sseu_set_eus(sseu, s, ss,
+ (1UL << sseu->eu_per_subslice) - 1);
+ }
+ }
+
+ sseu->eu_total = compute_eu_total(sseu);
+
+ /* No powergating for you. */
+ sseu->has_slice_pg = 0;
+ sseu->has_subslice_pg = 0;
+ sseu->has_eu_pg = 0;
+}
+
+void intel_sseu_info_init(struct intel_gt *gt)
+{
+ struct drm_i915_private *i915 = gt->i915;
+
+ if (IS_HASWELL(i915))
+ hsw_sseu_info_init(gt);
+ else if (IS_CHERRYVIEW(i915))
+ cherryview_sseu_info_init(gt);
+ else if (IS_BROADWELL(i915))
+ bdw_sseu_info_init(gt);
+ else if (IS_GEN(i915, 9))
+ gen9_sseu_info_init(gt);
+ else if (IS_GEN(i915, 10))
+ gen10_sseu_info_init(gt);
+ else if (IS_GEN(i915, 11))
+ gen11_sseu_info_init(gt);
+ else if (INTEL_GEN(i915) >= 12)
+ gen12_sseu_info_init(gt);
+}
+
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
const struct intel_sseu *req_sseu)
{
@@ -173,3 +715,48 @@ u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
return rpcs;
}
+
+void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
+{
+ int s;
+
+ drm_printf(p, "slice total: %u, mask=%04x\n",
+ hweight8(sseu->slice_mask), sseu->slice_mask);
+ drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu));
+ for (s = 0; s < sseu->max_slices; s++) {
+ drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
+ s, intel_sseu_subslices_per_slice(sseu, s),
+ intel_sseu_get_subslices(sseu, s));
+ }
+ drm_printf(p, "EU total: %u\n", sseu->eu_total);
+ drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
+ drm_printf(p, "has slice power gating: %s\n",
+ yesno(sseu->has_slice_pg));
+ drm_printf(p, "has subslice power gating: %s\n",
+ yesno(sseu->has_subslice_pg));
+ drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg));
+}
+
+void intel_sseu_print_topology(const struct sseu_dev_info *sseu,
+ struct drm_printer *p)
+{
+ int s, ss;
+
+ if (sseu->max_slices == 0) {
+ drm_printf(p, "Unavailable\n");
+ return;
+ }
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
+ s, intel_sseu_subslices_per_slice(sseu, s),
+ intel_sseu_get_subslices(sseu, s));
+
+ for (ss = 0; ss < sseu->max_subslices; ss++) {
+ u16 enabled_eus = sseu_get_eus(sseu, s, ss);
+
+ drm_printf(p, "\tsubslice%d: %u EUs (0x%hx)\n",
+ ss, hweight16(enabled_eus), enabled_eus);
+ }
+ }
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index d1d225204f09..f9c007f001e7 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -13,6 +13,8 @@
#include "i915_gem.h"
struct drm_i915_private;
+struct intel_gt;
+struct drm_printer;
#define GEN_MAX_SLICES (6) /* CNL upper bound */
#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
@@ -94,7 +96,13 @@ u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice);
void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
u32 ss_mask);
+void intel_sseu_info_init(struct intel_gt *gt);
+
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
const struct intel_sseu *req_sseu);
+void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p);
+void intel_sseu_print_topology(const struct sseu_dev_info *sseu,
+ struct drm_printer *p);
+
#endif /* __INTEL_SSEU_H__ */
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index cad1620d2a7e..c893a82c2d99 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1323,7 +1323,7 @@ static int i915_rcs_topology(struct seq_file *m, void *unused)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct drm_printer p = drm_seq_file_printer(m);
- intel_device_info_print_topology(&RUNTIME_INFO(dev_priv)->sseu, &p);
+ intel_sseu_print_topology(&RUNTIME_INFO(dev_priv)->sseu, &p);
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 9cb9aa39c33d..99b4a0261b13 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -626,7 +626,7 @@ static void err_print_capabilities(struct drm_i915_error_state_buf *m,
intel_device_info_print_static(&error->device_info, &p);
intel_device_info_print_runtime(&error->runtime_info, &p);
- intel_device_info_print_topology(&error->runtime_info.sseu, &p);
+ intel_sseu_print_topology(&error->runtime_info.sseu, &p);
intel_gt_info_print(&error->gt->info, &p);
intel_driver_caps_print(&error->driver_caps, &p);
}
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index a362a66fce11..d8daf224cbd3 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -29,6 +29,7 @@
#include "display/intel_de.h"
#include "intel_device_info.h"
#include "i915_drv.h"
+#include "gt/intel_sseu.h"
#define PLATFORM_NAME(x) [INTEL_##x] = #x
static const char * const platform_names[] = {
@@ -111,581 +112,16 @@ void intel_device_info_print_static(const struct intel_device_info *info,
#undef PRINT_FLAG
}
-static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
-{
- int s;
-
- drm_printf(p, "slice total: %u, mask=%04x\n",
- hweight8(sseu->slice_mask), sseu->slice_mask);
- drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu));
- for (s = 0; s < sseu->max_slices; s++) {
- drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
- s, intel_sseu_subslices_per_slice(sseu, s),
- intel_sseu_get_subslices(sseu, s));
- }
- drm_printf(p, "EU total: %u\n", sseu->eu_total);
- drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
- drm_printf(p, "has slice power gating: %s\n",
- yesno(sseu->has_slice_pg));
- drm_printf(p, "has subslice power gating: %s\n",
- yesno(sseu->has_subslice_pg));
- drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg));
-}
-
void intel_device_info_print_runtime(const struct intel_runtime_info *info,
struct drm_printer *p)
{
- sseu_dump(&info->sseu, p);
+ intel_sseu_dump(&info->sseu, p);
drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq);
drm_printf(p, "CS timestamp frequency: %u Hz\n",
info->cs_timestamp_frequency_hz);
}
-static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice,
- int subslice)
-{
- int slice_stride = sseu->max_subslices * sseu->eu_stride;
-
- return slice * slice_stride + subslice * sseu->eu_stride;
-}
-
-static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
- int subslice)
-{
- int i, offset = sseu_eu_idx(sseu, slice, subslice);
- u16 eu_mask = 0;
-
- for (i = 0; i < sseu->eu_stride; i++) {
- eu_mask |= ((u16)sseu->eu_mask[offset + i]) <<
- (i * BITS_PER_BYTE);
- }
-
- return eu_mask;
-}
-
-static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice,
- u16 eu_mask)
-{
- int i, offset = sseu_eu_idx(sseu, slice, subslice);
-
- for (i = 0; i < sseu->eu_stride; i++) {
- sseu->eu_mask[offset + i] =
- (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
- }
-}
-
-void intel_device_info_print_topology(const struct sseu_dev_info *sseu,
- struct drm_printer *p)
-{
- int s, ss;
-
- if (sseu->max_slices == 0) {
- drm_printf(p, "Unavailable\n");
- return;
- }
-
- for (s = 0; s < sseu->max_slices; s++) {
- drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
- s, intel_sseu_subslices_per_slice(sseu, s),
- intel_sseu_get_subslices(sseu, s));
-
- for (ss = 0; ss < sseu->max_subslices; ss++) {
- u16 enabled_eus = sseu_get_eus(sseu, s, ss);
-
- drm_printf(p, "\tsubslice%d: %u EUs (0x%hx)\n",
- ss, hweight16(enabled_eus), enabled_eus);
- }
- }
-}
-
-static u16 compute_eu_total(const struct sseu_dev_info *sseu)
-{
- u16 i, total = 0;
-
- for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++)
- total += hweight8(sseu->eu_mask[i]);
-
- return total;
-}
-
-static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
- u8 s_en, u32 ss_en, u16 eu_en)
-{
- int s, ss;
-
- /* ss_en represents entire subslice mask across all slices */
- GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
- sizeof(ss_en) * BITS_PER_BYTE);
-
- for (s = 0; s < sseu->max_slices; s++) {
- if ((s_en & BIT(s)) == 0)
- continue;
-
- sseu->slice_mask |= BIT(s);
-
- intel_sseu_set_subslices(sseu, s, ss_en);
-
- for (ss = 0; ss < sseu->max_subslices; ss++)
- if (intel_sseu_has_subslice(sseu, s, ss))
- sseu_set_eus(sseu, s, ss, eu_en);
- }
- sseu->eu_per_subslice = hweight16(eu_en);
- sseu->eu_total = compute_eu_total(sseu);
-}
-
-static void gen12_sseu_info_init(struct drm_i915_private *dev_priv)
-{
- struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
- struct intel_uncore *uncore = &dev_priv->uncore;
- u8 s_en;
- u32 dss_en;
- u16 eu_en = 0;
- u8 eu_en_fuse;
- int eu;
-
- /*
- * Gen12 has Dual-Subslices, which behave similarly to 2 gen11 SS.
- * Instead of splitting these, provide userspace with an array
- * of DSS to more closely represent the hardware resource.
- */
- intel_sseu_set_info(sseu, 1, 6, 16);
-
- s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
- GEN11_GT_S_ENA_MASK;
-
- dss_en = intel_uncore_read(uncore, GEN12_GT_DSS_ENABLE);
-
- /* one bit per pair of EUs */
- eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
- GEN11_EU_DIS_MASK);
- for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
- if (eu_en_fuse & BIT(eu))
- eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
-
- gen11_compute_sseu_info(sseu, s_en, dss_en, eu_en);
-
- /* TGL only supports slice-level power gating */
- sseu->has_slice_pg = 1;
-}
-
-static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
-{
- struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
- struct intel_uncore *uncore = &dev_priv->uncore;
- u8 s_en;
- u32 ss_en;
- u8 eu_en;
-
- if (IS_ELKHARTLAKE(dev_priv))
- intel_sseu_set_info(sseu, 1, 4, 8);
- else
- intel_sseu_set_info(sseu, 1, 8, 8);
-
- s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
- GEN11_GT_S_ENA_MASK;
- ss_en = ~intel_uncore_read(uncore, GEN11_GT_SUBSLICE_DISABLE);
-
- eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
- GEN11_EU_DIS_MASK);
-
- gen11_compute_sseu_info(sseu, s_en, ss_en, eu_en);
-
- /* ICL has no power gating restrictions. */
- sseu->has_slice_pg = 1;
- sseu->has_subslice_pg = 1;
- sseu->has_eu_pg = 1;
-}
-
-static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
-{
- struct intel_uncore *uncore = &dev_priv->uncore;
- struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
- const u32 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
- int s, ss;
- const int eu_mask = 0xff;
- u32 subslice_mask, eu_en;
-
- intel_sseu_set_info(sseu, 6, 4, 8);
-
- sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
- GEN10_F2_S_ENA_SHIFT;
-
- /* Slice0 */
- eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE0);
- for (ss = 0; ss < sseu->max_subslices; ss++)
- sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask);
- /* Slice1 */
- sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask);
- eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE1);
- sseu_set_eus(sseu, 1, 1, eu_en & eu_mask);
- /* Slice2 */
- sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask);
- sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask);
- /* Slice3 */
- sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask);
- eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE2);
- sseu_set_eus(sseu, 3, 1, eu_en & eu_mask);
- /* Slice4 */
- sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask);
- sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask);
- /* Slice5 */
- sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask);
- eu_en = ~intel_uncore_read(uncore, GEN10_EU_DISABLE3);
- sseu_set_eus(sseu, 5, 1, eu_en & eu_mask);
-
- subslice_mask = (1 << 4) - 1;
- subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
- GEN10_F2_SS_DIS_SHIFT);
-
- for (s = 0; s < sseu->max_slices; s++) {
- u32 subslice_mask_with_eus = subslice_mask;
-
- for (ss = 0; ss < sseu->max_subslices; ss++) {
- if (sseu_get_eus(sseu, s, ss) == 0)
- subslice_mask_with_eus &= ~BIT(ss);
- }
-
- /*
- * Slice0 can have up to 3 subslices, but there are only 2 in
- * slice1/2.
- */
- intel_sseu_set_subslices(sseu, s, s == 0 ?
- subslice_mask_with_eus :
- subslice_mask_with_eus & 0x3);
- }
-
- sseu->eu_total = compute_eu_total(sseu);
-
- /*
- * CNL is expected to always have a uniform distribution
- * of EU across subslices with the exception that any one
- * EU in any one subslice may be fused off for die
- * recovery.
- */
- sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ?
- DIV_ROUND_UP(sseu->eu_total,
- intel_sseu_subslice_total(sseu)) :
- 0;
-
- /* No restrictions on Power Gating */
- sseu->has_slice_pg = 1;
- sseu->has_subslice_pg = 1;
- sseu->has_eu_pg = 1;
-}
-
-static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
-{
- struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
- u32 fuse;
- u8 subslice_mask = 0;
-
- fuse = intel_uncore_read(&dev_priv->uncore, CHV_FUSE_GT);
-
- sseu->slice_mask = BIT(0);
- intel_sseu_set_info(sseu, 1, 2, 8);
-
- if (!(fuse & CHV_FGT_DISABLE_SS0)) {
- u8 disabled_mask =
- ((fuse & CHV_FGT_EU_DIS_SS0_R0_MASK) >>
- CHV_FGT_EU_DIS_SS0_R0_SHIFT) |
- (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
- CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
-
- subslice_mask |= BIT(0);
- sseu_set_eus(sseu, 0, 0, ~disabled_mask);
- }
-
- if (!(fuse & CHV_FGT_DISABLE_SS1)) {
- u8 disabled_mask =
- ((fuse & CHV_FGT_EU_DIS_SS1_R0_MASK) >>
- CHV_FGT_EU_DIS_SS1_R0_SHIFT) |
- (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
- CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
-
- subslice_mask |= BIT(1);
- sseu_set_eus(sseu, 0, 1, ~disabled_mask);
- }
-
- intel_sseu_set_subslices(sseu, 0, subslice_mask);
-
- sseu->eu_total = compute_eu_total(sseu);
-
- /*
- * CHV expected to always have a uniform distribution of EU
- * across subslices.
- */
- sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ?
- sseu->eu_total /
- intel_sseu_subslice_total(sseu) :
- 0;
- /*
- * CHV supports subslice power gating on devices with more than
- * one subslice, and supports EU power gating on devices with
- * more than one EU pair per subslice.
- */
- sseu->has_slice_pg = 0;
- sseu->has_subslice_pg = intel_sseu_subslice_total(sseu) > 1;
- sseu->has_eu_pg = (sseu->eu_per_subslice > 2);
-}
-
-static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
-{
- struct intel_device_info *info = mkwrite_device_info(dev_priv);
- struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
- struct intel_uncore *uncore = &dev_priv->uncore;
- int s, ss;
- u32 fuse2, eu_disable, subslice_mask;
- const u8 eu_mask = 0xff;
-
- fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
- sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
-
- /* BXT has a single slice and at most 3 subslices. */
- intel_sseu_set_info(sseu, IS_GEN9_LP(dev_priv) ? 1 : 3,
- IS_GEN9_LP(dev_priv) ? 3 : 4, 8);
-
- /*
- * The subslice disable field is global, i.e. it applies
- * to each of the enabled slices.
- */
- subslice_mask = (1 << sseu->max_subslices) - 1;
- subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >>
- GEN9_F2_SS_DIS_SHIFT);
-
- /*
- * Iterate through enabled slices and subslices to
- * count the total enabled EU.
- */
- for (s = 0; s < sseu->max_slices; s++) {
- if (!(sseu->slice_mask & BIT(s)))
- /* skip disabled slice */
- continue;
-
- intel_sseu_set_subslices(sseu, s, subslice_mask);
-
- eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s));
- for (ss = 0; ss < sseu->max_subslices; ss++) {
- int eu_per_ss;
- u8 eu_disabled_mask;
-
- if (!intel_sseu_has_subslice(sseu, s, ss))
- /* skip disabled subslice */
- continue;
-
- eu_disabled_mask = (eu_disable >> (ss * 8)) & eu_mask;
-
- sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
-
- eu_per_ss = sseu->max_eus_per_subslice -
- hweight8(eu_disabled_mask);
-
- /*
- * Record which subslice(s) has(have) 7 EUs. we
- * can tune the hash used to spread work among
- * subslices if they are unbalanced.
- */
- if (eu_per_ss == 7)
- sseu->subslice_7eu[s] |= BIT(ss);
- }
- }
-
- sseu->eu_total = compute_eu_total(sseu);
-
- /*
- * SKL is expected to always have a uniform distribution
- * of EU across subslices with the exception that any one
- * EU in any one subslice may be fused off for die
- * recovery. BXT is expected to be perfectly uniform in EU
- * distribution.
- */
- sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ?
- DIV_ROUND_UP(sseu->eu_total,
- intel_sseu_subslice_total(sseu)) :
- 0;
- /*
- * SKL+ supports slice power gating on devices with more than
- * one slice, and supports EU power gating on devices with
- * more than one EU pair per subslice. BXT+ supports subslice
- * power gating on devices with more than one subslice, and
- * supports EU power gating on devices with more than one EU
- * pair per subslice.
- */
- sseu->has_slice_pg =
- !IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1;
- sseu->has_subslice_pg =
- IS_GEN9_LP(dev_priv) && intel_sseu_subslice_total(sseu) > 1;
- sseu->has_eu_pg = sseu->eu_per_subslice > 2;
-
- if (IS_GEN9_LP(dev_priv)) {
-#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss)))
- info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3;
-
- sseu->min_eu_in_pool = 0;
- if (info->has_pooled_eu) {
- if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0))
- sseu->min_eu_in_pool = 3;
- else if (IS_SS_DISABLED(1))
- sseu->min_eu_in_pool = 6;
- else
- sseu->min_eu_in_pool = 9;
- }
-#undef IS_SS_DISABLED
- }
-}
-
-static void bdw_sseu_info_init(struct drm_i915_private *dev_priv)
-{
- struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
- struct intel_uncore *uncore = &dev_priv->uncore;
- int s, ss;
- u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */
- u32 eu_disable0, eu_disable1, eu_disable2;
-
- fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
- sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
- intel_sseu_set_info(sseu, 3, 3, 8);
-
- /*
- * The subslice disable field is global, i.e. it applies
- * to each of the enabled slices.
- */
- subslice_mask = GENMASK(sseu->max_subslices - 1, 0);
- subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >>
- GEN8_F2_SS_DIS_SHIFT);
- eu_disable0 = intel_uncore_read(uncore, GEN8_EU_DISABLE0);
- eu_disable1 = intel_uncore_read(uncore, GEN8_EU_DISABLE1);
- eu_disable2 = intel_uncore_read(uncore, GEN8_EU_DISABLE2);
- eu_disable[0] = eu_disable0 & GEN8_EU_DIS0_S0_MASK;
- eu_disable[1] = (eu_disable0 >> GEN8_EU_DIS0_S1_SHIFT) |
- ((eu_disable1 & GEN8_EU_DIS1_S1_MASK) <<
- (32 - GEN8_EU_DIS0_S1_SHIFT));
- eu_disable[2] = (eu_disable1 >> GEN8_EU_DIS1_S2_SHIFT) |
- ((eu_disable2 & GEN8_EU_DIS2_S2_MASK) <<
- (32 - GEN8_EU_DIS1_S2_SHIFT));
-
- /*
- * Iterate through enabled slices and subslices to
- * count the total enabled EU.
- */
- for (s = 0; s < sseu->max_slices; s++) {
- if (!(sseu->slice_mask & BIT(s)))
- /* skip disabled slice */
- continue;
-
- intel_sseu_set_subslices(sseu, s, subslice_mask);
-
- for (ss = 0; ss < sseu->max_subslices; ss++) {
- u8 eu_disabled_mask;
- u32 n_disabled;
-
- if (!intel_sseu_has_subslice(sseu, s, ss))
- /* skip disabled subslice */
- continue;
-
- eu_disabled_mask =
- eu_disable[s] >> (ss * sseu->max_eus_per_subslice);
-
- sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
-
- n_disabled = hweight8(eu_disabled_mask);
-
- /*
- * Record which subslices have 7 EUs.
- */
- if (sseu->max_eus_per_subslice - n_disabled == 7)
- sseu->subslice_7eu[s] |= 1 << ss;
- }
- }
-
- sseu->eu_total = compute_eu_total(sseu);
-
- /*
- * BDW is expected to always have a uniform distribution of EU across
- * subslices with the exception that any one EU in any one subslice may
- * be fused off for die recovery.
- */
- sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ?
- DIV_ROUND_UP(sseu->eu_total,
- intel_sseu_subslice_total(sseu)) :
- 0;
-
- /*
- * BDW supports slice power gating on devices with more than
- * one slice.
- */
- sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1;
- sseu->has_subslice_pg = 0;
- sseu->has_eu_pg = 0;
-}
-
-static void hsw_sseu_info_init(struct drm_i915_private *dev_priv)
-{
- struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
- u32 fuse1;
- u8 subslice_mask = 0;
- int s, ss;
-
- /*
- * There isn't a register to tell us how many slices/subslices. We
- * work off the PCI-ids here.
- */
- switch (INTEL_INFO(dev_priv)->gt) {
- default:
- MISSING_CASE(INTEL_INFO(dev_priv)->gt);
- /* fall through */
- case 1:
- sseu->slice_mask = BIT(0);
- subslice_mask = BIT(0);
- break;
- case 2:
- sseu->slice_mask = BIT(0);
- subslice_mask = BIT(0) | BIT(1);
- break;
- case 3:
- sseu->slice_mask = BIT(0) | BIT(1);
- subslice_mask = BIT(0) | BIT(1);
- break;
- }
-
- fuse1 = intel_uncore_read(&dev_priv->uncore, HSW_PAVP_FUSE1);
- switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) {
- default:
- MISSING_CASE((fuse1 & HSW_F1_EU_DIS_MASK) >>
- HSW_F1_EU_DIS_SHIFT);
- /* fall through */
- case HSW_F1_EU_DIS_10EUS:
- sseu->eu_per_subslice = 10;
- break;
- case HSW_F1_EU_DIS_8EUS:
- sseu->eu_per_subslice = 8;
- break;
- case HSW_F1_EU_DIS_6EUS:
- sseu->eu_per_subslice = 6;
- break;
- }
-
- intel_sseu_set_info(sseu, hweight8(sseu->slice_mask),
- hweight8(subslice_mask),
- sseu->eu_per_subslice);
-
- for (s = 0; s < sseu->max_slices; s++) {
- intel_sseu_set_subslices(sseu, s, subslice_mask);
-
- for (ss = 0; ss < sseu->max_subslices; ss++) {
- sseu_set_eus(sseu, s, ss,
- (1UL << sseu->eu_per_subslice) - 1);
- }
- }
-
- sseu->eu_total = compute_eu_total(sseu);
-
- /* No powergating for you. */
- sseu->has_slice_pg = 0;
- sseu->has_subslice_pg = 0;
- sseu->has_eu_pg = 0;
-}
-
static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv)
{
u32 ts_override = intel_uncore_read(&dev_priv->uncore,
@@ -1042,22 +478,6 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
info->display.has_dsc = 0;
}
- /* Initialize slice/subslice/EU info */
- if (IS_HASWELL(dev_priv))
- hsw_sseu_info_init(dev_priv);
- else if (IS_CHERRYVIEW(dev_priv))
- cherryview_sseu_info_init(dev_priv);
- else if (IS_BROADWELL(dev_priv))
- bdw_sseu_info_init(dev_priv);
- else if (IS_GEN(dev_priv, 9))
- gen9_sseu_info_init(dev_priv);
- else if (IS_GEN(dev_priv, 10))
- gen10_sseu_info_init(dev_priv);
- else if (IS_GEN(dev_priv, 11))
- gen11_sseu_info_init(dev_priv);
- else if (INTEL_GEN(dev_priv) >= 12)
- gen12_sseu_info_init(dev_priv);
-
if (IS_GEN(dev_priv, 6) && intel_vtd_active()) {
drm_info(&dev_priv->drm,
"Disabling ppGTT for VT-d support\n");
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index f03ed95af190..ce2ccee9b49b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -242,8 +242,6 @@ void intel_device_info_print_static(const struct intel_device_info *info,
struct drm_printer *p);
void intel_device_info_print_runtime(const struct intel_runtime_info *info,
struct drm_printer *p);
-void intel_device_info_print_topology(const struct sseu_dev_info *sseu,
- struct drm_printer *p);
void intel_driver_caps_print(const struct intel_driver_caps *caps,
struct drm_printer *p);
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH 7/7] drm/i915/sseu: Move sseu_info under gt_info
2020-06-25 23:42 [Intel-gfx] [PATCH 0/7] Move some device capabilities under intel_gt Daniele Ceraolo Spurio
` (5 preceding siblings ...)
2020-06-25 23:42 ` [Intel-gfx] [PATCH 6/7] drm/i915/sseu: Move sseu detection and dump to intel_sseu Daniele Ceraolo Spurio
@ 2020-06-25 23:42 ` Daniele Ceraolo Spurio
2020-06-26 15:22 ` Tvrtko Ursulin
2020-06-27 8:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Move some device capabilities under intel_gt Patchwork
2020-06-27 8:38 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
8 siblings, 1 reply; 26+ messages in thread
From: Daniele Ceraolo Spurio @ 2020-06-25 23:42 UTC (permalink / raw)
To: intel-gfx
From: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
SSEUs are a GT capability, so track them under gt_info.
Signed-off-by: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Andi Shyti <andi.shyti@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 7 ++++---
drivers/gpu/drm/i915/gem/i915_gem_context.h | 2 +-
.../drm/i915/gem/selftests/i915_gem_context.c | 5 ++++-
drivers/gpu/drm/i915/gt/intel_context_sseu.c | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_gt.c | 2 ++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +++
drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +-
drivers/gpu/drm/i915/gt/intel_rps.c | 3 ++-
drivers/gpu/drm/i915/gt/intel_sseu.c | 19 ++++++++++---------
drivers/gpu/drm/i915/gt/intel_sseu.h | 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++----
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 3 +--
drivers/gpu/drm/i915/i915_debugfs.c | 10 +++++-----
drivers/gpu/drm/i915/i915_getparam.c | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 4 ++--
drivers/gpu/drm/i915/i915_perf.c | 9 ++++-----
drivers/gpu/drm/i915/i915_query.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 3 ---
drivers/gpu/drm/i915/intel_device_info.h | 3 ---
20 files changed, 49 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 5c13809dc3c8..4fc641d5cb68 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1399,11 +1399,12 @@ static int get_ringsize(struct i915_gem_context *ctx,
}
int
-i915_gem_user_to_context_sseu(struct drm_i915_private *i915,
+i915_gem_user_to_context_sseu(struct intel_gt *gt,
const struct drm_i915_gem_context_param_sseu *user,
struct intel_sseu *context)
{
- const struct sseu_dev_info *device = &RUNTIME_INFO(i915)->sseu;
+ const struct sseu_dev_info *device = >->info.sseu;
+ struct drm_i915_private *i915 = gt->i915;
/* No zeros in any field. */
if (!user->slice_mask || !user->subslice_mask ||
@@ -1536,7 +1537,7 @@ static int set_sseu(struct i915_gem_context *ctx,
goto out_ce;
}
- ret = i915_gem_user_to_context_sseu(i915, &user_sseu, &sseu);
+ ret = i915_gem_user_to_context_sseu(ce->engine->gt, &user_sseu, &sseu);
if (ret)
goto out_ce;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index 3702b2fb27ab..a133f92bbedb 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -225,7 +225,7 @@ i915_gem_engines_iter_next(struct i915_gem_engines_iter *it);
struct i915_lut_handle *i915_lut_handle_alloc(void);
void i915_lut_handle_free(struct i915_lut_handle *lut);
-int i915_gem_user_to_context_sseu(struct drm_i915_private *i915,
+int i915_gem_user_to_context_sseu(struct intel_gt *gt,
const struct drm_i915_gem_context_param_sseu *user,
struct intel_sseu *context);
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index b81978890641..7ffc3c751432 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -1229,7 +1229,7 @@ __igt_ctx_sseu(struct drm_i915_private *i915,
int inst = 0;
int ret = 0;
- if (INTEL_GEN(i915) < 9 || !RUNTIME_INFO(i915)->sseu.has_slice_pg)
+ if (INTEL_GEN(i915) < 9)
return 0;
if (flags & TEST_RESET)
@@ -1255,6 +1255,9 @@ __igt_ctx_sseu(struct drm_i915_private *i915,
if (hweight32(engine->sseu.slice_mask) < 2)
continue;
+ if (!engine->gt->info.sseu.has_slice_pg)
+ continue;
+
/*
* Gen11 VME friendly power-gated configuration with
* half enabled sub-slices.
diff --git a/drivers/gpu/drm/i915/gt/intel_context_sseu.c b/drivers/gpu/drm/i915/gt/intel_context_sseu.c
index 27ae48049239..b9c8163978a3 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_context_sseu.c
@@ -30,7 +30,7 @@ static int gen8_emit_rpcs_config(struct i915_request *rq,
*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
*cs++ = lower_32_bits(offset);
*cs++ = upper_32_bits(offset);
- *cs++ = intel_sseu_make_rpcs(rq->engine->i915, &sseu);
+ *cs++ = intel_sseu_make_rpcs(rq->engine->gt, &sseu);
intel_ring_advance(rq, cs);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 3af58df3b13e..af08fdddd972 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -705,7 +705,7 @@ static int engine_setup_common(struct intel_engine_cs *engine)
/* Use the whole device by default */
engine->sseu =
- intel_sseu_from_device_info(&RUNTIME_INFO(engine->i915)->sseu);
+ intel_sseu_from_device_info(&engine->gt->info.sseu);
intel_engine_init_workarounds(engine);
intel_engine_init_whitelist(engine);
@@ -1071,7 +1071,7 @@ void intel_engine_get_instdone(const struct intel_engine_cs *engine,
struct intel_instdone *instdone)
{
struct drm_i915_private *i915 = engine->i915;
- const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
+ const struct sseu_dev_info *sseu = &engine->gt->info.sseu;
struct intel_uncore *uncore = engine->uncore;
u32 mmio_base = engine->mmio_base;
int slice;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index de95930f8627..b1748fa67eca 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -655,4 +655,6 @@ void intel_gt_info_print(const struct intel_gt_info *info,
struct drm_printer *p)
{
drm_printf(p, "available engines: %x\n", info->engine_mask);
+
+ intel_sseu_dump(&info->sseu, p);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index bb7551867c00..6d39a4a11bf3 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -116,6 +116,9 @@ struct intel_gt {
/* Media engine access to SFC per instance */
u8 vdbox_sfc_access;
+
+ /* Slice/subslice/EU info */
+ struct sseu_dev_info sseu;
} info;
};
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index e866b8d721ed..9e28b2f9df72 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3422,7 +3422,7 @@ __execlists_update_reg_state(const struct intel_context *ce,
/* RPCS */
if (engine->class == RENDER_CLASS) {
regs[CTX_R_PWR_CLK_STATE] =
- intel_sseu_make_rpcs(engine->i915, &ce->sseu);
+ intel_sseu_make_rpcs(engine->gt, &ce->sseu);
i915_oa_init_reg_state(ce, engine);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 296391deeb94..97ba14ad52e4 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1062,11 +1062,12 @@ static bool gen6_rps_enable(struct intel_rps *rps)
static int chv_rps_max_freq(struct intel_rps *rps)
{
struct drm_i915_private *i915 = rps_to_i915(rps);
+ struct intel_gt *gt = rps_to_gt(rps);
u32 val;
val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE);
- switch (RUNTIME_INFO(i915)->sseu.eu_total) {
+ switch (gt->info.sseu.eu_total) {
case 8:
/* (2 * 4) config */
val >>= FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT;
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 006f9118b319..e29f0785b3c5 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -130,7 +130,7 @@ static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
static void gen12_sseu_info_init(struct intel_gt *gt)
{
- struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
+ struct sseu_dev_info *sseu = >->info.sseu;
struct intel_uncore *uncore = gt->uncore;
u8 s_en;
u32 dss_en;
@@ -165,7 +165,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
static void gen11_sseu_info_init(struct intel_gt *gt)
{
- struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
+ struct sseu_dev_info *sseu = >->info.sseu;
struct intel_uncore *uncore = gt->uncore;
u8 s_en;
u32 ss_en;
@@ -194,7 +194,7 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
static void gen10_sseu_info_init(struct intel_gt *gt)
{
struct intel_uncore *uncore = gt->uncore;
- struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
+ struct sseu_dev_info *sseu = >->info.sseu;
const u32 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
int s, ss;
const int eu_mask = 0xff;
@@ -270,7 +270,7 @@ static void gen10_sseu_info_init(struct intel_gt *gt)
static void cherryview_sseu_info_init(struct intel_gt *gt)
{
- struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
+ struct sseu_dev_info *sseu = >->info.sseu;
u32 fuse;
u8 subslice_mask = 0;
@@ -327,7 +327,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
struct intel_device_info *info = mkwrite_device_info(i915);
- struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
+ struct sseu_dev_info *sseu = >->info.sseu;
struct intel_uncore *uncore = gt->uncore;
int s, ss;
u32 fuse2, eu_disable, subslice_mask;
@@ -431,7 +431,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
static void bdw_sseu_info_init(struct intel_gt *gt)
{
- struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
+ struct sseu_dev_info *sseu = >->info.sseu;
struct intel_uncore *uncore = gt->uncore;
int s, ss;
u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */
@@ -517,7 +517,7 @@ static void bdw_sseu_info_init(struct intel_gt *gt)
static void hsw_sseu_info_init(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
- struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
+ struct sseu_dev_info *sseu = >->info.sseu;
u32 fuse1;
u8 subslice_mask = 0;
int s, ss;
@@ -602,10 +602,11 @@ void intel_sseu_info_init(struct intel_gt *gt)
gen12_sseu_info_init(gt);
}
-u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
+u32 intel_sseu_make_rpcs(struct intel_gt *gt,
const struct intel_sseu *req_sseu)
{
- const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
+ struct drm_i915_private *i915 = gt->i915;
+ const struct sseu_dev_info *sseu = >->info.sseu;
bool subslice_pg = sseu->has_subslice_pg;
u8 slices, subslices;
u32 rpcs = 0;
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index f9c007f001e7..23ba6c2ebe70 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -98,7 +98,7 @@ void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
void intel_sseu_info_init(struct intel_gt *gt);
-u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
+u32 intel_sseu_make_rpcs(struct intel_gt *gt,
const struct intel_sseu *req_sseu);
void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p);
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 2da366821dda..dbafd923e5a1 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -404,7 +404,7 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine,
static void skl_tune_iz_hashing(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
- struct drm_i915_private *i915 = engine->i915;
+ struct intel_gt *gt = engine->gt;
u8 vals[3] = { 0, 0, 0 };
unsigned int i;
@@ -415,7 +415,7 @@ static void skl_tune_iz_hashing(struct intel_engine_cs *engine,
* Only consider slices where one, and only one, subslice has 7
* EUs
*/
- if (!is_power_of_2(RUNTIME_INFO(i915)->sseu.subslice_7eu[i]))
+ if (!is_power_of_2(gt->info.sseu.subslice_7eu[i]))
continue;
/*
@@ -424,7 +424,7 @@ static void skl_tune_iz_hashing(struct intel_engine_cs *engine,
*
* -> 0 <= ss <= 3;
*/
- ss = ffs(RUNTIME_INFO(i915)->sseu.subslice_7eu[i]) - 1;
+ ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1;
vals[i] = 3 - ss;
}
@@ -1036,7 +1036,7 @@ cfl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
static void
wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
- const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
+ const struct sseu_dev_info *sseu = &i915->gt.info.sseu;
unsigned int slice, subslice;
u32 l3_en, mcr, mcr_mask;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index c10ae1660e53..d44061033f23 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -68,7 +68,6 @@ struct __guc_ads_blob {
static void __guc_ads_init(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
- struct drm_i915_private *dev_priv = gt->i915;
struct __guc_ads_blob *blob = guc->ads_blob;
const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;
u32 base;
@@ -100,7 +99,7 @@ static void __guc_ads_init(struct intel_guc *guc)
}
/* System info */
- blob->system_info.slice_enabled = hweight8(RUNTIME_INFO(dev_priv)->sseu.slice_mask);
+ blob->system_info.slice_enabled = hweight8(gt->info.sseu.slice_mask);
blob->system_info.rcs_enabled = 1;
blob->system_info.bcs_enabled = 1;
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index c893a82c2d99..16b012b5673d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1323,7 +1323,7 @@ static int i915_rcs_topology(struct seq_file *m, void *unused)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct drm_printer p = drm_seq_file_printer(m);
- intel_sseu_print_topology(&RUNTIME_INFO(dev_priv)->sseu, &p);
+ intel_sseu_print_topology(&dev_priv->gt.info.sseu, &p);
return 0;
}
@@ -1624,7 +1624,7 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
{
#define SS_MAX 6
- const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
+ const struct intel_gt_info *info = &dev_priv->gt.info;
u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
int s, ss;
@@ -1681,7 +1681,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
{
#define SS_MAX 3
- const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
+ const struct intel_gt_info *info = &dev_priv->gt.info;
u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
int s, ss;
@@ -1739,7 +1739,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
static void bdw_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
{
- const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
+ const struct intel_gt_info *info = &dev_priv->gt.info;
u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
int s;
@@ -1802,7 +1802,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
static int i915_sseu_status(struct seq_file *m, void *unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
- const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
+ const struct intel_gt_info *info = &dev_priv->gt.info;
struct sseu_dev_info sseu;
intel_wakeref_t wakeref;
diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
index 40390b2352b1..421613219ae9 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -12,7 +12,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv)
{
struct drm_i915_private *i915 = to_i915(dev);
- const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
+ const struct sseu_dev_info *sseu = &i915->gt.info.sseu;
drm_i915_getparam_t *param = data;
int value;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 99b4a0261b13..678ddec3237f 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -426,7 +426,7 @@ static void err_compression_marker(struct drm_i915_error_state_buf *m)
static void error_print_instdone(struct drm_i915_error_state_buf *m,
const struct intel_engine_coredump *ee)
{
- const struct sseu_dev_info *sseu = &RUNTIME_INFO(m->i915)->sseu;
+ const struct sseu_dev_info *sseu = &ee->engine->gt->info.sseu;
int slice;
int subslice;
@@ -626,8 +626,8 @@ static void err_print_capabilities(struct drm_i915_error_state_buf *m,
intel_device_info_print_static(&error->device_info, &p);
intel_device_info_print_runtime(&error->runtime_info, &p);
- intel_sseu_print_topology(&error->runtime_info.sseu, &p);
intel_gt_info_print(&error->gt->info, &p);
+ intel_sseu_print_topology(&error->gt->info.sseu, &p);
intel_driver_caps_print(&error->driver_caps, &p);
}
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 25329b7600c9..37631ce0699b 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2196,7 +2196,7 @@ static int gen8_configure_context(struct i915_gem_context *ctx,
if (!intel_context_pin_if_active(ce))
continue;
- flex->value = intel_sseu_make_rpcs(ctx->i915, &ce->sseu);
+ flex->value = intel_sseu_make_rpcs(ce->engine->gt, &ce->sseu);
err = gen8_modify_context(ce, flex, count);
intel_context_unpin(ce);
@@ -2340,7 +2340,7 @@ oa_configure_all_contexts(struct i915_perf_stream *stream,
if (engine->class != RENDER_CLASS)
continue;
- regs[0].value = intel_sseu_make_rpcs(i915, &ce->sseu);
+ regs[0].value = intel_sseu_make_rpcs(engine->gt, &ce->sseu);
err = gen8_modify_self(ce, regs, num_regs, active);
if (err)
@@ -2740,8 +2740,7 @@ static void
get_default_sseu_config(struct intel_sseu *out_sseu,
struct intel_engine_cs *engine)
{
- const struct sseu_dev_info *devinfo_sseu =
- &RUNTIME_INFO(engine->i915)->sseu;
+ const struct sseu_dev_info *devinfo_sseu = &engine->gt->info.sseu;
*out_sseu = intel_sseu_from_device_info(devinfo_sseu);
@@ -2766,7 +2765,7 @@ get_sseu_config(struct intel_sseu *out_sseu,
drm_sseu->engine.engine_instance != engine->uabi_instance)
return -EINVAL;
- return i915_gem_user_to_context_sseu(engine->i915, drm_sseu, out_sseu);
+ return i915_gem_user_to_context_sseu(engine->gt, drm_sseu, out_sseu);
}
/**
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index c1ebda9b5627..fed337ad7b68 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -31,7 +31,7 @@ static int copy_query_item(void *query_hdr, size_t query_sz,
static int query_topology_info(struct drm_i915_private *dev_priv,
struct drm_i915_query_item *query_item)
{
- const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
+ const struct sseu_dev_info *sseu = &dev_priv->gt.info.sseu;
struct drm_i915_query_topology_info topo;
u32 slice_length, subslice_length, eu_length, total_length;
int ret;
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index d8daf224cbd3..3f5dc37d2b7c 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -29,7 +29,6 @@
#include "display/intel_de.h"
#include "intel_device_info.h"
#include "i915_drv.h"
-#include "gt/intel_sseu.h"
#define PLATFORM_NAME(x) [INTEL_##x] = #x
static const char * const platform_names[] = {
@@ -115,8 +114,6 @@ void intel_device_info_print_static(const struct intel_device_info *info,
void intel_device_info_print_runtime(const struct intel_runtime_info *info,
struct drm_printer *p)
{
- intel_sseu_dump(&info->sseu, p);
-
drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq);
drm_printf(p, "CS timestamp frequency: %u Hz\n",
info->cs_timestamp_frequency_hz);
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index ce2ccee9b49b..f6f897c06cc8 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -219,9 +219,6 @@ struct intel_runtime_info {
u8 num_sprites[I915_MAX_PIPES];
u8 num_scalers[I915_MAX_PIPES];
- /* Slice/subslice/EU info */
- struct sseu_dev_info sseu;
-
u32 rawclk_freq;
u32 cs_timestamp_frequency_hz;
--
2.24.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 1/7] drm/i915: Convert device_info to uncore/de_read
2020-06-25 23:42 ` [Intel-gfx] [PATCH 1/7] drm/i915: Convert device_info to uncore/de_read Daniele Ceraolo Spurio
@ 2020-06-26 14:18 ` Tvrtko Ursulin
0 siblings, 0 replies; 26+ messages in thread
From: Tvrtko Ursulin @ 2020-06-26 14:18 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx
On 26/06/2020 00:42, Daniele Ceraolo Spurio wrote:
> Use intel_<uncore/de>_read instead of I915_READ to read the
> informational registers.
>
> Extended from an original sseu-only patch by Sandeep.
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Andi Shyti <andi.shyti@intel.com>
> Cc: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
> ---
> drivers/gpu/drm/i915/intel_device_info.c | 77 +++++++++++++++---------
> 1 file changed, 47 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 544ac61fbc36..c27a56aff5de 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -26,6 +26,7 @@
> #include <drm/i915_pciids.h>
>
> #include "display/intel_cdclk.h"
> +#include "display/intel_de.h"
> #include "intel_device_info.h"
> #include "i915_drv.h"
>
> @@ -237,6 +238,7 @@ static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
> static void gen12_sseu_info_init(struct drm_i915_private *dev_priv)
> {
> struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
> + struct intel_uncore *uncore = &dev_priv->uncore;
> u8 s_en;
> u32 dss_en;
> u16 eu_en = 0;
> @@ -250,12 +252,14 @@ static void gen12_sseu_info_init(struct drm_i915_private *dev_priv)
> */
> intel_sseu_set_info(sseu, 1, 6, 16);
>
> - s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
> + s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
> + GEN11_GT_S_ENA_MASK;
>
> - dss_en = I915_READ(GEN12_GT_DSS_ENABLE);
> + dss_en = intel_uncore_read(uncore, GEN12_GT_DSS_ENABLE);
>
> /* one bit per pair of EUs */
> - eu_en_fuse = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK);
> + eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
> + GEN11_EU_DIS_MASK);
> for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
> if (eu_en_fuse & BIT(eu))
> eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
> @@ -269,6 +273,7 @@ static void gen12_sseu_info_init(struct drm_i915_private *dev_priv)
> static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
> {
> struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
> + struct intel_uncore *uncore = &dev_priv->uncore;
> u8 s_en;
> u32 ss_en;
> u8 eu_en;
> @@ -278,9 +283,12 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
> else
> intel_sseu_set_info(sseu, 1, 8, 8);
>
> - s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
> - ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
> - eu_en = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK);
> + s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
> + GEN11_GT_S_ENA_MASK;
> + ss_en = ~intel_uncore_read(uncore, GEN11_GT_SUBSLICE_DISABLE);
> +
> + eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
> + GEN11_EU_DIS_MASK);
>
> gen11_compute_sseu_info(sseu, s_en, ss_en, eu_en);
>
> @@ -292,8 +300,9 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
>
> static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
> {
> + struct intel_uncore *uncore = &dev_priv->uncore;
> struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
> - const u32 fuse2 = I915_READ(GEN8_FUSE2);
> + const u32 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
> int s, ss;
> const int eu_mask = 0xff;
> u32 subslice_mask, eu_en;
> @@ -304,26 +313,26 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
> GEN10_F2_S_ENA_SHIFT;
>
> /* Slice0 */
> - eu_en = ~I915_READ(GEN8_EU_DISABLE0);
> + eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE0);
> for (ss = 0; ss < sseu->max_subslices; ss++)
> sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask);
> /* Slice1 */
> sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask);
> - eu_en = ~I915_READ(GEN8_EU_DISABLE1);
> + eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE1);
> sseu_set_eus(sseu, 1, 1, eu_en & eu_mask);
> /* Slice2 */
> sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask);
> sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask);
> /* Slice3 */
> sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask);
> - eu_en = ~I915_READ(GEN8_EU_DISABLE2);
> + eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE2);
> sseu_set_eus(sseu, 3, 1, eu_en & eu_mask);
> /* Slice4 */
> sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask);
> sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask);
> /* Slice5 */
> sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask);
> - eu_en = ~I915_READ(GEN10_EU_DISABLE3);
> + eu_en = ~intel_uncore_read(uncore, GEN10_EU_DISABLE3);
> sseu_set_eus(sseu, 5, 1, eu_en & eu_mask);
>
> subslice_mask = (1 << 4) - 1;
> @@ -372,7 +381,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
> u32 fuse;
> u8 subslice_mask = 0;
>
> - fuse = I915_READ(CHV_FUSE_GT);
> + fuse = intel_uncore_read(&dev_priv->uncore, CHV_FUSE_GT);
>
> sseu->slice_mask = BIT(0);
> intel_sseu_set_info(sseu, 1, 2, 8);
> @@ -425,11 +434,12 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
> {
> struct intel_device_info *info = mkwrite_device_info(dev_priv);
> struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
> + struct intel_uncore *uncore = &dev_priv->uncore;
> int s, ss;
> u32 fuse2, eu_disable, subslice_mask;
> const u8 eu_mask = 0xff;
>
> - fuse2 = I915_READ(GEN8_FUSE2);
> + fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
> sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
>
> /* BXT has a single slice and at most 3 subslices. */
> @@ -455,7 +465,7 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
>
> intel_sseu_set_subslices(sseu, s, subslice_mask);
>
> - eu_disable = I915_READ(GEN9_EU_DISABLE(s));
> + eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s));
> for (ss = 0; ss < sseu->max_subslices; ss++) {
> int eu_per_ss;
> u8 eu_disabled_mask;
> @@ -528,10 +538,12 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
> static void bdw_sseu_info_init(struct drm_i915_private *dev_priv)
> {
> struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
> + struct intel_uncore *uncore = &dev_priv->uncore;
> int s, ss;
> u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */
> + u32 eu_disable0, eu_disable1, eu_disable2;
>
> - fuse2 = I915_READ(GEN8_FUSE2);
> + fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
> sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
> intel_sseu_set_info(sseu, 3, 3, 8);
>
> @@ -542,13 +554,15 @@ static void bdw_sseu_info_init(struct drm_i915_private *dev_priv)
> subslice_mask = GENMASK(sseu->max_subslices - 1, 0);
> subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >>
> GEN8_F2_SS_DIS_SHIFT);
> -
> - eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
> - eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
> - ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
> + eu_disable0 = intel_uncore_read(uncore, GEN8_EU_DISABLE0);
> + eu_disable1 = intel_uncore_read(uncore, GEN8_EU_DISABLE1);
> + eu_disable2 = intel_uncore_read(uncore, GEN8_EU_DISABLE2);
> + eu_disable[0] = eu_disable0 & GEN8_EU_DIS0_S0_MASK;
> + eu_disable[1] = (eu_disable0 >> GEN8_EU_DIS0_S1_SHIFT) |
> + ((eu_disable1 & GEN8_EU_DIS1_S1_MASK) <<
> (32 - GEN8_EU_DIS0_S1_SHIFT));
> - eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
> - ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
> + eu_disable[2] = (eu_disable1 >> GEN8_EU_DIS1_S2_SHIFT) |
> + ((eu_disable2 & GEN8_EU_DIS2_S2_MASK) <<
> (32 - GEN8_EU_DIS1_S2_SHIFT));
>
> /*
> @@ -635,7 +649,7 @@ static void hsw_sseu_info_init(struct drm_i915_private *dev_priv)
> break;
> }
>
> - fuse1 = I915_READ(HSW_PAVP_FUSE1);
> + fuse1 = intel_uncore_read(&dev_priv->uncore, HSW_PAVP_FUSE1);
> switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) {
> default:
> MISSING_CASE((fuse1 & HSW_F1_EU_DIS_MASK) >>
> @@ -675,7 +689,8 @@ static void hsw_sseu_info_init(struct drm_i915_private *dev_priv)
>
> static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv)
> {
> - u32 ts_override = I915_READ(GEN9_TIMESTAMP_OVERRIDE);
> + u32 ts_override = intel_uncore_read(&dev_priv->uncore,
> + GEN9_TIMESTAMP_OVERRIDE);
> u32 base_freq, frac_freq;
>
> base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >>
> @@ -738,6 +753,7 @@ static u32 gen11_get_crystal_clock_freq(struct drm_i915_private *dev_priv,
>
> static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
> {
> + struct intel_uncore *uncore = &dev_priv->uncore;
> u32 f12_5_mhz = 12500000;
> u32 f19_2_mhz = 19200000;
> u32 f24_mhz = 24000000;
> @@ -759,7 +775,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
> */
> return f12_5_mhz;
> } else if (INTEL_GEN(dev_priv) <= 9) {
> - u32 ctc_reg = I915_READ(CTC_MODE);
> + u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
> u32 freq = 0;
>
> if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
> @@ -777,7 +793,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
>
> return freq;
> } else if (INTEL_GEN(dev_priv) <= 12) {
> - u32 ctc_reg = I915_READ(CTC_MODE);
> + u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
> u32 freq = 0;
>
> /* First figure out the reference frequency. There are 2 ways
> @@ -788,7 +804,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
> if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
> freq = read_reference_ts_freq(dev_priv);
> } else {
> - u32 rpm_config_reg = I915_READ(RPM_CONFIG0);
> + u32 rpm_config_reg = intel_uncore_read(uncore, RPM_CONFIG0);
>
> if (INTEL_GEN(dev_priv) <= 10)
> freq = gen10_get_crystal_clock_freq(dev_priv,
> @@ -967,8 +983,8 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>
> if (HAS_DISPLAY(dev_priv) && IS_GEN_RANGE(dev_priv, 7, 8) &&
> HAS_PCH_SPLIT(dev_priv)) {
> - u32 fuse_strap = I915_READ(FUSE_STRAP);
> - u32 sfuse_strap = I915_READ(SFUSE_STRAP);
> + u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
> + u32 sfuse_strap = intel_de_read(dev_priv, SFUSE_STRAP);
>
> /*
> * SFUSE_STRAP is supposed to have a bit signalling the display
> @@ -993,7 +1009,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
> }
> } else if (HAS_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 9) {
> - u32 dfsm = I915_READ(SKL_DFSM);
> + u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);
>
> if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
> info->pipe_mask &= ~BIT(PIPE_A);
> @@ -1083,6 +1099,7 @@ void intel_driver_caps_print(const struct intel_driver_caps *caps,
> void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
> {
> struct intel_device_info *info = mkwrite_device_info(dev_priv);
> + struct intel_uncore *uncore = &dev_priv->uncore;
> unsigned int logical_vdbox = 0;
> unsigned int i;
> u32 media_fuse;
> @@ -1092,7 +1109,7 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
> if (INTEL_GEN(dev_priv) < 11)
> return;
>
> - media_fuse = ~I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE);
> + media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
>
> vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
> vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 2/7] drm/i915: Use the gt in HAS_ENGINE
2020-06-25 23:42 ` [Intel-gfx] [PATCH 2/7] drm/i915: Use the gt in HAS_ENGINE Daniele Ceraolo Spurio
@ 2020-06-26 14:20 ` Tvrtko Ursulin
2020-06-26 14:35 ` Chris Wilson
1 sibling, 0 replies; 26+ messages in thread
From: Tvrtko Ursulin @ 2020-06-26 14:20 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx
On 26/06/2020 00:42, Daniele Ceraolo Spurio wrote:
> A follow up patch will move the engine mask under the gt structure,
> so get ready for that.
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Cc: Andi Shyti <andi.shyti@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 2 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 7 ++++---
> drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
> drivers/gpu/drm/i915/gvt/interrupt.c | 2 +-
> drivers/gpu/drm/i915/gvt/mmio_context.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 15 ++++++++-------
> drivers/gpu/drm/i915/intel_device_info.c | 13 +++++++------
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> drivers/gpu/drm/i915/intel_uncore.c | 16 +++++++++-------
> drivers/gpu/drm/i915/intel_uncore.h | 4 +++-
> 12 files changed, 38 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 7bf2f76212f0..be92d1ef9aa9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -473,7 +473,7 @@ int intel_engines_init_mmio(struct intel_gt *gt)
> return -ENODEV;
>
> for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
> - if (!HAS_ENGINE(i915, i))
> + if (!HAS_ENGINE(gt, i))
> continue;
>
> err = intel_engine_setup(gt, i);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> index 0cc7dd54f4f9..e1964cf40fd6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -457,7 +457,7 @@ void gen5_gt_irq_postinstall(struct intel_gt *gt)
> * RPS interrupts will get enabled/disabled on demand when RPS
> * itself is enabled/disabled.
> */
> - if (HAS_ENGINE(gt->i915, VECS0)) {
> + if (HAS_ENGINE(gt, VECS0)) {
> pm_irqs |= PM_VEBOX_USER_INTERRUPT;
> gt->pm_ier |= PM_VEBOX_USER_INTERRUPT;
> }
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> index 101728006ae9..fbdd6b0677db 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> @@ -67,7 +67,8 @@ struct __guc_ads_blob {
>
> static void __guc_ads_init(struct intel_guc *guc)
> {
> - struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
> + struct intel_gt *gt = guc_to_gt(guc);
> + struct drm_i915_private *dev_priv = gt->i915;
> struct __guc_ads_blob *blob = guc->ads_blob;
> const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;
> u32 base;
> @@ -103,8 +104,8 @@ static void __guc_ads_init(struct intel_guc *guc)
> blob->system_info.rcs_enabled = 1;
> blob->system_info.bcs_enabled = 1;
>
> - blob->system_info.vdbox_enable_mask = VDBOX_MASK(dev_priv);
> - blob->system_info.vebox_enable_mask = VEBOX_MASK(dev_priv);
> + blob->system_info.vdbox_enable_mask = VDBOX_MASK(gt);
> + blob->system_info.vebox_enable_mask = VEBOX_MASK(gt);
> blob->system_info.vdbox_sfc_support_mask = RUNTIME_INFO(dev_priv)->vdbox_sfc_access;
>
> base = intel_guc_ggtt_offset(guc, guc->ads_vma);
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 26cae4846c82..ddefc52f6e09 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -1867,7 +1867,7 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
> MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
> MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
> MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
> - if (HAS_ENGINE(dev_priv, VCS1)) \
> + if (HAS_ENGINE(&dev_priv->gt, VCS1)) \
> MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
> } while (0)
>
> diff --git a/drivers/gpu/drm/i915/gvt/interrupt.c b/drivers/gpu/drm/i915/gvt/interrupt.c
> index 540017fed908..7498878e6289 100644
> --- a/drivers/gpu/drm/i915/gvt/interrupt.c
> +++ b/drivers/gpu/drm/i915/gvt/interrupt.c
> @@ -540,7 +540,7 @@ static void gen8_init_irq(
> SET_BIT_INFO(irq, 4, VCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT1);
> SET_BIT_INFO(irq, 8, VCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT1);
>
> - if (HAS_ENGINE(gvt->gt->i915, VCS1)) {
> + if (HAS_ENGINE(gvt->gt, VCS1)) {
> SET_BIT_INFO(irq, 16, VCS2_MI_USER_INTERRUPT,
> INTEL_GVT_IRQ_INFO_GT1);
> SET_BIT_INFO(irq, 20, VCS2_MI_FLUSH_DW,
> diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
> index 2ccaf78f96e8..86a60bdf0818 100644
> --- a/drivers/gpu/drm/i915/gvt/mmio_context.c
> +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
> @@ -171,7 +171,7 @@ static void load_render_mocs(const struct intel_engine_cs *engine)
> return;
>
> for (ring_id = 0; ring_id < cnt; ring_id++) {
> - if (!HAS_ENGINE(engine->i915, ring_id))
> + if (!HAS_ENGINE(engine->gt, ring_id))
> continue;
>
> offset.reg = regs[ring_id];
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 67102dc26fce..1f9c40cf10ae 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -533,7 +533,7 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
>
> intel_device_info_init_mmio(dev_priv);
>
> - intel_uncore_prune_mmio_domains(&dev_priv->uncore);
> + intel_uncore_prune_engine_fw_domains(&dev_priv->uncore, &dev_priv->gt);
>
> intel_uc_init_mmio(&dev_priv->gt.uc);
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 9aad3ec979bd..17cad4e2cb9c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1560,18 +1560,19 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
> #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
>
> -#define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id))
> +#define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
> +#define HAS_ENGINE(gt, id) __HAS_ENGINE(INTEL_INFO((gt)->i915)->engine_mask, id)
>
> -#define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({ \
> +#define ENGINE_INSTANCES_MASK(gt, first, count) ({ \
> unsigned int first__ = (first); \
> unsigned int count__ = (count); \
> - (INTEL_INFO(dev_priv)->engine_mask & \
> + (INTEL_INFO((gt)->i915)->engine_mask & \
> GENMASK(first__ + count__ - 1, first__)) >> first__; \
> })
> -#define VDBOX_MASK(dev_priv) \
> - ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS)
> -#define VEBOX_MASK(dev_priv) \
> - ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS)
> +#define VDBOX_MASK(gt) \
> + ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
> +#define VEBOX_MASK(gt) \
> + ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
>
> /*
> * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index c27a56aff5de..c0443afa12b9 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -1100,6 +1100,7 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
> {
> struct intel_device_info *info = mkwrite_device_info(dev_priv);
> struct intel_uncore *uncore = &dev_priv->uncore;
> + struct intel_gt *gt = &dev_priv->gt;
> unsigned int logical_vdbox = 0;
> unsigned int i;
> u32 media_fuse;
> @@ -1116,7 +1117,7 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
> GEN11_GT_VEBOX_DISABLE_SHIFT;
>
> for (i = 0; i < I915_MAX_VCS; i++) {
> - if (!HAS_ENGINE(dev_priv, _VCS(i))) {
> + if (!HAS_ENGINE(gt, _VCS(i))) {
> vdbox_mask &= ~BIT(i);
> continue;
> }
> @@ -1136,11 +1137,11 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
> RUNTIME_INFO(dev_priv)->vdbox_sfc_access |= BIT(i);
> }
> drm_dbg(&dev_priv->drm, "vdbox enable: %04x, instances: %04lx\n",
> - vdbox_mask, VDBOX_MASK(dev_priv));
> - GEM_BUG_ON(vdbox_mask != VDBOX_MASK(dev_priv));
> + vdbox_mask, VDBOX_MASK(gt));
> + GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
>
> for (i = 0; i < I915_MAX_VECS; i++) {
> - if (!HAS_ENGINE(dev_priv, _VECS(i))) {
> + if (!HAS_ENGINE(gt, _VECS(i))) {
> vebox_mask &= ~BIT(i);
> continue;
> }
> @@ -1151,6 +1152,6 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
> }
> }
> drm_dbg(&dev_priv->drm, "vebox enable: %04x, instances: %04lx\n",
> - vebox_mask, VEBOX_MASK(dev_priv));
> - GEM_BUG_ON(vebox_mask != VEBOX_MASK(dev_priv));
> + vebox_mask, VEBOX_MASK(gt));
> + GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
> }
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 2a32d6230795..40f6fe69b70a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7105,7 +7105,7 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
>
> /* This is not a WA. Enable VD HCP & MFX_ENC powergate */
> for (i = 0; i < I915_MAX_VCS; i++) {
> - if (HAS_ENGINE(dev_priv, _VCS(i)))
> + if (HAS_ENGINE(&dev_priv->gt, _VCS(i)))
> vd_pg_enable |= VDN_HCP_POWERGATE_ENABLE(i) |
> VDN_MFX_POWERGATE_ENABLE(i);
> }
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 592364aed2da..bd4b45191f7b 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1529,6 +1529,8 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
> (ret ?: (ret = __fw_domain_init((uncore__), (id__), (set__), (ack__))))
>
> if (INTEL_GEN(i915) >= 11) {
> + /* we'll prune the domains of missing engines later */
> + intel_engine_mask_t emask = INTEL_INFO(i915)->engine_mask;
> int i;
>
> uncore->funcs.force_wake_get = fw_domains_get_with_fallback;
> @@ -1541,7 +1543,7 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
> FORCEWAKE_ACK_BLITTER_GEN9);
>
> for (i = 0; i < I915_MAX_VCS; i++) {
> - if (!HAS_ENGINE(i915, _VCS(i)))
> + if (!__HAS_ENGINE(emask, _VCS(i)))
> continue;
>
> fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VDBOX0 + i,
> @@ -1549,7 +1551,7 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
> FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(i));
> }
> for (i = 0; i < I915_MAX_VECS; i++) {
> - if (!HAS_ENGINE(i915, _VECS(i)))
> + if (!__HAS_ENGINE(emask, _VECS(i)))
> continue;
>
> fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VEBOX0 + i,
> @@ -1844,20 +1846,20 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore)
> * the forcewake domains. Prune them, to make sure they only reference existing
> * engines.
> */
> -void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore)
> +void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
> + struct intel_gt *gt)
> {
> - struct drm_i915_private *i915 = uncore->i915;
> enum forcewake_domains fw_domains = uncore->fw_domains;
> enum forcewake_domain_id domain_id;
> int i;
>
> - if (!intel_uncore_has_forcewake(uncore) || INTEL_GEN(i915) < 11)
> + if (!intel_uncore_has_forcewake(uncore) || INTEL_GEN(uncore->i915) < 11)
> return;
>
> for (i = 0; i < I915_MAX_VCS; i++) {
> domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i;
>
> - if (HAS_ENGINE(i915, _VCS(i)))
> + if (HAS_ENGINE(gt, _VCS(i)))
> continue;
>
> if (fw_domains & BIT(domain_id))
> @@ -1867,7 +1869,7 @@ void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore)
> for (i = 0; i < I915_MAX_VECS; i++) {
> domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i;
>
> - if (HAS_ENGINE(i915, _VECS(i)))
> + if (HAS_ENGINE(gt, _VECS(i)))
> continue;
>
> if (fw_domains & BIT(domain_id))
> diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
> index 8d3aa8b9acf9..c4b22d9d0b45 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.h
> +++ b/drivers/gpu/drm/i915/intel_uncore.h
> @@ -35,6 +35,7 @@
> struct drm_i915_private;
> struct intel_runtime_pm;
> struct intel_uncore;
> +struct intel_gt;
>
> struct intel_uncore_mmio_debug {
> spinlock_t lock; /** lock is also taken in irq contexts. */
> @@ -186,7 +187,8 @@ intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug);
> void intel_uncore_init_early(struct intel_uncore *uncore,
> struct drm_i915_private *i915);
> int intel_uncore_init_mmio(struct intel_uncore *uncore);
> -void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore);
> +void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
> + struct intel_gt *gt);
> bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore);
> bool intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore);
> void intel_uncore_fini_mmio(struct intel_uncore *uncore);
>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 2/7] drm/i915: Use the gt in HAS_ENGINE
2020-06-25 23:42 ` [Intel-gfx] [PATCH 2/7] drm/i915: Use the gt in HAS_ENGINE Daniele Ceraolo Spurio
2020-06-26 14:20 ` Tvrtko Ursulin
@ 2020-06-26 14:35 ` Chris Wilson
2020-06-26 17:45 ` Daniele Ceraolo Spurio
1 sibling, 1 reply; 26+ messages in thread
From: Chris Wilson @ 2020-06-26 14:35 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx
Quoting Daniele Ceraolo Spurio (2020-06-26 00:42:07)
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 26cae4846c82..ddefc52f6e09 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -1867,7 +1867,7 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
> MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
> MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
> MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
> - if (HAS_ENGINE(dev_priv, VCS1)) \
> + if (HAS_ENGINE(&dev_priv->gt, VCS1)) \
Implicit param! It can switch to gvt->gt for all callsites, killing the
dev_priv locals.
-Chris
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 3/7] drm/i915: Move engine-related mmio init to engines_init_mmio
2020-06-25 23:42 ` [Intel-gfx] [PATCH 3/7] drm/i915: Move engine-related mmio init to engines_init_mmio Daniele Ceraolo Spurio
@ 2020-06-26 14:38 ` Tvrtko Ursulin
2020-06-26 14:38 ` Chris Wilson
1 sibling, 0 replies; 26+ messages in thread
From: Tvrtko Ursulin @ 2020-06-26 14:38 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx
On 26/06/2020 00:42, Daniele Ceraolo Spurio wrote:
> All the info we read in intel_device_info_init_mmio are engine-related
> and since we already have an engine_init_mmio function we can just
> perform the operations from there.
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Cc: Andi Shyti <andi.shyti@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 72 ++++++++++++++++++++++-
> drivers/gpu/drm/i915/i915_drv.c | 4 --
> drivers/gpu/drm/i915/intel_device_info.c | 66 ---------------------
> drivers/gpu/drm/i915/intel_device_info.h | 2 -
> 4 files changed, 71 insertions(+), 73 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index be92d1ef9aa9..8497106eb3a6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -450,6 +450,74 @@ void intel_engines_free(struct intel_gt *gt)
> }
> }
>
> +/*
> + * Determine which engines are fused off in our particular hardware. Since the
> + * fuse register is in the blitter powerwell, we need forcewake to be ready at
> + * this point (but later we need to prune the forcewake domains for engines that
> + * are indeed fused off).
> + */
> +static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
> +{
> + struct drm_i915_private *i915 = gt->i915;
> + struct intel_device_info *info = mkwrite_device_info(i915);
> + struct intel_uncore *uncore = gt->uncore;
> + unsigned int logical_vdbox = 0;
> + unsigned int i;
> + u32 media_fuse;
> + u16 vdbox_mask;
> + u16 vebox_mask;
> +
> + if (INTEL_GEN(i915) < 11)
> + return info->engine_mask;
> +
> + media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
> +
> + vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
> + vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
> + GEN11_GT_VEBOX_DISABLE_SHIFT;
> +
> + for (i = 0; i < I915_MAX_VCS; i++) {
> + if (!HAS_ENGINE(gt, _VCS(i))) {
> + vdbox_mask &= ~BIT(i);
> + continue;
> + }
> +
> + if (!(BIT(i) & vdbox_mask)) {
> + info->engine_mask &= ~BIT(_VCS(i));
> + drm_dbg(&i915->drm, "vcs%u fused off\n", i);
> + continue;
> + }
> +
> + /*
> + * In Gen11, only even numbered logical VDBOXes are
> + * hooked up to an SFC (Scaler & Format Converter) unit.
> + * In TGL each VDBOX has access to an SFC.
> + */
> + if (INTEL_GEN(i915) >= 12 || logical_vdbox++ % 2 == 0)
> + RUNTIME_INFO(i915)->vdbox_sfc_access |= BIT(i);
> + }
> + drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
> + vdbox_mask, VDBOX_MASK(gt));
> + GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
> +
> + for (i = 0; i < I915_MAX_VECS; i++) {
> + if (!HAS_ENGINE(gt, _VECS(i))) {
> + vebox_mask &= ~BIT(i);
> + continue;
> + }
> +
> + if (!(BIT(i) & vebox_mask)) {
> + info->engine_mask &= ~BIT(_VECS(i));
> + drm_dbg(&i915->drm, "vecs%u fused off\n", i);
> + }
> + }
> + drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n",
> + vebox_mask, VEBOX_MASK(gt));
> + GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
> +
> + return info->engine_mask;
> +}
> +
> /**
> * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers
> * @gt: pointer to struct intel_gt
> @@ -460,7 +528,7 @@ int intel_engines_init_mmio(struct intel_gt *gt)
> {
> struct drm_i915_private *i915 = gt->i915;
> struct intel_device_info *device_info = mkwrite_device_info(i915);
> - const unsigned int engine_mask = INTEL_INFO(i915)->engine_mask;
> + const unsigned int engine_mask = init_engine_mask(gt);
> unsigned int mask = 0;
> unsigned int i;
> int err;
> @@ -497,6 +565,8 @@ int intel_engines_init_mmio(struct intel_gt *gt)
>
> intel_setup_engine_capabilities(gt);
>
> + intel_uncore_prune_engine_fw_domains(gt->uncore, gt);
> +
> return 0;
>
> cleanup:
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 1f9c40cf10ae..611287353420 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -531,10 +531,6 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
> /* Try to make sure MCHBAR is enabled before poking at it */
> intel_setup_mchbar(dev_priv);
>
> - intel_device_info_init_mmio(dev_priv);
> -
> - intel_uncore_prune_engine_fw_domains(&dev_priv->uncore, &dev_priv->gt);
> -
> intel_uc_init_mmio(&dev_priv->gt.uc);
>
> ret = intel_engines_init_mmio(&dev_priv->gt);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index c0443afa12b9..92ebea35c752 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -1089,69 +1089,3 @@ void intel_driver_caps_print(const struct intel_driver_caps *caps,
> yesno(caps->has_logical_contexts));
> drm_printf(p, "scheduler: %x\n", caps->scheduler);
> }
> -
> -/*
> - * Determine which engines are fused off in our particular hardware. Since the
> - * fuse register is in the blitter powerwell, we need forcewake to be ready at
> - * this point (but later we need to prune the forcewake domains for engines that
> - * are indeed fused off).
> - */
> -void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
> -{
> - struct intel_device_info *info = mkwrite_device_info(dev_priv);
> - struct intel_uncore *uncore = &dev_priv->uncore;
> - struct intel_gt *gt = &dev_priv->gt;
> - unsigned int logical_vdbox = 0;
> - unsigned int i;
> - u32 media_fuse;
> - u16 vdbox_mask;
> - u16 vebox_mask;
> -
> - if (INTEL_GEN(dev_priv) < 11)
> - return;
> -
> - media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
> -
> - vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
> - vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
> - GEN11_GT_VEBOX_DISABLE_SHIFT;
> -
> - for (i = 0; i < I915_MAX_VCS; i++) {
> - if (!HAS_ENGINE(gt, _VCS(i))) {
> - vdbox_mask &= ~BIT(i);
> - continue;
> - }
> -
> - if (!(BIT(i) & vdbox_mask)) {
> - info->engine_mask &= ~BIT(_VCS(i));
> - drm_dbg(&dev_priv->drm, "vcs%u fused off\n", i);
> - continue;
> - }
> -
> - /*
> - * In Gen11, only even numbered logical VDBOXes are
> - * hooked up to an SFC (Scaler & Format Converter) unit.
> - * In TGL each VDBOX has access to an SFC.
> - */
> - if (INTEL_GEN(dev_priv) >= 12 || logical_vdbox++ % 2 == 0)
> - RUNTIME_INFO(dev_priv)->vdbox_sfc_access |= BIT(i);
> - }
> - drm_dbg(&dev_priv->drm, "vdbox enable: %04x, instances: %04lx\n",
> - vdbox_mask, VDBOX_MASK(gt));
> - GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
> -
> - for (i = 0; i < I915_MAX_VECS; i++) {
> - if (!HAS_ENGINE(gt, _VECS(i))) {
> - vebox_mask &= ~BIT(i);
> - continue;
> - }
> -
> - if (!(BIT(i) & vebox_mask)) {
> - info->engine_mask &= ~BIT(_VECS(i));
> - drm_dbg(&dev_priv->drm, "vecs%u fused off\n", i);
> - }
> - }
> - drm_dbg(&dev_priv->drm, "vebox enable: %04x, instances: %04lx\n",
> - vebox_mask, VEBOX_MASK(gt));
> - GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
> -}
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 8d62b8538585..fa60fdc1d75a 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -250,8 +250,6 @@ void intel_device_info_print_runtime(const struct intel_runtime_info *info,
> void intel_device_info_print_topology(const struct sseu_dev_info *sseu,
> struct drm_printer *p);
>
> -void intel_device_info_init_mmio(struct drm_i915_private *dev_priv);
> -
> void intel_driver_caps_print(const struct intel_driver_caps *caps,
> struct drm_printer *p);
>
>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 3/7] drm/i915: Move engine-related mmio init to engines_init_mmio
2020-06-25 23:42 ` [Intel-gfx] [PATCH 3/7] drm/i915: Move engine-related mmio init to engines_init_mmio Daniele Ceraolo Spurio
2020-06-26 14:38 ` Tvrtko Ursulin
@ 2020-06-26 14:38 ` Chris Wilson
2020-06-26 14:46 ` Daniele Ceraolo Spurio
1 sibling, 1 reply; 26+ messages in thread
From: Chris Wilson @ 2020-06-26 14:38 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx
Quoting Daniele Ceraolo Spurio (2020-06-26 00:42:08)
> All the info we read in intel_device_info_init_mmio are engine-related
> and since we already have an engine_init_mmio function we can just
> perform the operations from there.
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Cc: Andi Shyti <andi.shyti@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 72 ++++++++++++++++++++++-
> drivers/gpu/drm/i915/i915_drv.c | 4 --
> drivers/gpu/drm/i915/intel_device_info.c | 66 ---------------------
> drivers/gpu/drm/i915/intel_device_info.h | 2 -
> 4 files changed, 71 insertions(+), 73 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index be92d1ef9aa9..8497106eb3a6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -450,6 +450,74 @@ void intel_engines_free(struct intel_gt *gt)
> }
> }
>
> +/*
> + * Determine which engines are fused off in our particular hardware. Since the
> + * fuse register is in the blitter powerwell, we need forcewake to be ready at
> + * this point (but later we need to prune the forcewake domains for engines that
> + * are indeed fused off).
> + */
> +static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
> +{
> + struct drm_i915_private *i915 = gt->i915;
> + struct intel_device_info *info = mkwrite_device_info(i915);
> + struct intel_uncore *uncore = gt->uncore;
> + unsigned int logical_vdbox = 0;
> + unsigned int i;
> + u32 media_fuse;
> + u16 vdbox_mask;
> + u16 vebox_mask;
assert_forcewakes_active(uncore, FORCEWAKE_BLITTER) ?
Since it's called out in the comment, might as well reinforce that with
an assert.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 4/7] drm/i915: Move the engine mask to intel_gt_info
2020-06-25 23:42 ` [Intel-gfx] [PATCH 4/7] drm/i915: Move the engine mask to intel_gt_info Daniele Ceraolo Spurio
@ 2020-06-26 14:45 ` Tvrtko Ursulin
2020-06-26 16:44 ` Daniele Ceraolo Spurio
0 siblings, 1 reply; 26+ messages in thread
From: Tvrtko Ursulin @ 2020-06-26 14:45 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx
On 26/06/2020 00:42, Daniele Ceraolo Spurio wrote:
> Since the engines belong to the GT, move the runtime-updated list of
> available engines to the intel_gt struct. The original mask has been
> renamed to indicate it contains the maximum engine list that can be
> found on a matching device.
>
> In preparation for other info being moved to the gt in follow up patches
> (sseu), introduce an intel_gt_info structure to group all gt-related
> runtime info.
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Cc: Andi Shyti <andi.shyti@intel.com>
> Cc: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
> ---
> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 3 +-
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 13 +++---
> drivers/gpu/drm/i915/gt/intel_gt.c | 6 +++
> drivers/gpu/drm/i915/gt/intel_gt.h | 4 ++
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 8 ++++
> drivers/gpu/drm/i915/gt/intel_reset.c | 6 +--
> .../gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
> drivers/gpu/drm/i915/gt/selftest_lrc.c | 8 ++--
> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 2 +-
> drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
> drivers/gpu/drm/i915/i915_debugfs.c | 2 +
> drivers/gpu/drm/i915/i915_drv.c | 1 +
> drivers/gpu/drm/i915/i915_drv.h | 6 +--
> drivers/gpu/drm/i915/i915_gpu_error.c | 23 ++++++----
> drivers/gpu/drm/i915/i915_gpu_error.h | 3 ++
> drivers/gpu/drm/i915/i915_pci.c | 42 +++++++++----------
> drivers/gpu/drm/i915/intel_device_info.c | 1 -
> drivers/gpu/drm/i915/intel_device_info.h | 7 +---
> drivers/gpu/drm/i915/intel_uncore.c | 2 +-
> drivers/gpu/drm/i915/selftests/i915_request.c | 2 +-
> .../gpu/drm/i915/selftests/mock_gem_device.c | 3 +-
> 21 files changed, 84 insertions(+), 62 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index c38ab51e82f0..7ffac711e4b4 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -1973,8 +1973,7 @@ static int eb_submit(struct i915_execbuffer *eb, struct i915_vma *batch)
>
> static int num_vcs_engines(const struct drm_i915_private *i915)
> {
> - return hweight64(INTEL_INFO(i915)->engine_mask &
> - GENMASK_ULL(VCS0 + I915_MAX_VCS - 1, VCS0));
> + return hweight64(VDBOX_MASK(&i915->gt));
> }
>
> /*
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 8497106eb3a6..3af58df3b13e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -370,7 +370,7 @@ static void __setup_engine_capabilities(struct intel_engine_cs *engine)
> * instances.
> */
> if ((INTEL_GEN(i915) >= 11 &&
> - RUNTIME_INFO(i915)->vdbox_sfc_access & engine->mask) ||
> + engine->gt->info.vdbox_sfc_access & engine->mask) ||
> (INTEL_GEN(i915) >= 9 && engine->instance == 0))
> engine->uabi_capabilities |=
> I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
> @@ -459,7 +459,7 @@ void intel_engines_free(struct intel_gt *gt)
> static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
> {
> struct drm_i915_private *i915 = gt->i915;
> - struct intel_device_info *info = mkwrite_device_info(i915);
> + struct intel_gt_info *info = >->info;
> struct intel_uncore *uncore = gt->uncore;
> unsigned int logical_vdbox = 0;
> unsigned int i;
> @@ -467,6 +467,8 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
> u16 vdbox_mask;
> u16 vebox_mask;
>
> + info->engine_mask = INTEL_INFO(i915)->max_engine_mask;
> +
> if (INTEL_GEN(i915) < 11)
> return info->engine_mask;
>
> @@ -494,7 +496,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
> * In TGL each VDBOX has access to an SFC.
> */
> if (INTEL_GEN(i915) >= 12 || logical_vdbox++ % 2 == 0)
> - RUNTIME_INFO(i915)->vdbox_sfc_access |= BIT(i);
> + gt->info.vdbox_sfc_access |= BIT(i);
> }
> drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
> vdbox_mask, VDBOX_MASK(gt));
> @@ -527,7 +529,6 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
> int intel_engines_init_mmio(struct intel_gt *gt)
> {
> struct drm_i915_private *i915 = gt->i915;
> - struct intel_device_info *device_info = mkwrite_device_info(i915);
> const unsigned int engine_mask = init_engine_mask(gt);
> unsigned int mask = 0;
> unsigned int i;
> @@ -557,9 +558,9 @@ int intel_engines_init_mmio(struct intel_gt *gt)
> * engines.
> */
> if (drm_WARN_ON(&i915->drm, mask != engine_mask))
> - device_info->engine_mask = mask;
> + gt->info.engine_mask = mask;
>
> - RUNTIME_INFO(i915)->num_engines = hweight32(mask);
> + gt->info.num_engines = hweight32(mask);
>
> intel_gt_check_and_clear_faults(gt);
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index ebc29b6ee86c..d0ae1cb5c7c9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -642,3 +642,9 @@ void intel_gt_driver_late_release(struct intel_gt *gt)
> intel_gt_fini_timelines(gt);
> intel_engines_free(gt);
> }
> +
> +void intel_gt_info_print(const struct intel_gt_info *info,
> + struct drm_printer *p)
> +{
> + drm_printf(p, "available engines: %x\n", info->engine_mask);
> +}
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
> index 4fac043750aa..15142e2a3b22 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -11,6 +11,7 @@
> #include "intel_reset.h"
>
> struct drm_i915_private;
> +struct drm_printer;
>
> #define GT_TRACE(gt, fmt, ...) do { \
> const struct intel_gt *gt__ __maybe_unused = (gt); \
> @@ -68,4 +69,7 @@ static inline bool intel_gt_has_init_error(const struct intel_gt *gt)
> return test_bit(I915_WEDGED_ON_INIT, >->reset.flags);
> }
>
> +void intel_gt_info_print(const struct intel_gt_info *info,
> + struct drm_printer *p);
> +
> #endif /* __INTEL_GT_H__ */
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index 0cc1d6b185dc..bb7551867c00 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -109,6 +109,14 @@ struct intel_gt {
> struct intel_gt_buffer_pool buffer_pool;
>
> struct i915_vma *scratch;
> +
> + struct intel_gt_info {
> + intel_engine_mask_t engine_mask;
> + u8 num_engines;
> +
> + /* Media engine access to SFC per instance */
> + u8 vdbox_sfc_access;
> + } info;
> };
>
> enum intel_gt_scratch_field {
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
> index 0156f1f5c736..952cd6e9b88e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -342,7 +342,7 @@ static int gen6_reset_engines(struct intel_gt *gt,
> static int gen11_lock_sfc(struct intel_engine_cs *engine, u32 *hw_mask)
> {
> struct intel_uncore *uncore = engine->uncore;
> - u8 vdbox_sfc_access = RUNTIME_INFO(engine->i915)->vdbox_sfc_access;
> + u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;
> i915_reg_t sfc_forced_lock, sfc_forced_lock_ack;
> u32 sfc_forced_lock_bit, sfc_forced_lock_ack_bit;
> i915_reg_t sfc_usage;
> @@ -417,7 +417,7 @@ static int gen11_lock_sfc(struct intel_engine_cs *engine, u32 *hw_mask)
> static void gen11_unlock_sfc(struct intel_engine_cs *engine)
> {
> struct intel_uncore *uncore = engine->uncore;
> - u8 vdbox_sfc_access = RUNTIME_INFO(engine->i915)->vdbox_sfc_access;
> + u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;
> i915_reg_t sfc_forced_lock;
> u32 sfc_forced_lock_bit;
>
> @@ -1246,7 +1246,7 @@ void intel_gt_handle_error(struct intel_gt *gt,
> */
> wakeref = intel_runtime_pm_get(gt->uncore->rpm);
>
> - engine_mask &= INTEL_INFO(gt->i915)->engine_mask;
> + engine_mask &= gt->info.engine_mask;
>
> if (flags & I915_ERROR_CAPTURE) {
> i915_capture_error_state(gt->i915);
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index 68a08486fc87..b09b83deecef 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -649,7 +649,7 @@ static inline int mi_set_context(struct i915_request *rq,
> struct drm_i915_private *i915 = engine->i915;
> enum intel_engine_id id;
> const int num_engines =
> - IS_HASWELL(i915) ? RUNTIME_INFO(i915)->num_engines - 1 : 0;
> + IS_HASWELL(i915) ? engine->gt->info.num_engines - 1 : 0;
> bool force_restore = false;
> int len;
> u32 *cs;
> diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> index daa4aabab9a7..b3678b5f9655 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> @@ -963,7 +963,7 @@ slice_semaphore_queue(struct intel_engine_cs *outer,
> goto out;
>
> if (i915_request_wait(head, 0,
> - 2 * RUNTIME_INFO(outer->i915)->num_engines * (count + 2) * (count + 3)) < 0) {
> + 2 * engine->gt->info.num_engines * (count + 2) * (count + 3)) < 0) {
> pr_err("Failed to slice along semaphore chain of length (%d, %d)!\n",
> count, n);
> GEM_TRACE_DUMP();
> @@ -3569,8 +3569,7 @@ static int smoke_crescendo(struct preempt_smoke *smoke, unsigned int flags)
> }
>
> pr_info("Submitted %lu crescendo:%x requests across %d engines and %d contexts\n",
> - count, flags,
> - RUNTIME_INFO(smoke->gt->i915)->num_engines, smoke->ncontext);
> + count, flags, smoke->gt->info.num_engines, smoke->ncontext);
> return 0;
> }
>
> @@ -3597,8 +3596,7 @@ static int smoke_random(struct preempt_smoke *smoke, unsigned int flags)
> } while (count < smoke->ncontext && !__igt_timeout(end_time, NULL));
>
> pr_info("Submitted %lu random:%x requests across %d engines and %d contexts\n",
> - count, flags,
> - RUNTIME_INFO(smoke->gt->i915)->num_engines, smoke->ncontext);
> + count, flags, smoke->gt->info.num_engines, smoke->ncontext);
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> index fbdd6b0677db..c10ae1660e53 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> @@ -106,7 +106,7 @@ static void __guc_ads_init(struct intel_guc *guc)
>
> blob->system_info.vdbox_enable_mask = VDBOX_MASK(gt);
> blob->system_info.vebox_enable_mask = VEBOX_MASK(gt);
> - blob->system_info.vdbox_sfc_support_mask = RUNTIME_INFO(dev_priv)->vdbox_sfc_access;
> + blob->system_info.vdbox_sfc_support_mask = gt->info.vdbox_sfc_access;
>
> base = intel_guc_ggtt_offset(guc, guc->ads_vma);
>
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index ddefc52f6e09..e047a4950f5f 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -347,7 +347,7 @@ static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
> gvt_dbg_mmio("vgpu%d: request GUC Reset\n", vgpu->id);
> vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET;
> }
> - engine_mask &= INTEL_INFO(vgpu->gvt->gt->i915)->engine_mask;
> + engine_mask &= vgpu->gvt->gt->info.engine_mask;
> }
>
> /* vgpu_lock already hold by emulate mmio r/w */
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 8594a8ef08ce..cad1620d2a7e 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -34,6 +34,7 @@
> #include "gem/i915_gem_context.h"
> #include "gt/intel_gt_buffer_pool.h"
> #include "gt/intel_gt_clock_utils.h"
> +#include "gt/intel_gt.h"
> #include "gt/intel_gt_pm.h"
> #include "gt/intel_gt_requests.h"
> #include "gt/intel_reset.h"
> @@ -61,6 +62,7 @@ static int i915_capabilities(struct seq_file *m, void *data)
>
> intel_device_info_print_static(INTEL_INFO(i915), &p);
> intel_device_info_print_runtime(RUNTIME_INFO(i915), &p);
> + intel_gt_info_print(&i915->gt.info, &p);
> intel_driver_caps_print(&i915->caps, &p);
>
> kernel_param_lock(THIS_MODULE);
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 611287353420..67789df42be8 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -886,6 +886,7 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv)
>
> intel_device_info_print_static(INTEL_INFO(dev_priv), &p);
> intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p);
> + intel_gt_info_print(&dev_priv->gt.info, &p);
> }
>
> if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 17cad4e2cb9c..fa01bf0929e0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1254,7 +1254,7 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
>
> /* Iterator over subset of engines selected by mask */
> #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
> - for ((tmp__) = (mask__) & INTEL_INFO((gt__)->i915)->engine_mask; \
> + for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
> (tmp__) ? \
> ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
> 0;)
> @@ -1561,12 +1561,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
>
> #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
> -#define HAS_ENGINE(gt, id) __HAS_ENGINE(INTEL_INFO((gt)->i915)->engine_mask, id)
> +#define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
>
> #define ENGINE_INSTANCES_MASK(gt, first, count) ({ \
> unsigned int first__ = (first); \
> unsigned int count__ = (count); \
> - (INTEL_INFO((gt)->i915)->engine_mask & \
> + ((gt)->info.engine_mask & \
> GENMASK(first__ + count__ - 1, first__)) >> first__; \
> })
> #define VDBOX_MASK(gt) \
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 866166ada10e..9cb9aa39c33d 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -42,6 +42,7 @@
>
> #include "gem/i915_gem_context.h"
> #include "gem/i915_gem_lmem.h"
> +#include "gt/intel_gt.h"
> #include "gt/intel_gt_pm.h"
>
> #include "i915_drv.h"
> @@ -619,16 +620,15 @@ static void print_error_vma(struct drm_i915_error_state_buf *m,
> }
>
> static void err_print_capabilities(struct drm_i915_error_state_buf *m,
> - const struct intel_device_info *info,
> - const struct intel_runtime_info *runtime,
> - const struct intel_driver_caps *caps)
> + struct i915_gpu_coredump *error)
> {
> struct drm_printer p = i915_error_printer(m);
>
> - intel_device_info_print_static(info, &p);
> - intel_device_info_print_runtime(runtime, &p);
> - intel_device_info_print_topology(&runtime->sseu, &p);
> - intel_driver_caps_print(caps, &p);
> + intel_device_info_print_static(&error->device_info, &p);
> + intel_device_info_print_runtime(&error->runtime_info, &p);
> + intel_device_info_print_topology(&error->runtime_info.sseu, &p);
> + intel_gt_info_print(&error->gt->info, &p);
> + intel_driver_caps_print(&error->driver_caps, &p);
> }
>
> static void err_print_params(struct drm_i915_error_state_buf *m,
> @@ -798,8 +798,7 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
> if (error->display)
> intel_display_print_error_state(m, error->display);
>
> - err_print_capabilities(m, &error->device_info, &error->runtime_info,
> - &error->driver_caps);
> + err_print_capabilities(m, error);
> err_print_params(m, &error->params);
> }
>
> @@ -1630,6 +1629,11 @@ static void gt_record_regs(struct intel_gt_coredump *gt)
> gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER);
> }
>
> +static void gt_record_info(struct intel_gt_coredump *gt)
> +{
> + memcpy(>->info, >->_gt->info, sizeof(struct intel_gt_info));
> +}
> +
> /*
> * Generate a semi-unique error code. The code is not meant to have meaning, The
> * code's only purpose is to try to prevent false duplicated bug reports by
> @@ -1808,6 +1812,7 @@ struct i915_gpu_coredump *i915_gpu_coredump(struct drm_i915_private *i915)
> return ERR_PTR(-ENOMEM);
> }
>
> + gt_record_info(error->gt);
> gt_record_engines(error->gt, compress);
>
> if (INTEL_INFO(i915)->has_gt_uc)
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h b/drivers/gpu/drm/i915/i915_gpu_error.h
> index 76b80fbfb7e9..0220b0992808 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.h
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.h
> @@ -15,6 +15,7 @@
> #include <drm/drm_mm.h>
>
> #include "gt/intel_engine.h"
> +#include "gt/intel_gt_types.h"
> #include "gt/uc/intel_uc_fw.h"
>
> #include "intel_device_info.h"
> @@ -118,6 +119,8 @@ struct intel_gt_coredump {
> bool awake;
> bool simulated;
>
> + struct intel_gt_info info;
> +
> /* Generic register state */
> u32 eir;
> u32 pgtbl_er;
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index e5fdf17cd9cd..7658025a791f 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -168,7 +168,7 @@
> .gpu_reset_clobbers_display = true, \
> .hws_needs_physical = 1, \
> .unfenced_needs_alignment = 1, \
> - .engine_mask = BIT(RCS0), \
> + .max_engine_mask = BIT(RCS0), \
> .has_snoop = true, \
> .has_coherent_ggtt = false, \
> .dma_mask_size = 32, \
> @@ -188,7 +188,7 @@
> .gpu_reset_clobbers_display = true, \
> .hws_needs_physical = 1, \
> .unfenced_needs_alignment = 1, \
> - .engine_mask = BIT(RCS0), \
> + .max_engine_mask = BIT(RCS0), \
> .has_snoop = true, \
> .has_coherent_ggtt = false, \
> .dma_mask_size = 32, \
> @@ -225,7 +225,7 @@ static const struct intel_device_info i865g_info = {
> .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
> .display.has_gmch = 1, \
> .gpu_reset_clobbers_display = true, \
> - .engine_mask = BIT(RCS0), \
> + .max_engine_mask = BIT(RCS0), \
> .has_snoop = true, \
> .has_coherent_ggtt = true, \
> .dma_mask_size = 32, \
> @@ -316,7 +316,7 @@ static const struct intel_device_info pnv_m_info = {
> .display.has_hotplug = 1, \
> .display.has_gmch = 1, \
> .gpu_reset_clobbers_display = true, \
> - .engine_mask = BIT(RCS0), \
> + .max_engine_mask = BIT(RCS0), \
> .has_snoop = true, \
> .has_coherent_ggtt = true, \
> .dma_mask_size = 36, \
> @@ -348,7 +348,7 @@ static const struct intel_device_info i965gm_info = {
> static const struct intel_device_info g45_info = {
> GEN4_FEATURES,
> PLATFORM(INTEL_G45),
> - .engine_mask = BIT(RCS0) | BIT(VCS0),
> + .max_engine_mask = BIT(RCS0) | BIT(VCS0),
> .gpu_reset_clobbers_display = false,
> };
>
> @@ -358,7 +358,7 @@ static const struct intel_device_info gm45_info = {
> .is_mobile = 1,
> .display.has_fbc = 1,
> .display.supports_tv = 1,
> - .engine_mask = BIT(RCS0) | BIT(VCS0),
> + .max_engine_mask = BIT(RCS0) | BIT(VCS0),
> .gpu_reset_clobbers_display = false,
> };
>
> @@ -367,7 +367,7 @@ static const struct intel_device_info gm45_info = {
> .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
> .display.has_hotplug = 1, \
> - .engine_mask = BIT(RCS0) | BIT(VCS0), \
> + .max_engine_mask = BIT(RCS0) | BIT(VCS0), \
> .has_snoop = true, \
> .has_coherent_ggtt = true, \
> /* ilk does support rc6, but we do not implement [power] contexts */ \
> @@ -397,7 +397,7 @@ static const struct intel_device_info ilk_m_info = {
> .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
> .display.has_hotplug = 1, \
> .display.has_fbc = 1, \
> - .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
> + .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
> .has_coherent_ggtt = true, \
> .has_llc = 1, \
> .has_rc6 = 1, \
> @@ -448,7 +448,7 @@ static const struct intel_device_info snb_m_gt2_info = {
> .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
> .display.has_hotplug = 1, \
> .display.has_fbc = 1, \
> - .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
> + .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
> .has_coherent_ggtt = true, \
> .has_llc = 1, \
> .has_rc6 = 1, \
> @@ -519,7 +519,7 @@ static const struct intel_device_info vlv_info = {
> .ppgtt_size = 31,
> .has_snoop = true,
> .has_coherent_ggtt = false,
> - .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
> + .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
> .display_mmio_offset = VLV_DISPLAY_BASE,
> I9XX_PIPE_OFFSETS,
> I9XX_CURSOR_OFFSETS,
> @@ -530,7 +530,7 @@ static const struct intel_device_info vlv_info = {
>
> #define G75_FEATURES \
> GEN7_FEATURES, \
> - .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
> + .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
> .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
> .display.has_ddi = 1, \
> @@ -597,7 +597,7 @@ static const struct intel_device_info bdw_rsvd_info = {
> static const struct intel_device_info bdw_gt3_info = {
> BDW_PLATFORM,
> .gt = 3,
> - .engine_mask =
> + .max_engine_mask =
> BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
> };
>
> @@ -608,7 +608,7 @@ static const struct intel_device_info chv_info = {
> .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
> .display.has_hotplug = 1,
> .is_lp = 1,
> - .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
> + .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
> .has_64bit_reloc = 1,
> .has_runtime_pm = 1,
> .has_rc6 = 1,
> @@ -661,7 +661,7 @@ static const struct intel_device_info skl_gt2_info = {
>
> #define SKL_GT3_PLUS_PLATFORM \
> SKL_PLATFORM, \
> - .engine_mask = \
> + .max_engine_mask = \
> BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
>
>
> @@ -680,7 +680,7 @@ static const struct intel_device_info skl_gt4_info = {
> .is_lp = 1, \
> .num_supported_dbuf_slices = 1, \
> .display.has_hotplug = 1, \
> - .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
> + .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
> .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
> .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
> @@ -743,7 +743,7 @@ static const struct intel_device_info kbl_gt2_info = {
> static const struct intel_device_info kbl_gt3_info = {
> KBL_PLATFORM,
> .gt = 3,
> - .engine_mask =
> + .max_engine_mask =
> BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
> };
>
> @@ -764,7 +764,7 @@ static const struct intel_device_info cfl_gt2_info = {
> static const struct intel_device_info cfl_gt3_info = {
> CFL_PLATFORM,
> .gt = 3,
> - .engine_mask =
> + .max_engine_mask =
> BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
> };
>
> @@ -833,7 +833,7 @@ static const struct intel_device_info cnl_info = {
> static const struct intel_device_info icl_info = {
> GEN11_FEATURES,
> PLATFORM(INTEL_ICELAKE),
> - .engine_mask =
> + .max_engine_mask =
> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> };
>
> @@ -841,7 +841,7 @@ static const struct intel_device_info ehl_info = {
> GEN11_FEATURES,
> PLATFORM(INTEL_ELKHARTLAKE),
> .require_force_probe = 1,
> - .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
> + .max_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
> .ppgtt_size = 36,
> };
>
> @@ -877,7 +877,7 @@ static const struct intel_device_info tgl_info = {
> GEN12_FEATURES,
> PLATFORM(INTEL_TIGERLAKE),
> .display.has_modular_fia = 1,
> - .engine_mask =
> + .max_engine_mask =
> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> };
>
> @@ -890,7 +890,7 @@ static const struct intel_device_info rkl_info = {
> BIT(TRANSCODER_C),
> .require_force_probe = 1,
> .display.has_psr_hw_tracking = 0,
> - .engine_mask =
> + .max_engine_mask =
> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
> };
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 92ebea35c752..a362a66fce11 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -92,7 +92,6 @@ static const char *iommu_name(void)
> void intel_device_info_print_static(const struct intel_device_info *info,
> struct drm_printer *p)
> {
> - drm_printf(p, "engines: %x\n", info->engine_mask);
> drm_printf(p, "gen: %d\n", info->gen);
> drm_printf(p, "gt: %d\n", info->gt);
> drm_printf(p, "iommu: %s\n", iommu_name());
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index fa60fdc1d75a..f03ed95af190 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -157,7 +157,7 @@ struct intel_device_info {
>
> u8 gen;
> u8 gt; /* GT number, 0 if undefined */
> - intel_engine_mask_t engine_mask; /* Engines supported by the HW */
> + intel_engine_mask_t max_engine_mask; /* Engines supported by the HW */
>
> enum intel_platform platform;
>
> @@ -219,8 +219,6 @@ struct intel_runtime_info {
> u8 num_sprites[I915_MAX_PIPES];
> u8 num_scalers[I915_MAX_PIPES];
>
> - u8 num_engines;
> -
> /* Slice/subslice/EU info */
> struct sseu_dev_info sseu;
>
> @@ -228,9 +226,6 @@ struct intel_runtime_info {
>
> u32 cs_timestamp_frequency_hz;
> u32 cs_timestamp_period_ns;
> -
> - /* Media engine access to SFC per instance */
> - u8 vdbox_sfc_access;
> };
>
> struct intel_driver_caps {
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index bd4b45191f7b..f5548875836c 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1530,7 +1530,7 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
>
> if (INTEL_GEN(i915) >= 11) {
> /* we'll prune the domains of missing engines later */
> - intel_engine_mask_t emask = INTEL_INFO(i915)->engine_mask;
> + intel_engine_mask_t emask = INTEL_INFO(i915)->max_engine_mask;
> int i;
>
> uncore->funcs.force_wake_get = fw_domains_get_with_fallback;
> diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c
> index 9271aad7f779..57dd6f5122ee 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_request.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_request.c
> @@ -1454,7 +1454,7 @@ static int live_breadcrumbs_smoketest(void *arg)
> idx++;
> }
> pr_info("Completed %lu waits for %lu fences across %d engines and %d cpus\n",
> - num_waits, num_fences, RUNTIME_INFO(i915)->num_engines, ncpus);
> + num_waits, num_fences, idx, ncpus);
>
> ret = igt_live_test_end(&live) ?: ret;
> out_contexts:
> diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> index 9b105b811f1f..0916efa31889 100644
> --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> @@ -190,7 +190,8 @@ struct drm_i915_private *mock_gem_device(void)
> mock_init_ggtt(i915, &i915->ggtt);
> i915->gt.vm = i915_vm_get(&i915->ggtt.vm);
>
> - mkwrite_device_info(i915)->engine_mask = BIT(0);
> + mkwrite_device_info(i915)->max_engine_mask = BIT(0);
> + i915->gt.info.engine_mask = BIT(0);
>
> i915->gt.engine[RCS0] = mock_engine(i915, "mock", RCS0);
> if (!i915->gt.engine[RCS0])
>
Only thing which looks a bit sub-optimalis the name "max_engine_mask",
but maybe it is just me, that max and masks do not go well together.
Only alternative I have for the moment is platform_engine_mask? Or the
usual double underscore approach. Either way:
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 5/7] drm/i915: Introduce gt_init_mmio
2020-06-25 23:42 ` [Intel-gfx] [PATCH 5/7] drm/i915: Introduce gt_init_mmio Daniele Ceraolo Spurio
@ 2020-06-26 14:46 ` Tvrtko Ursulin
0 siblings, 0 replies; 26+ messages in thread
From: Tvrtko Ursulin @ 2020-06-26 14:46 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx
On 26/06/2020 00:42, Daniele Ceraolo Spurio wrote:
> We already call 2 gt-related init_mmio functions in driver_mmio_probe
> and a 3rd one will be added by a follow-up patch, so pre-emptively
> introduce a gt_init_mmio function to group them.
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Cc: Andi Shyti <andi.shyti@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 7 +++++++
> drivers/gpu/drm/i915/gt/intel_gt.h | 1 +
> drivers/gpu/drm/i915/i915_drv.c | 4 +---
> 3 files changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index d0ae1cb5c7c9..949114f09b82 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -44,6 +44,13 @@ void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt)
> gt->ggtt = ggtt;
> }
>
> +int intel_gt_init_mmio(struct intel_gt *gt)
> +{
> + intel_uc_init_mmio(>->uc);
> +
> + return intel_engines_init_mmio(gt);
> +}
> +
> static void init_unused_ring(struct intel_gt *gt, u32 base)
> {
> struct intel_uncore *uncore = gt->uncore;
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
> index 15142e2a3b22..4bd64ab2b686 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -36,6 +36,7 @@ static inline struct intel_gt *huc_to_gt(struct intel_huc *huc)
>
> void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
> void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt);
> +int intel_gt_init_mmio(struct intel_gt *gt);
> int __must_check intel_gt_init_hw(struct intel_gt *gt);
> int intel_gt_init(struct intel_gt *gt);
> void intel_gt_driver_register(struct intel_gt *gt);
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 67789df42be8..5fd5af4bc855 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -531,9 +531,7 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
> /* Try to make sure MCHBAR is enabled before poking at it */
> intel_setup_mchbar(dev_priv);
>
> - intel_uc_init_mmio(&dev_priv->gt.uc);
> -
> - ret = intel_engines_init_mmio(&dev_priv->gt);
> + ret = intel_gt_init_mmio(&dev_priv->gt);
> if (ret)
> goto err_uncore;
>
>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 3/7] drm/i915: Move engine-related mmio init to engines_init_mmio
2020-06-26 14:38 ` Chris Wilson
@ 2020-06-26 14:46 ` Daniele Ceraolo Spurio
2020-06-26 14:51 ` Chris Wilson
0 siblings, 1 reply; 26+ messages in thread
From: Daniele Ceraolo Spurio @ 2020-06-26 14:46 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 6/26/20 7:38 AM, Chris Wilson wrote:
> Quoting Daniele Ceraolo Spurio (2020-06-26 00:42:08)
>> All the info we read in intel_device_info_init_mmio are engine-related
>> and since we already have an engine_init_mmio function we can just
>> perform the operations from there.
>>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>> Cc: Andi Shyti <andi.shyti@intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 72 ++++++++++++++++++++++-
>> drivers/gpu/drm/i915/i915_drv.c | 4 --
>> drivers/gpu/drm/i915/intel_device_info.c | 66 ---------------------
>> drivers/gpu/drm/i915/intel_device_info.h | 2 -
>> 4 files changed, 71 insertions(+), 73 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> index be92d1ef9aa9..8497106eb3a6 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> @@ -450,6 +450,74 @@ void intel_engines_free(struct intel_gt *gt)
>> }
>> }
>>
>> +/*
>> + * Determine which engines are fused off in our particular hardware. Since the
>> + * fuse register is in the blitter powerwell, we need forcewake to be ready at
>> + * this point (but later we need to prune the forcewake domains for engines that
>> + * are indeed fused off).
>> + */
>> +static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
>> +{
>> + struct drm_i915_private *i915 = gt->i915;
>> + struct intel_device_info *info = mkwrite_device_info(i915);
>> + struct intel_uncore *uncore = gt->uncore;
>> + unsigned int logical_vdbox = 0;
>> + unsigned int i;
>> + u32 media_fuse;
>> + u16 vdbox_mask;
>> + u16 vebox_mask;
>
> assert_forcewakes_active(uncore, FORCEWAKE_BLITTER) ?
>
> Since it's called out in the comment, might as well reinforce that with
> an assert.
We don't expect it to be active, just to be initialized/usable.
This comment is there to remind us of the catch-22 issue we have where
we need forcewake to be initialized to read the fuses, but we need the
fuses values to know which engines are available and therefore which fw
domains are there (and that's why we prune the domains later).
Daniele
> -Chris
>
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 3/7] drm/i915: Move engine-related mmio init to engines_init_mmio
2020-06-26 14:46 ` Daniele Ceraolo Spurio
@ 2020-06-26 14:51 ` Chris Wilson
0 siblings, 0 replies; 26+ messages in thread
From: Chris Wilson @ 2020-06-26 14:51 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx
Quoting Daniele Ceraolo Spurio (2020-06-26 15:46:53)
>
>
> On 6/26/20 7:38 AM, Chris Wilson wrote:
> > Quoting Daniele Ceraolo Spurio (2020-06-26 00:42:08)
> >> All the info we read in intel_device_info_init_mmio are engine-related
> >> and since we already have an engine_init_mmio function we can just
> >> perform the operations from there.
> >>
> >> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> >> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> >> Cc: Andi Shyti <andi.shyti@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 72 ++++++++++++++++++++++-
> >> drivers/gpu/drm/i915/i915_drv.c | 4 --
> >> drivers/gpu/drm/i915/intel_device_info.c | 66 ---------------------
> >> drivers/gpu/drm/i915/intel_device_info.h | 2 -
> >> 4 files changed, 71 insertions(+), 73 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> >> index be92d1ef9aa9..8497106eb3a6 100644
> >> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> >> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> >> @@ -450,6 +450,74 @@ void intel_engines_free(struct intel_gt *gt)
> >> }
> >> }
> >>
> >> +/*
> >> + * Determine which engines are fused off in our particular hardware. Since the
> >> + * fuse register is in the blitter powerwell, we need forcewake to be ready at
> >> + * this point (but later we need to prune the forcewake domains for engines that
> >> + * are indeed fused off).
> >> + */
> >> +static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
> >> +{
> >> + struct drm_i915_private *i915 = gt->i915;
> >> + struct intel_device_info *info = mkwrite_device_info(i915);
> >> + struct intel_uncore *uncore = gt->uncore;
> >> + unsigned int logical_vdbox = 0;
> >> + unsigned int i;
> >> + u32 media_fuse;
> >> + u16 vdbox_mask;
> >> + u16 vebox_mask;
> >
> > assert_forcewakes_active(uncore, FORCEWAKE_BLITTER) ?
> >
> > Since it's called out in the comment, might as well reinforce that with
> > an assert.
>
> We don't expect it to be active, just to be initialized/usable.
> This comment is there to remind us of the catch-22 issue we have where
> we need forcewake to be initialized to read the fuses, but we need the
> fuses values to know which engines are available and therefore which fw
> domains are there (and that's why we prune the domains later).
Gotcha, I assumed 'ready' == 'powered up'
How about adding that explanation to the comment :)
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 6/7] drm/i915/sseu: Move sseu detection and dump to intel_sseu
2020-06-25 23:42 ` [Intel-gfx] [PATCH 6/7] drm/i915/sseu: Move sseu detection and dump to intel_sseu Daniele Ceraolo Spurio
@ 2020-06-26 15:00 ` Tvrtko Ursulin
0 siblings, 0 replies; 26+ messages in thread
From: Tvrtko Ursulin @ 2020-06-26 15:00 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx
On 26/06/2020 00:42, Daniele Ceraolo Spurio wrote:
> Keep all the SSEU code in the relevant file. The code has also been
> updated to use intel_gt instead of dev_priv.
>
> Based on an original patch by Sandeep.
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Cc: Andi Shyti <andi.shyti@intel.com>
> Cc: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
> drivers/gpu/drm/i915/gt/intel_sseu.c | 587 +++++++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_sseu.h | 8 +
> drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
> drivers/gpu/drm/i915/intel_device_info.c | 584 +---------------------
> drivers/gpu/drm/i915/intel_device_info.h | 2 -
> 7 files changed, 600 insertions(+), 586 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 949114f09b82..de95930f8627 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -47,6 +47,7 @@ void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt)
> int intel_gt_init_mmio(struct intel_gt *gt)
> {
> intel_uc_init_mmio(>->uc);
> + intel_sseu_info_init(gt);
>
> return intel_engines_init_mmio(gt);
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
> index d173271c7397..006f9118b319 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> @@ -60,6 +60,548 @@ intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
> return hweight32(intel_sseu_get_subslices(sseu, slice));
> }
>
> +static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice,
> + int subslice)
> +{
> + int slice_stride = sseu->max_subslices * sseu->eu_stride;
> +
> + return slice * slice_stride + subslice * sseu->eu_stride;
> +}
> +
> +static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
> + int subslice)
> +{
> + int i, offset = sseu_eu_idx(sseu, slice, subslice);
> + u16 eu_mask = 0;
> +
> + for (i = 0; i < sseu->eu_stride; i++) {
> + eu_mask |= ((u16)sseu->eu_mask[offset + i]) <<
> + (i * BITS_PER_BYTE);
> + }
> +
> + return eu_mask;
> +}
> +
> +static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice,
> + u16 eu_mask)
> +{
> + int i, offset = sseu_eu_idx(sseu, slice, subslice);
> +
> + for (i = 0; i < sseu->eu_stride; i++) {
> + sseu->eu_mask[offset + i] =
> + (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
> + }
> +}
> +
> +static u16 compute_eu_total(const struct sseu_dev_info *sseu)
> +{
> + u16 i, total = 0;
> +
> + for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++)
> + total += hweight8(sseu->eu_mask[i]);
> +
> + return total;
> +}
> +
> +static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
> + u8 s_en, u32 ss_en, u16 eu_en)
> +{
> + int s, ss;
> +
> + /* ss_en represents entire subslice mask across all slices */
> + GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
> + sizeof(ss_en) * BITS_PER_BYTE);
> +
> + for (s = 0; s < sseu->max_slices; s++) {
> + if ((s_en & BIT(s)) == 0)
> + continue;
> +
> + sseu->slice_mask |= BIT(s);
> +
> + intel_sseu_set_subslices(sseu, s, ss_en);
> +
> + for (ss = 0; ss < sseu->max_subslices; ss++)
> + if (intel_sseu_has_subslice(sseu, s, ss))
> + sseu_set_eus(sseu, s, ss, eu_en);
> + }
> + sseu->eu_per_subslice = hweight16(eu_en);
> + sseu->eu_total = compute_eu_total(sseu);
> +}
> +
> +static void gen12_sseu_info_init(struct intel_gt *gt)
> +{
> + struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
> + struct intel_uncore *uncore = gt->uncore;
> + u8 s_en;
> + u32 dss_en;
> + u16 eu_en = 0;
> + u8 eu_en_fuse;
> + int eu;
> +
> + /*
> + * Gen12 has Dual-Subslices, which behave similarly to 2 gen11 SS.
> + * Instead of splitting these, provide userspace with an array
> + * of DSS to more closely represent the hardware resource.
> + */
> + intel_sseu_set_info(sseu, 1, 6, 16);
> +
> + s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
> + GEN11_GT_S_ENA_MASK;
> +
> + dss_en = intel_uncore_read(uncore, GEN12_GT_DSS_ENABLE);
> +
> + /* one bit per pair of EUs */
> + eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
> + GEN11_EU_DIS_MASK);
> + for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
> + if (eu_en_fuse & BIT(eu))
> + eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
> +
> + gen11_compute_sseu_info(sseu, s_en, dss_en, eu_en);
> +
> + /* TGL only supports slice-level power gating */
> + sseu->has_slice_pg = 1;
> +}
> +
> +static void gen11_sseu_info_init(struct intel_gt *gt)
> +{
> + struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
> + struct intel_uncore *uncore = gt->uncore;
> + u8 s_en;
> + u32 ss_en;
> + u8 eu_en;
> +
> + if (IS_ELKHARTLAKE(gt->i915))
> + intel_sseu_set_info(sseu, 1, 4, 8);
> + else
> + intel_sseu_set_info(sseu, 1, 8, 8);
> +
> + s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
> + GEN11_GT_S_ENA_MASK;
> + ss_en = ~intel_uncore_read(uncore, GEN11_GT_SUBSLICE_DISABLE);
> +
> + eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
> + GEN11_EU_DIS_MASK);
> +
> + gen11_compute_sseu_info(sseu, s_en, ss_en, eu_en);
> +
> + /* ICL has no power gating restrictions. */
> + sseu->has_slice_pg = 1;
> + sseu->has_subslice_pg = 1;
> + sseu->has_eu_pg = 1;
> +}
> +
> +static void gen10_sseu_info_init(struct intel_gt *gt)
> +{
> + struct intel_uncore *uncore = gt->uncore;
> + struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
> + const u32 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
> + int s, ss;
> + const int eu_mask = 0xff;
> + u32 subslice_mask, eu_en;
> +
> + intel_sseu_set_info(sseu, 6, 4, 8);
> +
> + sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
> + GEN10_F2_S_ENA_SHIFT;
> +
> + /* Slice0 */
> + eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE0);
> + for (ss = 0; ss < sseu->max_subslices; ss++)
> + sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask);
> + /* Slice1 */
> + sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask);
> + eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE1);
> + sseu_set_eus(sseu, 1, 1, eu_en & eu_mask);
> + /* Slice2 */
> + sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask);
> + sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask);
> + /* Slice3 */
> + sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask);
> + eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE2);
> + sseu_set_eus(sseu, 3, 1, eu_en & eu_mask);
> + /* Slice4 */
> + sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask);
> + sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask);
> + /* Slice5 */
> + sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask);
> + eu_en = ~intel_uncore_read(uncore, GEN10_EU_DISABLE3);
> + sseu_set_eus(sseu, 5, 1, eu_en & eu_mask);
> +
> + subslice_mask = (1 << 4) - 1;
> + subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
> + GEN10_F2_SS_DIS_SHIFT);
> +
> + for (s = 0; s < sseu->max_slices; s++) {
> + u32 subslice_mask_with_eus = subslice_mask;
> +
> + for (ss = 0; ss < sseu->max_subslices; ss++) {
> + if (sseu_get_eus(sseu, s, ss) == 0)
> + subslice_mask_with_eus &= ~BIT(ss);
> + }
> +
> + /*
> + * Slice0 can have up to 3 subslices, but there are only 2 in
> + * slice1/2.
> + */
> + intel_sseu_set_subslices(sseu, s, s == 0 ?
> + subslice_mask_with_eus :
> + subslice_mask_with_eus & 0x3);
> + }
> +
> + sseu->eu_total = compute_eu_total(sseu);
> +
> + /*
> + * CNL is expected to always have a uniform distribution
> + * of EU across subslices with the exception that any one
> + * EU in any one subslice may be fused off for die
> + * recovery.
> + */
> + sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ?
> + DIV_ROUND_UP(sseu->eu_total,
> + intel_sseu_subslice_total(sseu)) :
> + 0;
> +
> + /* No restrictions on Power Gating */
> + sseu->has_slice_pg = 1;
> + sseu->has_subslice_pg = 1;
> + sseu->has_eu_pg = 1;
> +}
> +
> +static void cherryview_sseu_info_init(struct intel_gt *gt)
> +{
> + struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
> + u32 fuse;
> + u8 subslice_mask = 0;
> +
> + fuse = intel_uncore_read(gt->uncore, CHV_FUSE_GT);
> +
> + sseu->slice_mask = BIT(0);
> + intel_sseu_set_info(sseu, 1, 2, 8);
> +
> + if (!(fuse & CHV_FGT_DISABLE_SS0)) {
> + u8 disabled_mask =
> + ((fuse & CHV_FGT_EU_DIS_SS0_R0_MASK) >>
> + CHV_FGT_EU_DIS_SS0_R0_SHIFT) |
> + (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
> + CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
> +
> + subslice_mask |= BIT(0);
> + sseu_set_eus(sseu, 0, 0, ~disabled_mask);
> + }
> +
> + if (!(fuse & CHV_FGT_DISABLE_SS1)) {
> + u8 disabled_mask =
> + ((fuse & CHV_FGT_EU_DIS_SS1_R0_MASK) >>
> + CHV_FGT_EU_DIS_SS1_R0_SHIFT) |
> + (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
> + CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
> +
> + subslice_mask |= BIT(1);
> + sseu_set_eus(sseu, 0, 1, ~disabled_mask);
> + }
> +
> + intel_sseu_set_subslices(sseu, 0, subslice_mask);
> +
> + sseu->eu_total = compute_eu_total(sseu);
> +
> + /*
> + * CHV expected to always have a uniform distribution of EU
> + * across subslices.
> + */
> + sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ?
> + sseu->eu_total /
> + intel_sseu_subslice_total(sseu) :
> + 0;
> + /*
> + * CHV supports subslice power gating on devices with more than
> + * one subslice, and supports EU power gating on devices with
> + * more than one EU pair per subslice.
> + */
> + sseu->has_slice_pg = 0;
> + sseu->has_subslice_pg = intel_sseu_subslice_total(sseu) > 1;
> + sseu->has_eu_pg = (sseu->eu_per_subslice > 2);
> +}
> +
> +static void gen9_sseu_info_init(struct intel_gt *gt)
> +{
> + struct drm_i915_private *i915 = gt->i915;
> + struct intel_device_info *info = mkwrite_device_info(i915);
> + struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
> + struct intel_uncore *uncore = gt->uncore;
> + int s, ss;
> + u32 fuse2, eu_disable, subslice_mask;
> + const u8 eu_mask = 0xff;
> +
> + fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
> + sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
> +
> + /* BXT has a single slice and at most 3 subslices. */
> + intel_sseu_set_info(sseu, IS_GEN9_LP(i915) ? 1 : 3,
> + IS_GEN9_LP(i915) ? 3 : 4, 8);
> +
> + /*
> + * The subslice disable field is global, i.e. it applies
> + * to each of the enabled slices.
> + */
> + subslice_mask = (1 << sseu->max_subslices) - 1;
> + subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >>
> + GEN9_F2_SS_DIS_SHIFT);
> +
> + /*
> + * Iterate through enabled slices and subslices to
> + * count the total enabled EU.
> + */
> + for (s = 0; s < sseu->max_slices; s++) {
> + if (!(sseu->slice_mask & BIT(s)))
> + /* skip disabled slice */
> + continue;
> +
> + intel_sseu_set_subslices(sseu, s, subslice_mask);
> +
> + eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s));
> + for (ss = 0; ss < sseu->max_subslices; ss++) {
> + int eu_per_ss;
> + u8 eu_disabled_mask;
> +
> + if (!intel_sseu_has_subslice(sseu, s, ss))
> + /* skip disabled subslice */
> + continue;
> +
> + eu_disabled_mask = (eu_disable >> (ss * 8)) & eu_mask;
> +
> + sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
> +
> + eu_per_ss = sseu->max_eus_per_subslice -
> + hweight8(eu_disabled_mask);
> +
> + /*
> + * Record which subslice(s) has(have) 7 EUs. we
> + * can tune the hash used to spread work among
> + * subslices if they are unbalanced.
> + */
> + if (eu_per_ss == 7)
> + sseu->subslice_7eu[s] |= BIT(ss);
> + }
> + }
> +
> + sseu->eu_total = compute_eu_total(sseu);
> +
> + /*
> + * SKL is expected to always have a uniform distribution
> + * of EU across subslices with the exception that any one
> + * EU in any one subslice may be fused off for die
> + * recovery. BXT is expected to be perfectly uniform in EU
> + * distribution.
> + */
> + sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ?
> + DIV_ROUND_UP(sseu->eu_total,
> + intel_sseu_subslice_total(sseu)) :
> + 0;
> + /*
> + * SKL+ supports slice power gating on devices with more than
> + * one slice, and supports EU power gating on devices with
> + * more than one EU pair per subslice. BXT+ supports subslice
> + * power gating on devices with more than one subslice, and
> + * supports EU power gating on devices with more than one EU
> + * pair per subslice.
> + */
> + sseu->has_slice_pg =
> + !IS_GEN9_LP(i915) && hweight8(sseu->slice_mask) > 1;
> + sseu->has_subslice_pg =
> + IS_GEN9_LP(i915) && intel_sseu_subslice_total(sseu) > 1;
> + sseu->has_eu_pg = sseu->eu_per_subslice > 2;
> +
> + if (IS_GEN9_LP(i915)) {
> +#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss)))
> + info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3;
> +
> + sseu->min_eu_in_pool = 0;
> + if (info->has_pooled_eu) {
> + if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0))
> + sseu->min_eu_in_pool = 3;
> + else if (IS_SS_DISABLED(1))
> + sseu->min_eu_in_pool = 6;
> + else
> + sseu->min_eu_in_pool = 9;
> + }
> +#undef IS_SS_DISABLED
> + }
> +}
> +
> +static void bdw_sseu_info_init(struct intel_gt *gt)
> +{
> + struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
> + struct intel_uncore *uncore = gt->uncore;
> + int s, ss;
> + u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */
> + u32 eu_disable0, eu_disable1, eu_disable2;
> +
> + fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
> + sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
> + intel_sseu_set_info(sseu, 3, 3, 8);
> +
> + /*
> + * The subslice disable field is global, i.e. it applies
> + * to each of the enabled slices.
> + */
> + subslice_mask = GENMASK(sseu->max_subslices - 1, 0);
> + subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >>
> + GEN8_F2_SS_DIS_SHIFT);
> + eu_disable0 = intel_uncore_read(uncore, GEN8_EU_DISABLE0);
> + eu_disable1 = intel_uncore_read(uncore, GEN8_EU_DISABLE1);
> + eu_disable2 = intel_uncore_read(uncore, GEN8_EU_DISABLE2);
> + eu_disable[0] = eu_disable0 & GEN8_EU_DIS0_S0_MASK;
> + eu_disable[1] = (eu_disable0 >> GEN8_EU_DIS0_S1_SHIFT) |
> + ((eu_disable1 & GEN8_EU_DIS1_S1_MASK) <<
> + (32 - GEN8_EU_DIS0_S1_SHIFT));
> + eu_disable[2] = (eu_disable1 >> GEN8_EU_DIS1_S2_SHIFT) |
> + ((eu_disable2 & GEN8_EU_DIS2_S2_MASK) <<
> + (32 - GEN8_EU_DIS1_S2_SHIFT));
> +
> + /*
> + * Iterate through enabled slices and subslices to
> + * count the total enabled EU.
> + */
> + for (s = 0; s < sseu->max_slices; s++) {
> + if (!(sseu->slice_mask & BIT(s)))
> + /* skip disabled slice */
> + continue;
> +
> + intel_sseu_set_subslices(sseu, s, subslice_mask);
> +
> + for (ss = 0; ss < sseu->max_subslices; ss++) {
> + u8 eu_disabled_mask;
> + u32 n_disabled;
> +
> + if (!intel_sseu_has_subslice(sseu, s, ss))
> + /* skip disabled subslice */
> + continue;
> +
> + eu_disabled_mask =
> + eu_disable[s] >> (ss * sseu->max_eus_per_subslice);
> +
> + sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
> +
> + n_disabled = hweight8(eu_disabled_mask);
> +
> + /*
> + * Record which subslices have 7 EUs.
> + */
> + if (sseu->max_eus_per_subslice - n_disabled == 7)
> + sseu->subslice_7eu[s] |= 1 << ss;
> + }
> + }
> +
> + sseu->eu_total = compute_eu_total(sseu);
> +
> + /*
> + * BDW is expected to always have a uniform distribution of EU across
> + * subslices with the exception that any one EU in any one subslice may
> + * be fused off for die recovery.
> + */
> + sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ?
> + DIV_ROUND_UP(sseu->eu_total,
> + intel_sseu_subslice_total(sseu)) :
> + 0;
> +
> + /*
> + * BDW supports slice power gating on devices with more than
> + * one slice.
> + */
> + sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1;
> + sseu->has_subslice_pg = 0;
> + sseu->has_eu_pg = 0;
> +}
> +
> +static void hsw_sseu_info_init(struct intel_gt *gt)
> +{
> + struct drm_i915_private *i915 = gt->i915;
> + struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
> + u32 fuse1;
> + u8 subslice_mask = 0;
> + int s, ss;
> +
> + /*
> + * There isn't a register to tell us how many slices/subslices. We
> + * work off the PCI-ids here.
> + */
> + switch (INTEL_INFO(i915)->gt) {
> + default:
> + MISSING_CASE(INTEL_INFO(i915)->gt);
> + /* fall through */
> + case 1:
> + sseu->slice_mask = BIT(0);
> + subslice_mask = BIT(0);
> + break;
> + case 2:
> + sseu->slice_mask = BIT(0);
> + subslice_mask = BIT(0) | BIT(1);
> + break;
> + case 3:
> + sseu->slice_mask = BIT(0) | BIT(1);
> + subslice_mask = BIT(0) | BIT(1);
> + break;
> + }
> +
> + fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);
> + switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) {
> + default:
> + MISSING_CASE((fuse1 & HSW_F1_EU_DIS_MASK) >>
> + HSW_F1_EU_DIS_SHIFT);
> + /* fall through */
> + case HSW_F1_EU_DIS_10EUS:
> + sseu->eu_per_subslice = 10;
> + break;
> + case HSW_F1_EU_DIS_8EUS:
> + sseu->eu_per_subslice = 8;
> + break;
> + case HSW_F1_EU_DIS_6EUS:
> + sseu->eu_per_subslice = 6;
> + break;
> + }
> +
> + intel_sseu_set_info(sseu, hweight8(sseu->slice_mask),
> + hweight8(subslice_mask),
> + sseu->eu_per_subslice);
> +
> + for (s = 0; s < sseu->max_slices; s++) {
> + intel_sseu_set_subslices(sseu, s, subslice_mask);
> +
> + for (ss = 0; ss < sseu->max_subslices; ss++) {
> + sseu_set_eus(sseu, s, ss,
> + (1UL << sseu->eu_per_subslice) - 1);
> + }
> + }
> +
> + sseu->eu_total = compute_eu_total(sseu);
> +
> + /* No powergating for you. */
> + sseu->has_slice_pg = 0;
> + sseu->has_subslice_pg = 0;
> + sseu->has_eu_pg = 0;
> +}
> +
> +void intel_sseu_info_init(struct intel_gt *gt)
> +{
> + struct drm_i915_private *i915 = gt->i915;
> +
> + if (IS_HASWELL(i915))
> + hsw_sseu_info_init(gt);
> + else if (IS_CHERRYVIEW(i915))
> + cherryview_sseu_info_init(gt);
> + else if (IS_BROADWELL(i915))
> + bdw_sseu_info_init(gt);
> + else if (IS_GEN(i915, 9))
> + gen9_sseu_info_init(gt);
> + else if (IS_GEN(i915, 10))
> + gen10_sseu_info_init(gt);
> + else if (IS_GEN(i915, 11))
> + gen11_sseu_info_init(gt);
> + else if (INTEL_GEN(i915) >= 12)
> + gen12_sseu_info_init(gt);
> +}
> +
> u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
> const struct intel_sseu *req_sseu)
> {
> @@ -173,3 +715,48 @@ u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
>
> return rpcs;
> }
> +
> +void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
> +{
> + int s;
> +
> + drm_printf(p, "slice total: %u, mask=%04x\n",
> + hweight8(sseu->slice_mask), sseu->slice_mask);
> + drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu));
> + for (s = 0; s < sseu->max_slices; s++) {
> + drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
> + s, intel_sseu_subslices_per_slice(sseu, s),
> + intel_sseu_get_subslices(sseu, s));
> + }
> + drm_printf(p, "EU total: %u\n", sseu->eu_total);
> + drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
> + drm_printf(p, "has slice power gating: %s\n",
> + yesno(sseu->has_slice_pg));
> + drm_printf(p, "has subslice power gating: %s\n",
> + yesno(sseu->has_subslice_pg));
> + drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg));
> +}
> +
> +void intel_sseu_print_topology(const struct sseu_dev_info *sseu,
> + struct drm_printer *p)
> +{
> + int s, ss;
> +
> + if (sseu->max_slices == 0) {
> + drm_printf(p, "Unavailable\n");
> + return;
> + }
> +
> + for (s = 0; s < sseu->max_slices; s++) {
> + drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
> + s, intel_sseu_subslices_per_slice(sseu, s),
> + intel_sseu_get_subslices(sseu, s));
> +
> + for (ss = 0; ss < sseu->max_subslices; ss++) {
> + u16 enabled_eus = sseu_get_eus(sseu, s, ss);
> +
> + drm_printf(p, "\tsubslice%d: %u EUs (0x%hx)\n",
> + ss, hweight16(enabled_eus), enabled_eus);
> + }
> + }
> +}
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
> index d1d225204f09..f9c007f001e7 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> @@ -13,6 +13,8 @@
> #include "i915_gem.h"
>
> struct drm_i915_private;
> +struct intel_gt;
> +struct drm_printer;
>
> #define GEN_MAX_SLICES (6) /* CNL upper bound */
> #define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
> @@ -94,7 +96,13 @@ u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice);
> void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
> u32 ss_mask);
>
> +void intel_sseu_info_init(struct intel_gt *gt);
> +
> u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
> const struct intel_sseu *req_sseu);
>
> +void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p);
> +void intel_sseu_print_topology(const struct sseu_dev_info *sseu,
> + struct drm_printer *p);
> +
> #endif /* __INTEL_SSEU_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index cad1620d2a7e..c893a82c2d99 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1323,7 +1323,7 @@ static int i915_rcs_topology(struct seq_file *m, void *unused)
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> struct drm_printer p = drm_seq_file_printer(m);
>
> - intel_device_info_print_topology(&RUNTIME_INFO(dev_priv)->sseu, &p);
> + intel_sseu_print_topology(&RUNTIME_INFO(dev_priv)->sseu, &p);
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 9cb9aa39c33d..99b4a0261b13 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -626,7 +626,7 @@ static void err_print_capabilities(struct drm_i915_error_state_buf *m,
>
> intel_device_info_print_static(&error->device_info, &p);
> intel_device_info_print_runtime(&error->runtime_info, &p);
> - intel_device_info_print_topology(&error->runtime_info.sseu, &p);
> + intel_sseu_print_topology(&error->runtime_info.sseu, &p);
> intel_gt_info_print(&error->gt->info, &p);
> intel_driver_caps_print(&error->driver_caps, &p);
> }
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index a362a66fce11..d8daf224cbd3 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -29,6 +29,7 @@
> #include "display/intel_de.h"
> #include "intel_device_info.h"
> #include "i915_drv.h"
> +#include "gt/intel_sseu.h"
>
> #define PLATFORM_NAME(x) [INTEL_##x] = #x
> static const char * const platform_names[] = {
> @@ -111,581 +112,16 @@ void intel_device_info_print_static(const struct intel_device_info *info,
> #undef PRINT_FLAG
> }
>
> -static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
> -{
> - int s;
> -
> - drm_printf(p, "slice total: %u, mask=%04x\n",
> - hweight8(sseu->slice_mask), sseu->slice_mask);
> - drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu));
> - for (s = 0; s < sseu->max_slices; s++) {
> - drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
> - s, intel_sseu_subslices_per_slice(sseu, s),
> - intel_sseu_get_subslices(sseu, s));
> - }
> - drm_printf(p, "EU total: %u\n", sseu->eu_total);
> - drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
> - drm_printf(p, "has slice power gating: %s\n",
> - yesno(sseu->has_slice_pg));
> - drm_printf(p, "has subslice power gating: %s\n",
> - yesno(sseu->has_subslice_pg));
> - drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg));
> -}
> -
> void intel_device_info_print_runtime(const struct intel_runtime_info *info,
> struct drm_printer *p)
> {
> - sseu_dump(&info->sseu, p);
> + intel_sseu_dump(&info->sseu, p);
>
> drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq);
> drm_printf(p, "CS timestamp frequency: %u Hz\n",
> info->cs_timestamp_frequency_hz);
> }
>
> -static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice,
> - int subslice)
> -{
> - int slice_stride = sseu->max_subslices * sseu->eu_stride;
> -
> - return slice * slice_stride + subslice * sseu->eu_stride;
> -}
> -
> -static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
> - int subslice)
> -{
> - int i, offset = sseu_eu_idx(sseu, slice, subslice);
> - u16 eu_mask = 0;
> -
> - for (i = 0; i < sseu->eu_stride; i++) {
> - eu_mask |= ((u16)sseu->eu_mask[offset + i]) <<
> - (i * BITS_PER_BYTE);
> - }
> -
> - return eu_mask;
> -}
> -
> -static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice,
> - u16 eu_mask)
> -{
> - int i, offset = sseu_eu_idx(sseu, slice, subslice);
> -
> - for (i = 0; i < sseu->eu_stride; i++) {
> - sseu->eu_mask[offset + i] =
> - (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
> - }
> -}
> -
> -void intel_device_info_print_topology(const struct sseu_dev_info *sseu,
> - struct drm_printer *p)
> -{
> - int s, ss;
> -
> - if (sseu->max_slices == 0) {
> - drm_printf(p, "Unavailable\n");
> - return;
> - }
> -
> - for (s = 0; s < sseu->max_slices; s++) {
> - drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
> - s, intel_sseu_subslices_per_slice(sseu, s),
> - intel_sseu_get_subslices(sseu, s));
> -
> - for (ss = 0; ss < sseu->max_subslices; ss++) {
> - u16 enabled_eus = sseu_get_eus(sseu, s, ss);
> -
> - drm_printf(p, "\tsubslice%d: %u EUs (0x%hx)\n",
> - ss, hweight16(enabled_eus), enabled_eus);
> - }
> - }
> -}
> -
> -static u16 compute_eu_total(const struct sseu_dev_info *sseu)
> -{
> - u16 i, total = 0;
> -
> - for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++)
> - total += hweight8(sseu->eu_mask[i]);
> -
> - return total;
> -}
> -
> -static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
> - u8 s_en, u32 ss_en, u16 eu_en)
> -{
> - int s, ss;
> -
> - /* ss_en represents entire subslice mask across all slices */
> - GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
> - sizeof(ss_en) * BITS_PER_BYTE);
> -
> - for (s = 0; s < sseu->max_slices; s++) {
> - if ((s_en & BIT(s)) == 0)
> - continue;
> -
> - sseu->slice_mask |= BIT(s);
> -
> - intel_sseu_set_subslices(sseu, s, ss_en);
> -
> - for (ss = 0; ss < sseu->max_subslices; ss++)
> - if (intel_sseu_has_subslice(sseu, s, ss))
> - sseu_set_eus(sseu, s, ss, eu_en);
> - }
> - sseu->eu_per_subslice = hweight16(eu_en);
> - sseu->eu_total = compute_eu_total(sseu);
> -}
> -
> -static void gen12_sseu_info_init(struct drm_i915_private *dev_priv)
> -{
> - struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
> - struct intel_uncore *uncore = &dev_priv->uncore;
> - u8 s_en;
> - u32 dss_en;
> - u16 eu_en = 0;
> - u8 eu_en_fuse;
> - int eu;
> -
> - /*
> - * Gen12 has Dual-Subslices, which behave similarly to 2 gen11 SS.
> - * Instead of splitting these, provide userspace with an array
> - * of DSS to more closely represent the hardware resource.
> - */
> - intel_sseu_set_info(sseu, 1, 6, 16);
> -
> - s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
> - GEN11_GT_S_ENA_MASK;
> -
> - dss_en = intel_uncore_read(uncore, GEN12_GT_DSS_ENABLE);
> -
> - /* one bit per pair of EUs */
> - eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
> - GEN11_EU_DIS_MASK);
> - for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
> - if (eu_en_fuse & BIT(eu))
> - eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
> -
> - gen11_compute_sseu_info(sseu, s_en, dss_en, eu_en);
> -
> - /* TGL only supports slice-level power gating */
> - sseu->has_slice_pg = 1;
> -}
> -
> -static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
> -{
> - struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
> - struct intel_uncore *uncore = &dev_priv->uncore;
> - u8 s_en;
> - u32 ss_en;
> - u8 eu_en;
> -
> - if (IS_ELKHARTLAKE(dev_priv))
> - intel_sseu_set_info(sseu, 1, 4, 8);
> - else
> - intel_sseu_set_info(sseu, 1, 8, 8);
> -
> - s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
> - GEN11_GT_S_ENA_MASK;
> - ss_en = ~intel_uncore_read(uncore, GEN11_GT_SUBSLICE_DISABLE);
> -
> - eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
> - GEN11_EU_DIS_MASK);
> -
> - gen11_compute_sseu_info(sseu, s_en, ss_en, eu_en);
> -
> - /* ICL has no power gating restrictions. */
> - sseu->has_slice_pg = 1;
> - sseu->has_subslice_pg = 1;
> - sseu->has_eu_pg = 1;
> -}
> -
> -static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
> -{
> - struct intel_uncore *uncore = &dev_priv->uncore;
> - struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
> - const u32 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
> - int s, ss;
> - const int eu_mask = 0xff;
> - u32 subslice_mask, eu_en;
> -
> - intel_sseu_set_info(sseu, 6, 4, 8);
> -
> - sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
> - GEN10_F2_S_ENA_SHIFT;
> -
> - /* Slice0 */
> - eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE0);
> - for (ss = 0; ss < sseu->max_subslices; ss++)
> - sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask);
> - /* Slice1 */
> - sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask);
> - eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE1);
> - sseu_set_eus(sseu, 1, 1, eu_en & eu_mask);
> - /* Slice2 */
> - sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask);
> - sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask);
> - /* Slice3 */
> - sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask);
> - eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE2);
> - sseu_set_eus(sseu, 3, 1, eu_en & eu_mask);
> - /* Slice4 */
> - sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask);
> - sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask);
> - /* Slice5 */
> - sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask);
> - eu_en = ~intel_uncore_read(uncore, GEN10_EU_DISABLE3);
> - sseu_set_eus(sseu, 5, 1, eu_en & eu_mask);
> -
> - subslice_mask = (1 << 4) - 1;
> - subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
> - GEN10_F2_SS_DIS_SHIFT);
> -
> - for (s = 0; s < sseu->max_slices; s++) {
> - u32 subslice_mask_with_eus = subslice_mask;
> -
> - for (ss = 0; ss < sseu->max_subslices; ss++) {
> - if (sseu_get_eus(sseu, s, ss) == 0)
> - subslice_mask_with_eus &= ~BIT(ss);
> - }
> -
> - /*
> - * Slice0 can have up to 3 subslices, but there are only 2 in
> - * slice1/2.
> - */
> - intel_sseu_set_subslices(sseu, s, s == 0 ?
> - subslice_mask_with_eus :
> - subslice_mask_with_eus & 0x3);
> - }
> -
> - sseu->eu_total = compute_eu_total(sseu);
> -
> - /*
> - * CNL is expected to always have a uniform distribution
> - * of EU across subslices with the exception that any one
> - * EU in any one subslice may be fused off for die
> - * recovery.
> - */
> - sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ?
> - DIV_ROUND_UP(sseu->eu_total,
> - intel_sseu_subslice_total(sseu)) :
> - 0;
> -
> - /* No restrictions on Power Gating */
> - sseu->has_slice_pg = 1;
> - sseu->has_subslice_pg = 1;
> - sseu->has_eu_pg = 1;
> -}
> -
> -static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
> -{
> - struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
> - u32 fuse;
> - u8 subslice_mask = 0;
> -
> - fuse = intel_uncore_read(&dev_priv->uncore, CHV_FUSE_GT);
> -
> - sseu->slice_mask = BIT(0);
> - intel_sseu_set_info(sseu, 1, 2, 8);
> -
> - if (!(fuse & CHV_FGT_DISABLE_SS0)) {
> - u8 disabled_mask =
> - ((fuse & CHV_FGT_EU_DIS_SS0_R0_MASK) >>
> - CHV_FGT_EU_DIS_SS0_R0_SHIFT) |
> - (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
> - CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
> -
> - subslice_mask |= BIT(0);
> - sseu_set_eus(sseu, 0, 0, ~disabled_mask);
> - }
> -
> - if (!(fuse & CHV_FGT_DISABLE_SS1)) {
> - u8 disabled_mask =
> - ((fuse & CHV_FGT_EU_DIS_SS1_R0_MASK) >>
> - CHV_FGT_EU_DIS_SS1_R0_SHIFT) |
> - (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
> - CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
> -
> - subslice_mask |= BIT(1);
> - sseu_set_eus(sseu, 0, 1, ~disabled_mask);
> - }
> -
> - intel_sseu_set_subslices(sseu, 0, subslice_mask);
> -
> - sseu->eu_total = compute_eu_total(sseu);
> -
> - /*
> - * CHV expected to always have a uniform distribution of EU
> - * across subslices.
> - */
> - sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ?
> - sseu->eu_total /
> - intel_sseu_subslice_total(sseu) :
> - 0;
> - /*
> - * CHV supports subslice power gating on devices with more than
> - * one subslice, and supports EU power gating on devices with
> - * more than one EU pair per subslice.
> - */
> - sseu->has_slice_pg = 0;
> - sseu->has_subslice_pg = intel_sseu_subslice_total(sseu) > 1;
> - sseu->has_eu_pg = (sseu->eu_per_subslice > 2);
> -}
> -
> -static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
> -{
> - struct intel_device_info *info = mkwrite_device_info(dev_priv);
> - struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
> - struct intel_uncore *uncore = &dev_priv->uncore;
> - int s, ss;
> - u32 fuse2, eu_disable, subslice_mask;
> - const u8 eu_mask = 0xff;
> -
> - fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
> - sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
> -
> - /* BXT has a single slice and at most 3 subslices. */
> - intel_sseu_set_info(sseu, IS_GEN9_LP(dev_priv) ? 1 : 3,
> - IS_GEN9_LP(dev_priv) ? 3 : 4, 8);
> -
> - /*
> - * The subslice disable field is global, i.e. it applies
> - * to each of the enabled slices.
> - */
> - subslice_mask = (1 << sseu->max_subslices) - 1;
> - subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >>
> - GEN9_F2_SS_DIS_SHIFT);
> -
> - /*
> - * Iterate through enabled slices and subslices to
> - * count the total enabled EU.
> - */
> - for (s = 0; s < sseu->max_slices; s++) {
> - if (!(sseu->slice_mask & BIT(s)))
> - /* skip disabled slice */
> - continue;
> -
> - intel_sseu_set_subslices(sseu, s, subslice_mask);
> -
> - eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s));
> - for (ss = 0; ss < sseu->max_subslices; ss++) {
> - int eu_per_ss;
> - u8 eu_disabled_mask;
> -
> - if (!intel_sseu_has_subslice(sseu, s, ss))
> - /* skip disabled subslice */
> - continue;
> -
> - eu_disabled_mask = (eu_disable >> (ss * 8)) & eu_mask;
> -
> - sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
> -
> - eu_per_ss = sseu->max_eus_per_subslice -
> - hweight8(eu_disabled_mask);
> -
> - /*
> - * Record which subslice(s) has(have) 7 EUs. we
> - * can tune the hash used to spread work among
> - * subslices if they are unbalanced.
> - */
> - if (eu_per_ss == 7)
> - sseu->subslice_7eu[s] |= BIT(ss);
> - }
> - }
> -
> - sseu->eu_total = compute_eu_total(sseu);
> -
> - /*
> - * SKL is expected to always have a uniform distribution
> - * of EU across subslices with the exception that any one
> - * EU in any one subslice may be fused off for die
> - * recovery. BXT is expected to be perfectly uniform in EU
> - * distribution.
> - */
> - sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ?
> - DIV_ROUND_UP(sseu->eu_total,
> - intel_sseu_subslice_total(sseu)) :
> - 0;
> - /*
> - * SKL+ supports slice power gating on devices with more than
> - * one slice, and supports EU power gating on devices with
> - * more than one EU pair per subslice. BXT+ supports subslice
> - * power gating on devices with more than one subslice, and
> - * supports EU power gating on devices with more than one EU
> - * pair per subslice.
> - */
> - sseu->has_slice_pg =
> - !IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1;
> - sseu->has_subslice_pg =
> - IS_GEN9_LP(dev_priv) && intel_sseu_subslice_total(sseu) > 1;
> - sseu->has_eu_pg = sseu->eu_per_subslice > 2;
> -
> - if (IS_GEN9_LP(dev_priv)) {
> -#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss)))
> - info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3;
> -
> - sseu->min_eu_in_pool = 0;
> - if (info->has_pooled_eu) {
> - if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0))
> - sseu->min_eu_in_pool = 3;
> - else if (IS_SS_DISABLED(1))
> - sseu->min_eu_in_pool = 6;
> - else
> - sseu->min_eu_in_pool = 9;
> - }
> -#undef IS_SS_DISABLED
> - }
> -}
> -
> -static void bdw_sseu_info_init(struct drm_i915_private *dev_priv)
> -{
> - struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
> - struct intel_uncore *uncore = &dev_priv->uncore;
> - int s, ss;
> - u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */
> - u32 eu_disable0, eu_disable1, eu_disable2;
> -
> - fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
> - sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
> - intel_sseu_set_info(sseu, 3, 3, 8);
> -
> - /*
> - * The subslice disable field is global, i.e. it applies
> - * to each of the enabled slices.
> - */
> - subslice_mask = GENMASK(sseu->max_subslices - 1, 0);
> - subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >>
> - GEN8_F2_SS_DIS_SHIFT);
> - eu_disable0 = intel_uncore_read(uncore, GEN8_EU_DISABLE0);
> - eu_disable1 = intel_uncore_read(uncore, GEN8_EU_DISABLE1);
> - eu_disable2 = intel_uncore_read(uncore, GEN8_EU_DISABLE2);
> - eu_disable[0] = eu_disable0 & GEN8_EU_DIS0_S0_MASK;
> - eu_disable[1] = (eu_disable0 >> GEN8_EU_DIS0_S1_SHIFT) |
> - ((eu_disable1 & GEN8_EU_DIS1_S1_MASK) <<
> - (32 - GEN8_EU_DIS0_S1_SHIFT));
> - eu_disable[2] = (eu_disable1 >> GEN8_EU_DIS1_S2_SHIFT) |
> - ((eu_disable2 & GEN8_EU_DIS2_S2_MASK) <<
> - (32 - GEN8_EU_DIS1_S2_SHIFT));
> -
> - /*
> - * Iterate through enabled slices and subslices to
> - * count the total enabled EU.
> - */
> - for (s = 0; s < sseu->max_slices; s++) {
> - if (!(sseu->slice_mask & BIT(s)))
> - /* skip disabled slice */
> - continue;
> -
> - intel_sseu_set_subslices(sseu, s, subslice_mask);
> -
> - for (ss = 0; ss < sseu->max_subslices; ss++) {
> - u8 eu_disabled_mask;
> - u32 n_disabled;
> -
> - if (!intel_sseu_has_subslice(sseu, s, ss))
> - /* skip disabled subslice */
> - continue;
> -
> - eu_disabled_mask =
> - eu_disable[s] >> (ss * sseu->max_eus_per_subslice);
> -
> - sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
> -
> - n_disabled = hweight8(eu_disabled_mask);
> -
> - /*
> - * Record which subslices have 7 EUs.
> - */
> - if (sseu->max_eus_per_subslice - n_disabled == 7)
> - sseu->subslice_7eu[s] |= 1 << ss;
> - }
> - }
> -
> - sseu->eu_total = compute_eu_total(sseu);
> -
> - /*
> - * BDW is expected to always have a uniform distribution of EU across
> - * subslices with the exception that any one EU in any one subslice may
> - * be fused off for die recovery.
> - */
> - sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ?
> - DIV_ROUND_UP(sseu->eu_total,
> - intel_sseu_subslice_total(sseu)) :
> - 0;
> -
> - /*
> - * BDW supports slice power gating on devices with more than
> - * one slice.
> - */
> - sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1;
> - sseu->has_subslice_pg = 0;
> - sseu->has_eu_pg = 0;
> -}
> -
> -static void hsw_sseu_info_init(struct drm_i915_private *dev_priv)
> -{
> - struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
> - u32 fuse1;
> - u8 subslice_mask = 0;
> - int s, ss;
> -
> - /*
> - * There isn't a register to tell us how many slices/subslices. We
> - * work off the PCI-ids here.
> - */
> - switch (INTEL_INFO(dev_priv)->gt) {
> - default:
> - MISSING_CASE(INTEL_INFO(dev_priv)->gt);
> - /* fall through */
> - case 1:
> - sseu->slice_mask = BIT(0);
> - subslice_mask = BIT(0);
> - break;
> - case 2:
> - sseu->slice_mask = BIT(0);
> - subslice_mask = BIT(0) | BIT(1);
> - break;
> - case 3:
> - sseu->slice_mask = BIT(0) | BIT(1);
> - subslice_mask = BIT(0) | BIT(1);
> - break;
> - }
> -
> - fuse1 = intel_uncore_read(&dev_priv->uncore, HSW_PAVP_FUSE1);
> - switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) {
> - default:
> - MISSING_CASE((fuse1 & HSW_F1_EU_DIS_MASK) >>
> - HSW_F1_EU_DIS_SHIFT);
> - /* fall through */
> - case HSW_F1_EU_DIS_10EUS:
> - sseu->eu_per_subslice = 10;
> - break;
> - case HSW_F1_EU_DIS_8EUS:
> - sseu->eu_per_subslice = 8;
> - break;
> - case HSW_F1_EU_DIS_6EUS:
> - sseu->eu_per_subslice = 6;
> - break;
> - }
> -
> - intel_sseu_set_info(sseu, hweight8(sseu->slice_mask),
> - hweight8(subslice_mask),
> - sseu->eu_per_subslice);
> -
> - for (s = 0; s < sseu->max_slices; s++) {
> - intel_sseu_set_subslices(sseu, s, subslice_mask);
> -
> - for (ss = 0; ss < sseu->max_subslices; ss++) {
> - sseu_set_eus(sseu, s, ss,
> - (1UL << sseu->eu_per_subslice) - 1);
> - }
> - }
> -
> - sseu->eu_total = compute_eu_total(sseu);
> -
> - /* No powergating for you. */
> - sseu->has_slice_pg = 0;
> - sseu->has_subslice_pg = 0;
> - sseu->has_eu_pg = 0;
> -}
> -
> static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv)
> {
> u32 ts_override = intel_uncore_read(&dev_priv->uncore,
> @@ -1042,22 +478,6 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> info->display.has_dsc = 0;
> }
>
> - /* Initialize slice/subslice/EU info */
> - if (IS_HASWELL(dev_priv))
> - hsw_sseu_info_init(dev_priv);
> - else if (IS_CHERRYVIEW(dev_priv))
> - cherryview_sseu_info_init(dev_priv);
> - else if (IS_BROADWELL(dev_priv))
> - bdw_sseu_info_init(dev_priv);
> - else if (IS_GEN(dev_priv, 9))
> - gen9_sseu_info_init(dev_priv);
> - else if (IS_GEN(dev_priv, 10))
> - gen10_sseu_info_init(dev_priv);
> - else if (IS_GEN(dev_priv, 11))
> - gen11_sseu_info_init(dev_priv);
> - else if (INTEL_GEN(dev_priv) >= 12)
> - gen12_sseu_info_init(dev_priv);
> -
> if (IS_GEN(dev_priv, 6) && intel_vtd_active()) {
> drm_info(&dev_priv->drm,
> "Disabling ppGTT for VT-d support\n");
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index f03ed95af190..ce2ccee9b49b 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -242,8 +242,6 @@ void intel_device_info_print_static(const struct intel_device_info *info,
> struct drm_printer *p);
> void intel_device_info_print_runtime(const struct intel_runtime_info *info,
> struct drm_printer *p);
> -void intel_device_info_print_topology(const struct sseu_dev_info *sseu,
> - struct drm_printer *p);
>
> void intel_driver_caps_print(const struct intel_driver_caps *caps,
> struct drm_printer *p);
>
I tried to check side by side as much as I could. Occasionaly cut&paste
of wonky formatting strangely re-assured me move was good.
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 7/7] drm/i915/sseu: Move sseu_info under gt_info
2020-06-25 23:42 ` [Intel-gfx] [PATCH 7/7] drm/i915/sseu: Move sseu_info under gt_info Daniele Ceraolo Spurio
@ 2020-06-26 15:22 ` Tvrtko Ursulin
2020-06-26 16:49 ` Daniele Ceraolo Spurio
0 siblings, 1 reply; 26+ messages in thread
From: Tvrtko Ursulin @ 2020-06-26 15:22 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx
On 26/06/2020 00:42, Daniele Ceraolo Spurio wrote:
> From: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
>
> SSEUs are a GT capability, so track them under gt_info.
>
> Signed-off-by: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Andi Shyti <andi.shyti@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 7 ++++---
> drivers/gpu/drm/i915/gem/i915_gem_context.h | 2 +-
> .../drm/i915/gem/selftests/i915_gem_context.c | 5 ++++-
> drivers/gpu/drm/i915/gt/intel_context_sseu.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 ++--
> drivers/gpu/drm/i915/gt/intel_gt.c | 2 ++
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +++
> drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_rps.c | 3 ++-
> drivers/gpu/drm/i915/gt/intel_sseu.c | 19 ++++++++++---------
> drivers/gpu/drm/i915/gt/intel_sseu.h | 2 +-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++----
> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 3 +--
> drivers/gpu/drm/i915/i915_debugfs.c | 10 +++++-----
Add SSEU to debugfs_gt.c / debugfs_sseu.c ?
Regards,
Tvrtko
> drivers/gpu/drm/i915/i915_getparam.c | 2 +-
> drivers/gpu/drm/i915/i915_gpu_error.c | 4 ++--
> drivers/gpu/drm/i915/i915_perf.c | 9 ++++-----
> drivers/gpu/drm/i915/i915_query.c | 2 +-
> drivers/gpu/drm/i915/intel_device_info.c | 3 ---
> drivers/gpu/drm/i915/intel_device_info.h | 3 ---
> 20 files changed, 49 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index 5c13809dc3c8..4fc641d5cb68 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -1399,11 +1399,12 @@ static int get_ringsize(struct i915_gem_context *ctx,
> }
>
> int
> -i915_gem_user_to_context_sseu(struct drm_i915_private *i915,
> +i915_gem_user_to_context_sseu(struct intel_gt *gt,
> const struct drm_i915_gem_context_param_sseu *user,
> struct intel_sseu *context)
> {
> - const struct sseu_dev_info *device = &RUNTIME_INFO(i915)->sseu;
> + const struct sseu_dev_info *device = >->info.sseu;
> + struct drm_i915_private *i915 = gt->i915;
>
> /* No zeros in any field. */
> if (!user->slice_mask || !user->subslice_mask ||
> @@ -1536,7 +1537,7 @@ static int set_sseu(struct i915_gem_context *ctx,
> goto out_ce;
> }
>
> - ret = i915_gem_user_to_context_sseu(i915, &user_sseu, &sseu);
> + ret = i915_gem_user_to_context_sseu(ce->engine->gt, &user_sseu, &sseu);
> if (ret)
> goto out_ce;
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h
> index 3702b2fb27ab..a133f92bbedb 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
> @@ -225,7 +225,7 @@ i915_gem_engines_iter_next(struct i915_gem_engines_iter *it);
> struct i915_lut_handle *i915_lut_handle_alloc(void);
> void i915_lut_handle_free(struct i915_lut_handle *lut);
>
> -int i915_gem_user_to_context_sseu(struct drm_i915_private *i915,
> +int i915_gem_user_to_context_sseu(struct intel_gt *gt,
> const struct drm_i915_gem_context_param_sseu *user,
> struct intel_sseu *context);
>
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> index b81978890641..7ffc3c751432 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> @@ -1229,7 +1229,7 @@ __igt_ctx_sseu(struct drm_i915_private *i915,
> int inst = 0;
> int ret = 0;
>
> - if (INTEL_GEN(i915) < 9 || !RUNTIME_INFO(i915)->sseu.has_slice_pg)
> + if (INTEL_GEN(i915) < 9)
> return 0;
>
> if (flags & TEST_RESET)
> @@ -1255,6 +1255,9 @@ __igt_ctx_sseu(struct drm_i915_private *i915,
> if (hweight32(engine->sseu.slice_mask) < 2)
> continue;
>
> + if (!engine->gt->info.sseu.has_slice_pg)
> + continue;
> +
> /*
> * Gen11 VME friendly power-gated configuration with
> * half enabled sub-slices.
> diff --git a/drivers/gpu/drm/i915/gt/intel_context_sseu.c b/drivers/gpu/drm/i915/gt/intel_context_sseu.c
> index 27ae48049239..b9c8163978a3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_context_sseu.c
> +++ b/drivers/gpu/drm/i915/gt/intel_context_sseu.c
> @@ -30,7 +30,7 @@ static int gen8_emit_rpcs_config(struct i915_request *rq,
> *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> *cs++ = lower_32_bits(offset);
> *cs++ = upper_32_bits(offset);
> - *cs++ = intel_sseu_make_rpcs(rq->engine->i915, &sseu);
> + *cs++ = intel_sseu_make_rpcs(rq->engine->gt, &sseu);
>
> intel_ring_advance(rq, cs);
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 3af58df3b13e..af08fdddd972 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -705,7 +705,7 @@ static int engine_setup_common(struct intel_engine_cs *engine)
>
> /* Use the whole device by default */
> engine->sseu =
> - intel_sseu_from_device_info(&RUNTIME_INFO(engine->i915)->sseu);
> + intel_sseu_from_device_info(&engine->gt->info.sseu);
>
> intel_engine_init_workarounds(engine);
> intel_engine_init_whitelist(engine);
> @@ -1071,7 +1071,7 @@ void intel_engine_get_instdone(const struct intel_engine_cs *engine,
> struct intel_instdone *instdone)
> {
> struct drm_i915_private *i915 = engine->i915;
> - const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
> + const struct sseu_dev_info *sseu = &engine->gt->info.sseu;
> struct intel_uncore *uncore = engine->uncore;
> u32 mmio_base = engine->mmio_base;
> int slice;
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index de95930f8627..b1748fa67eca 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -655,4 +655,6 @@ void intel_gt_info_print(const struct intel_gt_info *info,
> struct drm_printer *p)
> {
> drm_printf(p, "available engines: %x\n", info->engine_mask);
> +
> + intel_sseu_dump(&info->sseu, p);
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index bb7551867c00..6d39a4a11bf3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -116,6 +116,9 @@ struct intel_gt {
>
> /* Media engine access to SFC per instance */
> u8 vdbox_sfc_access;
> +
> + /* Slice/subslice/EU info */
> + struct sseu_dev_info sseu;
> } info;
> };
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index e866b8d721ed..9e28b2f9df72 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -3422,7 +3422,7 @@ __execlists_update_reg_state(const struct intel_context *ce,
> /* RPCS */
> if (engine->class == RENDER_CLASS) {
> regs[CTX_R_PWR_CLK_STATE] =
> - intel_sseu_make_rpcs(engine->i915, &ce->sseu);
> + intel_sseu_make_rpcs(engine->gt, &ce->sseu);
>
> i915_oa_init_reg_state(ce, engine);
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> index 296391deeb94..97ba14ad52e4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -1062,11 +1062,12 @@ static bool gen6_rps_enable(struct intel_rps *rps)
> static int chv_rps_max_freq(struct intel_rps *rps)
> {
> struct drm_i915_private *i915 = rps_to_i915(rps);
> + struct intel_gt *gt = rps_to_gt(rps);
> u32 val;
>
> val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE);
>
> - switch (RUNTIME_INFO(i915)->sseu.eu_total) {
> + switch (gt->info.sseu.eu_total) {
> case 8:
> /* (2 * 4) config */
> val >>= FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT;
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
> index 006f9118b319..e29f0785b3c5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> @@ -130,7 +130,7 @@ static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
>
> static void gen12_sseu_info_init(struct intel_gt *gt)
> {
> - struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
> + struct sseu_dev_info *sseu = >->info.sseu;
> struct intel_uncore *uncore = gt->uncore;
> u8 s_en;
> u32 dss_en;
> @@ -165,7 +165,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
>
> static void gen11_sseu_info_init(struct intel_gt *gt)
> {
> - struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
> + struct sseu_dev_info *sseu = >->info.sseu;
> struct intel_uncore *uncore = gt->uncore;
> u8 s_en;
> u32 ss_en;
> @@ -194,7 +194,7 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
> static void gen10_sseu_info_init(struct intel_gt *gt)
> {
> struct intel_uncore *uncore = gt->uncore;
> - struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
> + struct sseu_dev_info *sseu = >->info.sseu;
> const u32 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
> int s, ss;
> const int eu_mask = 0xff;
> @@ -270,7 +270,7 @@ static void gen10_sseu_info_init(struct intel_gt *gt)
>
> static void cherryview_sseu_info_init(struct intel_gt *gt)
> {
> - struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
> + struct sseu_dev_info *sseu = >->info.sseu;
> u32 fuse;
> u8 subslice_mask = 0;
>
> @@ -327,7 +327,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
> {
> struct drm_i915_private *i915 = gt->i915;
> struct intel_device_info *info = mkwrite_device_info(i915);
> - struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
> + struct sseu_dev_info *sseu = >->info.sseu;
> struct intel_uncore *uncore = gt->uncore;
> int s, ss;
> u32 fuse2, eu_disable, subslice_mask;
> @@ -431,7 +431,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
>
> static void bdw_sseu_info_init(struct intel_gt *gt)
> {
> - struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
> + struct sseu_dev_info *sseu = >->info.sseu;
> struct intel_uncore *uncore = gt->uncore;
> int s, ss;
> u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */
> @@ -517,7 +517,7 @@ static void bdw_sseu_info_init(struct intel_gt *gt)
> static void hsw_sseu_info_init(struct intel_gt *gt)
> {
> struct drm_i915_private *i915 = gt->i915;
> - struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
> + struct sseu_dev_info *sseu = >->info.sseu;
> u32 fuse1;
> u8 subslice_mask = 0;
> int s, ss;
> @@ -602,10 +602,11 @@ void intel_sseu_info_init(struct intel_gt *gt)
> gen12_sseu_info_init(gt);
> }
>
> -u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
> +u32 intel_sseu_make_rpcs(struct intel_gt *gt,
> const struct intel_sseu *req_sseu)
> {
> - const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
> + struct drm_i915_private *i915 = gt->i915;
> + const struct sseu_dev_info *sseu = >->info.sseu;
> bool subslice_pg = sseu->has_subslice_pg;
> u8 slices, subslices;
> u32 rpcs = 0;
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
> index f9c007f001e7..23ba6c2ebe70 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> @@ -98,7 +98,7 @@ void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
>
> void intel_sseu_info_init(struct intel_gt *gt);
>
> -u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
> +u32 intel_sseu_make_rpcs(struct intel_gt *gt,
> const struct intel_sseu *req_sseu);
>
> void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p);
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 2da366821dda..dbafd923e5a1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -404,7 +404,7 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine,
> static void skl_tune_iz_hashing(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> {
> - struct drm_i915_private *i915 = engine->i915;
> + struct intel_gt *gt = engine->gt;
> u8 vals[3] = { 0, 0, 0 };
> unsigned int i;
>
> @@ -415,7 +415,7 @@ static void skl_tune_iz_hashing(struct intel_engine_cs *engine,
> * Only consider slices where one, and only one, subslice has 7
> * EUs
> */
> - if (!is_power_of_2(RUNTIME_INFO(i915)->sseu.subslice_7eu[i]))
> + if (!is_power_of_2(gt->info.sseu.subslice_7eu[i]))
> continue;
>
> /*
> @@ -424,7 +424,7 @@ static void skl_tune_iz_hashing(struct intel_engine_cs *engine,
> *
> * -> 0 <= ss <= 3;
> */
> - ss = ffs(RUNTIME_INFO(i915)->sseu.subslice_7eu[i]) - 1;
> + ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1;
> vals[i] = 3 - ss;
> }
>
> @@ -1036,7 +1036,7 @@ cfl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> static void
> wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
> {
> - const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
> + const struct sseu_dev_info *sseu = &i915->gt.info.sseu;
> unsigned int slice, subslice;
> u32 l3_en, mcr, mcr_mask;
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> index c10ae1660e53..d44061033f23 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> @@ -68,7 +68,6 @@ struct __guc_ads_blob {
> static void __guc_ads_init(struct intel_guc *guc)
> {
> struct intel_gt *gt = guc_to_gt(guc);
> - struct drm_i915_private *dev_priv = gt->i915;
> struct __guc_ads_blob *blob = guc->ads_blob;
> const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;
> u32 base;
> @@ -100,7 +99,7 @@ static void __guc_ads_init(struct intel_guc *guc)
> }
>
> /* System info */
> - blob->system_info.slice_enabled = hweight8(RUNTIME_INFO(dev_priv)->sseu.slice_mask);
> + blob->system_info.slice_enabled = hweight8(gt->info.sseu.slice_mask);
> blob->system_info.rcs_enabled = 1;
> blob->system_info.bcs_enabled = 1;
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index c893a82c2d99..16b012b5673d 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1323,7 +1323,7 @@ static int i915_rcs_topology(struct seq_file *m, void *unused)
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> struct drm_printer p = drm_seq_file_printer(m);
>
> - intel_sseu_print_topology(&RUNTIME_INFO(dev_priv)->sseu, &p);
> + intel_sseu_print_topology(&dev_priv->gt.info.sseu, &p);
>
> return 0;
> }
> @@ -1624,7 +1624,7 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
> struct sseu_dev_info *sseu)
> {
> #define SS_MAX 6
> - const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
> + const struct intel_gt_info *info = &dev_priv->gt.info;
> u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
> int s, ss;
>
> @@ -1681,7 +1681,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
> struct sseu_dev_info *sseu)
> {
> #define SS_MAX 3
> - const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
> + const struct intel_gt_info *info = &dev_priv->gt.info;
> u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
> int s, ss;
>
> @@ -1739,7 +1739,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
> static void bdw_sseu_device_status(struct drm_i915_private *dev_priv,
> struct sseu_dev_info *sseu)
> {
> - const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
> + const struct intel_gt_info *info = &dev_priv->gt.info;
> u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
> int s;
>
> @@ -1802,7 +1802,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
> static int i915_sseu_status(struct seq_file *m, void *unused)
> {
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> - const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
> + const struct intel_gt_info *info = &dev_priv->gt.info;
> struct sseu_dev_info sseu;
> intel_wakeref_t wakeref;
>
> diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
> index 40390b2352b1..421613219ae9 100644
> --- a/drivers/gpu/drm/i915/i915_getparam.c
> +++ b/drivers/gpu/drm/i915/i915_getparam.c
> @@ -12,7 +12,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
> struct drm_file *file_priv)
> {
> struct drm_i915_private *i915 = to_i915(dev);
> - const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
> + const struct sseu_dev_info *sseu = &i915->gt.info.sseu;
> drm_i915_getparam_t *param = data;
> int value;
>
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 99b4a0261b13..678ddec3237f 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -426,7 +426,7 @@ static void err_compression_marker(struct drm_i915_error_state_buf *m)
> static void error_print_instdone(struct drm_i915_error_state_buf *m,
> const struct intel_engine_coredump *ee)
> {
> - const struct sseu_dev_info *sseu = &RUNTIME_INFO(m->i915)->sseu;
> + const struct sseu_dev_info *sseu = &ee->engine->gt->info.sseu;
> int slice;
> int subslice;
>
> @@ -626,8 +626,8 @@ static void err_print_capabilities(struct drm_i915_error_state_buf *m,
>
> intel_device_info_print_static(&error->device_info, &p);
> intel_device_info_print_runtime(&error->runtime_info, &p);
> - intel_sseu_print_topology(&error->runtime_info.sseu, &p);
> intel_gt_info_print(&error->gt->info, &p);
> + intel_sseu_print_topology(&error->gt->info.sseu, &p);
> intel_driver_caps_print(&error->driver_caps, &p);
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 25329b7600c9..37631ce0699b 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -2196,7 +2196,7 @@ static int gen8_configure_context(struct i915_gem_context *ctx,
> if (!intel_context_pin_if_active(ce))
> continue;
>
> - flex->value = intel_sseu_make_rpcs(ctx->i915, &ce->sseu);
> + flex->value = intel_sseu_make_rpcs(ce->engine->gt, &ce->sseu);
> err = gen8_modify_context(ce, flex, count);
>
> intel_context_unpin(ce);
> @@ -2340,7 +2340,7 @@ oa_configure_all_contexts(struct i915_perf_stream *stream,
> if (engine->class != RENDER_CLASS)
> continue;
>
> - regs[0].value = intel_sseu_make_rpcs(i915, &ce->sseu);
> + regs[0].value = intel_sseu_make_rpcs(engine->gt, &ce->sseu);
>
> err = gen8_modify_self(ce, regs, num_regs, active);
> if (err)
> @@ -2740,8 +2740,7 @@ static void
> get_default_sseu_config(struct intel_sseu *out_sseu,
> struct intel_engine_cs *engine)
> {
> - const struct sseu_dev_info *devinfo_sseu =
> - &RUNTIME_INFO(engine->i915)->sseu;
> + const struct sseu_dev_info *devinfo_sseu = &engine->gt->info.sseu;
>
> *out_sseu = intel_sseu_from_device_info(devinfo_sseu);
>
> @@ -2766,7 +2765,7 @@ get_sseu_config(struct intel_sseu *out_sseu,
> drm_sseu->engine.engine_instance != engine->uabi_instance)
> return -EINVAL;
>
> - return i915_gem_user_to_context_sseu(engine->i915, drm_sseu, out_sseu);
> + return i915_gem_user_to_context_sseu(engine->gt, drm_sseu, out_sseu);
> }
>
> /**
> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> index c1ebda9b5627..fed337ad7b68 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -31,7 +31,7 @@ static int copy_query_item(void *query_hdr, size_t query_sz,
> static int query_topology_info(struct drm_i915_private *dev_priv,
> struct drm_i915_query_item *query_item)
> {
> - const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
> + const struct sseu_dev_info *sseu = &dev_priv->gt.info.sseu;
> struct drm_i915_query_topology_info topo;
> u32 slice_length, subslice_length, eu_length, total_length;
> int ret;
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index d8daf224cbd3..3f5dc37d2b7c 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -29,7 +29,6 @@
> #include "display/intel_de.h"
> #include "intel_device_info.h"
> #include "i915_drv.h"
> -#include "gt/intel_sseu.h"
>
> #define PLATFORM_NAME(x) [INTEL_##x] = #x
> static const char * const platform_names[] = {
> @@ -115,8 +114,6 @@ void intel_device_info_print_static(const struct intel_device_info *info,
> void intel_device_info_print_runtime(const struct intel_runtime_info *info,
> struct drm_printer *p)
> {
> - intel_sseu_dump(&info->sseu, p);
> -
> drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq);
> drm_printf(p, "CS timestamp frequency: %u Hz\n",
> info->cs_timestamp_frequency_hz);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index ce2ccee9b49b..f6f897c06cc8 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -219,9 +219,6 @@ struct intel_runtime_info {
> u8 num_sprites[I915_MAX_PIPES];
> u8 num_scalers[I915_MAX_PIPES];
>
> - /* Slice/subslice/EU info */
> - struct sseu_dev_info sseu;
> -
> u32 rawclk_freq;
>
> u32 cs_timestamp_frequency_hz;
>
_______________________________________________
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^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 4/7] drm/i915: Move the engine mask to intel_gt_info
2020-06-26 14:45 ` Tvrtko Ursulin
@ 2020-06-26 16:44 ` Daniele Ceraolo Spurio
2020-06-26 16:50 ` Chris Wilson
0 siblings, 1 reply; 26+ messages in thread
From: Daniele Ceraolo Spurio @ 2020-06-26 16:44 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx
On 6/26/20 7:45 AM, Tvrtko Ursulin wrote:
>
> On 26/06/2020 00:42, Daniele Ceraolo Spurio wrote:
>> Since the engines belong to the GT, move the runtime-updated list of
>> available engines to the intel_gt struct. The original mask has been
>> renamed to indicate it contains the maximum engine list that can be
>> found on a matching device.
>>
>> In preparation for other info being moved to the gt in follow up patches
>> (sseu), introduce an intel_gt_info structure to group all gt-related
>> runtime info.
>>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>> Cc: Andi Shyti <andi.shyti@intel.com>
>> Cc: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
>> ---
>> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 3 +-
>> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 13 +++---
>> drivers/gpu/drm/i915/gt/intel_gt.c | 6 +++
>> drivers/gpu/drm/i915/gt/intel_gt.h | 4 ++
>> drivers/gpu/drm/i915/gt/intel_gt_types.h | 8 ++++
>> drivers/gpu/drm/i915/gt/intel_reset.c | 6 +--
>> .../gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
>> drivers/gpu/drm/i915/gt/selftest_lrc.c | 8 ++--
>> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 2 +-
>> drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
>> drivers/gpu/drm/i915/i915_debugfs.c | 2 +
>> drivers/gpu/drm/i915/i915_drv.c | 1 +
>> drivers/gpu/drm/i915/i915_drv.h | 6 +--
>> drivers/gpu/drm/i915/i915_gpu_error.c | 23 ++++++----
>> drivers/gpu/drm/i915/i915_gpu_error.h | 3 ++
>> drivers/gpu/drm/i915/i915_pci.c | 42 +++++++++----------
>> drivers/gpu/drm/i915/intel_device_info.c | 1 -
>> drivers/gpu/drm/i915/intel_device_info.h | 7 +---
>> drivers/gpu/drm/i915/intel_uncore.c | 2 +-
>> drivers/gpu/drm/i915/selftests/i915_request.c | 2 +-
>> .../gpu/drm/i915/selftests/mock_gem_device.c | 3 +-
>> 21 files changed, 84 insertions(+), 62 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>> index c38ab51e82f0..7ffac711e4b4 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>> @@ -1973,8 +1973,7 @@ static int eb_submit(struct i915_execbuffer *eb,
>> struct i915_vma *batch)
>> static int num_vcs_engines(const struct drm_i915_private *i915)
>> {
>> - return hweight64(INTEL_INFO(i915)->engine_mask &
>> - GENMASK_ULL(VCS0 + I915_MAX_VCS - 1, VCS0));
>> + return hweight64(VDBOX_MASK(&i915->gt));
>> }
>> /*
>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> index 8497106eb3a6..3af58df3b13e 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> @@ -370,7 +370,7 @@ static void __setup_engine_capabilities(struct
>> intel_engine_cs *engine)
>> * instances.
>> */
>> if ((INTEL_GEN(i915) >= 11 &&
>> - RUNTIME_INFO(i915)->vdbox_sfc_access & engine->mask) ||
>> + engine->gt->info.vdbox_sfc_access & engine->mask) ||
>> (INTEL_GEN(i915) >= 9 && engine->instance == 0))
>> engine->uabi_capabilities |=
>> I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
>> @@ -459,7 +459,7 @@ void intel_engines_free(struct intel_gt *gt)
>> static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
>> {
>> struct drm_i915_private *i915 = gt->i915;
>> - struct intel_device_info *info = mkwrite_device_info(i915);
>> + struct intel_gt_info *info = >->info;
>> struct intel_uncore *uncore = gt->uncore;
>> unsigned int logical_vdbox = 0;
>> unsigned int i;
>> @@ -467,6 +467,8 @@ static intel_engine_mask_t init_engine_mask(struct
>> intel_gt *gt)
>> u16 vdbox_mask;
>> u16 vebox_mask;
>> + info->engine_mask = INTEL_INFO(i915)->max_engine_mask;
>> +
>> if (INTEL_GEN(i915) < 11)
>> return info->engine_mask;
>> @@ -494,7 +496,7 @@ static intel_engine_mask_t init_engine_mask(struct
>> intel_gt *gt)
>> * In TGL each VDBOX has access to an SFC.
>> */
>> if (INTEL_GEN(i915) >= 12 || logical_vdbox++ % 2 == 0)
>> - RUNTIME_INFO(i915)->vdbox_sfc_access |= BIT(i);
>> + gt->info.vdbox_sfc_access |= BIT(i);
>> }
>> drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
>> vdbox_mask, VDBOX_MASK(gt));
>> @@ -527,7 +529,6 @@ static intel_engine_mask_t init_engine_mask(struct
>> intel_gt *gt)
>> int intel_engines_init_mmio(struct intel_gt *gt)
>> {
>> struct drm_i915_private *i915 = gt->i915;
>> - struct intel_device_info *device_info = mkwrite_device_info(i915);
>> const unsigned int engine_mask = init_engine_mask(gt);
>> unsigned int mask = 0;
>> unsigned int i;
>> @@ -557,9 +558,9 @@ int intel_engines_init_mmio(struct intel_gt *gt)
>> * engines.
>> */
>> if (drm_WARN_ON(&i915->drm, mask != engine_mask))
>> - device_info->engine_mask = mask;
>> + gt->info.engine_mask = mask;
>> - RUNTIME_INFO(i915)->num_engines = hweight32(mask);
>> + gt->info.num_engines = hweight32(mask);
>> intel_gt_check_and_clear_faults(gt);
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
>> b/drivers/gpu/drm/i915/gt/intel_gt.c
>> index ebc29b6ee86c..d0ae1cb5c7c9 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
>> @@ -642,3 +642,9 @@ void intel_gt_driver_late_release(struct intel_gt
>> *gt)
>> intel_gt_fini_timelines(gt);
>> intel_engines_free(gt);
>> }
>> +
>> +void intel_gt_info_print(const struct intel_gt_info *info,
>> + struct drm_printer *p)
>> +{
>> + drm_printf(p, "available engines: %x\n", info->engine_mask);
>> +}
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
>> b/drivers/gpu/drm/i915/gt/intel_gt.h
>> index 4fac043750aa..15142e2a3b22 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
>> @@ -11,6 +11,7 @@
>> #include "intel_reset.h"
>> struct drm_i915_private;
>> +struct drm_printer;
>> #define GT_TRACE(gt, fmt, ...) do { \
>> const struct intel_gt *gt__ __maybe_unused = (gt); \
>> @@ -68,4 +69,7 @@ static inline bool intel_gt_has_init_error(const
>> struct intel_gt *gt)
>> return test_bit(I915_WEDGED_ON_INIT, >->reset.flags);
>> }
>> +void intel_gt_info_print(const struct intel_gt_info *info,
>> + struct drm_printer *p);
>> +
>> #endif /* __INTEL_GT_H__ */
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
>> b/drivers/gpu/drm/i915/gt/intel_gt_types.h
>> index 0cc1d6b185dc..bb7551867c00 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
>> @@ -109,6 +109,14 @@ struct intel_gt {
>> struct intel_gt_buffer_pool buffer_pool;
>> struct i915_vma *scratch;
>> +
>> + struct intel_gt_info {
>> + intel_engine_mask_t engine_mask;
>> + u8 num_engines;
>> +
>> + /* Media engine access to SFC per instance */
>> + u8 vdbox_sfc_access;
>> + } info;
>> };
>> enum intel_gt_scratch_field {
>> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
>> b/drivers/gpu/drm/i915/gt/intel_reset.c
>> index 0156f1f5c736..952cd6e9b88e 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
>> @@ -342,7 +342,7 @@ static int gen6_reset_engines(struct intel_gt *gt,
>> static int gen11_lock_sfc(struct intel_engine_cs *engine, u32 *hw_mask)
>> {
>> struct intel_uncore *uncore = engine->uncore;
>> - u8 vdbox_sfc_access = RUNTIME_INFO(engine->i915)->vdbox_sfc_access;
>> + u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;
>> i915_reg_t sfc_forced_lock, sfc_forced_lock_ack;
>> u32 sfc_forced_lock_bit, sfc_forced_lock_ack_bit;
>> i915_reg_t sfc_usage;
>> @@ -417,7 +417,7 @@ static int gen11_lock_sfc(struct intel_engine_cs
>> *engine, u32 *hw_mask)
>> static void gen11_unlock_sfc(struct intel_engine_cs *engine)
>> {
>> struct intel_uncore *uncore = engine->uncore;
>> - u8 vdbox_sfc_access = RUNTIME_INFO(engine->i915)->vdbox_sfc_access;
>> + u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;
>> i915_reg_t sfc_forced_lock;
>> u32 sfc_forced_lock_bit;
>> @@ -1246,7 +1246,7 @@ void intel_gt_handle_error(struct intel_gt *gt,
>> */
>> wakeref = intel_runtime_pm_get(gt->uncore->rpm);
>> - engine_mask &= INTEL_INFO(gt->i915)->engine_mask;
>> + engine_mask &= gt->info.engine_mask;
>> if (flags & I915_ERROR_CAPTURE) {
>> i915_capture_error_state(gt->i915);
>> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
>> b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
>> index 68a08486fc87..b09b83deecef 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
>> @@ -649,7 +649,7 @@ static inline int mi_set_context(struct
>> i915_request *rq,
>> struct drm_i915_private *i915 = engine->i915;
>> enum intel_engine_id id;
>> const int num_engines =
>> - IS_HASWELL(i915) ? RUNTIME_INFO(i915)->num_engines - 1 : 0;
>> + IS_HASWELL(i915) ? engine->gt->info.num_engines - 1 : 0;
>> bool force_restore = false;
>> int len;
>> u32 *cs;
>> diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
>> b/drivers/gpu/drm/i915/gt/selftest_lrc.c
>> index daa4aabab9a7..b3678b5f9655 100644
>> --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
>> +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
>> @@ -963,7 +963,7 @@ slice_semaphore_queue(struct intel_engine_cs *outer,
>> goto out;
>> if (i915_request_wait(head, 0,
>> - 2 * RUNTIME_INFO(outer->i915)->num_engines * (count
>> + 2) * (count + 3)) < 0) {
>> + 2 * engine->gt->info.num_engines * (count + 2) *
>> (count + 3)) < 0) {
>> pr_err("Failed to slice along semaphore chain of length (%d,
>> %d)!\n",
>> count, n);
>> GEM_TRACE_DUMP();
>> @@ -3569,8 +3569,7 @@ static int smoke_crescendo(struct preempt_smoke
>> *smoke, unsigned int flags)
>> }
>> pr_info("Submitted %lu crescendo:%x requests across %d engines
>> and %d contexts\n",
>> - count, flags,
>> - RUNTIME_INFO(smoke->gt->i915)->num_engines, smoke->ncontext);
>> + count, flags, smoke->gt->info.num_engines, smoke->ncontext);
>> return 0;
>> }
>> @@ -3597,8 +3596,7 @@ static int smoke_random(struct preempt_smoke
>> *smoke, unsigned int flags)
>> } while (count < smoke->ncontext && !__igt_timeout(end_time,
>> NULL));
>> pr_info("Submitted %lu random:%x requests across %d engines and
>> %d contexts\n",
>> - count, flags,
>> - RUNTIME_INFO(smoke->gt->i915)->num_engines, smoke->ncontext);
>> + count, flags, smoke->gt->info.num_engines, smoke->ncontext);
>> return 0;
>> }
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
>> index fbdd6b0677db..c10ae1660e53 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
>> @@ -106,7 +106,7 @@ static void __guc_ads_init(struct intel_guc *guc)
>> blob->system_info.vdbox_enable_mask = VDBOX_MASK(gt);
>> blob->system_info.vebox_enable_mask = VEBOX_MASK(gt);
>> - blob->system_info.vdbox_sfc_support_mask =
>> RUNTIME_INFO(dev_priv)->vdbox_sfc_access;
>> + blob->system_info.vdbox_sfc_support_mask =
>> gt->info.vdbox_sfc_access;
>> base = intel_guc_ggtt_offset(guc, guc->ads_vma);
>> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c
>> b/drivers/gpu/drm/i915/gvt/handlers.c
>> index ddefc52f6e09..e047a4950f5f 100644
>> --- a/drivers/gpu/drm/i915/gvt/handlers.c
>> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
>> @@ -347,7 +347,7 @@ static int gdrst_mmio_write(struct intel_vgpu
>> *vgpu, unsigned int offset,
>> gvt_dbg_mmio("vgpu%d: request GUC Reset\n", vgpu->id);
>> vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET;
>> }
>> - engine_mask &= INTEL_INFO(vgpu->gvt->gt->i915)->engine_mask;
>> + engine_mask &= vgpu->gvt->gt->info.engine_mask;
>> }
>> /* vgpu_lock already hold by emulate mmio r/w */
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
>> b/drivers/gpu/drm/i915/i915_debugfs.c
>> index 8594a8ef08ce..cad1620d2a7e 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -34,6 +34,7 @@
>> #include "gem/i915_gem_context.h"
>> #include "gt/intel_gt_buffer_pool.h"
>> #include "gt/intel_gt_clock_utils.h"
>> +#include "gt/intel_gt.h"
>> #include "gt/intel_gt_pm.h"
>> #include "gt/intel_gt_requests.h"
>> #include "gt/intel_reset.h"
>> @@ -61,6 +62,7 @@ static int i915_capabilities(struct seq_file *m,
>> void *data)
>> intel_device_info_print_static(INTEL_INFO(i915), &p);
>> intel_device_info_print_runtime(RUNTIME_INFO(i915), &p);
>> + intel_gt_info_print(&i915->gt.info, &p);
>> intel_driver_caps_print(&i915->caps, &p);
>> kernel_param_lock(THIS_MODULE);
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c
>> b/drivers/gpu/drm/i915/i915_drv.c
>> index 611287353420..67789df42be8 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -886,6 +886,7 @@ static void i915_welcome_messages(struct
>> drm_i915_private *dev_priv)
>> intel_device_info_print_static(INTEL_INFO(dev_priv), &p);
>> intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p);
>> + intel_gt_info_print(&dev_priv->gt.info, &p);
>> }
>> if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index 17cad4e2cb9c..fa01bf0929e0 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1254,7 +1254,7 @@ static inline struct drm_i915_private
>> *pdev_to_i915(struct pci_dev *pdev)
>> /* Iterator over subset of engines selected by mask */
>> #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
>> - for ((tmp__) = (mask__) & INTEL_INFO((gt__)->i915)->engine_mask; \
>> + for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
>> (tmp__) ? \
>> ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
>> 0;)
>> @@ -1561,12 +1561,12 @@ IS_SUBPLATFORM(const struct drm_i915_private
>> *i915,
>> #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) &&
>> !IS_LP(dev_priv))
>> #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
>> -#define HAS_ENGINE(gt, id)
>> __HAS_ENGINE(INTEL_INFO((gt)->i915)->engine_mask, id)
>> +#define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
>> #define ENGINE_INSTANCES_MASK(gt, first, count) ({ \
>> unsigned int first__ = (first); \
>> unsigned int count__ = (count); \
>> - (INTEL_INFO((gt)->i915)->engine_mask & \
>> + ((gt)->info.engine_mask & \
>> GENMASK(first__ + count__ - 1, first__)) >> first__; \
>> })
>> #define VDBOX_MASK(gt) \
>> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
>> b/drivers/gpu/drm/i915/i915_gpu_error.c
>> index 866166ada10e..9cb9aa39c33d 100644
>> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
>> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
>> @@ -42,6 +42,7 @@
>> #include "gem/i915_gem_context.h"
>> #include "gem/i915_gem_lmem.h"
>> +#include "gt/intel_gt.h"
>> #include "gt/intel_gt_pm.h"
>> #include "i915_drv.h"
>> @@ -619,16 +620,15 @@ static void print_error_vma(struct
>> drm_i915_error_state_buf *m,
>> }
>> static void err_print_capabilities(struct drm_i915_error_state_buf *m,
>> - const struct intel_device_info *info,
>> - const struct intel_runtime_info *runtime,
>> - const struct intel_driver_caps *caps)
>> + struct i915_gpu_coredump *error)
>> {
>> struct drm_printer p = i915_error_printer(m);
>> - intel_device_info_print_static(info, &p);
>> - intel_device_info_print_runtime(runtime, &p);
>> - intel_device_info_print_topology(&runtime->sseu, &p);
>> - intel_driver_caps_print(caps, &p);
>> + intel_device_info_print_static(&error->device_info, &p);
>> + intel_device_info_print_runtime(&error->runtime_info, &p);
>> + intel_device_info_print_topology(&error->runtime_info.sseu, &p);
>> + intel_gt_info_print(&error->gt->info, &p);
>> + intel_driver_caps_print(&error->driver_caps, &p);
>> }
>> static void err_print_params(struct drm_i915_error_state_buf *m,
>> @@ -798,8 +798,7 @@ static void __err_print_to_sgl(struct
>> drm_i915_error_state_buf *m,
>> if (error->display)
>> intel_display_print_error_state(m, error->display);
>> - err_print_capabilities(m, &error->device_info, &error->runtime_info,
>> - &error->driver_caps);
>> + err_print_capabilities(m, error);
>> err_print_params(m, &error->params);
>> }
>> @@ -1630,6 +1629,11 @@ static void gt_record_regs(struct
>> intel_gt_coredump *gt)
>> gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER);
>> }
>> +static void gt_record_info(struct intel_gt_coredump *gt)
>> +{
>> + memcpy(>->info, >->_gt->info, sizeof(struct intel_gt_info));
>> +}
>> +
>> /*
>> * Generate a semi-unique error code. The code is not meant to have
>> meaning, The
>> * code's only purpose is to try to prevent false duplicated bug
>> reports by
>> @@ -1808,6 +1812,7 @@ struct i915_gpu_coredump
>> *i915_gpu_coredump(struct drm_i915_private *i915)
>> return ERR_PTR(-ENOMEM);
>> }
>> + gt_record_info(error->gt);
>> gt_record_engines(error->gt, compress);
>> if (INTEL_INFO(i915)->has_gt_uc)
>> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h
>> b/drivers/gpu/drm/i915/i915_gpu_error.h
>> index 76b80fbfb7e9..0220b0992808 100644
>> --- a/drivers/gpu/drm/i915/i915_gpu_error.h
>> +++ b/drivers/gpu/drm/i915/i915_gpu_error.h
>> @@ -15,6 +15,7 @@
>> #include <drm/drm_mm.h>
>> #include "gt/intel_engine.h"
>> +#include "gt/intel_gt_types.h"
>> #include "gt/uc/intel_uc_fw.h"
>> #include "intel_device_info.h"
>> @@ -118,6 +119,8 @@ struct intel_gt_coredump {
>> bool awake;
>> bool simulated;
>> + struct intel_gt_info info;
>> +
>> /* Generic register state */
>> u32 eir;
>> u32 pgtbl_er;
>> diff --git a/drivers/gpu/drm/i915/i915_pci.c
>> b/drivers/gpu/drm/i915/i915_pci.c
>> index e5fdf17cd9cd..7658025a791f 100644
>> --- a/drivers/gpu/drm/i915/i915_pci.c
>> +++ b/drivers/gpu/drm/i915/i915_pci.c
>> @@ -168,7 +168,7 @@
>> .gpu_reset_clobbers_display = true, \
>> .hws_needs_physical = 1, \
>> .unfenced_needs_alignment = 1, \
>> - .engine_mask = BIT(RCS0), \
>> + .max_engine_mask = BIT(RCS0), \
>> .has_snoop = true, \
>> .has_coherent_ggtt = false, \
>> .dma_mask_size = 32, \
>> @@ -188,7 +188,7 @@
>> .gpu_reset_clobbers_display = true, \
>> .hws_needs_physical = 1, \
>> .unfenced_needs_alignment = 1, \
>> - .engine_mask = BIT(RCS0), \
>> + .max_engine_mask = BIT(RCS0), \
>> .has_snoop = true, \
>> .has_coherent_ggtt = false, \
>> .dma_mask_size = 32, \
>> @@ -225,7 +225,7 @@ static const struct intel_device_info i865g_info = {
>> .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
>> .display.has_gmch = 1, \
>> .gpu_reset_clobbers_display = true, \
>> - .engine_mask = BIT(RCS0), \
>> + .max_engine_mask = BIT(RCS0), \
>> .has_snoop = true, \
>> .has_coherent_ggtt = true, \
>> .dma_mask_size = 32, \
>> @@ -316,7 +316,7 @@ static const struct intel_device_info pnv_m_info = {
>> .display.has_hotplug = 1, \
>> .display.has_gmch = 1, \
>> .gpu_reset_clobbers_display = true, \
>> - .engine_mask = BIT(RCS0), \
>> + .max_engine_mask = BIT(RCS0), \
>> .has_snoop = true, \
>> .has_coherent_ggtt = true, \
>> .dma_mask_size = 36, \
>> @@ -348,7 +348,7 @@ static const struct intel_device_info i965gm_info = {
>> static const struct intel_device_info g45_info = {
>> GEN4_FEATURES,
>> PLATFORM(INTEL_G45),
>> - .engine_mask = BIT(RCS0) | BIT(VCS0),
>> + .max_engine_mask = BIT(RCS0) | BIT(VCS0),
>> .gpu_reset_clobbers_display = false,
>> };
>> @@ -358,7 +358,7 @@ static const struct intel_device_info gm45_info = {
>> .is_mobile = 1,
>> .display.has_fbc = 1,
>> .display.supports_tv = 1,
>> - .engine_mask = BIT(RCS0) | BIT(VCS0),
>> + .max_engine_mask = BIT(RCS0) | BIT(VCS0),
>> .gpu_reset_clobbers_display = false,
>> };
>> @@ -367,7 +367,7 @@ static const struct intel_device_info gm45_info = {
>> .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
>> .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
>> .display.has_hotplug = 1, \
>> - .engine_mask = BIT(RCS0) | BIT(VCS0), \
>> + .max_engine_mask = BIT(RCS0) | BIT(VCS0), \
>> .has_snoop = true, \
>> .has_coherent_ggtt = true, \
>> /* ilk does support rc6, but we do not implement [power]
>> contexts */ \
>> @@ -397,7 +397,7 @@ static const struct intel_device_info ilk_m_info = {
>> .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
>> .display.has_hotplug = 1, \
>> .display.has_fbc = 1, \
>> - .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
>> + .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
>> .has_coherent_ggtt = true, \
>> .has_llc = 1, \
>> .has_rc6 = 1, \
>> @@ -448,7 +448,7 @@ static const struct intel_device_info
>> snb_m_gt2_info = {
>> .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
>> BIT(TRANSCODER_C), \
>> .display.has_hotplug = 1, \
>> .display.has_fbc = 1, \
>> - .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
>> + .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
>> .has_coherent_ggtt = true, \
>> .has_llc = 1, \
>> .has_rc6 = 1, \
>> @@ -519,7 +519,7 @@ static const struct intel_device_info vlv_info = {
>> .ppgtt_size = 31,
>> .has_snoop = true,
>> .has_coherent_ggtt = false,
>> - .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
>> + .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
>> .display_mmio_offset = VLV_DISPLAY_BASE,
>> I9XX_PIPE_OFFSETS,
>> I9XX_CURSOR_OFFSETS,
>> @@ -530,7 +530,7 @@ static const struct intel_device_info vlv_info = {
>> #define G75_FEATURES \
>> GEN7_FEATURES, \
>> - .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
>> + .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
>> .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
>> BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
>> .display.has_ddi = 1, \
>> @@ -597,7 +597,7 @@ static const struct intel_device_info
>> bdw_rsvd_info = {
>> static const struct intel_device_info bdw_gt3_info = {
>> BDW_PLATFORM,
>> .gt = 3,
>> - .engine_mask =
>> + .max_engine_mask =
>> BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
>> };
>> @@ -608,7 +608,7 @@ static const struct intel_device_info chv_info = {
>> .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
>> BIT(TRANSCODER_C),
>> .display.has_hotplug = 1,
>> .is_lp = 1,
>> - .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
>> + .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
>> .has_64bit_reloc = 1,
>> .has_runtime_pm = 1,
>> .has_rc6 = 1,
>> @@ -661,7 +661,7 @@ static const struct intel_device_info skl_gt2_info
>> = {
>> #define SKL_GT3_PLUS_PLATFORM \
>> SKL_PLATFORM, \
>> - .engine_mask = \
>> + .max_engine_mask = \
>> BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
>> @@ -680,7 +680,7 @@ static const struct intel_device_info skl_gt4_info
>> = {
>> .is_lp = 1, \
>> .num_supported_dbuf_slices = 1, \
>> .display.has_hotplug = 1, \
>> - .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
>> + .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
>> .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
>> .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
>> BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
>> @@ -743,7 +743,7 @@ static const struct intel_device_info kbl_gt2_info
>> = {
>> static const struct intel_device_info kbl_gt3_info = {
>> KBL_PLATFORM,
>> .gt = 3,
>> - .engine_mask =
>> + .max_engine_mask =
>> BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
>> };
>> @@ -764,7 +764,7 @@ static const struct intel_device_info cfl_gt2_info
>> = {
>> static const struct intel_device_info cfl_gt3_info = {
>> CFL_PLATFORM,
>> .gt = 3,
>> - .engine_mask =
>> + .max_engine_mask =
>> BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
>> };
>> @@ -833,7 +833,7 @@ static const struct intel_device_info cnl_info = {
>> static const struct intel_device_info icl_info = {
>> GEN11_FEATURES,
>> PLATFORM(INTEL_ICELAKE),
>> - .engine_mask =
>> + .max_engine_mask =
>> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
>> };
>> @@ -841,7 +841,7 @@ static const struct intel_device_info ehl_info = {
>> GEN11_FEATURES,
>> PLATFORM(INTEL_ELKHARTLAKE),
>> .require_force_probe = 1,
>> - .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
>> + .max_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
>> .ppgtt_size = 36,
>> };
>> @@ -877,7 +877,7 @@ static const struct intel_device_info tgl_info = {
>> GEN12_FEATURES,
>> PLATFORM(INTEL_TIGERLAKE),
>> .display.has_modular_fia = 1,
>> - .engine_mask =
>> + .max_engine_mask =
>> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
>> };
>> @@ -890,7 +890,7 @@ static const struct intel_device_info rkl_info = {
>> BIT(TRANSCODER_C),
>> .require_force_probe = 1,
>> .display.has_psr_hw_tracking = 0,
>> - .engine_mask =
>> + .max_engine_mask =
>> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
>> };
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
>> b/drivers/gpu/drm/i915/intel_device_info.c
>> index 92ebea35c752..a362a66fce11 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -92,7 +92,6 @@ static const char *iommu_name(void)
>> void intel_device_info_print_static(const struct intel_device_info
>> *info,
>> struct drm_printer *p)
>> {
>> - drm_printf(p, "engines: %x\n", info->engine_mask);
>> drm_printf(p, "gen: %d\n", info->gen);
>> drm_printf(p, "gt: %d\n", info->gt);
>> drm_printf(p, "iommu: %s\n", iommu_name());
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
>> b/drivers/gpu/drm/i915/intel_device_info.h
>> index fa60fdc1d75a..f03ed95af190 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.h
>> +++ b/drivers/gpu/drm/i915/intel_device_info.h
>> @@ -157,7 +157,7 @@ struct intel_device_info {
>> u8 gen;
>> u8 gt; /* GT number, 0 if undefined */
>> - intel_engine_mask_t engine_mask; /* Engines supported by the HW */
>> + intel_engine_mask_t max_engine_mask; /* Engines supported by the
>> HW */
>> enum intel_platform platform;
>> @@ -219,8 +219,6 @@ struct intel_runtime_info {
>> u8 num_sprites[I915_MAX_PIPES];
>> u8 num_scalers[I915_MAX_PIPES];
>> - u8 num_engines;
>> -
>> /* Slice/subslice/EU info */
>> struct sseu_dev_info sseu;
>> @@ -228,9 +226,6 @@ struct intel_runtime_info {
>> u32 cs_timestamp_frequency_hz;
>> u32 cs_timestamp_period_ns;
>> -
>> - /* Media engine access to SFC per instance */
>> - u8 vdbox_sfc_access;
>> };
>> struct intel_driver_caps {
>> diff --git a/drivers/gpu/drm/i915/intel_uncore.c
>> b/drivers/gpu/drm/i915/intel_uncore.c
>> index bd4b45191f7b..f5548875836c 100644
>> --- a/drivers/gpu/drm/i915/intel_uncore.c
>> +++ b/drivers/gpu/drm/i915/intel_uncore.c
>> @@ -1530,7 +1530,7 @@ static int intel_uncore_fw_domains_init(struct
>> intel_uncore *uncore)
>> if (INTEL_GEN(i915) >= 11) {
>> /* we'll prune the domains of missing engines later */
>> - intel_engine_mask_t emask = INTEL_INFO(i915)->engine_mask;
>> + intel_engine_mask_t emask = INTEL_INFO(i915)->max_engine_mask;
>> int i;
>> uncore->funcs.force_wake_get = fw_domains_get_with_fallback;
>> diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c
>> b/drivers/gpu/drm/i915/selftests/i915_request.c
>> index 9271aad7f779..57dd6f5122ee 100644
>> --- a/drivers/gpu/drm/i915/selftests/i915_request.c
>> +++ b/drivers/gpu/drm/i915/selftests/i915_request.c
>> @@ -1454,7 +1454,7 @@ static int live_breadcrumbs_smoketest(void *arg)
>> idx++;
>> }
>> pr_info("Completed %lu waits for %lu fences across %d engines
>> and %d cpus\n",
>> - num_waits, num_fences, RUNTIME_INFO(i915)->num_engines, ncpus);
>> + num_waits, num_fences, idx, ncpus);
>> ret = igt_live_test_end(&live) ?: ret;
>> out_contexts:
>> diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
>> b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
>> index 9b105b811f1f..0916efa31889 100644
>> --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
>> +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
>> @@ -190,7 +190,8 @@ struct drm_i915_private *mock_gem_device(void)
>> mock_init_ggtt(i915, &i915->ggtt);
>> i915->gt.vm = i915_vm_get(&i915->ggtt.vm);
>> - mkwrite_device_info(i915)->engine_mask = BIT(0);
>> + mkwrite_device_info(i915)->max_engine_mask = BIT(0);
>> + i915->gt.info.engine_mask = BIT(0);
>> i915->gt.engine[RCS0] = mock_engine(i915, "mock", RCS0);
>> if (!i915->gt.engine[RCS0])
>>
>
> Only thing which looks a bit sub-optimalis the name "max_engine_mask",
> but maybe it is just me, that max and masks do not go well together.
> Only alternative I have for the moment is platform_engine_mask? Or the
> usual double underscore approach. Either way:
>
I wasn't fully convinced of max_engine_mask either, buy I had no better
ideas :)
platform_engine_mask sounds good to me, I'll use that.
Daniele
> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Regards,
>
> Tvrtko
_______________________________________________
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^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 7/7] drm/i915/sseu: Move sseu_info under gt_info
2020-06-26 15:22 ` Tvrtko Ursulin
@ 2020-06-26 16:49 ` Daniele Ceraolo Spurio
0 siblings, 0 replies; 26+ messages in thread
From: Daniele Ceraolo Spurio @ 2020-06-26 16:49 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx
On 6/26/20 8:22 AM, Tvrtko Ursulin wrote:
>
> On 26/06/2020 00:42, Daniele Ceraolo Spurio wrote:
>> From: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
>>
>> SSEUs are a GT capability, so track them under gt_info.
>>
>> Signed-off-by: Venkata Sandeep Dhanalakota
>> <venkata.s.dhanalakota@intel.com>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Cc: Andi Shyti <andi.shyti@intel.com>
>> ---
>> drivers/gpu/drm/i915/gem/i915_gem_context.c | 7 ++++---
>> drivers/gpu/drm/i915/gem/i915_gem_context.h | 2 +-
>> .../drm/i915/gem/selftests/i915_gem_context.c | 5 ++++-
>> drivers/gpu/drm/i915/gt/intel_context_sseu.c | 2 +-
>> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 ++--
>> drivers/gpu/drm/i915/gt/intel_gt.c | 2 ++
>> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +++
>> drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +-
>> drivers/gpu/drm/i915/gt/intel_rps.c | 3 ++-
>> drivers/gpu/drm/i915/gt/intel_sseu.c | 19 ++++++++++---------
>> drivers/gpu/drm/i915/gt/intel_sseu.h | 2 +-
>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++----
>> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 3 +--
>> drivers/gpu/drm/i915/i915_debugfs.c | 10 +++++-----
>
> Add SSEU to debugfs_gt.c / debugfs_sseu.c ?
I'd prefer not to add it in this patch, to keep it focused on the move.
I'll add an extra patch with the debugfs when I send v2 of the series.
Do you think it is worth having an sseu file by itself or better to have
an info/capabilities one printing both the gt_info and the topology?
Daniele
>
> Regards,
>
> Tvrtko
>
>> drivers/gpu/drm/i915/i915_getparam.c | 2 +-
>> drivers/gpu/drm/i915/i915_gpu_error.c | 4 ++--
>> drivers/gpu/drm/i915/i915_perf.c | 9 ++++-----
>> drivers/gpu/drm/i915/i915_query.c | 2 +-
>> drivers/gpu/drm/i915/intel_device_info.c | 3 ---
>> drivers/gpu/drm/i915/intel_device_info.h | 3 ---
>> 20 files changed, 49 insertions(+), 46 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
>> b/drivers/gpu/drm/i915/gem/i915_gem_context.c
>> index 5c13809dc3c8..4fc641d5cb68 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
>> @@ -1399,11 +1399,12 @@ static int get_ringsize(struct
>> i915_gem_context *ctx,
>> }
>> int
>> -i915_gem_user_to_context_sseu(struct drm_i915_private *i915,
>> +i915_gem_user_to_context_sseu(struct intel_gt *gt,
>> const struct drm_i915_gem_context_param_sseu *user,
>> struct intel_sseu *context)
>> {
>> - const struct sseu_dev_info *device = &RUNTIME_INFO(i915)->sseu;
>> + const struct sseu_dev_info *device = >->info.sseu;
>> + struct drm_i915_private *i915 = gt->i915;
>> /* No zeros in any field. */
>> if (!user->slice_mask || !user->subslice_mask ||
>> @@ -1536,7 +1537,7 @@ static int set_sseu(struct i915_gem_context *ctx,
>> goto out_ce;
>> }
>> - ret = i915_gem_user_to_context_sseu(i915, &user_sseu, &sseu);
>> + ret = i915_gem_user_to_context_sseu(ce->engine->gt, &user_sseu,
>> &sseu);
>> if (ret)
>> goto out_ce;
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
>> b/drivers/gpu/drm/i915/gem/i915_gem_context.h
>> index 3702b2fb27ab..a133f92bbedb 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
>> @@ -225,7 +225,7 @@ i915_gem_engines_iter_next(struct
>> i915_gem_engines_iter *it);
>> struct i915_lut_handle *i915_lut_handle_alloc(void);
>> void i915_lut_handle_free(struct i915_lut_handle *lut);
>> -int i915_gem_user_to_context_sseu(struct drm_i915_private *i915,
>> +int i915_gem_user_to_context_sseu(struct intel_gt *gt,
>> const struct drm_i915_gem_context_param_sseu *user,
>> struct intel_sseu *context);
>> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
>> b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
>> index b81978890641..7ffc3c751432 100644
>> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
>> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
>> @@ -1229,7 +1229,7 @@ __igt_ctx_sseu(struct drm_i915_private *i915,
>> int inst = 0;
>> int ret = 0;
>> - if (INTEL_GEN(i915) < 9 || !RUNTIME_INFO(i915)->sseu.has_slice_pg)
>> + if (INTEL_GEN(i915) < 9)
>> return 0;
>> if (flags & TEST_RESET)
>> @@ -1255,6 +1255,9 @@ __igt_ctx_sseu(struct drm_i915_private *i915,
>> if (hweight32(engine->sseu.slice_mask) < 2)
>> continue;
>> + if (!engine->gt->info.sseu.has_slice_pg)
>> + continue;
>> +
>> /*
>> * Gen11 VME friendly power-gated configuration with
>> * half enabled sub-slices.
>> diff --git a/drivers/gpu/drm/i915/gt/intel_context_sseu.c
>> b/drivers/gpu/drm/i915/gt/intel_context_sseu.c
>> index 27ae48049239..b9c8163978a3 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_context_sseu.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_context_sseu.c
>> @@ -30,7 +30,7 @@ static int gen8_emit_rpcs_config(struct i915_request
>> *rq,
>> *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
>> *cs++ = lower_32_bits(offset);
>> *cs++ = upper_32_bits(offset);
>> - *cs++ = intel_sseu_make_rpcs(rq->engine->i915, &sseu);
>> + *cs++ = intel_sseu_make_rpcs(rq->engine->gt, &sseu);
>> intel_ring_advance(rq, cs);
>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> index 3af58df3b13e..af08fdddd972 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> @@ -705,7 +705,7 @@ static int engine_setup_common(struct
>> intel_engine_cs *engine)
>> /* Use the whole device by default */
>> engine->sseu =
>> - intel_sseu_from_device_info(&RUNTIME_INFO(engine->i915)->sseu);
>> + intel_sseu_from_device_info(&engine->gt->info.sseu);
>> intel_engine_init_workarounds(engine);
>> intel_engine_init_whitelist(engine);
>> @@ -1071,7 +1071,7 @@ void intel_engine_get_instdone(const struct
>> intel_engine_cs *engine,
>> struct intel_instdone *instdone)
>> {
>> struct drm_i915_private *i915 = engine->i915;
>> - const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
>> + const struct sseu_dev_info *sseu = &engine->gt->info.sseu;
>> struct intel_uncore *uncore = engine->uncore;
>> u32 mmio_base = engine->mmio_base;
>> int slice;
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
>> b/drivers/gpu/drm/i915/gt/intel_gt.c
>> index de95930f8627..b1748fa67eca 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
>> @@ -655,4 +655,6 @@ void intel_gt_info_print(const struct
>> intel_gt_info *info,
>> struct drm_printer *p)
>> {
>> drm_printf(p, "available engines: %x\n", info->engine_mask);
>> +
>> + intel_sseu_dump(&info->sseu, p);
>> }
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
>> b/drivers/gpu/drm/i915/gt/intel_gt_types.h
>> index bb7551867c00..6d39a4a11bf3 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
>> @@ -116,6 +116,9 @@ struct intel_gt {
>> /* Media engine access to SFC per instance */
>> u8 vdbox_sfc_access;
>> +
>> + /* Slice/subslice/EU info */
>> + struct sseu_dev_info sseu;
>> } info;
>> };
>> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
>> b/drivers/gpu/drm/i915/gt/intel_lrc.c
>> index e866b8d721ed..9e28b2f9df72 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
>> @@ -3422,7 +3422,7 @@ __execlists_update_reg_state(const struct
>> intel_context *ce,
>> /* RPCS */
>> if (engine->class == RENDER_CLASS) {
>> regs[CTX_R_PWR_CLK_STATE] =
>> - intel_sseu_make_rpcs(engine->i915, &ce->sseu);
>> + intel_sseu_make_rpcs(engine->gt, &ce->sseu);
>> i915_oa_init_reg_state(ce, engine);
>> }
>> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
>> b/drivers/gpu/drm/i915/gt/intel_rps.c
>> index 296391deeb94..97ba14ad52e4 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
>> @@ -1062,11 +1062,12 @@ static bool gen6_rps_enable(struct intel_rps
>> *rps)
>> static int chv_rps_max_freq(struct intel_rps *rps)
>> {
>> struct drm_i915_private *i915 = rps_to_i915(rps);
>> + struct intel_gt *gt = rps_to_gt(rps);
>> u32 val;
>> val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE);
>> - switch (RUNTIME_INFO(i915)->sseu.eu_total) {
>> + switch (gt->info.sseu.eu_total) {
>> case 8:
>> /* (2 * 4) config */
>> val >>= FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT;
>> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
>> b/drivers/gpu/drm/i915/gt/intel_sseu.c
>> index 006f9118b319..e29f0785b3c5 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
>> @@ -130,7 +130,7 @@ static void gen11_compute_sseu_info(struct
>> sseu_dev_info *sseu,
>> static void gen12_sseu_info_init(struct intel_gt *gt)
>> {
>> - struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
>> + struct sseu_dev_info *sseu = >->info.sseu;
>> struct intel_uncore *uncore = gt->uncore;
>> u8 s_en;
>> u32 dss_en;
>> @@ -165,7 +165,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
>> static void gen11_sseu_info_init(struct intel_gt *gt)
>> {
>> - struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
>> + struct sseu_dev_info *sseu = >->info.sseu;
>> struct intel_uncore *uncore = gt->uncore;
>> u8 s_en;
>> u32 ss_en;
>> @@ -194,7 +194,7 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
>> static void gen10_sseu_info_init(struct intel_gt *gt)
>> {
>> struct intel_uncore *uncore = gt->uncore;
>> - struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
>> + struct sseu_dev_info *sseu = >->info.sseu;
>> const u32 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
>> int s, ss;
>> const int eu_mask = 0xff;
>> @@ -270,7 +270,7 @@ static void gen10_sseu_info_init(struct intel_gt *gt)
>> static void cherryview_sseu_info_init(struct intel_gt *gt)
>> {
>> - struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
>> + struct sseu_dev_info *sseu = >->info.sseu;
>> u32 fuse;
>> u8 subslice_mask = 0;
>> @@ -327,7 +327,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
>> {
>> struct drm_i915_private *i915 = gt->i915;
>> struct intel_device_info *info = mkwrite_device_info(i915);
>> - struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
>> + struct sseu_dev_info *sseu = >->info.sseu;
>> struct intel_uncore *uncore = gt->uncore;
>> int s, ss;
>> u32 fuse2, eu_disable, subslice_mask;
>> @@ -431,7 +431,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
>> static void bdw_sseu_info_init(struct intel_gt *gt)
>> {
>> - struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
>> + struct sseu_dev_info *sseu = >->info.sseu;
>> struct intel_uncore *uncore = gt->uncore;
>> int s, ss;
>> u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */
>> @@ -517,7 +517,7 @@ static void bdw_sseu_info_init(struct intel_gt *gt)
>> static void hsw_sseu_info_init(struct intel_gt *gt)
>> {
>> struct drm_i915_private *i915 = gt->i915;
>> - struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
>> + struct sseu_dev_info *sseu = >->info.sseu;
>> u32 fuse1;
>> u8 subslice_mask = 0;
>> int s, ss;
>> @@ -602,10 +602,11 @@ void intel_sseu_info_init(struct intel_gt *gt)
>> gen12_sseu_info_init(gt);
>> }
>> -u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
>> +u32 intel_sseu_make_rpcs(struct intel_gt *gt,
>> const struct intel_sseu *req_sseu)
>> {
>> - const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
>> + struct drm_i915_private *i915 = gt->i915;
>> + const struct sseu_dev_info *sseu = >->info.sseu;
>> bool subslice_pg = sseu->has_subslice_pg;
>> u8 slices, subslices;
>> u32 rpcs = 0;
>> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
>> b/drivers/gpu/drm/i915/gt/intel_sseu.h
>> index f9c007f001e7..23ba6c2ebe70 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
>> @@ -98,7 +98,7 @@ void intel_sseu_set_subslices(struct sseu_dev_info
>> *sseu, int slice,
>> void intel_sseu_info_init(struct intel_gt *gt);
>> -u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
>> +u32 intel_sseu_make_rpcs(struct intel_gt *gt,
>> const struct intel_sseu *req_sseu);
>> void intel_sseu_dump(const struct sseu_dev_info *sseu, struct
>> drm_printer *p);
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index 2da366821dda..dbafd923e5a1 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -404,7 +404,7 @@ static void gen9_ctx_workarounds_init(struct
>> intel_engine_cs *engine,
>> static void skl_tune_iz_hashing(struct intel_engine_cs *engine,
>> struct i915_wa_list *wal)
>> {
>> - struct drm_i915_private *i915 = engine->i915;
>> + struct intel_gt *gt = engine->gt;
>> u8 vals[3] = { 0, 0, 0 };
>> unsigned int i;
>> @@ -415,7 +415,7 @@ static void skl_tune_iz_hashing(struct
>> intel_engine_cs *engine,
>> * Only consider slices where one, and only one, subslice has 7
>> * EUs
>> */
>> - if (!is_power_of_2(RUNTIME_INFO(i915)->sseu.subslice_7eu[i]))
>> + if (!is_power_of_2(gt->info.sseu.subslice_7eu[i]))
>> continue;
>> /*
>> @@ -424,7 +424,7 @@ static void skl_tune_iz_hashing(struct
>> intel_engine_cs *engine,
>> *
>> * -> 0 <= ss <= 3;
>> */
>> - ss = ffs(RUNTIME_INFO(i915)->sseu.subslice_7eu[i]) - 1;
>> + ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1;
>> vals[i] = 3 - ss;
>> }
>> @@ -1036,7 +1036,7 @@ cfl_gt_workarounds_init(struct drm_i915_private
>> *i915, struct i915_wa_list *wal)
>> static void
>> wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
>> {
>> - const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
>> + const struct sseu_dev_info *sseu = &i915->gt.info.sseu;
>> unsigned int slice, subslice;
>> u32 l3_en, mcr, mcr_mask;
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
>> index c10ae1660e53..d44061033f23 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
>> @@ -68,7 +68,6 @@ struct __guc_ads_blob {
>> static void __guc_ads_init(struct intel_guc *guc)
>> {
>> struct intel_gt *gt = guc_to_gt(guc);
>> - struct drm_i915_private *dev_priv = gt->i915;
>> struct __guc_ads_blob *blob = guc->ads_blob;
>> const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE +
>> LR_HW_CONTEXT_SIZE;
>> u32 base;
>> @@ -100,7 +99,7 @@ static void __guc_ads_init(struct intel_guc *guc)
>> }
>> /* System info */
>> - blob->system_info.slice_enabled =
>> hweight8(RUNTIME_INFO(dev_priv)->sseu.slice_mask);
>> + blob->system_info.slice_enabled =
>> hweight8(gt->info.sseu.slice_mask);
>> blob->system_info.rcs_enabled = 1;
>> blob->system_info.bcs_enabled = 1;
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
>> b/drivers/gpu/drm/i915/i915_debugfs.c
>> index c893a82c2d99..16b012b5673d 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -1323,7 +1323,7 @@ static int i915_rcs_topology(struct seq_file *m,
>> void *unused)
>> struct drm_i915_private *dev_priv = node_to_i915(m->private);
>> struct drm_printer p = drm_seq_file_printer(m);
>> - intel_sseu_print_topology(&RUNTIME_INFO(dev_priv)->sseu, &p);
>> + intel_sseu_print_topology(&dev_priv->gt.info.sseu, &p);
>> return 0;
>> }
>> @@ -1624,7 +1624,7 @@ static void gen10_sseu_device_status(struct
>> drm_i915_private *dev_priv,
>> struct sseu_dev_info *sseu)
>> {
>> #define SS_MAX 6
>> - const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
>> + const struct intel_gt_info *info = &dev_priv->gt.info;
>> u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
>> int s, ss;
>> @@ -1681,7 +1681,7 @@ static void gen9_sseu_device_status(struct
>> drm_i915_private *dev_priv,
>> struct sseu_dev_info *sseu)
>> {
>> #define SS_MAX 3
>> - const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
>> + const struct intel_gt_info *info = &dev_priv->gt.info;
>> u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
>> int s, ss;
>> @@ -1739,7 +1739,7 @@ static void gen9_sseu_device_status(struct
>> drm_i915_private *dev_priv,
>> static void bdw_sseu_device_status(struct drm_i915_private *dev_priv,
>> struct sseu_dev_info *sseu)
>> {
>> - const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
>> + const struct intel_gt_info *info = &dev_priv->gt.info;
>> u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
>> int s;
>> @@ -1802,7 +1802,7 @@ static void i915_print_sseu_info(struct seq_file
>> *m, bool is_available_info,
>> static int i915_sseu_status(struct seq_file *m, void *unused)
>> {
>> struct drm_i915_private *dev_priv = node_to_i915(m->private);
>> - const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
>> + const struct intel_gt_info *info = &dev_priv->gt.info;
>> struct sseu_dev_info sseu;
>> intel_wakeref_t wakeref;
>> diff --git a/drivers/gpu/drm/i915/i915_getparam.c
>> b/drivers/gpu/drm/i915/i915_getparam.c
>> index 40390b2352b1..421613219ae9 100644
>> --- a/drivers/gpu/drm/i915/i915_getparam.c
>> +++ b/drivers/gpu/drm/i915/i915_getparam.c
>> @@ -12,7 +12,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void
>> *data,
>> struct drm_file *file_priv)
>> {
>> struct drm_i915_private *i915 = to_i915(dev);
>> - const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
>> + const struct sseu_dev_info *sseu = &i915->gt.info.sseu;
>> drm_i915_getparam_t *param = data;
>> int value;
>> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
>> b/drivers/gpu/drm/i915/i915_gpu_error.c
>> index 99b4a0261b13..678ddec3237f 100644
>> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
>> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
>> @@ -426,7 +426,7 @@ static void err_compression_marker(struct
>> drm_i915_error_state_buf *m)
>> static void error_print_instdone(struct drm_i915_error_state_buf *m,
>> const struct intel_engine_coredump *ee)
>> {
>> - const struct sseu_dev_info *sseu = &RUNTIME_INFO(m->i915)->sseu;
>> + const struct sseu_dev_info *sseu = &ee->engine->gt->info.sseu;
>> int slice;
>> int subslice;
>> @@ -626,8 +626,8 @@ static void err_print_capabilities(struct
>> drm_i915_error_state_buf *m,
>> intel_device_info_print_static(&error->device_info, &p);
>> intel_device_info_print_runtime(&error->runtime_info, &p);
>> - intel_sseu_print_topology(&error->runtime_info.sseu, &p);
>> intel_gt_info_print(&error->gt->info, &p);
>> + intel_sseu_print_topology(&error->gt->info.sseu, &p);
>> intel_driver_caps_print(&error->driver_caps, &p);
>> }
>> diff --git a/drivers/gpu/drm/i915/i915_perf.c
>> b/drivers/gpu/drm/i915/i915_perf.c
>> index 25329b7600c9..37631ce0699b 100644
>> --- a/drivers/gpu/drm/i915/i915_perf.c
>> +++ b/drivers/gpu/drm/i915/i915_perf.c
>> @@ -2196,7 +2196,7 @@ static int gen8_configure_context(struct
>> i915_gem_context *ctx,
>> if (!intel_context_pin_if_active(ce))
>> continue;
>> - flex->value = intel_sseu_make_rpcs(ctx->i915, &ce->sseu);
>> + flex->value = intel_sseu_make_rpcs(ce->engine->gt, &ce->sseu);
>> err = gen8_modify_context(ce, flex, count);
>> intel_context_unpin(ce);
>> @@ -2340,7 +2340,7 @@ oa_configure_all_contexts(struct
>> i915_perf_stream *stream,
>> if (engine->class != RENDER_CLASS)
>> continue;
>> - regs[0].value = intel_sseu_make_rpcs(i915, &ce->sseu);
>> + regs[0].value = intel_sseu_make_rpcs(engine->gt, &ce->sseu);
>> err = gen8_modify_self(ce, regs, num_regs, active);
>> if (err)
>> @@ -2740,8 +2740,7 @@ static void
>> get_default_sseu_config(struct intel_sseu *out_sseu,
>> struct intel_engine_cs *engine)
>> {
>> - const struct sseu_dev_info *devinfo_sseu =
>> - &RUNTIME_INFO(engine->i915)->sseu;
>> + const struct sseu_dev_info *devinfo_sseu = &engine->gt->info.sseu;
>> *out_sseu = intel_sseu_from_device_info(devinfo_sseu);
>> @@ -2766,7 +2765,7 @@ get_sseu_config(struct intel_sseu *out_sseu,
>> drm_sseu->engine.engine_instance != engine->uabi_instance)
>> return -EINVAL;
>> - return i915_gem_user_to_context_sseu(engine->i915, drm_sseu,
>> out_sseu);
>> + return i915_gem_user_to_context_sseu(engine->gt, drm_sseu,
>> out_sseu);
>> }
>> /**
>> diff --git a/drivers/gpu/drm/i915/i915_query.c
>> b/drivers/gpu/drm/i915/i915_query.c
>> index c1ebda9b5627..fed337ad7b68 100644
>> --- a/drivers/gpu/drm/i915/i915_query.c
>> +++ b/drivers/gpu/drm/i915/i915_query.c
>> @@ -31,7 +31,7 @@ static int copy_query_item(void *query_hdr, size_t
>> query_sz,
>> static int query_topology_info(struct drm_i915_private *dev_priv,
>> struct drm_i915_query_item *query_item)
>> {
>> - const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
>> + const struct sseu_dev_info *sseu = &dev_priv->gt.info.sseu;
>> struct drm_i915_query_topology_info topo;
>> u32 slice_length, subslice_length, eu_length, total_length;
>> int ret;
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
>> b/drivers/gpu/drm/i915/intel_device_info.c
>> index d8daf224cbd3..3f5dc37d2b7c 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -29,7 +29,6 @@
>> #include "display/intel_de.h"
>> #include "intel_device_info.h"
>> #include "i915_drv.h"
>> -#include "gt/intel_sseu.h"
>> #define PLATFORM_NAME(x) [INTEL_##x] = #x
>> static const char * const platform_names[] = {
>> @@ -115,8 +114,6 @@ void intel_device_info_print_static(const struct
>> intel_device_info *info,
>> void intel_device_info_print_runtime(const struct intel_runtime_info
>> *info,
>> struct drm_printer *p)
>> {
>> - intel_sseu_dump(&info->sseu, p);
>> -
>> drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq);
>> drm_printf(p, "CS timestamp frequency: %u Hz\n",
>> info->cs_timestamp_frequency_hz);
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
>> b/drivers/gpu/drm/i915/intel_device_info.h
>> index ce2ccee9b49b..f6f897c06cc8 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.h
>> +++ b/drivers/gpu/drm/i915/intel_device_info.h
>> @@ -219,9 +219,6 @@ struct intel_runtime_info {
>> u8 num_sprites[I915_MAX_PIPES];
>> u8 num_scalers[I915_MAX_PIPES];
>> - /* Slice/subslice/EU info */
>> - struct sseu_dev_info sseu;
>> -
>> u32 rawclk_freq;
>> u32 cs_timestamp_frequency_hz;
>>
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 4/7] drm/i915: Move the engine mask to intel_gt_info
2020-06-26 16:44 ` Daniele Ceraolo Spurio
@ 2020-06-26 16:50 ` Chris Wilson
0 siblings, 0 replies; 26+ messages in thread
From: Chris Wilson @ 2020-06-26 16:50 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, Tvrtko Ursulin, intel-gfx
Quoting Daniele Ceraolo Spurio (2020-06-26 17:44:20)
>
>
> On 6/26/20 7:45 AM, Tvrtko Ursulin wrote:
> >
> > Only thing which looks a bit sub-optimalis the name "max_engine_mask",
> > but maybe it is just me, that max and masks do not go well together.
> > Only alternative I have for the moment is platform_engine_mask? Or the
> > usual double underscore approach. Either way:
> >
>
> I wasn't fully convinced of max_engine_mask either, buy I had no better
> ideas :)
>
> platform_engine_mask sounds good to me, I'll use that.
all_engine_mask
full_engine_mask
possible_engine_mask
platform_engine_mask
+1 for platform_engine_mask
-Chris
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 2/7] drm/i915: Use the gt in HAS_ENGINE
2020-06-26 14:35 ` Chris Wilson
@ 2020-06-26 17:45 ` Daniele Ceraolo Spurio
2020-06-26 18:03 ` Chris Wilson
0 siblings, 1 reply; 26+ messages in thread
From: Daniele Ceraolo Spurio @ 2020-06-26 17:45 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 6/26/20 7:35 AM, Chris Wilson wrote:
> Quoting Daniele Ceraolo Spurio (2020-06-26 00:42:07)
>> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
>> index 26cae4846c82..ddefc52f6e09 100644
>> --- a/drivers/gpu/drm/i915/gvt/handlers.c
>> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
>> @@ -1867,7 +1867,7 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
>> MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
>> MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
>> MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
>> - if (HAS_ENGINE(dev_priv, VCS1)) \
>> + if (HAS_ENGINE(&dev_priv->gt, VCS1)) \
>
> Implicit param! It can switch to gvt->gt for all callsites, killing the
> dev_priv locals.
I've switched this to gvt->gt, but unfortunately the locals will have to
stay because some of the display register definitions still use dev_priv
implicitly to access the display mmio base and the
pipe_offsets/trans_offsets arrays.
Daniele
> -Chris
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 2/7] drm/i915: Use the gt in HAS_ENGINE
2020-06-26 17:45 ` Daniele Ceraolo Spurio
@ 2020-06-26 18:03 ` Chris Wilson
0 siblings, 0 replies; 26+ messages in thread
From: Chris Wilson @ 2020-06-26 18:03 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx
Quoting Daniele Ceraolo Spurio (2020-06-26 18:45:56)
>
>
> On 6/26/20 7:35 AM, Chris Wilson wrote:
> > Quoting Daniele Ceraolo Spurio (2020-06-26 00:42:07)
> >> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> >> index 26cae4846c82..ddefc52f6e09 100644
> >> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> >> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> >> @@ -1867,7 +1867,7 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
> >> MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
> >> MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
> >> MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
> >> - if (HAS_ENGINE(dev_priv, VCS1)) \
> >> + if (HAS_ENGINE(&dev_priv->gt, VCS1)) \
> >
> > Implicit param! It can switch to gvt->gt for all callsites, killing the
> > dev_priv locals.
>
> I've switched this to gvt->gt, but unfortunately the locals will have to
> stay because some of the display register definitions still use dev_priv
> implicitly to access the display mmio base and the
> pipe_offsets/trans_offsets arrays.
Curses. Maybe one day.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Move some device capabilities under intel_gt
2020-06-25 23:42 [Intel-gfx] [PATCH 0/7] Move some device capabilities under intel_gt Daniele Ceraolo Spurio
` (6 preceding siblings ...)
2020-06-25 23:42 ` [Intel-gfx] [PATCH 7/7] drm/i915/sseu: Move sseu_info under gt_info Daniele Ceraolo Spurio
@ 2020-06-27 8:13 ` Patchwork
2020-06-27 8:38 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
8 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2020-06-27 8:13 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: Move some device capabilities under intel_gt
URL : https://patchwork.freedesktop.org/series/78829/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
999ecfc5fc75 drm/i915: Convert device_info to uncore/de_read
cb6b1a857f72 drm/i915: Use the gt in HAS_ENGINE
72189c790177 drm/i915: Move engine-related mmio init to engines_init_mmio
f77f0e80766d drm/i915: Move the engine mask to intel_gt_info
09b520c7dacc drm/i915: Introduce gt_init_mmio
5ba87fdd277d drm/i915/sseu: Move sseu detection and dump to intel_sseu
-:285: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the * on each line
#285: FILE: drivers/gpu/drm/i915/gt/intel_sseu.c:311:
+ * across subslices.
+ */
-:294: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the * on each line
#294: FILE: drivers/gpu/drm/i915/gt/intel_sseu.c:320:
+ * more than one EU pair per subslice.
+ */
-:320: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the * on each line
#320: FILE: drivers/gpu/drm/i915/gt/intel_sseu.c:346:
+ * to each of the enabled slices.
+ */
-:328: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the * on each line
#328: FILE: drivers/gpu/drm/i915/gt/intel_sseu.c:354:
+ * count the total enabled EU.
+ */
-:370: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the * on each line
#370: FILE: drivers/gpu/drm/i915/gt/intel_sseu.c:396:
+ * distribution.
+ */
-:382: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the * on each line
#382: FILE: drivers/gpu/drm/i915/gt/intel_sseu.c:408:
+ * pair per subslice.
+ */
-:506: WARNING:PREFER_FALLTHROUGH: Prefer 'fallthrough;' over fallthrough comment
#506: FILE: drivers/gpu/drm/i915/gt/intel_sseu.c:532:
+ /* fall through */
-:526: WARNING:PREFER_FALLTHROUGH: Prefer 'fallthrough;' over fallthrough comment
#526: FILE: drivers/gpu/drm/i915/gt/intel_sseu.c:552:
+ /* fall through */
total: 0 errors, 8 warnings, 0 checks, 1259 lines checked
f739bfbef07e drm/i915/sseu: Move sseu_info under gt_info
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for Move some device capabilities under intel_gt
2020-06-25 23:42 [Intel-gfx] [PATCH 0/7] Move some device capabilities under intel_gt Daniele Ceraolo Spurio
` (7 preceding siblings ...)
2020-06-27 8:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Move some device capabilities under intel_gt Patchwork
@ 2020-06-27 8:38 ` Patchwork
8 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2020-06-27 8:38 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: Move some device capabilities under intel_gt
URL : https://patchwork.freedesktop.org/series/78829/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8668 -> Patchwork_18029
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18029 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18029, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18029:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@execlists:
- fi-cfl-8109u: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-cfl-8109u/igt@i915_selftest@live@execlists.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-cfl-8109u/igt@i915_selftest@live@execlists.html
- fi-apl-guc: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-apl-guc/igt@i915_selftest@live@execlists.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-apl-guc/igt@i915_selftest@live@execlists.html
- fi-icl-u2: [PASS][5] -> [INCOMPLETE][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-icl-u2/igt@i915_selftest@live@execlists.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-icl-u2/igt@i915_selftest@live@execlists.html
- fi-skl-6600u: [PASS][7] -> [INCOMPLETE][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-skl-6600u/igt@i915_selftest@live@execlists.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-skl-6600u/igt@i915_selftest@live@execlists.html
- fi-cfl-8700k: [PASS][9] -> [INCOMPLETE][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-cfl-8700k/igt@i915_selftest@live@execlists.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-cfl-8700k/igt@i915_selftest@live@execlists.html
- fi-tgl-u2: [PASS][11] -> [INCOMPLETE][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-tgl-u2/igt@i915_selftest@live@execlists.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-tgl-u2/igt@i915_selftest@live@execlists.html
- fi-cml-s: [PASS][13] -> [INCOMPLETE][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-cml-s/igt@i915_selftest@live@execlists.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-cml-s/igt@i915_selftest@live@execlists.html
- fi-skl-guc: [PASS][15] -> [INCOMPLETE][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-skl-guc/igt@i915_selftest@live@execlists.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-skl-guc/igt@i915_selftest@live@execlists.html
- fi-cfl-guc: [PASS][17] -> [INCOMPLETE][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-cfl-guc/igt@i915_selftest@live@execlists.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-cfl-guc/igt@i915_selftest@live@execlists.html
- fi-icl-y: [PASS][19] -> [INCOMPLETE][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-icl-y/igt@i915_selftest@live@execlists.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-icl-y/igt@i915_selftest@live@execlists.html
- fi-bxt-dsi: [PASS][21] -> [INCOMPLETE][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-bxt-dsi/igt@i915_selftest@live@execlists.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-bxt-dsi/igt@i915_selftest@live@execlists.html
- fi-whl-u: [PASS][23] -> [INCOMPLETE][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-whl-u/igt@i915_selftest@live@execlists.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-whl-u/igt@i915_selftest@live@execlists.html
- fi-cml-u2: [PASS][25] -> [INCOMPLETE][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-cml-u2/igt@i915_selftest@live@execlists.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-cml-u2/igt@i915_selftest@live@execlists.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@execlists:
- {fi-ehl-1}: [PASS][27] -> [INCOMPLETE][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-ehl-1/igt@i915_selftest@live@execlists.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-ehl-1/igt@i915_selftest@live@execlists.html
- {fi-tgl-dsi}: [PASS][29] -> [INCOMPLETE][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-tgl-dsi/igt@i915_selftest@live@execlists.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-tgl-dsi/igt@i915_selftest@live@execlists.html
Known issues
------------
Here are the changes found in Patchwork_18029 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@reload:
- fi-byt-j1900: [PASS][31] -> [DMESG-WARN][32] ([i915#1982])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-byt-j1900/igt@i915_module_load@reload.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-byt-j1900/igt@i915_module_load@reload.html
* igt@i915_pm_rpm@module-reload:
- fi-kbl-guc: [PASS][33] -> [SKIP][34] ([fdo#109271])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@execlists:
- fi-glk-dsi: [PASS][35] -> [INCOMPLETE][36] ([i915#58] / [k.org#198133])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-glk-dsi/igt@i915_selftest@live@execlists.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-glk-dsi/igt@i915_selftest@live@execlists.html
- fi-kbl-x1275: [PASS][37] -> [INCOMPLETE][38] ([i915#794])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-kbl-x1275/igt@i915_selftest@live@execlists.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-kbl-x1275/igt@i915_selftest@live@execlists.html
- fi-kbl-soraka: [PASS][39] -> [INCOMPLETE][40] ([i915#794])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-kbl-soraka/igt@i915_selftest@live@execlists.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-kbl-soraka/igt@i915_selftest@live@execlists.html
- fi-kbl-guc: [PASS][41] -> [INCOMPLETE][42] ([i915#794])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-kbl-guc/igt@i915_selftest@live@execlists.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-kbl-guc/igt@i915_selftest@live@execlists.html
- fi-kbl-8809g: [PASS][43] -> [INCOMPLETE][44] ([i915#794])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-kbl-8809g/igt@i915_selftest@live@execlists.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-kbl-8809g/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@gt_lrc:
- fi-bsw-n3050: [PASS][45] -> [INCOMPLETE][46] ([i915#1436])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html
* igt@kms_busy@basic@flip:
- fi-kbl-x1275: [PASS][47] -> [DMESG-WARN][48] ([i915#62] / [i915#92] / [i915#95])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-kbl-x1275/igt@kms_busy@basic@flip.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-kbl-x1275/igt@kms_busy@basic@flip.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-bsw-kefka: [PASS][49] -> [DMESG-WARN][50] ([i915#1982])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
#### Possible fixes ####
* igt@debugfs_test@read_all_entries:
- fi-bsw-nick: [INCOMPLETE][51] ([i915#1250] / [i915#1436]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-bsw-nick/igt@debugfs_test@read_all_entries.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-bsw-nick/igt@debugfs_test@read_all_entries.html
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-u2: [FAIL][53] ([i915#1888]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html
* igt@i915_module_load@reload:
- fi-bxt-dsi: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-bxt-dsi/igt@i915_module_load@reload.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-bxt-dsi/igt@i915_module_load@reload.html
* igt@i915_pm_backlight@basic-brightness:
- fi-whl-u: [DMESG-WARN][57] ([i915#95]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-whl-u/igt@i915_pm_backlight@basic-brightness.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-whl-u/igt@i915_pm_backlight@basic-brightness.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-bsw-n3050: [DMESG-WARN][59] ([i915#1982]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- {fi-kbl-7560u}: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
#### Warnings ####
* igt@debugfs_test@read_all_entries:
- fi-kbl-x1275: [DMESG-WARN][63] ([i915#62] / [i915#92]) -> [DMESG-WARN][64] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-kbl-x1275/igt@debugfs_test@read_all_entries.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-kbl-x1275/igt@debugfs_test@read_all_entries.html
* igt@kms_force_connector_basic@force-edid:
- fi-kbl-x1275: [DMESG-WARN][65] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][66] ([i915#62] / [i915#92]) +6 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1250]: https://gitlab.freedesktop.org/drm/intel/issues/1250
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#794]: https://gitlab.freedesktop.org/drm/intel/issues/794
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (45 -> 38)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_8668 -> Patchwork_18029
CI-20190529: 20190529
CI_DRM_8668: ebcb5923cc316fea9d46629cce83960511da889e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18029: f739bfbef07e9f83a169c892888fc16de307f0db @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f739bfbef07e drm/i915/sseu: Move sseu_info under gt_info
5ba87fdd277d drm/i915/sseu: Move sseu detection and dump to intel_sseu
09b520c7dacc drm/i915: Introduce gt_init_mmio
f77f0e80766d drm/i915: Move the engine mask to intel_gt_info
72189c790177 drm/i915: Move engine-related mmio init to engines_init_mmio
cb6b1a857f72 drm/i915: Use the gt in HAS_ENGINE
999ecfc5fc75 drm/i915: Convert device_info to uncore/de_read
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2020-06-27 8:38 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-06-25 23:42 [Intel-gfx] [PATCH 0/7] Move some device capabilities under intel_gt Daniele Ceraolo Spurio
2020-06-25 23:42 ` [Intel-gfx] [PATCH 1/7] drm/i915: Convert device_info to uncore/de_read Daniele Ceraolo Spurio
2020-06-26 14:18 ` Tvrtko Ursulin
2020-06-25 23:42 ` [Intel-gfx] [PATCH 2/7] drm/i915: Use the gt in HAS_ENGINE Daniele Ceraolo Spurio
2020-06-26 14:20 ` Tvrtko Ursulin
2020-06-26 14:35 ` Chris Wilson
2020-06-26 17:45 ` Daniele Ceraolo Spurio
2020-06-26 18:03 ` Chris Wilson
2020-06-25 23:42 ` [Intel-gfx] [PATCH 3/7] drm/i915: Move engine-related mmio init to engines_init_mmio Daniele Ceraolo Spurio
2020-06-26 14:38 ` Tvrtko Ursulin
2020-06-26 14:38 ` Chris Wilson
2020-06-26 14:46 ` Daniele Ceraolo Spurio
2020-06-26 14:51 ` Chris Wilson
2020-06-25 23:42 ` [Intel-gfx] [PATCH 4/7] drm/i915: Move the engine mask to intel_gt_info Daniele Ceraolo Spurio
2020-06-26 14:45 ` Tvrtko Ursulin
2020-06-26 16:44 ` Daniele Ceraolo Spurio
2020-06-26 16:50 ` Chris Wilson
2020-06-25 23:42 ` [Intel-gfx] [PATCH 5/7] drm/i915: Introduce gt_init_mmio Daniele Ceraolo Spurio
2020-06-26 14:46 ` Tvrtko Ursulin
2020-06-25 23:42 ` [Intel-gfx] [PATCH 6/7] drm/i915/sseu: Move sseu detection and dump to intel_sseu Daniele Ceraolo Spurio
2020-06-26 15:00 ` Tvrtko Ursulin
2020-06-25 23:42 ` [Intel-gfx] [PATCH 7/7] drm/i915/sseu: Move sseu_info under gt_info Daniele Ceraolo Spurio
2020-06-26 15:22 ` Tvrtko Ursulin
2020-06-26 16:49 ` Daniele Ceraolo Spurio
2020-06-27 8:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Move some device capabilities under intel_gt Patchwork
2020-06-27 8:38 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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