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From: Rajendra Nayak <rnayak@codeaurora.org>
To: agross@kernel.org, bjorn.andersson@linaro.org
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, mka@chromium.org,
	Rajendra Nayak <rnayak@codeaurora.org>
Subject: [PATCH 2/4] arm64: dts: sc7180: Add OPP table for all qup devices
Date: Tue, 30 Jun 2020 14:15:10 +0530	[thread overview]
Message-ID: <1593506712-24557-3-git-send-email-rnayak@codeaurora.org> (raw)
In-Reply-To: <1593506712-24557-1-git-send-email-rnayak@codeaurora.org>

qup has a requirement to vote on the performance state of the CX domain
in sc7180 devices. Add OPP tables for these and also add power-domains
property for all qup instances for uart and spi.
i2c does not support scaling and uses a fixed clock.

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 59 ++++++++++++++++++++++++++++++++++++
 1 file changed, 59 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index ad57df2..78fef54 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -537,6 +537,25 @@
 			status = "disabled";
 		};
 
+		qup_opp_table: qup-opp-table {
+			compatible = "operating-points-v2";
+
+			opp-75000000 {
+				opp-hz = /bits/ 64 <75000000>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+			};
+
+			opp-100000000 {
+				opp-hz = /bits/ 64 <100000000>;
+				required-opps = <&rpmhpd_opp_svs>;
+			};
+
+			opp-128000000 {
+				opp-hz = /bits/ 64 <128000000>;
+				required-opps = <&rpmhpd_opp_nom>;
+			};
+		};
+
 		qupv3_id_0: geniqup@8c0000 {
 			compatible = "qcom,geni-se-qup";
 			reg = <0 0x008c0000 0 0x6000>;
@@ -579,6 +598,8 @@
 				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 				#address-cells = <1>;
 				#size-cells = <0>;
+				power-domains = <&rpmhpd SC7180_CX>;
+				operating-points-v2 = <&qup_opp_table>;
 				interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
 						<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
 				interconnect-names = "qup-core", "qup-config";
@@ -593,6 +614,8 @@
 				pinctrl-names = "default";
 				pinctrl-0 = <&qup_uart0_default>;
 				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SC7180_CX>;
+				operating-points-v2 = <&qup_opp_table>;
 				interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
 						<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
 				interconnect-names = "qup-core", "qup-config";
@@ -627,6 +650,8 @@
 				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 				#address-cells = <1>;
 				#size-cells = <0>;
+				power-domains = <&rpmhpd SC7180_CX>;
+				operating-points-v2 = <&qup_opp_table>;
 				interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
 						<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
 				interconnect-names = "qup-core", "qup-config";
@@ -641,6 +666,8 @@
 				pinctrl-names = "default";
 				pinctrl-0 = <&qup_uart1_default>;
 				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SC7180_CX>;
+				operating-points-v2 = <&qup_opp_table>;
 				interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
 						<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
 				interconnect-names = "qup-core", "qup-config";
@@ -673,6 +700,8 @@
 				pinctrl-names = "default";
 				pinctrl-0 = <&qup_uart2_default>;
 				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SC7180_CX>;
+				operating-points-v2 = <&qup_opp_table>;
 				interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
 						<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
 				interconnect-names = "qup-core", "qup-config";
@@ -707,6 +736,8 @@
 				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 				#address-cells = <1>;
 				#size-cells = <0>;
+				power-domains = <&rpmhpd SC7180_CX>;
+				operating-points-v2 = <&qup_opp_table>;
 				interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
 						<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
 				interconnect-names = "qup-core", "qup-config";
@@ -721,6 +752,8 @@
 				pinctrl-names = "default";
 				pinctrl-0 = <&qup_uart3_default>;
 				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SC7180_CX>;
+				operating-points-v2 = <&qup_opp_table>;
 				interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
 						<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
 				interconnect-names = "qup-core", "qup-config";
@@ -753,6 +786,8 @@
 				pinctrl-names = "default";
 				pinctrl-0 = <&qup_uart4_default>;
 				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SC7180_CX>;
+				operating-points-v2 = <&qup_opp_table>;
 				interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
 						<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
 				interconnect-names = "qup-core", "qup-config";
@@ -787,6 +822,8 @@
 				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 				#address-cells = <1>;
 				#size-cells = <0>;
+				power-domains = <&rpmhpd SC7180_CX>;
+				operating-points-v2 = <&qup_opp_table>;
 				interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
 						<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
 				interconnect-names = "qup-core", "qup-config";
@@ -801,6 +838,8 @@
 				pinctrl-names = "default";
 				pinctrl-0 = <&qup_uart5_default>;
 				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SC7180_CX>;
+				operating-points-v2 = <&qup_opp_table>;
 				interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
 						<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
 				interconnect-names = "qup-core", "qup-config";
@@ -850,6 +889,8 @@
 				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
 				#address-cells = <1>;
 				#size-cells = <0>;
+				power-domains = <&rpmhpd SC7180_CX>;
+				operating-points-v2 = <&qup_opp_table>;
 				interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
 						<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
 				interconnect-names = "qup-core", "qup-config";
@@ -864,6 +905,8 @@
 				pinctrl-names = "default";
 				pinctrl-0 = <&qup_uart6_default>;
 				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SC7180_CX>;
+				operating-points-v2 = <&qup_opp_table>;
 				interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
 						<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
 				interconnect-names = "qup-core", "qup-config";
@@ -896,6 +939,8 @@
 				pinctrl-names = "default";
 				pinctrl-0 = <&qup_uart7_default>;
 				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SC7180_CX>;
+				operating-points-v2 = <&qup_opp_table>;
 				interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
 						<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
 				interconnect-names = "qup-core", "qup-config";
@@ -930,6 +975,8 @@
 				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
 				#address-cells = <1>;
 				#size-cells = <0>;
+				power-domains = <&rpmhpd SC7180_CX>;
+				operating-points-v2 = <&qup_opp_table>;
 				interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
 						<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
 				interconnect-names = "qup-core", "qup-config";
@@ -944,6 +991,8 @@
 				pinctrl-names = "default";
 				pinctrl-0 = <&qup_uart8_default>;
 				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SC7180_CX>;
+				operating-points-v2 = <&qup_opp_table>;
 				interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
 						<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
 				interconnect-names = "qup-core", "qup-config";
@@ -976,6 +1025,8 @@
 				pinctrl-names = "default";
 				pinctrl-0 = <&qup_uart9_default>;
 				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SC7180_CX>;
+				operating-points-v2 = <&qup_opp_table>;
 				interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
 						<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
 				interconnect-names = "qup-core", "qup-config";
@@ -1010,6 +1061,8 @@
 				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
 				#address-cells = <1>;
 				#size-cells = <0>;
+				power-domains = <&rpmhpd SC7180_CX>;
+				operating-points-v2 = <&qup_opp_table>;
 				interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
 						<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
 				interconnect-names = "qup-core", "qup-config";
@@ -1024,6 +1077,8 @@
 				pinctrl-names = "default";
 				pinctrl-0 = <&qup_uart10_default>;
 				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SC7180_CX>;
+				operating-points-v2 = <&qup_opp_table>;
 				interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
 						<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
 				interconnect-names = "qup-core", "qup-config";
@@ -1058,6 +1113,8 @@
 				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
 				#address-cells = <1>;
 				#size-cells = <0>;
+				power-domains = <&rpmhpd SC7180_CX>;
+				operating-points-v2 = <&qup_opp_table>;
 				interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
 						<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
 				interconnect-names = "qup-core", "qup-config";
@@ -1072,6 +1129,8 @@
 				pinctrl-names = "default";
 				pinctrl-0 = <&qup_uart11_default>;
 				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SC7180_CX>;
+				operating-points-v2 = <&qup_opp_table>;
 				interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
 						<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
 				interconnect-names = "qup-core", "qup-config";
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation


  parent reply	other threads:[~2020-06-30  8:46 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-30  8:45 [PATCH 0/4] sdm845/sc7180: Add OPP tables to support IO DVFS Rajendra Nayak
2020-06-30  8:45 ` [PATCH 1/4] arm64: dts: sdm845: Add OPP table for all qup devices Rajendra Nayak
2020-06-30 23:32   ` Matthias Kaehlcke
2020-06-30  8:45 ` Rajendra Nayak [this message]
2020-06-30 23:37   ` [PATCH 2/4] arm64: dts: sc7180: " Matthias Kaehlcke
2020-06-30  8:45 ` [PATCH 3/4] arm64: dts: sdm845: Add sdhc opps and power-domains Rajendra Nayak
2020-06-30 23:43   ` Matthias Kaehlcke
2020-06-30  8:45 ` [PATCH 4/4] arm64: dts: sc7180: " Rajendra Nayak
2020-06-30 23:45   ` Matthias Kaehlcke

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