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S1726991AbgGMHpr (ORCPT ); Mon, 13 Jul 2020 03:45:47 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:65462 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725818AbgGMHpr (ORCPT ); Mon, 13 Jul 2020 03:45:47 -0400 X-UUID: 01bbdec13ccc442cbdb451e08e087b3f-20200713 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=4x8ya6Vnce3yiQGPD2JZIDEZ1YPf+zCABzP2yiH62kQ=; b=L6bbJVRN3dh6XIRQIx0OesVnJ6mtEixSmGhz5VqxCkvYbKMTe8bQ+BEwQ31pgVCd0JL3tj/bA1567mYMnCwin4E1XQQ2FKsRr4xHDMPRPZu7uifJO+wnkbHh8Wp6KMduBZiGwrcizjsUYMvE2Fe3sPEnDHFEVmBejqRfE567I/g=; X-UUID: 01bbdec13ccc442cbdb451e08e087b3f-20200713 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1760003620; Mon, 13 Jul 2020 15:45:38 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 13 Jul 2020 15:45:34 +0800 Received: from [172.21.77.33] (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 13 Jul 2020 15:45:35 +0800 Message-ID: <1594626336.22730.36.camel@mtkswgap22> Subject: Re: [PATCH v2 2/2] soc: mediatek: add mtk-devapc driver From: Neal Liu To: Matthias Brugger CC: Neal Liu , Rob Herring , , , , lkml , Date: Mon, 13 Jul 2020 15:45:36 +0800 In-Reply-To: References: <1594285927-1840-1-git-send-email-neal.liu@mediatek.com> <1594285927-1840-3-git-send-email-neal.liu@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 MIME-Version: 1.0 X-TM-SNTS-SMTP: 02EEB14808AABAF9D2F91D0886FDE7959125C6CE24A27BAE0F2A544E5BF812232000:8 X-MTK: N Content-Transfer-Encoding: base64 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org T24gRnJpLCAyMDIwLTA3LTEwIGF0IDE0OjE0ICswMjAwLCBNYXR0aGlhcyBCcnVnZ2VyIHdyb3Rl Og0KPiANCltzbmlwXQ0KPiA+ICsNCj4gPiArc3RhdGljIGludCBnZXRfdmlvX3NsYXZlX251bShp bnQgc2xhdmVfdHlwZSkNCj4gDQo+IEkgaGF2ZSBhIGhhcmQgdGltZSB0byB1bmRlcnN0YW5kIHRo ZSB1c2VmdWxsbmVzcyBvZiB0aGlzLCBjYW4geW91IHBsZWFzZSBleHBsYWluLg0KPiANCg0KVGhl IGJhc2ljIGlkZWEgaXMgdG8gZ2V0IHRvdGFsIG51bWJlcnMgb2Ygc2xhdmVzLiBBbmQgd2UgY2Fu IHVzZSBpdCB0bw0Kc2NhbiBhbGwgc2xhdmVzIHdoaWNoIGhhcyBiZWVuIHRyaWdnZXJlZCB2aW9s YXRpb24uDQpJIHRoaW5rIEkgY2FuIHBhc3MgaXQgdGhyb3VnaCBEVCBkYXRhIGluc3RlYWQgb2Yg dXNpbmcgbXRrX2RldmljZV9pbmZvDQphcnJheS4gSSdsbCBzZW5kIGFub3RoZXIgcGF0Y2hlcyB0 byBjaGFuZ2UgaXQuDQoNCj4gPiArew0KPiA+ICsJaWYgKHNsYXZlX3R5cGUgPT0gMCkNCj4gPiAr CQlyZXR1cm4gQVJSQVlfU0laRShtdGtfZGV2aWNlc19pbmZyYSk7DQo+ID4gKw0KPiA+ICsJcmV0 dXJuIDA7DQo+ID4gK30NCj4gPiArDQo+ID4gK3N0YXRpYyB1MzIgZ2V0X3NoaWZ0X2dyb3VwKHN0 cnVjdCBtdGtfZGV2YXBjX2NvbnRleHQgKmRldmFwY19jdHgsDQo+ID4gKwkJCSAgIGludCBzbGF2 ZV90eXBlLCBpbnQgdmlvX2lkeCkNCj4gPiArew0KPiA+ICsJdTMyIHZpb19zaGlmdF9zdGE7DQo+ ID4gKwl2b2lkIF9faW9tZW0gKnJlZzsNCj4gPiArCWludCBiaXQ7DQo+ID4gKw0KPiA+ICsJcmVn ID0gbXRrX2RldmFwY19wZF9nZXQoZGV2YXBjX2N0eCwgc2xhdmVfdHlwZSwgVklPX1NISUZUX1NU QSwgMCk7DQo+ID4gKwl2aW9fc2hpZnRfc3RhID0gcmVhZGwocmVnKTsNCj4gPiArDQo+ID4gKwlm b3IgKGJpdCA9IDA7IGJpdCA8IDMyOyBiaXQrKykgew0KPiA+ICsJCWlmICgodmlvX3NoaWZ0X3N0 YSA+PiBiaXQpICYgMHgxKSA+ICsJCQlicmVhazsNCj4gPiArCX0NCj4gPiArDQo+ID4gKwlyZXR1 cm4gYml0Ow0KPiANCj4gV2UgcmV0dXJuIHRoZSBmaXJzdCBwb3NpdGlvbiAoZnJvbSB0aGUgcmln aHQpIG9mIHRoZSByaWdzdGVyIHdpdGggdGhlIGJpdCBzZXQgdG8gDQo+IG9uZS4gQ29ycmVjdD8N Cj4gQ2FuJ3Qgd2UgdXNlIF9fZmZzKCkgZm9yIHRoaXM/DQoNClllcywgdGhhbmtzIGZvciB5b3Vy IHJlbWluZHMgdG8gdXNlIF9fZmZzKCkuDQpJJ2xsIHJldmlzZSBpdCBpbiBuZXh0IHBhdGNoZXMu DQoNCj4gDQo+ID4gK30NCj4gPiArDQo+ID4gK3N0YXRpYyBpbnQgY2hlY2tfdmlvX21hc2tfc3Rh KHN0cnVjdCBtdGtfZGV2YXBjX2NvbnRleHQgKmRldmFwY19jdHgsDQo+ID4gKwkJCSAgICAgIGlu dCBzbGF2ZV90eXBlLCB1MzIgbW9kdWxlLCBpbnQgcGRfcmVnX3R5cGUpDQo+ID4gK3sNCj4gPiAr CXUzMiByZWdfaW5kZXgsIHJlZ19vZmZzZXQ7DQo+ID4gKwl2b2lkIF9faW9tZW0gKnJlZzsNCj4g PiArCXUzMiB2YWx1ZTsNCj4gPiArDQo+ID4gKwlWSU9fTUFTS19TVEFfUkVHX0dFVChtb2R1bGUp Ow0KPiA+ICsNCj4gPiArCXJlZyA9IG10a19kZXZhcGNfcGRfZ2V0KGRldmFwY19jdHgsIHNsYXZl X3R5cGUsIHBkX3JlZ190eXBlLCByZWdfaW5kZXgpOw0KPiANCj4gcmVnID0gbXRrX2RldmFwY19w ZF9nZXQoZGV2YXBjX2N0eCwgc2xhdmVfdHlwZSwgcGRfcmVnX3R5cGUsIA0KPiBWSU9fTU9EX1RP X1JFR19JTkQobW9kdWxlKSk7DQoNCk9rYXksIEknbGwgcmV2aXNlIGl0IGluIG5leHQgcGF0Y2hl cy4NCg0KPiANCj4gPiArCXZhbHVlID0gcmVhZGwocmVnKTsNCj4gPiArDQo+ID4gKwlyZXR1cm4g KCh2YWx1ZSA+PiByZWdfb2Zmc2V0KSAmIDB4MSk7DQo+IA0KPiByZXR1cm4gKCh2YWx1ZSA+PiBW SU9fTU9EX1RPX1JFR19PRkYobW9kdWxlKSkgJiAweDEpOw0KDQpPa2F5LCBJJ2xsIHJldmlzZSBp dCBpbiBuZXh0IHBhdGNoZXMuDQoNCj4gDQo+ID4gK30NCj4gPiArDQo+ID4gK3N0YXRpYyBpbnQg Y2hlY2tfdmlvX21hc2soc3RydWN0IG10a19kZXZhcGNfY29udGV4dCAqZGV2YXBjX2N0eCwgaW50 IHNsYXZlX3R5cGUsDQo+ID4gKwkJCSAgdTMyIG1vZHVsZSkNCj4gPiArew0KPiA+ICsJcmV0dXJu IGNoZWNrX3Zpb19tYXNrX3N0YShkZXZhcGNfY3R4LCBzbGF2ZV90eXBlLCBtb2R1bGUsIFZJT19N QVNLKTsNCj4gPiArfQ0KPiA+ICsNCj4gPiArc3RhdGljIGludCBjaGVja192aW9fc3RhdHVzKHN0 cnVjdCBtdGtfZGV2YXBjX2NvbnRleHQgKmRldmFwY19jdHgsDQo+ID4gKwkJCSAgICBpbnQgc2xh dmVfdHlwZSwgdTMyIG1vZHVsZSkNCj4gPiArew0KPiA+ICsJcmV0dXJuIGNoZWNrX3Zpb19tYXNr X3N0YShkZXZhcGNfY3R4LCBzbGF2ZV90eXBlLCBtb2R1bGUsIFZJT19TVEEpOw0KPiA+ICt9DQo+ ID4gKw0KPiA+ICtzdGF0aWMgdm9pZCBjbGVhcl92aW9fc3RhdHVzKHN0cnVjdCBtdGtfZGV2YXBj X2NvbnRleHQgKmRldmFwY19jdHgsDQo+ID4gKwkJCSAgICAgaW50IHNsYXZlX3R5cGUsIHUzMiBt b2R1bGUpDQo+ID4gK3sNCj4gPiArCXUzMiByZWdfaW5kZXgsIHJlZ19vZmZzZXQ7DQo+ID4gKwl2 b2lkIF9faW9tZW0gKnJlZzsNCj4gPiArDQo+ID4gKwlWSU9fTUFTS19TVEFfUkVHX0dFVChtb2R1 bGUpOw0KPiA+ICsNCj4gPiArCXJlZyA9IG10a19kZXZhcGNfcGRfZ2V0KGRldmFwY19jdHgsIHNs YXZlX3R5cGUsIFZJT19TVEEsIHJlZ19pbmRleCk7DQo+ID4gKwl3cml0ZWwoMHgxIDw8IHJlZ19v ZmZzZXQsIHJlZyk7DQo+ID4gKw0KPiA+ICsJaWYgKGNoZWNrX3Zpb19zdGF0dXMoZGV2YXBjX2N0 eCwgc2xhdmVfdHlwZSwgbW9kdWxlKSkNCj4gPiArCQlwcl9lcnIoUEZYICIlczogQ2xlYXIgZmFp bGVkLCBzbGF2ZV90eXBlOjB4JXgsIG1vZHVsZV9pbmRleDoweCV4XG4iLA0KPiA+ICsJCSAgICAg ICBfX2Z1bmNfXywgc2xhdmVfdHlwZSwgbW9kdWxlKTsNCj4gPiArfQ0KPiA+ICsNCj4gPiArc3Rh dGljIHZvaWQgbWFza19tb2R1bGVfaXJxKHN0cnVjdCBtdGtfZGV2YXBjX2NvbnRleHQgKmRldmFw Y19jdHgsDQo+ID4gKwkJCSAgICBpbnQgc2xhdmVfdHlwZSwgdTMyIG1vZHVsZSwgYm9vbCBtYXNr KQ0KPiA+ICt7DQo+ID4gKwl1MzIgcmVnX2luZGV4LCByZWdfb2Zmc2V0Ow0KPiA+ICsJdm9pZCBf X2lvbWVtICpyZWc7DQo+ID4gKwl1MzIgdmFsdWU7DQo+ID4gKw0KPiA+ICsJVklPX01BU0tfU1RB X1JFR19HRVQobW9kdWxlKTsNCj4gPiArDQo+ID4gKwlyZWcgPSBtdGtfZGV2YXBjX3BkX2dldChk ZXZhcGNfY3R4LCBzbGF2ZV90eXBlLCBWSU9fTUFTSywgcmVnX2luZGV4KTsNCj4gPiArDQo+ID4g Kwl2YWx1ZSA9IHJlYWRsKHJlZyk7DQo+ID4gKwlpZiAobWFzaykNCj4gPiArCQl2YWx1ZSB8PSAo MHgxIDw8IHJlZ19vZmZzZXQpOw0KPiA+ICsJZWxzZQ0KPiA+ICsJCXZhbHVlICY9IH4oMHgxIDw8 IHJlZ19vZmZzZXQpOw0KPiA+ICsNCj4gPiArCXdyaXRlbCh2YWx1ZSwgcmVnKTsNCj4gPiArfQ0K PiA+ICsNCj4gPiArI2RlZmluZSBUSU1FT1VUX01TCQkxMDAwMA0KPiA+ICsNCj4gPiArc3RhdGlj IGludCByZWFkX3BvbGxfdGltZW91dCh2b2lkIF9faW9tZW0gKmFkZHIsIHUzMiBtYXNrKQ0KPiAN Cj4gVGhhdCBmdW5jdGlvbiBpcyBkZWZpbmVkIGluIGluY2x1ZGUvbGludXgvaW9wb2xsLmgNCj4g DQo+ID4gK3sNCj4gPiArCXVuc2lnbmVkIGxvbmcgdGltZW91dCA9IGppZmZpZXMgKyBtc2Vjc190 b19qaWZmaWVzKFRJTUVPVVRfTVMpOw0KPiA+ICsNCj4gPiArCWRvIHsNCj4gPiArCQlpZiAocmVh ZGxfcmVsYXhlZChhZGRyKSAmIG1hc2spDQo+IA0KPiBQbGVhc2UgdXNlIGEgdmFyaWFibGUgd2hl cmUgeW91IHdyaXRlIHlvdXIgdmFsdWUgdG8gYW5kIHRoZW4gY2hlY2sgZm9yIHRoZSBtYXNrLiAN Cj4gVGhhdCBtYWtzIHRoZSBjb2RlIGVhc2llciB0byByZWFkIGFuZCBJIHRoaW5rIGlzIHBhcnQg b2YgdGhlIGNvZGluZyBzdHlsZS4NCj4gDQoNCk9rYXksIEknbGwgdXNlIHRoZSBmdW5jdGlvbiBp biBpb3BvbGwuaCBpbnN0ZWFkLg0KVGhhbmtzIGZvciB5b3VyIHJlbWluZHMuDQoNCj4gPiArCQkJ cmV0dXJuIDA7DQo+ID4gKw0KPiA+ICsJfSB3aGlsZSAoIXRpbWVfYWZ0ZXIoamlmZmllcywgdGlt ZW91dCkpOw0KPiA+ICsNCj4gPiArCXJldHVybiAocmVhZGxfcmVsYXhlZChhZGRyKSAmIG1hc2sp ID8gMCA6IC1FVElNRURPVVQ7DQo+ID4gK30NCj4gPiArDQo+ID4gKy8qDQo+ID4gKyAqIHN5bmNf dmlvX2RiZyAtIHN0YXJ0IHRvIGdldCB2aW9sYXRpb24gaW5mb3JtYXRpb24gYnkgc2VsZWN0aW5n IHZpb2xhdGlvbg0KPiA+ICsgKgkJICBncm91cCBhbmQgZW5hYmxlIHZpb2xhdGlvbiBzaGlmdC4N Cj4gPiArICoNCj4gPiArICogUmV0dXJucyBzeW5jIGRvbmUgb3Igbm90DQo+ID4gKyAqLw0KPiA+ ICtzdGF0aWMgdTMyIHN5bmNfdmlvX2RiZyhzdHJ1Y3QgbXRrX2RldmFwY19jb250ZXh0ICpkZXZh cGNfY3R4LCBpbnQgc2xhdmVfdHlwZSwNCj4gPiArCQkJdTMyIHNoaWZ0X2JpdCkNCj4gPiArew0K PiA+ICsJdm9pZCBfX2lvbWVtICpwZF92aW9fc2hpZnRfc3RhX3JlZzsNCj4gPiArCXZvaWQgX19p b21lbSAqcGRfdmlvX3NoaWZ0X3NlbF9yZWc7DQo+ID4gKwl2b2lkIF9faW9tZW0gKnBkX3Zpb19z aGlmdF9jb25fcmVnOw0KPiA+ICsJdTMyIHN5bmNfZG9uZSA9IDA7DQo+ID4gKw0KPiA+ICsJcGRf dmlvX3NoaWZ0X3N0YV9yZWcgPSBtdGtfZGV2YXBjX3BkX2dldChkZXZhcGNfY3R4LCBzbGF2ZV90 eXBlLA0KPiA+ICsJCQkJCQkgVklPX1NISUZUX1NUQSwgMCk7DQo+ID4gKwlwZF92aW9fc2hpZnRf c2VsX3JlZyA9IG10a19kZXZhcGNfcGRfZ2V0KGRldmFwY19jdHgsIHNsYXZlX3R5cGUsDQo+ID4g KwkJCQkJCSBWSU9fU0hJRlRfU0VMLCAwKTsNCj4gPiArCXBkX3Zpb19zaGlmdF9jb25fcmVnID0g bXRrX2RldmFwY19wZF9nZXQoZGV2YXBjX2N0eCwgc2xhdmVfdHlwZSwNCj4gPiArCQkJCQkJIFZJ T19TSElGVF9DT04sIDApOw0KPiA+ICsNCj4gPiArCXdyaXRlbCgweDEgPDwgc2hpZnRfYml0LCBw ZF92aW9fc2hpZnRfc2VsX3JlZyk7DQo+ID4gKwl3cml0ZWwoMHgxLCBwZF92aW9fc2hpZnRfY29u X3JlZyk7DQo+ID4gKw0KPiA+ICsJaWYgKCFyZWFkX3BvbGxfdGltZW91dChwZF92aW9fc2hpZnRf Y29uX3JlZywgMHgyKSkNCj4gPiArCQlzeW5jX2RvbmUgPSAxOw0KPiA+ICsJZWxzZQ0KPiA+ICsJ CXByX2VycihQRlggIiVzOiBTaGlmdCB2aW9sYXRpb24gaW5mbyBmYWlsZWRcbiIsIF9fZnVuY19f KTsNCj4gPiArDQo+ID4gKwkvKiBEaXNhYmxlIHNoaWZ0IG1lY2hhbmlzbSAqLw0KPiANCj4gUGxl YXNlIGFkZCBhIGNvbW1lbnQgZXhwbGFpbmluZyB3aGF0IHRoZSBzaGlmdCBtZWNoYW5pc20gaXMg YWJvdXQuDQoNCk9rYXksIEknbGwgYWRkIGEgY29tbWVudCB0byBleHBsYWluIGl0IGF0IHRoZSBi ZWdpbm5pbmcgb2YgdGhpcw0KZnVuY3Rpb24uDQoNCj4gDQo+ID4gKwl3cml0ZWwoMHgwLCBwZF92 aW9fc2hpZnRfY29uX3JlZyk7DQo+ID4gKwl3cml0ZWwoMHgwLCBwZF92aW9fc2hpZnRfc2VsX3Jl Zyk7DQo+ID4gKwl3cml0ZWwoMHgxIDw8IHNoaWZ0X2JpdCwgcGRfdmlvX3NoaWZ0X3N0YV9yZWcp Ow0KPiA+ICsNCj4gPiArCXJldHVybiBzeW5jX2RvbmU7DQo+ID4gK30NCj4gPiArDQo+ID4gK3N0 YXRpYyB2b2lkIGRldmFwY192aW9faW5mb19wcmludChzdHJ1Y3QgbXRrX2RldmFwY19jb250ZXh0 ICpkZXZhcGNfY3R4KQ0KPiA+ICt7DQo+ID4gKwlzdHJ1Y3QgbXRrX2RldmFwY192aW9faW5mbyAq dmlvX2luZm8gPSBkZXZhcGNfY3R4LT52aW9faW5mbzsNCj4gPiArDQo+ID4gKwkvKiBQcmludCB2 aW9sYXRpb24gaW5mb3JtYXRpb24gKi8NCj4gPiArCWlmICh2aW9faW5mby0+d3JpdGUpDQo+ID4g KwkJcHJfaW5mbyhQRlggIldyaXRlIFZpb2xhdGlvblxuIik7DQo+ID4gKwllbHNlIGlmICh2aW9f aW5mby0+cmVhZCkNCj4gPiArCQlwcl9pbmZvKFBGWCAiUmVhZCBWaW9sYXRpb25cbiIpOw0KPiA+ ICsNCj4gPiArCXByX2luZm8oUEZYICIlcyV4LCAlcyV4LCAlcyV4LCAlcyV4XG4iLA0KPiA+ICsJ CSJWaW8gQWRkcjoweCIsIHZpb19pbmZvLT52aW9fYWRkciwNCj4gPiArCQkiSGlnaDoweCIsIHZp b19pbmZvLT52aW9fYWRkcl9oaWdoLA0KPiA+ICsJCSJCdXMgSUQ6MHgiLCB2aW9faW5mby0+bWFz dGVyX2lkLA0KPiA+ICsJCSJEb20gSUQ6MHgiLCB2aW9faW5mby0+ZG9tYWluX2lkKTsNCj4gPiAr fQ0KPiA+ICsNCj4gPiArc3RhdGljIHZvaWQgZGV2YXBjX2V4dHJhY3RfdmlvX2RiZyhzdHJ1Y3Qg bXRrX2RldmFwY19jb250ZXh0ICpkZXZhcGNfY3R4LA0KPiA+ICsJCQkJICAgaW50IHNsYXZlX3R5 cGUpDQo+ID4gK3sNCj4gPiArCXZvaWQgX19pb21lbSAqdmlvX2RiZzBfcmVnLCAqdmlvX2RiZzFf cmVnOw0KPiA+ICsJc3RydWN0IG10a19kZXZhcGNfdmlvX2RiZ3NfZGVzYyAqdmlvX2RiZ3M7DQo+ ID4gKwlzdHJ1Y3QgbXRrX2RldmFwY192aW9faW5mbyAqdmlvX2luZm87DQo+ID4gKwl1MzIgZGJn MDsNCj4gPiArDQo+ID4gKwl2aW9fZGJnMF9yZWcgPSBtdGtfZGV2YXBjX3BkX2dldChkZXZhcGNf Y3R4LCBzbGF2ZV90eXBlLCBWSU9fREJHMCwgMCk7DQo+ID4gKwl2aW9fZGJnMV9yZWcgPSBtdGtf ZGV2YXBjX3BkX2dldChkZXZhcGNfY3R4LCBzbGF2ZV90eXBlLCBWSU9fREJHMSwgMCk7DQo+ID4g Kw0KPiA+ICsJdmlvX2RiZ3MgPSBkZXZhcGNfY3R4LT52aW9fZGJnc19kZXNjOw0KPiA+ICsJdmlv X2luZm8gPSBkZXZhcGNfY3R4LT52aW9faW5mbzsNCj4gPiArDQo+ID4gKwkvKiBFeHRyYWN0IHZp b2xhdGlvbiBpbmZvcm1hdGlvbiAqLw0KPiA+ICsJZGJnMCA9IHJlYWRsKHZpb19kYmcwX3JlZyk7 DQo+ID4gKwl2aW9faW5mby0+dmlvX2FkZHIgPSByZWFkbCh2aW9fZGJnMV9yZWcpOw0KPiA+ICsN Cj4gPiArCXZpb19pbmZvLT5tYXN0ZXJfaWQgPSAoZGJnMCAmIHZpb19kYmdzW01TVElEXS5tYXNr KSA+Pg0KPiA+ICsJCQkgICAgICB2aW9fZGJnc1tNU1RJRF0uc3RhcnRfYml0Ow0KPiA+ICsJdmlv X2luZm8tPmRvbWFpbl9pZCA9IChkYmcwICYgdmlvX2RiZ3NbRE1OSURdLm1hc2spID4+DQo+ID4g KwkJCSAgICAgIHZpb19kYmdzW0RNTklEXS5zdGFydF9iaXQ7DQo+ID4gKwl2aW9faW5mby0+d3Jp dGUgPSAoKGRiZzAgJiB2aW9fZGJnc1tWSU9fV10ubWFzaykgPj4NCj4gPiArCQkJICAgdmlvX2Ri Z3NbVklPX1ddLnN0YXJ0X2JpdCkgPT0gMTsNCj4gPiArCXZpb19pbmZvLT5yZWFkID0gKChkYmcw ICYgdmlvX2RiZ3NbVklPX1JdLm1hc2spID4+DQo+ID4gKwkJCSAgdmlvX2RiZ3NbVklPX1JdLnN0 YXJ0X2JpdCkgPT0gMTsNCj4gPiArCXZpb19pbmZvLT52aW9fYWRkcl9oaWdoID0gKGRiZzAgJiB2 aW9fZGJnc1tBRERSX0hdLm1hc2spID4+DQo+ID4gKwkJCQkgIHZpb19kYmdzW0FERFJfSF0uc3Rh cnRfYml0Ow0KPiA+ICsNCj4gPiArCWRldmFwY192aW9faW5mb19wcmludChkZXZhcGNfY3R4KTsN Cj4gPiArfQ0KPiA+ICsNCj4gPiArLyoNCj4gPiArICogbXRrX2RldmFwY19kdW1wX3Zpb19kYmcg LSBzaGlmdCAmIGR1bXAgdGhlIHZpb2xhdGlvbiBkZWJ1ZyBpbmZvcm1hdGlvbi4NCj4gPiArICov DQo+ID4gK3N0YXRpYyBib29sIG10a19kZXZhcGNfZHVtcF92aW9fZGJnKHN0cnVjdCBtdGtfZGV2 YXBjX2NvbnRleHQgKmRldmFwY19jdHgsDQo+ID4gKwkJCQkgICAgaW50IHNsYXZlX3R5cGUsIGlu dCAqdmlvX2lkeCkNCj4gPiArew0KPiA+ICsJY29uc3Qgc3RydWN0IG10a19kZXZpY2VfaW5mbyAq KmRldmljZV9pbmZvOw0KPiA+ICsJdTMyIHNoaWZ0X2JpdDsNCj4gPiArCWludCBpOw0KPiA+ICsN Cj4gPiArCWRldmljZV9pbmZvID0gZGV2YXBjX2N0eC0+ZGV2aWNlX2luZm87DQo+ID4gKw0KPiA+ ICsJZm9yIChpID0gMDsgaSA8IGdldF92aW9fc2xhdmVfbnVtKHNsYXZlX3R5cGUpOyBpKyspIHsN Cj4gPiArCQkqdmlvX2lkeCA9IGRldmljZV9pbmZvW3NsYXZlX3R5cGVdW2ldLnZpb19pbmRleDsN Cj4gPiArDQo+ID4gKwkJaWYgKGNoZWNrX3Zpb19tYXNrKGRldmFwY19jdHgsIHNsYXZlX3R5cGUs ICp2aW9faWR4KSkNCj4gPiArCQkJY29udGludWU7DQo+ID4gKw0KPiA+ICsJCWlmICghY2hlY2tf dmlvX3N0YXR1cyhkZXZhcGNfY3R4LCBzbGF2ZV90eXBlLCAqdmlvX2lkeCkpDQo+ID4gKwkJCWNv bnRpbnVlOw0KPiA+ICsNCj4gPiArCQlzaGlmdF9iaXQgPSBnZXRfc2hpZnRfZ3JvdXAoZGV2YXBj X2N0eCwgc2xhdmVfdHlwZSwgKnZpb19pZHgpOw0KPiA+ICsNCj4gPiArCQlpZiAoIXN5bmNfdmlv X2RiZyhkZXZhcGNfY3R4LCBzbGF2ZV90eXBlLCBzaGlmdF9iaXQpKQ0KPiA+ICsJCQljb250aW51 ZTsNCj4gPiArDQo+ID4gKwkJZGV2YXBjX2V4dHJhY3RfdmlvX2RiZyhkZXZhcGNfY3R4LCBzbGF2 ZV90eXBlKTsNCj4gPiArDQo+ID4gKwkJcmV0dXJuIHRydWU7DQo+ID4gKwl9DQo+ID4gKw0KPiA+ ICsJcmV0dXJuIGZhbHNlOw0KPiA+ICt9DQo+ID4gKw0KPiA+ICsvKg0KPiA+ICsgKiBkZXZhcGNf dmlvbGF0aW9uX2lycSAtIHRoZSBkZXZhcGMgSW50ZXJydXB0IFNlcnZpY2UgUm91dGluZSAoSVNS KSB3aWxsIGR1bXANCj4gPiArICoJCQkgIHZpb2xhdGlvbiBpbmZvcm1hdGlvbiBpbmNsdWRpbmcg d2hpY2ggbWFzdGVyIHZpb2xhdGVzDQo+ID4gKyAqCQkJICBhY2Nlc3Mgc2xhdmUuDQo+ID4gKyAq Lw0KPiA+ICtzdGF0aWMgaXJxcmV0dXJuX3QgZGV2YXBjX3Zpb2xhdGlvbl9pcnEoaW50IGlycV9u dW1iZXIsDQo+ID4gKwkJCQkJc3RydWN0IG10a19kZXZhcGNfY29udGV4dCAqZGV2YXBjX2N0eCkN Cj4gPiArew0KPiA+ICsJY29uc3Qgc3RydWN0IG10a19kZXZpY2VfaW5mbyAqKmRldmljZV9pbmZv Ow0KPiA+ICsJaW50IHNsYXZlX3R5cGVfbnVtOw0KPiA+ICsJaW50IHZpb19pZHggPSAtMTsNCj4g PiArCWludCBzbGF2ZV90eXBlOw0KPiA+ICsNCj4gPiArCXNsYXZlX3R5cGVfbnVtID0gZGV2YXBj X2N0eC0+c2xhdmVfdHlwZV9udW07DQo+ID4gKwlkZXZpY2VfaW5mbyA9IGRldmFwY19jdHgtPmRl dmljZV9pbmZvOw0KPiA+ICsNCj4gPiArCWZvciAoc2xhdmVfdHlwZSA9IDA7IHNsYXZlX3R5cGUg PCBzbGF2ZV90eXBlX251bTsgc2xhdmVfdHlwZSsrKSB7DQo+ID4gKwkJaWYgKCFtdGtfZGV2YXBj X2R1bXBfdmlvX2RiZyhkZXZhcGNfY3R4LCBzbGF2ZV90eXBlLCAmdmlvX2lkeCkpDQo+ID4gKwkJ CWNvbnRpbnVlOw0KPiA+ICsNCj4gPiArCQkvKiBFbnN1cmUgdGhhdCB2aW9sYXRpb24gaW5mbyBh cmUgd3JpdHRlbiBiZWZvcmUNCj4gPiArCQkgKiBmdXJ0aGVyIG9wZXJhdGlvbnMNCj4gPiArCQkg Ki8NCj4gPiArCQlzbXBfbWIoKTsNCj4gPiArDQo+ID4gKwkJbWFza19tb2R1bGVfaXJxKGRldmFw Y19jdHgsIHNsYXZlX3R5cGUsIHZpb19pZHgsIHRydWUpOw0KPiA+ICsNCj4gPiArCQljbGVhcl92 aW9fc3RhdHVzKGRldmFwY19jdHgsIHNsYXZlX3R5cGUsIHZpb19pZHgpOw0KPiA+ICsNCj4gPiAr CQltYXNrX21vZHVsZV9pcnEoZGV2YXBjX2N0eCwgc2xhdmVfdHlwZSwgdmlvX2lkeCwgZmFsc2Up Ow0KPiA+ICsJfQ0KPiA+ICsNCj4gPiArCXJldHVybiBJUlFfSEFORExFRDsNCj4gPiArfQ0KPiA+ ICsNCj4gPiArLyoNCj4gPiArICogc3RhcnRfZGV2YXBjIC0gaW5pdGlhbGl6ZSBkZXZhcGMgc3Rh dHVzIGFuZCBzdGFydCByZWNlaXZpbmcgaW50ZXJydXB0DQo+ID4gKyAqCQkgIHdoaWxlIGRldmFw YyB2aW9sYXRpb24gaXMgdHJpZ2dlcmVkLg0KPiA+ICsgKi8NCj4gPiArc3RhdGljIHZvaWQgc3Rh cnRfZGV2YXBjKHN0cnVjdCBtdGtfZGV2YXBjX2NvbnRleHQgKmRldmFwY19jdHgpDQo+ID4gK3sN Cj4gPiArCWNvbnN0IHN0cnVjdCBtdGtfZGV2aWNlX2luZm8gKipkZXZpY2VfaW5mbzsNCj4gPiAr CXZvaWQgX19pb21lbSAqcGRfdmlvX3NoaWZ0X3N0YV9yZWc7DQo+ID4gKwl2b2lkIF9faW9tZW0g KnBkX2FwY19jb25fcmVnOw0KPiA+ICsJdTMyIHZpb19zaGlmdF9zdGE7DQo+ID4gKwlpbnQgc2xh dmVfdHlwZSwgc2xhdmVfdHlwZV9udW07DQo+ID4gKwlpbnQgaSwgdmlvX2lkeDsNCj4gPiArDQo+ ID4gKwlkZXZpY2VfaW5mbyA9IGRldmFwY19jdHgtPmRldmljZV9pbmZvOw0KPiA+ICsJc2xhdmVf dHlwZV9udW0gPSBkZXZhcGNfY3R4LT5zbGF2ZV90eXBlX251bTsNCj4gPiArDQo+ID4gKwlmb3Ig KHNsYXZlX3R5cGUgPSAwOyBzbGF2ZV90eXBlIDwgc2xhdmVfdHlwZV9udW07IHNsYXZlX3R5cGUr Kykgew0KPiA+ICsJCXBkX2FwY19jb25fcmVnID0gbXRrX2RldmFwY19wZF9nZXQoZGV2YXBjX2N0 eCwgc2xhdmVfdHlwZSwNCj4gPiArCQkJCQkJICAgQVBDX0NPTiwgMCk7DQo+ID4gKwkJcGRfdmlv X3NoaWZ0X3N0YV9yZWcgPSBtdGtfZGV2YXBjX3BkX2dldChkZXZhcGNfY3R4LCBzbGF2ZV90eXBl LA0KPiA+ICsJCQkJCQkJIFZJT19TSElGVF9TVEEsIDApOw0KPiA+ICsJCWlmICghcGRfYXBjX2Nv bl9yZWcgfHwgIXBkX3Zpb19zaGlmdF9zdGFfcmVnKQ0KPiA+ICsJCQlyZXR1cm47DQo+ID4gKw0K PiA+ICsJCS8qIENsZWFyIGRldmFwYyB2aW9sYXRpb24gc3RhdHVzICovDQo+ID4gKwkJd3JpdGVs KEJJVCgzMSksIHBkX2FwY19jb25fcmVnKTsNCj4gPiArDQo+ID4gKwkJLyogQ2xlYXIgdmlvbGF0 aW9uIHNoaWZ0IHN0YXR1cyAqLw0KPiA+ICsJCXZpb19zaGlmdF9zdGEgPSByZWFkbChwZF92aW9f c2hpZnRfc3RhX3JlZyk7DQo+ID4gKwkJaWYgKHZpb19zaGlmdF9zdGEpDQo+ID4gKwkJCXdyaXRl bCh2aW9fc2hpZnRfc3RhLCBwZF92aW9fc2hpZnRfc3RhX3JlZyk7DQo+ID4gKw0KPiA+ICsJCS8q IENsZWFyIHNsYXZlIHZpb2xhdGlvbiBzdGF0dXMgKi8NCj4gPiArCQlmb3IgKGkgPSAwOyBpIDwg Z2V0X3Zpb19zbGF2ZV9udW0oc2xhdmVfdHlwZSk7IGkrKykgew0KPiA+ICsJCQl2aW9faWR4ID0g ZGV2aWNlX2luZm9bc2xhdmVfdHlwZV1baV0udmlvX2luZGV4Ow0KPiA+ICsNCj4gPiArCQkJY2xl YXJfdmlvX3N0YXR1cyhkZXZhcGNfY3R4LCBzbGF2ZV90eXBlLCB2aW9faWR4KTsNCj4gPiArDQo+ ID4gKwkJCW1hc2tfbW9kdWxlX2lycShkZXZhcGNfY3R4LCBzbGF2ZV90eXBlLCB2aW9faWR4LCBm YWxzZSk7DQo+ID4gKwkJfQ0KPiA+ICsJfQ0KPiA+ICt9DQo+ID4gKw0KPiA+ICtzdGF0aWMgaW50 IG10a19kZXZhcGNfcHJvYmUoc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRldikNCj4gPiArew0K PiA+ICsJc3RydWN0IGRldmljZV9ub2RlICpub2RlID0gcGRldi0+ZGV2Lm9mX25vZGU7DQo+ID4g KwlzdHJ1Y3QgbXRrX2RldmFwY19jb250ZXh0ICpkZXZhcGNfY3R4Ow0KPiA+ICsJc3RydWN0IGNs ayAqZGV2YXBjX2luZnJhX2NsazsNCj4gPiArCXUzMiB2aW9fZGJnc19udW0sIHBkc19udW07DQo+ ID4gKwl1OCBzbGF2ZV90eXBlX251bTsNCj4gPiArCXUzMiBkZXZhcGNfaXJxOw0KPiA+ICsJc2l6 ZV90IHNpemU7DQo+ID4gKwlpbnQgaSwgcmV0Ow0KPiA+ICsNCj4gPiArCWlmIChJU19FUlIobm9k ZSkpDQo+ID4gKwkJcmV0dXJuIC1FTk9ERVY7DQo+ID4gKw0KPiA+ICsJZGV2YXBjX2N0eCA9IGRl dm1fa3phbGxvYygmcGRldi0+ZGV2LCBzaXplb2Yoc3RydWN0IG10a19kZXZhcGNfY29udGV4dCks DQo+ID4gKwkJCQkgIEdGUF9LRVJORUwpOw0KPiA+ICsJaWYgKCFkZXZhcGNfY3R4KQ0KPiA+ICsJ CXJldHVybiAtRU5PTUVNOw0KPiA+ICsNCj4gPiArCWlmIChvZl9wcm9wZXJ0eV9yZWFkX3U4KG5v ZGUsICJtZWRpYXRlay1zbHZfdHlwZV9udW0iLCAmc2xhdmVfdHlwZV9udW0pKQ0KPiA+ICsJCXJl dHVybiAtRU5YSU87DQo+ID4gKw0KPiA+ICsJZGV2YXBjX2N0eC0+c2xhdmVfdHlwZV9udW0gPSBz bGF2ZV90eXBlX251bTsNCj4gPiArDQo+ID4gKwlzaXplID0gc2xhdmVfdHlwZV9udW0gKiBzaXpl b2Yodm9pZCAqKTsNCj4gPiArCWRldmFwY19jdHgtPmRldmFwY19wZF9iYXNlID0gZGV2bV9remFs bG9jKCZwZGV2LT5kZXYsIHNpemUsIEdGUF9LRVJORUwpOw0KPiA+ICsJaWYgKCFkZXZhcGNfY3R4 LT5kZXZhcGNfcGRfYmFzZSkNCj4gPiArCQlyZXR1cm4gLUVOT01FTTsNCj4gPiArDQo+ID4gKwlz aXplID0gc2xhdmVfdHlwZV9udW0gKiBzaXplb2Yoc3RydWN0IG10a19kZXZpY2VfaW5mbyAqKTsN Cj4gPiArCWRldmFwY19jdHgtPmRldmljZV9pbmZvID0gZGV2bV9remFsbG9jKCZwZGV2LT5kZXYs IHNpemUsIEdGUF9LRVJORUwpOw0KPiA+ICsJaWYgKCFkZXZhcGNfY3R4LT5kZXZpY2VfaW5mbykN Cj4gPiArCQlyZXR1cm4gLUVOT01FTTsNCj4gPiArDQo+ID4gKwlmb3IgKGkgPSAwOyBpIDwgc2xh dmVfdHlwZV9udW07IGkrKykgew0KPiA+ICsJCWRldmFwY19jdHgtPmRldmFwY19wZF9iYXNlW2ld ID0gb2ZfaW9tYXAobm9kZSwgaSk7DQo+ID4gKwkJaWYgKCFkZXZhcGNfY3R4LT5kZXZhcGNfcGRf YmFzZVtpXSkNCj4gPiArCQkJcmV0dXJuIC1FSU5WQUw7DQo+ID4gKw0KPiA+ICsJCWlmIChpID09 IDApDQo+ID4gKwkJCWRldmFwY19jdHgtPmRldmljZV9pbmZvW2ldID0gbXRrX2RldmljZXNfaW5m cmE7DQo+ID4gKwl9DQo+ID4gKw0KPiA+ICsJc2l6ZSA9IHNpemVvZihzdHJ1Y3QgbXRrX2RldmFw Y192aW9faW5mbyk7DQo+ID4gKwlkZXZhcGNfY3R4LT52aW9faW5mbyA9IGRldm1fa3phbGxvYygm cGRldi0+ZGV2LCBzaXplLCBHRlBfS0VSTkVMKTsNCj4gPiArCWlmICghZGV2YXBjX2N0eC0+dmlv X2luZm8pDQo+ID4gKwkJcmV0dXJuIC1FTk9NRU07DQo+ID4gKw0KPiA+ICsJdmlvX2RiZ3NfbnVt ID0gb2ZfcHJvcGVydHlfY291bnRfdTMyX2VsZW1zKG5vZGUsICJtZWRpYXRlay12aW9fZGJncyIp Ow0KPiA+ICsJaWYgKHZpb19kYmdzX251bSA8PSAwKQ0KPiA+ICsJCXJldHVybiAtRU5YSU87DQo+ ID4gKw0KPiA+ICsJc2l6ZSA9ICh2aW9fZGJnc19udW0gLyAyKSAqIHNpemVvZihzdHJ1Y3QgbXRr X2RldmFwY192aW9fZGJnc19kZXNjKTsNCj4gPiArCWRldmFwY19jdHgtPnZpb19kYmdzX2Rlc2Mg PSBkZXZtX2t6YWxsb2MoJnBkZXYtPmRldiwgc2l6ZSwgR0ZQX0tFUk5FTCk7DQo+ID4gKwlpZiAo IWRldmFwY19jdHgtPnZpb19kYmdzX2Rlc2MpDQo+ID4gKwkJcmV0dXJuIC1FTk9NRU07DQo+ID4g Kw0KPiA+ICsJZm9yIChpID0gMDsgaSA8IHZpb19kYmdzX251bSAvIDI7IGkrKykgew0KPiA+ICsJ CWlmIChvZl9wcm9wZXJ0eV9yZWFkX3UzMl9pbmRleChub2RlLCAibWVkaWF0ZWstdmlvX2RiZ3Mi LA0KPiA+ICsJCQkJCSAgICAgICBpICogMiwNCj4gPiArCQkJCQkgICAgICAgJmRldmFwY19jdHgt PnZpb19kYmdzX2Rlc2NbaV0ubWFzaykpDQo+ID4gKwkJCXJldHVybiAtRU5YSU87DQo+ID4gKw0K PiA+ICsJCWlmIChvZl9wcm9wZXJ0eV9yZWFkX3UzMl9pbmRleChub2RlLCAibWVkaWF0ZWstdmlv X2RiZ3MiLA0KPiA+ICsJCQkJCSAgICAgICAoaSAqIDIpICsgMSwNCj4gPiArCQkJCQkgICAgICAg JmRldmFwY19jdHgtPnZpb19kYmdzX2Rlc2NbaV0uc3RhcnRfYml0KSkNCj4gPiArCQkJcmV0dXJu IC1FTlhJTzsNCj4gPiArCX0NCj4gPiArDQo+ID4gKwlwZHNfbnVtID0gb2ZfcHJvcGVydHlfY291 bnRfdTMyX2VsZW1zKG5vZGUsICJtZWRpYXRlay1wZHNfb2Zmc2V0Iik7DQo+ID4gKwlpZiAocGRz X251bSA8PSAwKQ0KPiA+ICsJCXJldHVybiAtRU5YSU87DQo+ID4gKw0KPiA+ICsJc2l6ZSA9IHBk c19udW0gKiBzaXplb2YodTMyKTsNCj4gPiArCWRldmFwY19jdHgtPnBkc19vZmZzZXQgPSBkZXZt X2t6YWxsb2MoJnBkZXYtPmRldiwgc2l6ZSwgR0ZQX0tFUk5FTCk7DQo+ID4gKwlpZiAoIWRldmFw Y19jdHgtPnBkc19vZmZzZXQpDQo+ID4gKwkJcmV0dXJuIC1FTk9NRU07DQo+ID4gKw0KPiA+ICsJ Zm9yIChpID0gMDsgaSA8IHBkc19udW07IGkrKykgew0KPiA+ICsJCWlmIChvZl9wcm9wZXJ0eV9y ZWFkX3UzMl9pbmRleChub2RlLCAibWVkaWF0ZWstcGRzX29mZnNldCIsIGksDQo+ID4gKwkJCQkJ ICAgICAgICZkZXZhcGNfY3R4LT5wZHNfb2Zmc2V0W2ldKSkNCj4gPiArCQkJcmV0dXJuIC1FTlhJ TzsNCj4gPiArCX0NCj4gPiArDQo+ID4gKwlkZXZhcGNfaXJxID0gaXJxX29mX3BhcnNlX2FuZF9t YXAobm9kZSwgMCk7DQo+ID4gKwlpZiAoIWRldmFwY19pcnEpDQo+ID4gKwkJcmV0dXJuIC1FSU5W QUw7DQo+ID4gKw0KPiA+ICsJZGV2YXBjX2luZnJhX2NsayA9IGRldm1fY2xrX2dldCgmcGRldi0+ ZGV2LCAiZGV2YXBjLWluZnJhLWNsb2NrIik7DQo+ID4gKwlpZiAoSVNfRVJSKGRldmFwY19pbmZy YV9jbGspKQ0KPiA+ICsJCXJldHVybiAtRUlOVkFMOw0KPiA+ICsNCj4gPiArCWlmIChjbGtfcHJl cGFyZV9lbmFibGUoZGV2YXBjX2luZnJhX2NsaykpDQo+ID4gKwkJcmV0dXJuIC1FSU5WQUw7DQo+ ID4gKw0KPiA+ICsJc3RhcnRfZGV2YXBjKGRldmFwY19jdHgpOw0KPiA+ICsNCj4gPiArCXJldCA9 IGRldm1fcmVxdWVzdF9pcnEoJnBkZXYtPmRldiwgZGV2YXBjX2lycSwNCj4gPiArCQkJICAgICAg IChpcnFfaGFuZGxlcl90KWRldmFwY192aW9sYXRpb25faXJxLA0KPiA+ICsJCQkgICAgICAgSVJR Rl9UUklHR0VSX05PTkUsICJkZXZhcGMiLCBkZXZhcGNfY3R4KTsNCj4gPiArCWlmIChyZXQpDQo+ ID4gKwkJcmV0dXJuIHJldDsNCj4gPiArDQo+ID4gKwlyZXR1cm4gMDsNCj4gPiArfQ0KPiA+ICsN Cj4gPiArc3RhdGljIGludCBtdGtfZGV2YXBjX3JlbW92ZShzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNl ICpkZXYpDQo+ID4gK3sNCj4gPiArCXJldHVybiAwOw0KPiA+ICt9DQo+ID4gKw0KPiA+ICtzdGF0 aWMgY29uc3Qgc3RydWN0IG9mX2RldmljZV9pZCBtdGtfZGV2YXBjX2R0X21hdGNoW10gPSB7DQo+ ID4gKwl7IC5jb21wYXRpYmxlID0gIm1lZGlhdGVrLG10Njc3OS1kZXZhcGMiIH0sDQo+ID4gKwl7 fSwNCj4gPiArfTsNCj4gPiArDQo+ID4gK3N0YXRpYyBzdHJ1Y3QgcGxhdGZvcm1fZHJpdmVyIG10 a19kZXZhcGNfZHJpdmVyID0gew0KPiA+ICsJLnByb2JlID0gbXRrX2RldmFwY19wcm9iZSwNCj4g PiArCS5yZW1vdmUgPSBtdGtfZGV2YXBjX3JlbW92ZSwNCj4gPiArCS5kcml2ZXIgPSB7DQo+ID4g KwkJLm5hbWUgPSBLQlVJTERfTU9ETkFNRSwNCj4gPiArCQkub2ZfbWF0Y2hfdGFibGUgPSBtdGtf ZGV2YXBjX2R0X21hdGNoLA0KPiA+ICsJfSwNCj4gPiArfTsNCj4gPiArDQo+ID4gK21vZHVsZV9w bGF0Zm9ybV9kcml2ZXIobXRrX2RldmFwY19kcml2ZXIpOw0KPiA+ICsNCj4gPiArTU9EVUxFX0RF U0NSSVBUSU9OKCJNZWRpYXRlayBEZXZpY2UgQVBDIERyaXZlciIpOw0KPiA+ICtNT0RVTEVfQVVU SE9SKCJOZWFsIExpdSA8bmVhbC5saXVAbWVkaWF0ZWsuY29tPiIpOw0KPiA+ICtNT0RVTEVfTElD RU5TRSgiR1BMIik7DQo+ID4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvc29jL21lZGlhdGVrL210ay1k ZXZhcGMuaCBiL2RyaXZlcnMvc29jL21lZGlhdGVrL210ay1kZXZhcGMuaA0KPiA+IG5ldyBmaWxl IG1vZGUgMTAwNjQ0DQo+ID4gaW5kZXggMDAwMDAwMC4uYWIyY2IxNA0KPiA+IC0tLSAvZGV2L251 bGwNCj4gPiArKysgYi9kcml2ZXJzL3NvYy9tZWRpYXRlay9tdGstZGV2YXBjLmgNCj4gPiBAQCAt MCwwICsxLDY3MCBAQA0KPiA+ICsvKiBTUERYLUxpY2Vuc2UtSWRlbnRpZmllcjogR1BMLTIuMCAq Lw0KPiA+ICsvKg0KPiA+ICsgKiBDb3B5cmlnaHQgKEMpIDIwMjAgTWVkaWFUZWsgSW5jLg0KPiA+ ICsgKi8NCj4gPiArDQo+ID4gKyNpZm5kZWYgX19NVEtfREVWQVBDX0hfXw0KPiA+ICsjZGVmaW5l IF9fTVRLX0RFVkFQQ19IX18NCj4gPiArDQo+ID4gKyNkZWZpbmUgUEZYCQkJIltERVZBUENdOiAi DQo+IA0KPiB1c2UgZGV2X2VycigpIGFuZCBmcmllbmRzIGluc3RlYWQuDQoNCk9rYXksIEknbGwg cmVtb3ZlIGl0Lg0KDQo+IA0KPiA+ICsNCj4gPiArI2RlZmluZSBWSU9fTUFTS19TVEFfUkVHX0dF VChtKSBcDQo+ID4gKyh7IFwNCj4gPiArCXR5cGVvZihtKSAoX20pID0gKG0pOyBcDQo+ID4gKwly ZWdfaW5kZXggPSBfbSAvIDMyOyBcDQo+ID4gKwlyZWdfb2Zmc2V0ID0gX20gJSAzMjsgXA0KPiA+ ICt9KQ0KPiANCj4gZG9uJ3QgZG8gdGhhdC4gbm8gZXhwbGljaXQgdmFyaWFibGUgYXNzaW5nbWVu dCBpbiBhIG1hY3JvLCB0aGUgbWFjcm8gc2hvdWxkIA0KPiByZXR1cm4gdGhlIHZhbHVlLg0KDQpP a2F5LCBJJ2xsIHJldmlzZSBpdCBpbiBuZXh0IHBhdGNoZXMuDQoNCj4gDQo+ID4gKw0KPiA+ICtl bnVtIERFVkFQQ19QRF9SRUdfVFlQRSB7DQo+ID4gKwlWSU9fTUFTSyA9IDAsDQo+ID4gKwlWSU9f U1RBLA0KPiA+ICsJVklPX0RCRzAsDQo+ID4gKwlWSU9fREJHMSwNCj4gPiArCUFQQ19DT04sDQo+ ID4gKwlWSU9fU0hJRlRfU1RBLA0KPiA+ICsJVklPX1NISUZUX1NFTCwNCj4gPiArCVZJT19TSElG VF9DT04sDQo+ID4gKwlQRF9SRUdfVFlQRV9OVU0sDQo+ID4gK307DQo+ID4gKw0KPiA+ICtlbnVt IERFVkFQQ19WSU9fREJHU19UWVBFIHsNCj4gPiArCU1TVElEID0gMCwNCj4gPiArCURNTklELA0K PiA+ICsJVklPX1csDQo+ID4gKwlWSU9fUiwNCj4gPiArCUFERFJfSCwNCj4gPiArfTsNCj4gPiAr DQo+ID4gK3N0cnVjdCBtdGtfZGV2aWNlX2luZm8gew0KPiA+ICsJaW50IHN5c19pbmRleDsNCj4g PiArCWludCBjdHJsX2luZGV4Ow0KPiA+ICsJaW50IHZpb19pbmRleDsNCj4gPiArfTsNCj4gPiAr DQo+ID4gK3N0YXRpYyBzdHJ1Y3QgbXRrX2RldmljZV9pbmZvIG10a19kZXZpY2VzX2luZnJhW10g PSB7DQo+IA0KPiBUaGF0J3MgZm9yIG10Njc3OSwgY29ycmVjdD8gU2hvdWxkIGJlIHN0YXRlZCBp biB0aGUgbmFtZS4NCg0KT2theS4gSSBoYXZlIGFub3RoZXIgd2F5IHRvIHJlYWNoIHRoZSBnb2Fs IHdpdGhvdXQgdXNpbmcgdGhpcyBzdHJ1Y3QNCmFycmF5LiBJJ2xsIHNlbmQgYW5vdGhlciBwYXRj aGVzLg0KDQo+IA0KPiA+ICsJLyogc3lzX2lkeCwgY3RybF9pZHgsIHZpb19pZHggKi8NCj4gPiAr CS8qIDAgKi8NCj4gPiArCXswLCAwLCAwfSwNCj4gPiArCXswLCAxLCAxfSwNCj4gPiArCXswLCAy LCAyfSwNCj4gPiArCXswLCAzLCAzfSwNCj4gPiArCXswLCA0LCA0fSwNCj4gPiArCXswLCA1LCA1 fSwNCj4gPiArCXswLCA2LCA2fSwNCj4gPiArCXswLCA3LCA3fSwNCj4gPiArCXswLCA4LCA4fSwN Cj4gPiArCXswLCA5LCA5fSwNCj4gPiArDQo+ID4gKwkvKiAxMCAqLw0KPiA+ICsJezAsIDEwLCAx MH0sDQo+ID4gKwl7MCwgMTEsIDExfSwNCj4gPiArCXswLCAxMiwgMTJ9LA0KPiA+ICsJezAsIDEz LCAxM30sDQo+ID4gKwl7MCwgMTQsIDE0fSwNCj4gPiArCXswLCAxNSwgMTV9LA0KPiA+ICsJezAs IDE2LCAxNn0sDQo+ID4gKwl7MCwgMTcsIDE3fSwNCj4gPiArCXswLCAxOCwgMTh9LA0KPiA+ICsJ ezAsIDE5LCAxOX0sDQo+ID4gKw0KPiA+ICsJLyogMjAgKi8NCj4gPiArCXswLCAyMCwgMjB9LA0K PiA+ICsJezAsIDIxLCAyMX0sDQo+ID4gKwl7MCwgMjIsIDIyfSwNCj4gPiArCXswLCAyMywgMjN9 LA0KPiA+ICsJezAsIDI0LCAyNH0sDQo+ID4gKwl7MCwgMjUsIDI1fSwNCj4gPiArCXswLCAyNiwg MjZ9LA0KPiA+ICsJezAsIDI3LCAyN30sDQo+ID4gKwl7MCwgMjgsIDI4fSwNCj4gPiArCXswLCAy OSwgMjl9LA0KPiA+ICsNCj4gPiArCS8qIDMwICovDQo+ID4gKwl7MCwgMzAsIDMwfSwNCj4gPiAr CXswLCAzMSwgMzF9LA0KPiA+ICsJezAsIDMyLCAzMn0sDQo+ID4gKwl7MCwgMzMsIDc3fSwNCj4g PiArCXswLCAzNCwgNzh9LA0KPiA+ICsJezAsIDM1LCA3OX0sDQo+ID4gKwl7MCwgMzUsIDgwfSwN Cj4gPiArCXswLCAzNywgMzd9LA0KPiA+ICsJezAsIDM4LCAzOH0sDQo+ID4gKwl7MCwgMzksIDM5 fSwNCj4gPiArDQo+ID4gKwkvKiA0MCAqLw0KPiA+ICsJezAsIDQwLCA0MH0sDQo+ID4gKwl7MCwg NDEsIDQxfSwNCj4gPiArCXswLCA0MiwgNDJ9LA0KPiA+ICsJezAsIDQzLCA0M30sDQo+ID4gKwl7 MCwgNDQsIDQ0fSwNCj4gPiArCXswLCA0NSwgNDV9LA0KPiA+ICsJezAsIDQ2LCA0Nn0sDQo+ID4g Kwl7MCwgNDcsIDQ3fSwNCj4gPiArCXswLCA0OCwgNDh9LA0KPiA+ICsJezAsIDQ5LCA0OX0sDQo+ ID4gKw0KPiA+ICsJLyogNTAgKi8NCj4gPiArCXswLCA1MCwgNTB9LA0KPiA+ICsJezAsIDUxLCA1 MX0sDQo+ID4gKwl7MCwgNTIsIDUyfSwNCj4gPiArCXswLCA1MywgNTN9LA0KPiA+ICsJezAsIDU0 LCA1NH0sDQo+ID4gKwl7MCwgNTUsIDU1fSwNCj4gPiArCXswLCA1NiwgNTZ9LA0KPiA+ICsJezAs IDU3LCA1N30sDQo+ID4gKwl7MCwgNTgsIDU4fSwNCj4gPiArCXswLCA1OSwgNTl9LA0KPiA+ICsN Cj4gPiArCS8qIDYwICovDQo+ID4gKwl7MCwgNjAsIDYwfSwNCj4gPiArCXswLCA2MSwgNjF9LA0K PiA+ICsJezAsIDYyLCA2Mn0sDQo+ID4gKwl7MCwgNjMsIDYzfSwNCj4gPiArCXswLCA2NCwgNjR9 LA0KPiA+ICsJezAsIDY1LCA3MH0sDQo+ID4gKwl7MCwgNjYsIDcxfSwNCj4gPiArCXswLCA2Nywg NzJ9LA0KPiA+ICsJezAsIDY4LCA3M30sDQo+ID4gKwl7MCwgNzAsIDgxfSwNCj4gPiArDQo+ID4g KwkvKiA3MCAqLw0KPiA+ICsJezAsIDcxLCA4Mn0sDQo+ID4gKwl7MCwgNzIsIDgzfSwNCj4gPiAr CXswLCA3MywgODR9LA0KPiA+ICsJezAsIDc0LCA4NX0sDQo+ID4gKwl7MCwgNzUsIDg2fSwNCj4g PiArCXswLCA3NiwgODd9LA0KPiA+ICsJezAsIDc3LCA4OH0sDQo+ID4gKwl7MCwgNzgsIDg5fSwN Cj4gPiArCXswLCA3OSwgOTB9LA0KPiA+ICsJezAsIDgwLCA5MX0sDQo+ID4gKw0KPiA+ICsJLyog ODAgKi8NCj4gPiArCXswLCA4MSwgOTJ9LA0KPiA+ICsJezAsIDgyLCA5M30sDQo+ID4gKwl7MCwg ODMsIDk0fSwNCj4gPiArCXswLCA4NCwgOTV9LA0KPiA+ICsJezAsIDg1LCA5Nn0sDQo+ID4gKwl7 MCwgODYsIDk3fSwNCj4gPiArCXswLCA4NywgOTh9LA0KPiA+ICsJezAsIDg4LCA5OX0sDQo+ID4g Kwl7MCwgODksIDEwMH0sDQo+ID4gKwl7MCwgOTAsIDEwMX0sDQo+ID4gKw0KPiA+ICsJLyogOTAg Ki8NCj4gPiArCXswLCA5MSwgMTAyfSwNCj4gPiArCXswLCA5MiwgMTAzfSwNCj4gPiArCXswLCA5 MywgMTA0fSwNCj4gPiArCXswLCA5NCwgMTA1fSwNCj4gPiArCXswLCA5NSwgMTA2fSwNCj4gPiAr CXswLCA5NiwgMTA3fSwNCj4gPiArCXswLCA5NywgMTA4fSwNCj4gPiArCXswLCA5OCwgMTA5fSwN Cj4gPiArCXswLCAxMTAsIDExMH0sDQo+ID4gKwl7MCwgMTExLCAxMTF9LA0KPiA+ICsNCj4gPiAr CS8qIDEwMCAqLw0KPiA+ICsJezAsIDExMiwgMTEyfSwNCj4gPiArCXswLCAxMTMsIDExM30sDQo+ ID4gKwl7MCwgMTE0LCAxMTR9LA0KPiA+ICsJezAsIDExNSwgMTE1fSwNCj4gPiArCXswLCAxMTYs IDExNn0sDQo+ID4gKwl7MCwgMTE3LCAxMTd9LA0KPiA+ICsJezAsIDExOCwgMTE4fSwNCj4gPiAr CXswLCAxMTksIDExOX0sDQo+ID4gKwl7MCwgMTIwLCAxMjB9LA0KPiA+ICsJezAsIDEyMSwgMTIx fSwNCj4gPiArDQo+ID4gKwkvKiAxMTAgKi8NCj4gPiArCXswLCAxMjIsIDEyMn0sDQo+ID4gKwl7 MCwgMTIzLCAxMjN9LA0KPiA+ICsJezAsIDEyNCwgMTI0fSwNCj4gPiArCXswLCAxMjUsIDEyNX0s DQo+ID4gKwl7MCwgMTI2LCAxMjZ9LA0KPiA+ICsJezAsIDEyNywgMTI3fSwNCj4gPiArCXswLCAx MjgsIDEyOH0sDQo+ID4gKwl7MCwgMTI5LCAxMjl9LA0KPiA+ICsJezAsIDEzMCwgMTMwfSwNCj4g PiArCXswLCAxMzEsIDEzMX0sDQo+ID4gKw0KPiA+ICsJLyogMTIwICovDQo+ID4gKwl7MCwgMTMy LCAxMzJ9LA0KPiA+ICsJezAsIDEzMywgMTMzfSwNCj4gPiArCXswLCAxMzQsIDEzNH0sDQo+ID4g Kwl7MCwgMTM1LCAxMzV9LA0KPiA+ICsJezAsIDEzNiwgMTM2fSwNCj4gPiArCXswLCAxMzcsIDEz N30sDQo+ID4gKwl7MCwgMTM4LCAxMzh9LA0KPiA+ICsJezAsIDEzOSwgMTM5fSwNCj4gPiArCXsw LCAxNDAsIDE0MH0sDQo+ID4gKwl7MCwgMTQxLCAxNDF9LA0KPiA+ICsNCj4gPiArCS8qIDEzMCAq Lw0KPiA+ICsJezAsIDE0MiwgMTQyfSwNCj4gPiArCXswLCAxNDMsIDE0M30sDQo+ID4gKwl7MCwg MTQ0LCAxNDR9LA0KPiA+ICsJezAsIDE0NSwgMTQ1fSwNCj4gPiArCXswLCAxNDYsIDE0Nn0sDQo+ ID4gKwl7MCwgMTQ3LCAxNDd9LA0KPiA+ICsJezAsIDE0OCwgMTQ4fSwNCj4gPiArCXswLCAxNDks IDE0OX0sDQo+ID4gKwl7MCwgMTUwLCAxNTB9LA0KPiA+ICsJezAsIDE1MSwgMTUxfSwNCj4gPiAr DQo+ID4gKwkvKiAxNDAgKi8NCj4gPiArCXswLCAxNTIsIDE1Mn0sDQo+ID4gKwl7MCwgMTUzLCAx NTN9LA0KPiA+ICsJezAsIDE1NCwgMTU0fSwNCj4gPiArCXswLCAxNTUsIDE1NX0sDQo+ID4gKwl7 MCwgMTU2LCAxNTZ9LA0KPiA+ICsJezAsIDE1NywgMTU3fSwNCj4gPiArCXswLCAxNTgsIDE1OH0s DQo+ID4gKwl7MCwgMTU5LCAxNTl9LA0KPiA+ICsJezAsIDE2MCwgMTYwfSwNCj4gPiArCXswLCAx NjEsIDE2MX0sDQo+ID4gKw0KPiA+ICsJLyogMTUwICovDQo+ID4gKwl7MCwgMTYyLCAxNjJ9LA0K PiA+ICsJezAsIDE2MywgMTYzfSwNCj4gPiArCXswLCAxNjQsIDE2NH0sDQo+ID4gKwl7MCwgMTY1 LCAxNjV9LA0KPiA+ICsJezAsIDE2NiwgMTY2fSwNCj4gPiArCXswLCAxNjcsIDE2N30sDQo+ID4g Kwl7MCwgMTY4LCAxNjh9LA0KPiA+ICsJezAsIDE2OSwgMTY5fSwNCj4gPiArCXswLCAxNzAsIDE3 MH0sDQo+ID4gKwl7MCwgMTcxLCAxNzF9LA0KPiA+ICsNCj4gPiArCS8qIDE2MCAqLw0KPiA+ICsJ ezAsIDE3MiwgMTcyfSwNCj4gPiArCXswLCAxNzMsIDE3M30sDQo+ID4gKwl7MCwgMTc0LCAxNzR9 LA0KPiA+ICsJezAsIDE3NSwgMTc1fSwNCj4gPiArCXswLCAxNzYsIDE3Nn0sDQo+ID4gKwl7MCwg MTc3LCAxNzd9LA0KPiA+ICsJezAsIDE3OCwgMTc4fSwNCj4gPiArCXswLCAxNzksIDE3OX0sDQo+ ID4gKwl7MCwgMTgwLCAxODB9LA0KPiA+ICsJezAsIDE4MSwgMTgxfSwNCj4gPiArDQo+ID4gKwkv KiAxNzAgKi8NCj4gPiArCXswLCAxODIsIDE4Mn0sDQo+ID4gKwl7MCwgMTgzLCAxODN9LA0KPiA+ ICsJezAsIDE4NCwgMTg0fSwNCj4gPiArCXswLCAxODUsIDE4NX0sDQo+ID4gKwl7MCwgMTg2LCAx ODZ9LA0KPiA+ICsJezAsIDE4NywgMTg3fSwNCj4gPiArCXswLCAxODgsIDE4OH0sDQo+ID4gKwl7 MCwgMTg5LCAxODl9LA0KPiA+ICsJezAsIDE5MCwgMTkwfSwNCj4gPiArCXswLCAxOTEsIDE5MX0s DQo+ID4gKw0KPiA+ICsJLyogMTgwICovDQo+ID4gKwl7MCwgMTkyLCAxOTJ9LA0KPiA+ICsJezAs IDE5MywgMTkzfSwNCj4gPiArCXswLCAxOTQsIDE5NH0sDQo+ID4gKwl7MCwgMTk1LCAxOTV9LA0K PiA+ICsJezAsIDE5NiwgMTk2fSwNCj4gPiArCXswLCAxOTcsIDE5N30sDQo+ID4gKwl7MCwgMTk4 LCAxOTh9LA0KPiA+ICsJezAsIDE5OSwgMTk5fSwNCj4gPiArCXswLCAyMDAsIDIwMH0sDQo+ID4g Kwl7MCwgMjAxLCAyMDF9LA0KPiA+ICsNCj4gPiArCS8qIDE5MCAqLw0KPiA+ICsJezAsIDIwMiwg MjAyfSwNCj4gPiArCXswLCAyMDMsIDIwM30sDQo+ID4gKwl7MCwgMjA0LCAyMDR9LA0KPiA+ICsJ ezAsIDIwNSwgMjA1fSwNCj4gPiArCXswLCAyMDYsIDIwNn0sDQo+ID4gKwl7MCwgMjA3LCAyMDd9 LA0KPiA+ICsJezAsIDIwOCwgMjA4fSwNCj4gPiArCXswLCAyMDksIDIwOX0sDQo+ID4gKwl7MCwg MjEwLCAyMTB9LA0KPiA+ICsJezAsIDIxMSwgMjExfSwNCj4gPiArDQo+ID4gKwkvKiAyMDAgKi8N Cj4gPiArCXswLCAyMTIsIDIxMn0sDQo+ID4gKwl7MCwgMjEzLCAyMTN9LA0KPiA+ICsJezAsIDIx NCwgMjE0fSwNCj4gPiArCXswLCAyMTUsIDIxNX0sDQo+ID4gKwl7MCwgMjE2LCAyMTZ9LA0KPiA+ ICsJezAsIDIxNywgMjE3fSwNCj4gPiArCXswLCAyMTgsIDIxOH0sDQo+ID4gKwl7MCwgMjE5LCAy MTl9LA0KPiA+ICsJezAsIDIyMCwgMjIwfSwNCj4gPiArCXswLCAyMjEsIDIyMX0sDQo+ID4gKw0K PiA+ICsJLyogMjEwICovDQo+ID4gKwl7MCwgMjIyLCAyMjJ9LA0KPiA+ICsJezAsIDIyMywgMjIz fSwNCj4gPiArCXswLCAyMjQsIDIyNH0sDQo+ID4gKwl7MCwgMjI1LCAyMjV9LA0KPiA+ICsJezAs IDIyNiwgMjI2fSwNCj4gPiArCXswLCAyMjcsIDIyN30sDQo+ID4gKwl7MCwgMjI4LCAyMjh9LA0K PiA+ICsJezAsIDIyOSwgMjI5fSwNCj4gPiArCXswLCAyMzAsIDIzMH0sDQo+ID4gKwl7MCwgMjMx LCAyMzF9LA0KPiA+ICsNCj4gPiArCS8qIDIyMCAqLw0KPiA+ICsJezEsIDAsIDIzMn0sDQo+ID4g Kwl7MSwgMSwgMjMzfSwNCj4gPiArCXsxLCAyLCAyMzR9LA0KPiA+ICsJezEsIDMsIDIzNX0sDQo+ ID4gKwl7MSwgNCwgMjM2fSwNCj4gPiArCXsxLCA1LCAyMzd9LA0KPiA+ICsJezEsIDYsIDIzOH0s DQo+ID4gKwl7MSwgNywgMjM5fSwNCj4gPiArCXsxLCA4LCAyNDB9LA0KPiA+ICsJezEsIDksIDI0 MX0sDQo+ID4gKw0KPiA+ICsJLyogMjMwICovDQo+ID4gKwl7MSwgMTAsIDI0Mn0sDQo+ID4gKwl7 MSwgMTEsIDI0M30sDQo+ID4gKwl7MSwgMTIsIDI0NH0sDQo+ID4gKwl7MSwgMTMsIDI0NX0sDQo+ ID4gKwl7MSwgMTQsIDI0Nn0sDQo+ID4gKwl7MSwgMTUsIDI0N30sDQo+ID4gKwl7MSwgMTYsIDI0 OH0sDQo+ID4gKwl7MSwgMTcsIDI0OX0sDQo+ID4gKwl7MSwgMTgsIDI1MH0sDQo+ID4gKwl7MSwg MTksIDI1MX0sDQo+ID4gKw0KPiA+ICsJLyogMjQwICovDQo+ID4gKwl7MSwgMjAsIDI1Mn0sDQo+ ID4gKwl7MSwgMjEsIDI1M30sDQo+ID4gKwl7MSwgMjIsIDI1NH0sDQo+ID4gKwl7MSwgMjMsIDI1 NX0sDQo+ID4gKwl7MSwgMjQsIDI1Nn0sDQo+ID4gKwl7MSwgMjUsIDI1N30sDQo+ID4gKwl7MSwg MjYsIDI1OH0sDQo+ID4gKwl7MSwgMjcsIDI1OX0sDQo+ID4gKwl7MSwgMjgsIDI2MH0sDQo+ID4g Kwl7MSwgMjksIDI2MX0sDQo+ID4gKw0KPiA+ICsJLyogMjUwICovDQo+ID4gKwl7MSwgMzAsIDI2 Mn0sDQo+ID4gKwl7MSwgMzEsIDI2M30sDQo+ID4gKwl7MSwgMzIsIDI2NH0sDQo+ID4gKwl7MSwg MzMsIDI2NX0sDQo+ID4gKwl7MSwgMzQsIDI2Nn0sDQo+ID4gKwl7MSwgMzUsIDI2N30sDQo+ID4g Kwl7MSwgMzYsIDI2OH0sDQo+ID4gKwl7MSwgMzcsIDI2OX0sDQo+ID4gKwl7MSwgMzgsIDI3MH0s DQo+ID4gKwl7MSwgMzksIDI3MX0sDQo+ID4gKw0KPiA+ICsJLyogMjYwICovDQo+ID4gKwl7MSwg NDAsIDI3Mn0sDQo+ID4gKwl7MSwgNDEsIDI3M30sDQo+ID4gKwl7MSwgNDIsIDI3NH0sDQo+ID4g Kwl7MSwgNDMsIDI3NX0sDQo+ID4gKwl7MSwgNDQsIDI3Nn0sDQo+ID4gKwl7MSwgNDUsIDI3N30s DQo+ID4gKwl7MSwgNDYsIDI3OH0sDQo+ID4gKwl7MSwgNDcsIDI3OX0sDQo+ID4gKwl7MSwgNDgs IDI4MH0sDQo+ID4gKwl7MSwgNDksIDI4MX0sDQo+ID4gKw0KPiA+ICsJLyogMjcwICovDQo+ID4g Kwl7MSwgNTAsIDI4Mn0sDQo+ID4gKwl7MSwgNTEsIDI4M30sDQo+ID4gKwl7MSwgNTIsIDI4NH0s DQo+ID4gKwl7MSwgNTMsIDI4NX0sDQo+ID4gKwl7MSwgNTQsIDI4Nn0sDQo+ID4gKwl7MSwgNTUs IDI4N30sDQo+ID4gKwl7MSwgNTYsIDI4OH0sDQo+ID4gKwl7MSwgNTcsIDI4OX0sDQo+ID4gKwl7 MSwgNTgsIDI5MH0sDQo+ID4gKwl7MSwgNTksIDI5MX0sDQo+ID4gKw0KPiA+ICsJLyogMjgwICov DQo+ID4gKwl7MSwgNjAsIDI5Mn0sDQo+ID4gKwl7MSwgNjEsIDI5M30sDQo+ID4gKwl7MSwgNjIs IDI5NH0sDQo+ID4gKwl7MSwgNjMsIDI5NX0sDQo+ID4gKwl7MSwgNjQsIDI5Nn0sDQo+ID4gKwl7 MSwgNjUsIDI5N30sDQo+ID4gKwl7MSwgNjYsIDI5OH0sDQo+ID4gKwl7MSwgNjcsIDI5OX0sDQo+ ID4gKwl7MSwgNjgsIDMwMH0sDQo+ID4gKwl7MSwgNjksIDMwMX0sDQo+ID4gKw0KPiA+ICsJLyog MjkwICovDQo+ID4gKwl7MSwgNzAsIDMwMn0sDQo+ID4gKwl7MSwgNzEsIDMwM30sDQo+ID4gKwl7 MSwgNzIsIDMwNH0sDQo+ID4gKwl7MSwgNzMsIDMwNX0sDQo+ID4gKwl7MSwgNzQsIDMwNn0sDQo+ ID4gKwl7MSwgNzUsIDMwN30sDQo+ID4gKwl7MSwgNzYsIDMwOH0sDQo+ID4gKwl7MSwgNzcsIDMw OX0sDQo+ID4gKwl7MSwgNzgsIDMxMH0sDQo+ID4gKwl7MSwgNzksIDMxMX0sDQo+ID4gKw0KPiA+ ICsJLyogMzAwICovDQo+ID4gKwl7MSwgODAsIDMxMn0sDQo+ID4gKwl7MSwgODEsIDMxM30sDQo+ ID4gKwl7MSwgODIsIDMxNH0sDQo+ID4gKwl7MSwgODMsIDMxNX0sDQo+ID4gKwl7MSwgODQsIDMx Nn0sDQo+ID4gKwl7MSwgODUsIDMxN30sDQo+ID4gKwl7MSwgODYsIDMxOH0sDQo+ID4gKwl7MSwg ODcsIDMxOX0sDQo+ID4gKwl7MSwgODgsIDMyMH0sDQo+ID4gKwl7MSwgODksIDMyMX0sDQo+ID4g Kw0KPiA+ICsJLyogMzEwICovDQo+ID4gKwl7MSwgOTAsIDMyMn0sDQo+ID4gKwl7MSwgOTEsIDMy M30sDQo+ID4gKwl7MSwgOTIsIDMyNH0sDQo+ID4gKwl7MSwgOTMsIDMyNX0sDQo+ID4gKwl7MSwg OTQsIDMyNn0sDQo+ID4gKwl7MSwgOTUsIDMyN30sDQo+ID4gKwl7MSwgOTYsIDMyOH0sDQo+ID4g Kwl7MSwgOTcsIDMyOX0sDQo+ID4gKwl7MSwgOTgsIDMzMH0sDQo+ID4gKwl7MSwgOTksIDMzMX0s DQo+ID4gKw0KPiA+ICsJLyogMzIwICovDQo+ID4gKwl7MSwgMTAwLCAzMzJ9LA0KPiA+ICsJezEs IDEwMSwgMzMzfSwNCj4gPiArCXsxLCAxMDIsIDMzNH0sDQo+ID4gKwl7MSwgMTAzLCAzMzV9LA0K PiA+ICsJezEsIDEwNCwgMzM2fSwNCj4gPiArCXsxLCAxMDUsIDMzN30sDQo+ID4gKwl7MSwgMTA2 LCAzMzh9LA0KPiA+ICsJezEsIDEwNywgMzM5fSwNCj4gPiArCXsxLCAxMDgsIDM0MH0sDQo+ID4g Kwl7MSwgMTA5LCAzNDF9LA0KPiA+ICsNCj4gPiArCS8qIDMzMCAqLw0KPiA+ICsJezEsIDExMCwg MzQyfSwNCj4gPiArCXsxLCAxMTEsIDM0M30sDQo+ID4gKwl7MSwgMTEyLCAzNDR9LA0KPiA+ICsJ ezEsIDExMywgMzQ1fSwNCj4gPiArCXsxLCAxMTQsIDM0Nn0sDQo+ID4gKwl7MSwgMTE1LCAzNDd9 LA0KPiA+ICsJezEsIDExNiwgMzQ4fSwNCj4gPiArCXsxLCAxMTcsIDM0OX0sDQo+ID4gKwl7MSwg MTE4LCAzNTB9LA0KPiA+ICsJezEsIDExOSwgMzUxfSwNCj4gPiArDQo+ID4gKwkvKiAzNDAgKi8N Cj4gPiArCXsxLCAxMjAsIDM1Mn0sDQo+ID4gKwl7MSwgMTIxLCAzNTN9LA0KPiA+ICsJezEsIDEy MiwgMzU0fSwNCj4gPiArCXsxLCAxMjMsIDM1NX0sDQo+ID4gKwl7MSwgMTI0LCAzNTZ9LA0KPiA+ ICsJezEsIDEyNSwgMzU3fSwNCj4gPiArCXsxLCAxMjYsIDM1OH0sDQo+ID4gKwl7MSwgMTI3LCAz NTl9LA0KPiA+ICsJezEsIDEyOCwgMzYwfSwNCj4gPiArCXsxLCAxMjksIDM2MX0sDQo+ID4gKw0K PiA+ICsJLyogMzUwICovDQo+ID4gKwl7MSwgMTMwLCAzNjJ9LA0KPiA+ICsJezEsIDEzMSwgMzYz fSwNCj4gPiArCXsxLCAxMzIsIDM2NH0sDQo+ID4gKwl7MSwgMTMzLCAzNjV9LA0KPiA+ICsJezEs IDEzNCwgMzY2fSwNCj4gPiArCXsxLCAxMzUsIDM2N30sDQo+ID4gKwl7MSwgMTM2LCAzNjh9LA0K PiA+ICsJezEsIDEzNywgMzY5fSwNCj4gPiArCXsxLCAxMzgsIDM3MH0sDQo+ID4gKwl7MSwgMTM5 LCAzNzF9LA0KPiA+ICsNCj4gPiArCS8qIDM2MCAqLw0KPiA+ICsJezEsIDE0MCwgMzcyfSwNCj4g PiArCXsxLCAxNDEsIDM3M30sDQo+ID4gKwl7MSwgMTQyLCAzNzR9LA0KPiA+ICsJezEsIDE0Mywg Mzc1fSwNCj4gPiArCXsxLCAxNDQsIDM3Nn0sDQo+ID4gKwl7MSwgMTQ1LCAzNzd9LA0KPiA+ICsJ ezEsIDE0NiwgMzc4fSwNCj4gPiArCXsxLCAxNDcsIDM3OX0sDQo+ID4gKwl7MSwgMTQ4LCAzODB9 LA0KPiA+ICsJezEsIDE0OSwgMzgxfSwNCj4gPiArDQo+ID4gKwkvKiAzNzAgKi8NCj4gPiArCXsx LCAxNTAsIDM4Mn0sDQo+ID4gKwl7MSwgMTUxLCAzODN9LA0KPiA+ICsJezEsIDE1MiwgMzg0fSwN Cj4gPiArCXsxLCAxNTMsIDM4NX0sDQo+ID4gKwl7MSwgMTU0LCAzODZ9LA0KPiA+ICsJezEsIDE1 NSwgMzg3fSwNCj4gPiArCXsxLCAxNTYsIDM4OH0sDQo+ID4gKwl7MSwgMTU3LCAzODl9LA0KPiA+ ICsJezEsIDE1OCwgMzkwfSwNCj4gPiArCXsxLCAxNTksIDM5MX0sDQo+ID4gKw0KPiA+ICsJLyog MzgwICovDQo+ID4gKwl7MSwgMTYwLCAzOTJ9LA0KPiA+ICsJezEsIDE2MSwgMzkzfSwNCj4gPiAr CXsxLCAxNjIsIDM5NH0sDQo+ID4gKwl7MSwgMTYzLCAzOTV9LA0KPiA+ICsJezEsIDE2NCwgMzk2 fSwNCj4gPiArCXsxLCAxNjUsIDM5N30sDQo+ID4gKwl7MSwgMTY2LCAzOTh9LA0KPiA+ICsJezEs IDE2NywgMzk5fSwNCj4gPiArCXsxLCAxNjgsIDQwMH0sDQo+ID4gKwl7MSwgMTY5LCA0MDF9LA0K PiA+ICsNCj4gPiArCS8qIDM5MCAqLw0KPiA+ICsJezEsIDE3MCwgNDAyfSwNCj4gPiArCXsxLCAx NzEsIDQwM30sDQo+ID4gKwl7MSwgMTcyLCA0MDR9LA0KPiA+ICsJezEsIDE3MywgNDA1fSwNCj4g PiArCXsxLCAxNzQsIDQwNn0sDQo+ID4gKwl7MSwgMTc1LCA0MDd9LA0KPiA+ICsJezEsIDE3Niwg NDA4fSwNCj4gPiArCXsxLCAxNzcsIDQwOX0sDQo+ID4gKwl7MSwgMTc4LCA0MTB9LA0KPiA+ICsJ ezEsIDE3OSwgNDExfSwNCj4gPiArDQo+ID4gKwkvKiA0MDAgKi8NCj4gPiArCXsxLCAxODAsIDQx Mn0sDQo+ID4gKwl7MSwgMTgxLCA0MTN9LA0KPiA+ICsJezEsIDE4MiwgNDE0fSwNCj4gPiArCXsx LCAxODMsIDQxNX0sDQo+ID4gKwl7MSwgMTg0LCA0MTZ9LA0KPiA+ICsJezEsIDE4NSwgNDE3fSwN Cj4gPiArCXsxLCAxODYsIDQxOH0sDQo+ID4gKwl7MSwgMTg3LCA0MTl9LA0KPiA+ICsJezEsIDE4 OCwgNDIwfSwNCj4gPiArCXsxLCAxODksIDQyMX0sDQo+ID4gKw0KPiA+ICsJLyogNDEwICovDQo+ ID4gKwl7MSwgMTkwLCA0MjJ9LA0KPiA+ICsJezEsIDE5MSwgNDIzfSwNCj4gPiArCXsxLCAxOTIs IDQyNH0sDQo+ID4gKwl7MSwgMTkzLCA0MjV9LA0KPiA+ICsJezEsIDE5NCwgNDI2fSwNCj4gPiAr CXsxLCAxOTUsIDQyN30sDQo+ID4gKwl7MSwgMTk2LCA0Mjh9LA0KPiA+ICsJezEsIDE5NywgNDI5 fSwNCj4gPiArCXsxLCAxOTgsIDQzMH0sDQo+ID4gKwl7MSwgMTk5LCA0MzF9LA0KPiA+ICsNCj4g PiArCS8qIDQyMCAqLw0KPiA+ICsJezEsIDIwMCwgNDMyfSwNCj4gPiArCXsxLCAyMDEsIDQzM30s DQo+ID4gKwl7MSwgMjAyLCA0MzR9LA0KPiA+ICsJezEsIDIwMywgNDM1fSwNCj4gPiArCXsxLCAy MDQsIDQzNn0sDQo+ID4gKwl7MSwgMjA1LCA0Mzd9LA0KPiA+ICsJezEsIDIwNiwgNDM4fSwNCj4g PiArCXsxLCAyMDcsIDQzOX0sDQo+ID4gKwl7MSwgMjA4LCA0NDB9LA0KPiA+ICsJezEsIDIwOSwg NDQxfSwNCj4gPiArDQo+ID4gKwkvKiA0MzAgKi8NCj4gPiArCXsxLCAyMTAsIDQ0Mn0sDQo+ID4g Kwl7MSwgMjExLCA0NDN9LA0KPiA+ICsJezEsIDIxMiwgNDQ0fSwNCj4gPiArCXsxLCAyMTMsIDQ0 NX0sDQo+ID4gKwl7MSwgMjE0LCA0NDZ9LA0KPiA+ICsJezEsIDIxNSwgNDQ3fSwNCj4gPiArCXsx LCAyMTYsIDQ0OH0sDQo+ID4gKwl7MSwgMjE3LCA0NDl9LA0KPiA+ICsJezEsIDIxOCwgNDUwfSwN Cj4gPiArCXsxLCAyMTksIDQ1MX0sDQo+ID4gKw0KPiA+ICsJLyogNDQwICovDQo+ID4gKwl7MSwg MjIwLCA0NTJ9LA0KPiA+ICsJezEsIDIyMSwgNDUzfSwNCj4gPiArCXsxLCAyMjIsIDQ1NH0sDQo+ ID4gKwl7MSwgMjIzLCA0NTV9LA0KPiA+ICsJezEsIDIyNCwgNDU2fSwNCj4gPiArCXsxLCAyMjUs IDQ1N30sDQo+ID4gKwl7MSwgMjI2LCA0NTh9LA0KPiA+ICsJezEsIDIyNywgNDU5fSwNCj4gPiAr CXsxLCAyMjgsIDQ2MH0sDQo+ID4gKwl7MSwgMjI5LCA0NjF9LA0KPiA+ICsNCj4gPiArCS8qIDQ1 MCAqLw0KPiA+ICsJezEsIDIzMCwgNDYyfSwNCj4gPiArCXsxLCAyMzEsIDQ2M30sDQo+ID4gKwl7 MSwgMjMyLCA0NjR9LA0KPiA+ICsJezEsIDIzMywgNDY1fSwNCj4gPiArCXsxLCAyMzQsIDQ2Nn0s DQo+ID4gKwl7MSwgMjM1LCA0Njd9LA0KPiA+ICsJezEsIDIzNiwgNDY4fSwNCj4gPiArCXsxLCAy MzcsIDQ2OX0sDQo+ID4gKwl7MSwgMjM4LCA0NzB9LA0KPiA+ICsJezEsIDIzOSwgNDcxfSwNCj4g PiArDQo+ID4gKwkvKiA0NjAgKi8NCj4gPiArCXsxLCAyNDAsIDQ3Mn0sDQo+ID4gKwl7MSwgMjQx LCA0NzN9LA0KPiA+ICsJezEsIDI0MiwgNDc0fSwNCj4gPiArCXsxLCAyNDMsIDQ3NX0sDQo+ID4g Kwl7MSwgMjQ0LCA0NzZ9LA0KPiA+ICsJezEsIDI0NSwgNDc3fSwNCj4gPiArCXsxLCAyNDYsIDQ3 OH0sDQo+ID4gKwl7LTEsIC0xLCA0Nzl9LA0KPiA+ICsJey0xLCAtMSwgNDgwfSwNCj4gPiArCXst MSwgLTEsIDQ4MX0sDQo+ID4gKw0KPiA+ICsJLyogNDcwICovDQo+ID4gKwl7LTEsIC0xLCA0ODJ9 LA0KPiA+ICsJey0xLCAtMSwgNDgzfSwNCj4gPiArCXstMSwgLTEsIDQ4NH0sDQo+ID4gKwl7LTEs IC0xLCA0ODV9LA0KPiA+ICsJey0xLCAtMSwgNDg2fSwNCj4gPiArCXstMSwgLTEsIDQ4N30sDQo+ ID4gKwl7LTEsIC0xLCA0ODh9LA0KPiA+ICsJey0xLCAtMSwgNDg5fSwNCj4gPiArCXstMSwgLTEs IDQ5MH0sDQo+ID4gKwl7LTEsIC0xLCA0OTF9LA0KPiA+ICsNCj4gPiArCS8qIDQ4MCAqLw0KPiA+ ICsJey0xLCAtMSwgNDkyfSwNCj4gPiArCXstMSwgLTEsIDQ5M30sDQo+ID4gKwl7LTEsIC0xLCA0 OTR9LA0KPiA+ICsJey0xLCAtMSwgNDk1fSwNCj4gPiArCXstMSwgLTEsIDQ5Nn0sDQo+ID4gKwl7 LTEsIC0xLCA0OTd9LA0KPiA+ICsJey0xLCAtMSwgNDk4fSwNCj4gPiArCXstMSwgLTEsIDQ5OX0s DQo+ID4gKwl7LTEsIC0xLCA1MDB9LA0KPiA+ICsJey0xLCAtMSwgNTAxfSwNCj4gPiArDQo+ID4g KwkvKiA0OTAgKi8NCj4gPiArCXstMSwgLTEsIDUwMn0sDQo+ID4gKwl7LTEsIC0xLCA1MDN9LA0K PiA+ICsJey0xLCAtMSwgNTA0fSwNCj4gPiArCXstMSwgLTEsIDUwNX0sDQo+ID4gKwl7LTEsIC0x LCA1MDZ9LA0KPiA+ICsJey0xLCAtMSwgNTA3fSwNCj4gPiArCXstMSwgLTEsIDUwOH0sDQo+ID4g Kwl7LTEsIC0xLCA1MDl9LA0KPiA+ICsJey0xLCAtMSwgNTEwfSwNCj4gPiArDQo+ID4gK307DQo+ ID4gKw0KPiA+ICtzdHJ1Y3QgbXRrX2RldmFwY192aW9faW5mbyB7DQo+ID4gKwlib29sIHJlYWQ7 DQo+ID4gKwlib29sIHdyaXRlOw0KPiA+ICsJdTMyIHZpb19hZGRyOw0KPiA+ICsJdTMyIHZpb19h ZGRyX2hpZ2g7DQo+ID4gKwl1MzIgbWFzdGVyX2lkOw0KPiA+ICsJdTMyIGRvbWFpbl9pZDsNCj4g PiArfTsNCj4gPiArDQo+ID4gK3N0cnVjdCBtdGtfZGV2YXBjX3Zpb19kYmdzX2Rlc2Mgew0KPiA+ ICsJdTMyIG1hc2s7DQo+ID4gKwl1MzIgc3RhcnRfYml0Ow0KPiA+ICt9Ow0KPiA+ICsNCj4gPiAr c3RydWN0IG10a19kZXZhcGNfY29udGV4dCB7DQo+ID4gKwl1OCBzbGF2ZV90eXBlX251bTsNCj4g PiArCXZvaWQgX19pb21lbSAqKmRldmFwY19wZF9iYXNlOw0KPiA+ICsJY29uc3Qgc3RydWN0IG10 a19kZXZpY2VfaW5mbyAqKmRldmljZV9pbmZvOw0KPiA+ICsJc3RydWN0IG10a19kZXZhcGNfdmlv X2luZm8gKnZpb19pbmZvOw0KPiA+ICsJc3RydWN0IG10a19kZXZhcGNfdmlvX2RiZ3NfZGVzYyAq dmlvX2RiZ3NfZGVzYzsNCj4gPiArCXUzMiAqcGRzX29mZnNldDsNCj4gPiArfTsNCj4gPiArDQo+ IA0KPiBOb3Qgc3VyZSBpZiBJIGdldCB0aGlzIHJpZ2h0Og0KPiANCj4gc3RydWN0IG10a19kZXZh cGNfb2Zmc2V0IHsNCj4gCXUzMiB2aW9fbWFzazsNCj4gCXUzMiB2aW9fc3RhOw0KPiAJdTMyIHZp b19kYmcwOw0KPiAJdTMyIHZpb19kYmcxOw0KPiAJLi4uDQo+IH0NCj4gDQo+IHN0cnVjdCBtdGtf ZGV2YXBjX2NvbnRleHQgew0KPiAJdTggcGRfYmFzZV9udW07DQo+IAl2b2lkIF9faW9tZW0gKipk ZXZhcGNfcGRfYmFzZTsNCj4gCXN0cnVjdCBtdGtfZGV2YXBjX29mZnNldCAqb2Zmc2V0Ow0KPiAJ Y29uc3Qgc3RydWN0IG10a19kZXZpY2VfaW5mbyAqKmRldmljZV9pbmZvOw0KPiAJc3RydWN0IG10 a19kZXZhcGNfdmlvX2luZm8gKnZpb19pbmZvOw0KPiAJc3RydWN0IG10a19kZXZhcGNfdmlvX2Ri Z3NfZGVzYyAqdmlvX2RiZ3NfZGVzYzsNCj4gfTsNCj4gDQo+IFdpdGggdGhpcyBJIHRoaW5rIHdl IGNhbiBnZXQgcmlkIG9mIG10a19kZXZhcGNfcGRfZ2V0KCkuDQo+IA0KDQptdGtfZGV2YXBjX3Bk X2dldCgpIGlzIHVzZWQgdG8gY2FsY3VsYXRlIHRoZSB2YWRkciBvZiBkZXZhcGMgcGQNCnJlZ2lz dGVyLiBJdCdzIGJhc2VkIG9uIGRpZmZlcmVudCBzbGF2ZV90eXBlLCBwZF9yZWdfdHlwZSBhbmQg cmVnX2lkeC4NCkkgZG9uJ3QgdGhpbmsgaXQgY2FuIGJlIHJlcGxhY2VkIHdpdGggc3VjaCBzaW1w bGUgZGF0YSBzdHJ1Y3R1cmVzLg0KDQoNCj4gU29ycnkgSSdtIG5vdCBhYmxlIHRvIHJldmlldyB0 aGUgd2hvbGUgZHJpdmVyIHJpZ2h0IG5vdy4gUGxlYXNlIGFsc28gaGF2ZSBhIGxvb2sgDQo+IG9u IG15IGNvbW1lbnRzIGZyb20gdjEuDQo+IA0KPiBXZSB3aWxsIGhhdmUgdG8gZ28gbGl0dGxlIGJ5 IGxpdHRsZSB0byBnZXQgdGhpcyBpbnRvIGEgZ29vZCBzdGF0ZS4gSW4gY2FzZSBpdCANCj4gbWFr ZXMgc2Vuc2UgdG8gaGF2ZSB0aGlzIGluIHRoZSBrZXJuZWwgYXQgYWxsLg0KPiANCj4gUmVnYXJk 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from [172.21.77.33] (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 13 Jul 2020 15:45:35 +0800 Message-ID: <1594626336.22730.36.camel@mtkswgap22> Subject: Re: [PATCH v2 2/2] soc: mediatek: add mtk-devapc driver From: Neal Liu To: Matthias Brugger Date: Mon, 13 Jul 2020 15:45:36 +0800 In-Reply-To: References: <1594285927-1840-1-git-send-email-neal.liu@mediatek.com> <1594285927-1840-3-git-send-email-neal.liu@mediatek.com> X-Mailer: Evolution 3.2.3-0ubuntu6 MIME-Version: 1.0 X-TM-SNTS-SMTP: 02EEB14808AABAF9D2F91D0886FDE7959125C6CE24A27BAE0F2A544E5BF812232000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200713_034546_514828_59E60AD2 X-CRM114-Status: GOOD ( 27.40 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, wsd_upstream@mediatek.com, lkml , Rob Herring , linux-mediatek@lists.infradead.org, Neal Liu , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Fri, 2020-07-10 at 14:14 +0200, Matthias Brugger wrote: > [snip] > > + > > +static int get_vio_slave_num(int slave_type) > > I have a hard time to understand the usefullness of this, can you please explain. > The basic idea is to get total numbers of slaves. And we can use it to scan all slaves which has been triggered violation. I think I can pass it through DT data instead of using mtk_device_info array. I'll send another patches to change it. > > +{ > > + if (slave_type == 0) > > + return ARRAY_SIZE(mtk_devices_infra); > > + > > + return 0; > > +} > > + > > +static u32 get_shift_group(struct mtk_devapc_context *devapc_ctx, > > + int slave_type, int vio_idx) > > +{ > > + u32 vio_shift_sta; > > + void __iomem *reg; > > + int bit; > > + > > + reg = mtk_devapc_pd_get(devapc_ctx, slave_type, VIO_SHIFT_STA, 0); > > + vio_shift_sta = readl(reg); > > + > > + for (bit = 0; bit < 32; bit++) { > > + if ((vio_shift_sta >> bit) & 0x1) > + break; > > + } > > + > > + return bit; > > We return the first position (from the right) of the rigster with the bit set to > one. Correct? > Can't we use __ffs() for this? Yes, thanks for your reminds to use __ffs(). I'll revise it in next patches. > > > +} > > + > > +static int check_vio_mask_sta(struct mtk_devapc_context *devapc_ctx, > > + int slave_type, u32 module, int pd_reg_type) > > +{ > > + u32 reg_index, reg_offset; > > + void __iomem *reg; > > + u32 value; > > + > > + VIO_MASK_STA_REG_GET(module); > > + > > + reg = mtk_devapc_pd_get(devapc_ctx, slave_type, pd_reg_type, reg_index); > > reg = mtk_devapc_pd_get(devapc_ctx, slave_type, pd_reg_type, > VIO_MOD_TO_REG_IND(module)); Okay, I'll revise it in next patches. > > > + value = readl(reg); > > + > > + return ((value >> reg_offset) & 0x1); > > return ((value >> VIO_MOD_TO_REG_OFF(module)) & 0x1); Okay, I'll revise it in next patches. > > > +} > > + > > +static int check_vio_mask(struct mtk_devapc_context *devapc_ctx, int slave_type, > > + u32 module) > > +{ > > + return check_vio_mask_sta(devapc_ctx, slave_type, module, VIO_MASK); > > +} > > + > > +static int check_vio_status(struct mtk_devapc_context *devapc_ctx, > > + int slave_type, u32 module) > > +{ > > + return check_vio_mask_sta(devapc_ctx, slave_type, module, VIO_STA); > > +} > > + > > +static void clear_vio_status(struct mtk_devapc_context *devapc_ctx, > > + int slave_type, u32 module) > > +{ > > + u32 reg_index, reg_offset; > > + void __iomem *reg; > > + > > + VIO_MASK_STA_REG_GET(module); > > + > > + reg = mtk_devapc_pd_get(devapc_ctx, slave_type, VIO_STA, reg_index); > > + writel(0x1 << reg_offset, reg); > > + > > + if (check_vio_status(devapc_ctx, slave_type, module)) > > + pr_err(PFX "%s: Clear failed, slave_type:0x%x, module_index:0x%x\n", > > + __func__, slave_type, module); > > +} > > + > > +static void mask_module_irq(struct mtk_devapc_context *devapc_ctx, > > + int slave_type, u32 module, bool mask) > > +{ > > + u32 reg_index, reg_offset; > > + void __iomem *reg; > > + u32 value; > > + > > + VIO_MASK_STA_REG_GET(module); > > + > > + reg = mtk_devapc_pd_get(devapc_ctx, slave_type, VIO_MASK, reg_index); > > + > > + value = readl(reg); > > + if (mask) > > + value |= (0x1 << reg_offset); > > + else > > + value &= ~(0x1 << reg_offset); > > + > > + writel(value, reg); > > +} > > + > > +#define TIMEOUT_MS 10000 > > + > > +static int read_poll_timeout(void __iomem *addr, u32 mask) > > That function is defined in include/linux/iopoll.h > > > +{ > > + unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS); > > + > > + do { > > + if (readl_relaxed(addr) & mask) > > Please use a variable where you write your value to and then check for the mask. > That maks the code easier to read and I think is part of the coding style. > Okay, I'll use the function in iopoll.h instead. Thanks for your reminds. > > + return 0; > > + > > + } while (!time_after(jiffies, timeout)); > > + > > + return (readl_relaxed(addr) & mask) ? 0 : -ETIMEDOUT; > > +} > > + > > +/* > > + * sync_vio_dbg - start to get violation information by selecting violation > > + * group and enable violation shift. > > + * > > + * Returns sync done or not > > + */ > > +static u32 sync_vio_dbg(struct mtk_devapc_context *devapc_ctx, int slave_type, > > + u32 shift_bit) > > +{ > > + void __iomem *pd_vio_shift_sta_reg; > > + void __iomem *pd_vio_shift_sel_reg; > > + void __iomem *pd_vio_shift_con_reg; > > + u32 sync_done = 0; > > + > > + pd_vio_shift_sta_reg = mtk_devapc_pd_get(devapc_ctx, slave_type, > > + VIO_SHIFT_STA, 0); > > + pd_vio_shift_sel_reg = mtk_devapc_pd_get(devapc_ctx, slave_type, > > + VIO_SHIFT_SEL, 0); > > + pd_vio_shift_con_reg = mtk_devapc_pd_get(devapc_ctx, slave_type, > > + VIO_SHIFT_CON, 0); > > + > > + writel(0x1 << shift_bit, pd_vio_shift_sel_reg); > > + writel(0x1, pd_vio_shift_con_reg); > > + > > + if (!read_poll_timeout(pd_vio_shift_con_reg, 0x2)) > > + sync_done = 1; > > + else > > + pr_err(PFX "%s: Shift violation info failed\n", __func__); > > + > > + /* Disable shift mechanism */ > > Please add a comment explaining what the shift mechanism is about. Okay, I'll add a comment to explain it at the beginning of this function. > > > + writel(0x0, pd_vio_shift_con_reg); > > + writel(0x0, pd_vio_shift_sel_reg); > > + writel(0x1 << shift_bit, pd_vio_shift_sta_reg); > > + > > + return sync_done; > > +} > > + > > +static void devapc_vio_info_print(struct mtk_devapc_context *devapc_ctx) > > +{ > > + struct mtk_devapc_vio_info *vio_info = devapc_ctx->vio_info; > > + > > + /* Print violation information */ > > + if (vio_info->write) > > + pr_info(PFX "Write Violation\n"); > > + else if (vio_info->read) > > + pr_info(PFX "Read Violation\n"); > > + > > + pr_info(PFX "%s%x, %s%x, %s%x, %s%x\n", > > + "Vio Addr:0x", vio_info->vio_addr, > > + "High:0x", vio_info->vio_addr_high, > > + "Bus ID:0x", vio_info->master_id, > > + "Dom ID:0x", vio_info->domain_id); > > +} > > + > > +static void devapc_extract_vio_dbg(struct mtk_devapc_context *devapc_ctx, > > + int slave_type) > > +{ > > + void __iomem *vio_dbg0_reg, *vio_dbg1_reg; > > + struct mtk_devapc_vio_dbgs_desc *vio_dbgs; > > + struct mtk_devapc_vio_info *vio_info; > > + u32 dbg0; > > + > > + vio_dbg0_reg = mtk_devapc_pd_get(devapc_ctx, slave_type, VIO_DBG0, 0); > > + vio_dbg1_reg = mtk_devapc_pd_get(devapc_ctx, slave_type, VIO_DBG1, 0); > > + > > + vio_dbgs = devapc_ctx->vio_dbgs_desc; > > + vio_info = devapc_ctx->vio_info; > > + > > + /* Extract violation information */ > > + dbg0 = readl(vio_dbg0_reg); > > + vio_info->vio_addr = readl(vio_dbg1_reg); > > + > > + vio_info->master_id = (dbg0 & vio_dbgs[MSTID].mask) >> > > + vio_dbgs[MSTID].start_bit; > > + vio_info->domain_id = (dbg0 & vio_dbgs[DMNID].mask) >> > > + vio_dbgs[DMNID].start_bit; > > + vio_info->write = ((dbg0 & vio_dbgs[VIO_W].mask) >> > > + vio_dbgs[VIO_W].start_bit) == 1; > > + vio_info->read = ((dbg0 & vio_dbgs[VIO_R].mask) >> > > + vio_dbgs[VIO_R].start_bit) == 1; > > + vio_info->vio_addr_high = (dbg0 & vio_dbgs[ADDR_H].mask) >> > > + vio_dbgs[ADDR_H].start_bit; > > + > > + devapc_vio_info_print(devapc_ctx); > > +} > > + > > +/* > > + * mtk_devapc_dump_vio_dbg - shift & dump the violation debug information. > > + */ > > +static bool mtk_devapc_dump_vio_dbg(struct mtk_devapc_context *devapc_ctx, > > + int slave_type, int *vio_idx) > > +{ > > + const struct mtk_device_info **device_info; > > + u32 shift_bit; > > + int i; > > + > > + device_info = devapc_ctx->device_info; > > + > > + for (i = 0; i < get_vio_slave_num(slave_type); i++) { > > + *vio_idx = device_info[slave_type][i].vio_index; > > + > > + if (check_vio_mask(devapc_ctx, slave_type, *vio_idx)) > > + continue; > > + > > + if (!check_vio_status(devapc_ctx, slave_type, *vio_idx)) > > + continue; > > + > > + shift_bit = get_shift_group(devapc_ctx, slave_type, *vio_idx); > > + > > + if (!sync_vio_dbg(devapc_ctx, slave_type, shift_bit)) > > + continue; > > + > > + devapc_extract_vio_dbg(devapc_ctx, slave_type); > > + > > + return true; > > + } > > + > > + return false; > > +} > > + > > +/* > > + * devapc_violation_irq - the devapc Interrupt Service Routine (ISR) will dump > > + * violation information including which master violates > > + * access slave. > > + */ > > +static irqreturn_t devapc_violation_irq(int irq_number, > > + struct mtk_devapc_context *devapc_ctx) > > +{ > > + const struct mtk_device_info **device_info; > > + int slave_type_num; > > + int vio_idx = -1; > > + int slave_type; > > + > > + slave_type_num = devapc_ctx->slave_type_num; > > + device_info = devapc_ctx->device_info; > > + > > + for (slave_type = 0; slave_type < slave_type_num; slave_type++) { > > + if (!mtk_devapc_dump_vio_dbg(devapc_ctx, slave_type, &vio_idx)) > > + continue; > > + > > + /* Ensure that violation info are written before > > + * further operations > > + */ > > + smp_mb(); > > + > > + mask_module_irq(devapc_ctx, slave_type, vio_idx, true); > > + > > + clear_vio_status(devapc_ctx, slave_type, vio_idx); > > + > > + mask_module_irq(devapc_ctx, slave_type, vio_idx, false); > > + } > > + > > + return IRQ_HANDLED; > > +} > > + > > +/* > > + * start_devapc - initialize devapc status and start receiving interrupt > > + * while devapc violation is triggered. > > + */ > > +static void start_devapc(struct mtk_devapc_context *devapc_ctx) > > +{ > > + const struct mtk_device_info **device_info; > > + void __iomem *pd_vio_shift_sta_reg; > > + void __iomem *pd_apc_con_reg; > > + u32 vio_shift_sta; > > + int slave_type, slave_type_num; > > + int i, vio_idx; > > + > > + device_info = devapc_ctx->device_info; > > + slave_type_num = devapc_ctx->slave_type_num; > > + > > + for (slave_type = 0; slave_type < slave_type_num; slave_type++) { > > + pd_apc_con_reg = mtk_devapc_pd_get(devapc_ctx, slave_type, > > + APC_CON, 0); > > + pd_vio_shift_sta_reg = mtk_devapc_pd_get(devapc_ctx, slave_type, > > + VIO_SHIFT_STA, 0); > > + if (!pd_apc_con_reg || !pd_vio_shift_sta_reg) > > + return; > > + > > + /* Clear devapc violation status */ > > + writel(BIT(31), pd_apc_con_reg); > > + > > + /* Clear violation shift status */ > > + vio_shift_sta = readl(pd_vio_shift_sta_reg); > > + if (vio_shift_sta) > > + writel(vio_shift_sta, pd_vio_shift_sta_reg); > > + > > + /* Clear slave violation status */ > > + for (i = 0; i < get_vio_slave_num(slave_type); i++) { > > + vio_idx = device_info[slave_type][i].vio_index; > > + > > + clear_vio_status(devapc_ctx, slave_type, vio_idx); > > + > > + mask_module_irq(devapc_ctx, slave_type, vio_idx, false); > > + } > > + } > > +} > > + > > +static int mtk_devapc_probe(struct platform_device *pdev) > > +{ > > + struct device_node *node = pdev->dev.of_node; > > + struct mtk_devapc_context *devapc_ctx; > > + struct clk *devapc_infra_clk; > > + u32 vio_dbgs_num, pds_num; > > + u8 slave_type_num; > > + u32 devapc_irq; > > + size_t size; > > + int i, ret; > > + > > + if (IS_ERR(node)) > > + return -ENODEV; > > + > > + devapc_ctx = devm_kzalloc(&pdev->dev, sizeof(struct mtk_devapc_context), > > + GFP_KERNEL); > > + if (!devapc_ctx) > > + return -ENOMEM; > > + > > + if (of_property_read_u8(node, "mediatek-slv_type_num", &slave_type_num)) > > + return -ENXIO; > > + > > + devapc_ctx->slave_type_num = slave_type_num; > > + > > + size = slave_type_num * sizeof(void *); > > + devapc_ctx->devapc_pd_base = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); > > + if (!devapc_ctx->devapc_pd_base) > > + return -ENOMEM; > > + > > + size = slave_type_num * sizeof(struct mtk_device_info *); > > + devapc_ctx->device_info = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); > > + if (!devapc_ctx->device_info) > > + return -ENOMEM; > > + > > + for (i = 0; i < slave_type_num; i++) { > > + devapc_ctx->devapc_pd_base[i] = of_iomap(node, i); > > + if (!devapc_ctx->devapc_pd_base[i]) > > + return -EINVAL; > > + > > + if (i == 0) > > + devapc_ctx->device_info[i] = mtk_devices_infra; > > + } > > + > > + size = sizeof(struct mtk_devapc_vio_info); > > + devapc_ctx->vio_info = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); > > + if (!devapc_ctx->vio_info) > > + return -ENOMEM; > > + > > + vio_dbgs_num = of_property_count_u32_elems(node, "mediatek-vio_dbgs"); > > + if (vio_dbgs_num <= 0) > > + return -ENXIO; > > + > > + size = (vio_dbgs_num / 2) * sizeof(struct mtk_devapc_vio_dbgs_desc); > > + devapc_ctx->vio_dbgs_desc = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); > > + if (!devapc_ctx->vio_dbgs_desc) > > + return -ENOMEM; > > + > > + for (i = 0; i < vio_dbgs_num / 2; i++) { > > + if (of_property_read_u32_index(node, "mediatek-vio_dbgs", > > + i * 2, > > + &devapc_ctx->vio_dbgs_desc[i].mask)) > > + return -ENXIO; > > + > > + if (of_property_read_u32_index(node, "mediatek-vio_dbgs", > > + (i * 2) + 1, > > + &devapc_ctx->vio_dbgs_desc[i].start_bit)) > > + return -ENXIO; > > + } > > + > > + pds_num = of_property_count_u32_elems(node, "mediatek-pds_offset"); > > + if (pds_num <= 0) > > + return -ENXIO; > > + > > + size = pds_num * sizeof(u32); > > + devapc_ctx->pds_offset = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); > > + if (!devapc_ctx->pds_offset) > > + return -ENOMEM; > > + > > + for (i = 0; i < pds_num; i++) { > > + if (of_property_read_u32_index(node, "mediatek-pds_offset", i, > > + &devapc_ctx->pds_offset[i])) > > + return -ENXIO; > > + } > > + > > + devapc_irq = irq_of_parse_and_map(node, 0); > > + if (!devapc_irq) > > + return -EINVAL; > > + > > + devapc_infra_clk = devm_clk_get(&pdev->dev, "devapc-infra-clock"); > > + if (IS_ERR(devapc_infra_clk)) > > + return -EINVAL; > > + > > + if (clk_prepare_enable(devapc_infra_clk)) > > + return -EINVAL; > > + > > + start_devapc(devapc_ctx); > > + > > + ret = devm_request_irq(&pdev->dev, devapc_irq, > > + (irq_handler_t)devapc_violation_irq, > > + IRQF_TRIGGER_NONE, "devapc", devapc_ctx); > > + if (ret) > > + return ret; > > + > > + return 0; > > +} > > + > > +static int mtk_devapc_remove(struct platform_device *dev) > > +{ > > + return 0; > > +} > > + > > +static const struct of_device_id mtk_devapc_dt_match[] = { > > + { .compatible = "mediatek,mt6779-devapc" }, > > + {}, > > +}; > > + > > +static struct platform_driver mtk_devapc_driver = { > > + .probe = mtk_devapc_probe, > > + .remove = mtk_devapc_remove, > > + .driver = { > > + .name = KBUILD_MODNAME, > > + .of_match_table = mtk_devapc_dt_match, > > + }, > > +}; > > + > > +module_platform_driver(mtk_devapc_driver); > > + > > +MODULE_DESCRIPTION("Mediatek Device APC Driver"); > > +MODULE_AUTHOR("Neal Liu "); > > +MODULE_LICENSE("GPL"); > > diff --git a/drivers/soc/mediatek/mtk-devapc.h b/drivers/soc/mediatek/mtk-devapc.h > > new file mode 100644 > > index 0000000..ab2cb14 > > --- /dev/null > > +++ b/drivers/soc/mediatek/mtk-devapc.h > > @@ -0,0 +1,670 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * Copyright (C) 2020 MediaTek Inc. > > + */ > > + > > +#ifndef __MTK_DEVAPC_H__ > > +#define __MTK_DEVAPC_H__ > > + > > +#define PFX "[DEVAPC]: " > > use dev_err() and friends instead. Okay, I'll remove it. > > > + > > +#define VIO_MASK_STA_REG_GET(m) \ > > +({ \ > > + typeof(m) (_m) = (m); \ > > + reg_index = _m / 32; \ > > + reg_offset = _m % 32; \ > > +}) > > don't do that. no explicit variable assingment in a macro, the macro should > return the value. Okay, I'll revise it in next patches. > > > + > > +enum DEVAPC_PD_REG_TYPE { > > + VIO_MASK = 0, > > + VIO_STA, > > + VIO_DBG0, > > + VIO_DBG1, > > + APC_CON, > > + VIO_SHIFT_STA, > > + VIO_SHIFT_SEL, > > + VIO_SHIFT_CON, > > + PD_REG_TYPE_NUM, > > +}; > > + > > +enum DEVAPC_VIO_DBGS_TYPE { > > + MSTID = 0, > > + DMNID, > > + VIO_W, > > + VIO_R, > > + ADDR_H, > > +}; > > + > > +struct mtk_device_info { > > + int sys_index; > > + int ctrl_index; > > + int vio_index; > > +}; > > + > > +static struct mtk_device_info mtk_devices_infra[] = { > > That's for mt6779, correct? Should be stated in the name. Okay. I have another way to reach the goal without using this struct array. I'll send another patches. > > > + /* sys_idx, ctrl_idx, vio_idx */ > > + /* 0 */ > > + {0, 0, 0}, > > + {0, 1, 1}, > > + {0, 2, 2}, > > + {0, 3, 3}, > > + {0, 4, 4}, > > + {0, 5, 5}, > > + {0, 6, 6}, > > + {0, 7, 7}, > > + {0, 8, 8}, > > + {0, 9, 9}, > > + > > + /* 10 */ > > + {0, 10, 10}, > > + {0, 11, 11}, > > + {0, 12, 12}, > > + {0, 13, 13}, > > + {0, 14, 14}, > > + {0, 15, 15}, > > + {0, 16, 16}, > > + {0, 17, 17}, > > + {0, 18, 18}, > > + {0, 19, 19}, > > + > > + /* 20 */ > > + {0, 20, 20}, > > + {0, 21, 21}, > > + {0, 22, 22}, > > + {0, 23, 23}, > > + {0, 24, 24}, > > + {0, 25, 25}, > > + {0, 26, 26}, > > + {0, 27, 27}, > > + {0, 28, 28}, > > + {0, 29, 29}, > > + > > + /* 30 */ > > + {0, 30, 30}, > > + {0, 31, 31}, > > + {0, 32, 32}, > > + {0, 33, 77}, > > + {0, 34, 78}, > > + {0, 35, 79}, > > + {0, 35, 80}, > > + {0, 37, 37}, > > + {0, 38, 38}, > > + {0, 39, 39}, > > + > > + /* 40 */ > > + {0, 40, 40}, > > + {0, 41, 41}, > > + {0, 42, 42}, > > + {0, 43, 43}, > > + {0, 44, 44}, > > + {0, 45, 45}, > > + {0, 46, 46}, > > + {0, 47, 47}, > > + {0, 48, 48}, > > + {0, 49, 49}, > > + > > + /* 50 */ > > + {0, 50, 50}, > > + {0, 51, 51}, > > + {0, 52, 52}, > > + {0, 53, 53}, > > + {0, 54, 54}, > > + {0, 55, 55}, > > + {0, 56, 56}, > > + {0, 57, 57}, > > + {0, 58, 58}, > > + {0, 59, 59}, > > + > > + /* 60 */ > > + {0, 60, 60}, > > + {0, 61, 61}, > > + {0, 62, 62}, > > + {0, 63, 63}, > > + {0, 64, 64}, > > + {0, 65, 70}, > > + {0, 66, 71}, > > + {0, 67, 72}, > > + {0, 68, 73}, > > + {0, 70, 81}, > > + > > + /* 70 */ > > + {0, 71, 82}, > > + {0, 72, 83}, > > + {0, 73, 84}, > > + {0, 74, 85}, > > + {0, 75, 86}, > > + {0, 76, 87}, > > + {0, 77, 88}, > > + {0, 78, 89}, > > + {0, 79, 90}, > > + {0, 80, 91}, > > + > > + /* 80 */ > > + {0, 81, 92}, > > + {0, 82, 93}, > > + {0, 83, 94}, > > + {0, 84, 95}, > > + {0, 85, 96}, > > + {0, 86, 97}, > > + {0, 87, 98}, > > + {0, 88, 99}, > > + {0, 89, 100}, > > + {0, 90, 101}, > > + > > + /* 90 */ > > + {0, 91, 102}, > > + {0, 92, 103}, > > + {0, 93, 104}, > > + {0, 94, 105}, > > + {0, 95, 106}, > > + {0, 96, 107}, > > + {0, 97, 108}, > > + {0, 98, 109}, > > + {0, 110, 110}, > > + {0, 111, 111}, > > + > > + /* 100 */ > > + {0, 112, 112}, > > + {0, 113, 113}, > > + {0, 114, 114}, > > + {0, 115, 115}, > > + {0, 116, 116}, > > + {0, 117, 117}, > > + {0, 118, 118}, > > + {0, 119, 119}, > > + {0, 120, 120}, > > + {0, 121, 121}, > > + > > + /* 110 */ > > + {0, 122, 122}, > > + {0, 123, 123}, > > + {0, 124, 124}, > > + {0, 125, 125}, > > + {0, 126, 126}, > > + {0, 127, 127}, > > + {0, 128, 128}, > > + {0, 129, 129}, > > + {0, 130, 130}, > > + {0, 131, 131}, > > + > > + /* 120 */ > > + {0, 132, 132}, > > + {0, 133, 133}, > > + {0, 134, 134}, > > + {0, 135, 135}, > > + {0, 136, 136}, > > + {0, 137, 137}, > > + {0, 138, 138}, > > + {0, 139, 139}, > > + {0, 140, 140}, > > + {0, 141, 141}, > > + > > + /* 130 */ > > + {0, 142, 142}, > > + {0, 143, 143}, > > + {0, 144, 144}, > > + {0, 145, 145}, > > + {0, 146, 146}, > > + {0, 147, 147}, > > + {0, 148, 148}, > > + {0, 149, 149}, > > + {0, 150, 150}, > > + {0, 151, 151}, > > + > > + /* 140 */ > > + {0, 152, 152}, > > + {0, 153, 153}, > > + {0, 154, 154}, > > + {0, 155, 155}, > > + {0, 156, 156}, > > + {0, 157, 157}, > > + {0, 158, 158}, > > + {0, 159, 159}, > > + {0, 160, 160}, > > + {0, 161, 161}, > > + > > + /* 150 */ > > + {0, 162, 162}, > > + {0, 163, 163}, > > + {0, 164, 164}, > > + {0, 165, 165}, > > + {0, 166, 166}, > > + {0, 167, 167}, > > + {0, 168, 168}, > > + {0, 169, 169}, > > + {0, 170, 170}, > > + {0, 171, 171}, > > + > > + /* 160 */ > > + {0, 172, 172}, > > + {0, 173, 173}, > > + {0, 174, 174}, > > + {0, 175, 175}, > > + {0, 176, 176}, > > + {0, 177, 177}, > > + {0, 178, 178}, > > + {0, 179, 179}, > > + {0, 180, 180}, > > + {0, 181, 181}, > > + > > + /* 170 */ > > + {0, 182, 182}, > > + {0, 183, 183}, > > + {0, 184, 184}, > > + {0, 185, 185}, > > + {0, 186, 186}, > > + {0, 187, 187}, > > + {0, 188, 188}, > > + {0, 189, 189}, > > + {0, 190, 190}, > > + {0, 191, 191}, > > + > > + /* 180 */ > > + {0, 192, 192}, > > + {0, 193, 193}, > > + {0, 194, 194}, > > + {0, 195, 195}, > > + {0, 196, 196}, > > + {0, 197, 197}, > > + {0, 198, 198}, > > + {0, 199, 199}, > > + {0, 200, 200}, > > + {0, 201, 201}, > > + > > + /* 190 */ > > + {0, 202, 202}, > > + {0, 203, 203}, > > + {0, 204, 204}, > > + {0, 205, 205}, > > + {0, 206, 206}, > > + {0, 207, 207}, > > + {0, 208, 208}, > > + {0, 209, 209}, > > + {0, 210, 210}, > > + {0, 211, 211}, > > + > > + /* 200 */ > > + {0, 212, 212}, > > + {0, 213, 213}, > > + {0, 214, 214}, > > + {0, 215, 215}, > > + {0, 216, 216}, > > + {0, 217, 217}, > > + {0, 218, 218}, > > + {0, 219, 219}, > > + {0, 220, 220}, > > + {0, 221, 221}, > > + > > + /* 210 */ > > + {0, 222, 222}, > > + {0, 223, 223}, > > + {0, 224, 224}, > > + {0, 225, 225}, > > + {0, 226, 226}, > > + {0, 227, 227}, > > + {0, 228, 228}, > > + {0, 229, 229}, > > + {0, 230, 230}, > > + {0, 231, 231}, > > + > > + /* 220 */ > > + {1, 0, 232}, > > + {1, 1, 233}, > > + {1, 2, 234}, > > + {1, 3, 235}, > > + {1, 4, 236}, > > + {1, 5, 237}, > > + {1, 6, 238}, > > + {1, 7, 239}, > > + {1, 8, 240}, > > + {1, 9, 241}, > > + > > + /* 230 */ > > + {1, 10, 242}, > > + {1, 11, 243}, > > + {1, 12, 244}, > > + {1, 13, 245}, > > + {1, 14, 246}, > > + {1, 15, 247}, > > + {1, 16, 248}, > > + {1, 17, 249}, > > + {1, 18, 250}, > > + {1, 19, 251}, > > + > > + /* 240 */ > > + {1, 20, 252}, > > + {1, 21, 253}, > > + {1, 22, 254}, > > + {1, 23, 255}, > > + {1, 24, 256}, > > + {1, 25, 257}, > > + {1, 26, 258}, > > + {1, 27, 259}, > > + {1, 28, 260}, > > + {1, 29, 261}, > > + > > + /* 250 */ > > + {1, 30, 262}, > > + {1, 31, 263}, > > + {1, 32, 264}, > > + {1, 33, 265}, > > + {1, 34, 266}, > > + {1, 35, 267}, > > + {1, 36, 268}, > > + {1, 37, 269}, > > + {1, 38, 270}, > > + {1, 39, 271}, > > + > > + /* 260 */ > > + {1, 40, 272}, > > + {1, 41, 273}, > > + {1, 42, 274}, > > + {1, 43, 275}, > > + {1, 44, 276}, > > + {1, 45, 277}, > > + {1, 46, 278}, > > + {1, 47, 279}, > > + {1, 48, 280}, > > + {1, 49, 281}, > > + > > + /* 270 */ > > + {1, 50, 282}, > > + {1, 51, 283}, > > + {1, 52, 284}, > > + {1, 53, 285}, > > + {1, 54, 286}, > > + {1, 55, 287}, > > + {1, 56, 288}, > > + {1, 57, 289}, > > + {1, 58, 290}, > > + {1, 59, 291}, > > + > > + /* 280 */ > > + {1, 60, 292}, > > + {1, 61, 293}, > > + {1, 62, 294}, > > + {1, 63, 295}, > > + {1, 64, 296}, > > + {1, 65, 297}, > > + {1, 66, 298}, > > + {1, 67, 299}, > > + {1, 68, 300}, > > + {1, 69, 301}, > > + > > + /* 290 */ > > + {1, 70, 302}, > > + {1, 71, 303}, > > + {1, 72, 304}, > > + {1, 73, 305}, > > + {1, 74, 306}, > > + {1, 75, 307}, > > + {1, 76, 308}, > > + {1, 77, 309}, > > + {1, 78, 310}, > > + {1, 79, 311}, > > + > > + /* 300 */ > > + {1, 80, 312}, > > + {1, 81, 313}, > > + {1, 82, 314}, > > + {1, 83, 315}, > > + {1, 84, 316}, > > + {1, 85, 317}, > > + {1, 86, 318}, > > + {1, 87, 319}, > > + {1, 88, 320}, > > + {1, 89, 321}, > > + > > + /* 310 */ > > + {1, 90, 322}, > > + {1, 91, 323}, > > + {1, 92, 324}, > > + {1, 93, 325}, > > + {1, 94, 326}, > > + {1, 95, 327}, > > + {1, 96, 328}, > > + {1, 97, 329}, > > + {1, 98, 330}, > > + {1, 99, 331}, > > + > > + /* 320 */ > > + {1, 100, 332}, > > + {1, 101, 333}, > > + {1, 102, 334}, > > + {1, 103, 335}, > > + {1, 104, 336}, > > + {1, 105, 337}, > > + {1, 106, 338}, > > + {1, 107, 339}, > > + {1, 108, 340}, > > + {1, 109, 341}, > > + > > + /* 330 */ > > + {1, 110, 342}, > > + {1, 111, 343}, > > + {1, 112, 344}, > > + {1, 113, 345}, > > + {1, 114, 346}, > > + {1, 115, 347}, > > + {1, 116, 348}, > > + {1, 117, 349}, > > + {1, 118, 350}, > > + {1, 119, 351}, > > + > > + /* 340 */ > > + {1, 120, 352}, > > + {1, 121, 353}, > > + {1, 122, 354}, > > + {1, 123, 355}, > > + {1, 124, 356}, > > + {1, 125, 357}, > > + {1, 126, 358}, > > + {1, 127, 359}, > > + {1, 128, 360}, > > + {1, 129, 361}, > > + > > + /* 350 */ > > + {1, 130, 362}, > > + {1, 131, 363}, > > + {1, 132, 364}, > > + {1, 133, 365}, > > + {1, 134, 366}, > > + {1, 135, 367}, > > + {1, 136, 368}, > > + {1, 137, 369}, > > + {1, 138, 370}, > > + {1, 139, 371}, > > + > > + /* 360 */ > > + {1, 140, 372}, > > + {1, 141, 373}, > > + {1, 142, 374}, > > + {1, 143, 375}, > > + {1, 144, 376}, > > + {1, 145, 377}, > > + {1, 146, 378}, > > + {1, 147, 379}, > > + {1, 148, 380}, > > + {1, 149, 381}, > > + > > + /* 370 */ > > + {1, 150, 382}, > > + {1, 151, 383}, > > + {1, 152, 384}, > > + {1, 153, 385}, > > + {1, 154, 386}, > > + {1, 155, 387}, > > + {1, 156, 388}, > > + {1, 157, 389}, > > + {1, 158, 390}, > > + {1, 159, 391}, > > + > > + /* 380 */ > > + {1, 160, 392}, > > + {1, 161, 393}, > > + {1, 162, 394}, > > + {1, 163, 395}, > > + {1, 164, 396}, > > + {1, 165, 397}, > > + {1, 166, 398}, > > + {1, 167, 399}, > > + {1, 168, 400}, > > + {1, 169, 401}, > > + > > + /* 390 */ > > + {1, 170, 402}, > > + {1, 171, 403}, > > + {1, 172, 404}, > > + {1, 173, 405}, > > + {1, 174, 406}, > > + {1, 175, 407}, > > + {1, 176, 408}, > > + {1, 177, 409}, > > + {1, 178, 410}, > > + {1, 179, 411}, > > + > > + /* 400 */ > > + {1, 180, 412}, > > + {1, 181, 413}, > > + {1, 182, 414}, > > + {1, 183, 415}, > > + {1, 184, 416}, > > + {1, 185, 417}, > > + {1, 186, 418}, > > + {1, 187, 419}, > > + {1, 188, 420}, > > + {1, 189, 421}, > > + > > + /* 410 */ > > + {1, 190, 422}, > > + {1, 191, 423}, > > + {1, 192, 424}, > > + {1, 193, 425}, > > + {1, 194, 426}, > > + {1, 195, 427}, > > + {1, 196, 428}, > > + {1, 197, 429}, > > + {1, 198, 430}, > > + {1, 199, 431}, > > + > > + /* 420 */ > > + {1, 200, 432}, > > + {1, 201, 433}, > > + {1, 202, 434}, > > + {1, 203, 435}, > > + {1, 204, 436}, > > + {1, 205, 437}, > > + {1, 206, 438}, > > + {1, 207, 439}, > > + {1, 208, 440}, > > + {1, 209, 441}, > > + > > + /* 430 */ > > + {1, 210, 442}, > > + {1, 211, 443}, > > + {1, 212, 444}, > > + {1, 213, 445}, > > + {1, 214, 446}, > > + {1, 215, 447}, > > + {1, 216, 448}, > > + {1, 217, 449}, > > + {1, 218, 450}, > > + {1, 219, 451}, > > + > > + /* 440 */ > > + {1, 220, 452}, > > + {1, 221, 453}, > > + {1, 222, 454}, > > + {1, 223, 455}, > > + {1, 224, 456}, > > + {1, 225, 457}, > > + {1, 226, 458}, > > + {1, 227, 459}, > > + {1, 228, 460}, > > + {1, 229, 461}, > > + > > + /* 450 */ > > + {1, 230, 462}, > > + {1, 231, 463}, > > + {1, 232, 464}, > > + {1, 233, 465}, > > + {1, 234, 466}, > > + {1, 235, 467}, > > + {1, 236, 468}, > > + {1, 237, 469}, > > + {1, 238, 470}, > > + {1, 239, 471}, > > + > > + /* 460 */ > > + {1, 240, 472}, > > + {1, 241, 473}, > > + {1, 242, 474}, > > + {1, 243, 475}, > > + {1, 244, 476}, > > + {1, 245, 477}, > > + {1, 246, 478}, > > + {-1, -1, 479}, > > + {-1, -1, 480}, > > + {-1, -1, 481}, > > + > > + /* 470 */ > > + {-1, -1, 482}, > > + {-1, -1, 483}, > > + {-1, -1, 484}, > > + {-1, -1, 485}, > > + {-1, -1, 486}, > > + {-1, -1, 487}, > > + {-1, -1, 488}, > > + {-1, -1, 489}, > > + {-1, -1, 490}, > > + {-1, -1, 491}, > > + > > + /* 480 */ > > + {-1, -1, 492}, > > + {-1, -1, 493}, > > + {-1, -1, 494}, > > + {-1, -1, 495}, > > + {-1, -1, 496}, > > + {-1, -1, 497}, > > + {-1, -1, 498}, > > + {-1, -1, 499}, > > + {-1, -1, 500}, > > + {-1, -1, 501}, > > + > > + /* 490 */ > > + {-1, -1, 502}, > > + {-1, -1, 503}, > > + {-1, -1, 504}, > > + {-1, -1, 505}, > > + {-1, -1, 506}, > > + {-1, -1, 507}, > > + {-1, -1, 508}, > > + {-1, -1, 509}, > > + {-1, -1, 510}, > > + > > +}; > > + > > +struct mtk_devapc_vio_info { > > + bool read; > > + bool write; > > + u32 vio_addr; > > + u32 vio_addr_high; > > + u32 master_id; > > + u32 domain_id; > > +}; > > + > > +struct mtk_devapc_vio_dbgs_desc { > > + u32 mask; > > + u32 start_bit; > > +}; > > + > > +struct mtk_devapc_context { > > + u8 slave_type_num; > > + void __iomem **devapc_pd_base; > > + const struct mtk_device_info **device_info; > > + struct mtk_devapc_vio_info *vio_info; > > + struct mtk_devapc_vio_dbgs_desc *vio_dbgs_desc; > > + u32 *pds_offset; > > +}; > > + > > Not sure if I get this right: > > struct mtk_devapc_offset { > u32 vio_mask; > u32 vio_sta; > u32 vio_dbg0; > u32 vio_dbg1; > ... > } > > struct mtk_devapc_context { > u8 pd_base_num; > void __iomem **devapc_pd_base; > struct mtk_devapc_offset *offset; > const struct mtk_device_info **device_info; > struct mtk_devapc_vio_info *vio_info; > struct mtk_devapc_vio_dbgs_desc *vio_dbgs_desc; > }; > > With this I think we can get rid of mtk_devapc_pd_get(). > mtk_devapc_pd_get() is used to calculate the vaddr of devapc pd register. It's based on different slave_type, pd_reg_type and reg_idx. I don't think it can be replaced with such simple data structures. > Sorry I'm not able to review the whole driver right now. Please also have a look > on my comments from v1. > > We will have to go little by little to get this into a good state. In case it > makes sense to have this in the kernel at all. > > Regards, > Matthias I'm appreciated for your review. It helps me to write better code and get closer to the kernel. _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68B33C433DF for ; Mon, 13 Jul 2020 07:47:31 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2D19320674 for ; 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bh=4x8ya6Vnce3yiQGPD2JZIDEZ1YPf+zCABzP2yiH62kQ=; b=L6bbJVRN3dh6XIRQIx0OesVnJ6mtEixSmGhz5VqxCkvYbKMTe8bQ+BEwQ31pgVCd0JL3tj/bA1567mYMnCwin4E1XQQ2FKsRr4xHDMPRPZu7uifJO+wnkbHh8Wp6KMduBZiGwrcizjsUYMvE2Fe3sPEnDHFEVmBejqRfE567I/g=; X-UUID: 84b14b1375fb408ebb850f44d57f1577-20200712 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1957728728; Sun, 12 Jul 2020 23:45:38 -0800 Received: from MTKMBS01N2.mediatek.inc (172.21.101.79) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 13 Jul 2020 00:45:36 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 13 Jul 2020 15:45:34 +0800 Received: from [172.21.77.33] (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 13 Jul 2020 15:45:35 +0800 Message-ID: <1594626336.22730.36.camel@mtkswgap22> Subject: Re: [PATCH v2 2/2] soc: mediatek: add mtk-devapc driver From: Neal Liu To: Matthias Brugger Date: Mon, 13 Jul 2020 15:45:36 +0800 In-Reply-To: References: <1594285927-1840-1-git-send-email-neal.liu@mediatek.com> <1594285927-1840-3-git-send-email-neal.liu@mediatek.com> X-Mailer: Evolution 3.2.3-0ubuntu6 MIME-Version: 1.0 X-TM-SNTS-SMTP: 02EEB14808AABAF9D2F91D0886FDE7959125C6CE24A27BAE0F2A544E5BF812232000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200713_034546_514828_59E60AD2 X-CRM114-Status: GOOD ( 27.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, wsd_upstream@mediatek.com, lkml , Rob Herring , linux-mediatek@lists.infradead.org, Neal Liu , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 2020-07-10 at 14:14 +0200, Matthias Brugger wrote: > [snip] > > + > > +static int get_vio_slave_num(int slave_type) > > I have a hard time to understand the usefullness of this, can you please explain. > The basic idea is to get total numbers of slaves. And we can use it to scan all slaves which has been triggered violation. I think I can pass it through DT data instead of using mtk_device_info array. I'll send another patches to change it. > > +{ > > + if (slave_type == 0) > > + return ARRAY_SIZE(mtk_devices_infra); > > + > > + return 0; > > +} > > + > > +static u32 get_shift_group(struct mtk_devapc_context *devapc_ctx, > > + int slave_type, int vio_idx) > > +{ > > + u32 vio_shift_sta; > > + void __iomem *reg; > > + int bit; > > + > > + reg = mtk_devapc_pd_get(devapc_ctx, slave_type, VIO_SHIFT_STA, 0); > > + vio_shift_sta = readl(reg); > > + > > + for (bit = 0; bit < 32; bit++) { > > + if ((vio_shift_sta >> bit) & 0x1) > + break; > > + } > > + > > + return bit; > > We return the first position (from the right) of the rigster with the bit set to > one. Correct? > Can't we use __ffs() for this? Yes, thanks for your reminds to use __ffs(). I'll revise it in next patches. > > > +} > > + > > +static int check_vio_mask_sta(struct mtk_devapc_context *devapc_ctx, > > + int slave_type, u32 module, int pd_reg_type) > > +{ > > + u32 reg_index, reg_offset; > > + void __iomem *reg; > > + u32 value; > > + > > + VIO_MASK_STA_REG_GET(module); > > + > > + reg = mtk_devapc_pd_get(devapc_ctx, slave_type, pd_reg_type, reg_index); > > reg = mtk_devapc_pd_get(devapc_ctx, slave_type, pd_reg_type, > VIO_MOD_TO_REG_IND(module)); Okay, I'll revise it in next patches. > > > + value = readl(reg); > > + > > + return ((value >> reg_offset) & 0x1); > > return ((value >> VIO_MOD_TO_REG_OFF(module)) & 0x1); Okay, I'll revise it in next patches. > > > +} > > + > > +static int check_vio_mask(struct mtk_devapc_context *devapc_ctx, int slave_type, > > + u32 module) > > +{ > > + return check_vio_mask_sta(devapc_ctx, slave_type, module, VIO_MASK); > > +} > > + > > +static int check_vio_status(struct mtk_devapc_context *devapc_ctx, > > + int slave_type, u32 module) > > +{ > > + return check_vio_mask_sta(devapc_ctx, slave_type, module, VIO_STA); > > +} > > + > > +static void clear_vio_status(struct mtk_devapc_context *devapc_ctx, > > + int slave_type, u32 module) > > +{ > > + u32 reg_index, reg_offset; > > + void __iomem *reg; > > + > > + VIO_MASK_STA_REG_GET(module); > > + > > + reg = mtk_devapc_pd_get(devapc_ctx, slave_type, VIO_STA, reg_index); > > + writel(0x1 << reg_offset, reg); > > + > > + if (check_vio_status(devapc_ctx, slave_type, module)) > > + pr_err(PFX "%s: Clear failed, slave_type:0x%x, module_index:0x%x\n", > > + __func__, slave_type, module); > > +} > > + > > +static void mask_module_irq(struct mtk_devapc_context *devapc_ctx, > > + int slave_type, u32 module, bool mask) > > +{ > > + u32 reg_index, reg_offset; > > + void __iomem *reg; > > + u32 value; > > + > > + VIO_MASK_STA_REG_GET(module); > > + > > + reg = mtk_devapc_pd_get(devapc_ctx, slave_type, VIO_MASK, reg_index); > > + > > + value = readl(reg); > > + if (mask) > > + value |= (0x1 << reg_offset); > > + else > > + value &= ~(0x1 << reg_offset); > > + > > + writel(value, reg); > > +} > > + > > +#define TIMEOUT_MS 10000 > > + > > +static int read_poll_timeout(void __iomem *addr, u32 mask) > > That function is defined in include/linux/iopoll.h > > > +{ > > + unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS); > > + > > + do { > > + if (readl_relaxed(addr) & mask) > > Please use a variable where you write your value to and then check for the mask. > That maks the code easier to read and I think is part of the coding style. > Okay, I'll use the function in iopoll.h instead. Thanks for your reminds. > > + return 0; > > + > > + } while (!time_after(jiffies, timeout)); > > + > > + return (readl_relaxed(addr) & mask) ? 0 : -ETIMEDOUT; > > +} > > + > > +/* > > + * sync_vio_dbg - start to get violation information by selecting violation > > + * group and enable violation shift. > > + * > > + * Returns sync done or not > > + */ > > +static u32 sync_vio_dbg(struct mtk_devapc_context *devapc_ctx, int slave_type, > > + u32 shift_bit) > > +{ > > + void __iomem *pd_vio_shift_sta_reg; > > + void __iomem *pd_vio_shift_sel_reg; > > + void __iomem *pd_vio_shift_con_reg; > > + u32 sync_done = 0; > > + > > + pd_vio_shift_sta_reg = mtk_devapc_pd_get(devapc_ctx, slave_type, > > + VIO_SHIFT_STA, 0); > > + pd_vio_shift_sel_reg = mtk_devapc_pd_get(devapc_ctx, slave_type, > > + VIO_SHIFT_SEL, 0); > > + pd_vio_shift_con_reg = mtk_devapc_pd_get(devapc_ctx, slave_type, > > + VIO_SHIFT_CON, 0); > > + > > + writel(0x1 << shift_bit, pd_vio_shift_sel_reg); > > + writel(0x1, pd_vio_shift_con_reg); > > + > > + if (!read_poll_timeout(pd_vio_shift_con_reg, 0x2)) > > + sync_done = 1; > > + else > > + pr_err(PFX "%s: Shift violation info failed\n", __func__); > > + > > + /* Disable shift mechanism */ > > Please add a comment explaining what the shift mechanism is about. Okay, I'll add a comment to explain it at the beginning of this function. > > > + writel(0x0, pd_vio_shift_con_reg); > > + writel(0x0, pd_vio_shift_sel_reg); > > + writel(0x1 << shift_bit, pd_vio_shift_sta_reg); > > + > > + return sync_done; > > +} > > + > > +static void devapc_vio_info_print(struct mtk_devapc_context *devapc_ctx) > > +{ > > + struct mtk_devapc_vio_info *vio_info = devapc_ctx->vio_info; > > + > > + /* Print violation information */ > > + if (vio_info->write) > > + pr_info(PFX "Write Violation\n"); > > + else if (vio_info->read) > > + pr_info(PFX "Read Violation\n"); > > + > > + pr_info(PFX "%s%x, %s%x, %s%x, %s%x\n", > > + "Vio Addr:0x", vio_info->vio_addr, > > + "High:0x", vio_info->vio_addr_high, > > + "Bus ID:0x", vio_info->master_id, > > + "Dom ID:0x", vio_info->domain_id); > > +} > > + > > +static void devapc_extract_vio_dbg(struct mtk_devapc_context *devapc_ctx, > > + int slave_type) > > +{ > > + void __iomem *vio_dbg0_reg, *vio_dbg1_reg; > > + struct mtk_devapc_vio_dbgs_desc *vio_dbgs; > > + struct mtk_devapc_vio_info *vio_info; > > + u32 dbg0; > > + > > + vio_dbg0_reg = mtk_devapc_pd_get(devapc_ctx, slave_type, VIO_DBG0, 0); > > + vio_dbg1_reg = mtk_devapc_pd_get(devapc_ctx, slave_type, VIO_DBG1, 0); > > + > > + vio_dbgs = devapc_ctx->vio_dbgs_desc; > > + vio_info = devapc_ctx->vio_info; > > + > > + /* Extract violation information */ > > + dbg0 = readl(vio_dbg0_reg); > > + vio_info->vio_addr = readl(vio_dbg1_reg); > > + > > + vio_info->master_id = (dbg0 & vio_dbgs[MSTID].mask) >> > > + vio_dbgs[MSTID].start_bit; > > + vio_info->domain_id = (dbg0 & vio_dbgs[DMNID].mask) >> > > + vio_dbgs[DMNID].start_bit; > > + vio_info->write = ((dbg0 & vio_dbgs[VIO_W].mask) >> > > + vio_dbgs[VIO_W].start_bit) == 1; > > + vio_info->read = ((dbg0 & vio_dbgs[VIO_R].mask) >> > > + vio_dbgs[VIO_R].start_bit) == 1; > > + vio_info->vio_addr_high = (dbg0 & vio_dbgs[ADDR_H].mask) >> > > + vio_dbgs[ADDR_H].start_bit; > > + > > + devapc_vio_info_print(devapc_ctx); > > +} > > + > > +/* > > + * mtk_devapc_dump_vio_dbg - shift & dump the violation debug information. > > + */ > > +static bool mtk_devapc_dump_vio_dbg(struct mtk_devapc_context *devapc_ctx, > > + int slave_type, int *vio_idx) > > +{ > > + const struct mtk_device_info **device_info; > > + u32 shift_bit; > > + int i; > > + > > + device_info = devapc_ctx->device_info; > > + > > + for (i = 0; i < get_vio_slave_num(slave_type); i++) { > > + *vio_idx = device_info[slave_type][i].vio_index; > > + > > + if (check_vio_mask(devapc_ctx, slave_type, *vio_idx)) > > + continue; > > + > > + if (!check_vio_status(devapc_ctx, slave_type, *vio_idx)) > > + continue; > > + > > + shift_bit = get_shift_group(devapc_ctx, slave_type, *vio_idx); > > + > > + if (!sync_vio_dbg(devapc_ctx, slave_type, shift_bit)) > > + continue; > > + > > + devapc_extract_vio_dbg(devapc_ctx, slave_type); > > + > > + return true; > > + } > > + > > + return false; > > +} > > + > > +/* > > + * devapc_violation_irq - the devapc Interrupt Service Routine (ISR) will dump > > + * violation information including which master violates > > + * access slave. > > + */ > > +static irqreturn_t devapc_violation_irq(int irq_number, > > + struct mtk_devapc_context *devapc_ctx) > > +{ > > + const struct mtk_device_info **device_info; > > + int slave_type_num; > > + int vio_idx = -1; > > + int slave_type; > > + > > + slave_type_num = devapc_ctx->slave_type_num; > > + device_info = devapc_ctx->device_info; > > + > > + for (slave_type = 0; slave_type < slave_type_num; slave_type++) { > > + if (!mtk_devapc_dump_vio_dbg(devapc_ctx, slave_type, &vio_idx)) > > + continue; > > + > > + /* Ensure that violation info are written before > > + * further operations > > + */ > > + smp_mb(); > > + > > + mask_module_irq(devapc_ctx, slave_type, vio_idx, true); > > + > > + clear_vio_status(devapc_ctx, slave_type, vio_idx); > > + > > + mask_module_irq(devapc_ctx, slave_type, vio_idx, false); > > + } > > + > > + return IRQ_HANDLED; > > +} > > + > > +/* > > + * start_devapc - initialize devapc status and start receiving interrupt > > + * while devapc violation is triggered. > > + */ > > +static void start_devapc(struct mtk_devapc_context *devapc_ctx) > > +{ > > + const struct mtk_device_info **device_info; > > + void __iomem *pd_vio_shift_sta_reg; > > + void __iomem *pd_apc_con_reg; > > + u32 vio_shift_sta; > > + int slave_type, slave_type_num; > > + int i, vio_idx; > > + > > + device_info = devapc_ctx->device_info; > > + slave_type_num = devapc_ctx->slave_type_num; > > + > > + for (slave_type = 0; slave_type < slave_type_num; slave_type++) { > > + pd_apc_con_reg = mtk_devapc_pd_get(devapc_ctx, slave_type, > > + APC_CON, 0); > > + pd_vio_shift_sta_reg = mtk_devapc_pd_get(devapc_ctx, slave_type, > > + VIO_SHIFT_STA, 0); > > + if (!pd_apc_con_reg || !pd_vio_shift_sta_reg) > > + return; > > + > > + /* Clear devapc violation status */ > > + writel(BIT(31), pd_apc_con_reg); > > + > > + /* Clear violation shift status */ > > + vio_shift_sta = readl(pd_vio_shift_sta_reg); > > + if (vio_shift_sta) > > + writel(vio_shift_sta, pd_vio_shift_sta_reg); > > + > > + /* Clear slave violation status */ > > + for (i = 0; i < get_vio_slave_num(slave_type); i++) { > > + vio_idx = device_info[slave_type][i].vio_index; > > + > > + clear_vio_status(devapc_ctx, slave_type, vio_idx); > > + > > + mask_module_irq(devapc_ctx, slave_type, vio_idx, false); > > + } > > + } > > +} > > + > > +static int mtk_devapc_probe(struct platform_device *pdev) > > +{ > > + struct device_node *node = pdev->dev.of_node; > > + struct mtk_devapc_context *devapc_ctx; > > + struct clk *devapc_infra_clk; > > + u32 vio_dbgs_num, pds_num; > > + u8 slave_type_num; > > + u32 devapc_irq; > > + size_t size; > > + int i, ret; > > + > > + if (IS_ERR(node)) > > + return -ENODEV; > > + > > + devapc_ctx = devm_kzalloc(&pdev->dev, sizeof(struct mtk_devapc_context), > > + GFP_KERNEL); > > + if (!devapc_ctx) > > + return -ENOMEM; > > + > > + if (of_property_read_u8(node, "mediatek-slv_type_num", &slave_type_num)) > > + return -ENXIO; > > + > > + devapc_ctx->slave_type_num = slave_type_num; > > + > > + size = slave_type_num * sizeof(void *); > > + devapc_ctx->devapc_pd_base = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); > > + if (!devapc_ctx->devapc_pd_base) > > + return -ENOMEM; > > + > > + size = slave_type_num * sizeof(struct mtk_device_info *); > > + devapc_ctx->device_info = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); > > + if (!devapc_ctx->device_info) > > + return -ENOMEM; > > + > > + for (i = 0; i < slave_type_num; i++) { > > + devapc_ctx->devapc_pd_base[i] = of_iomap(node, i); > > + if (!devapc_ctx->devapc_pd_base[i]) > > + return -EINVAL; > > + > > + if (i == 0) > > + devapc_ctx->device_info[i] = mtk_devices_infra; > > + } > > + > > + size = sizeof(struct mtk_devapc_vio_info); > > + devapc_ctx->vio_info = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); > > + if (!devapc_ctx->vio_info) > > + return -ENOMEM; > > + > > + vio_dbgs_num = of_property_count_u32_elems(node, "mediatek-vio_dbgs"); > > + if (vio_dbgs_num <= 0) > > + return -ENXIO; > > + > > + size = (vio_dbgs_num / 2) * sizeof(struct mtk_devapc_vio_dbgs_desc); > > + devapc_ctx->vio_dbgs_desc = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); > > + if (!devapc_ctx->vio_dbgs_desc) > > + return -ENOMEM; > > + > > + for (i = 0; i < vio_dbgs_num / 2; i++) { > > + if (of_property_read_u32_index(node, "mediatek-vio_dbgs", > > + i * 2, > > + &devapc_ctx->vio_dbgs_desc[i].mask)) > > + return -ENXIO; > > + > > + if (of_property_read_u32_index(node, "mediatek-vio_dbgs", > > + (i * 2) + 1, > > + &devapc_ctx->vio_dbgs_desc[i].start_bit)) > > + return -ENXIO; > > + } > > + > > + pds_num = of_property_count_u32_elems(node, "mediatek-pds_offset"); > > + if (pds_num <= 0) > > + return -ENXIO; > > + > > + size = pds_num * sizeof(u32); > > + devapc_ctx->pds_offset = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); > > + if (!devapc_ctx->pds_offset) > > + return -ENOMEM; > > + > > + for (i = 0; i < pds_num; i++) { > > + if (of_property_read_u32_index(node, "mediatek-pds_offset", i, > > + &devapc_ctx->pds_offset[i])) > > + return -ENXIO; > > + } > > + > > + devapc_irq = irq_of_parse_and_map(node, 0); > > + if (!devapc_irq) > > + return -EINVAL; > > + > > + devapc_infra_clk = devm_clk_get(&pdev->dev, "devapc-infra-clock"); > > + if (IS_ERR(devapc_infra_clk)) > > + return -EINVAL; > > + > > + if (clk_prepare_enable(devapc_infra_clk)) > > + return -EINVAL; > > + > > + start_devapc(devapc_ctx); > > + > > + ret = devm_request_irq(&pdev->dev, devapc_irq, > > + (irq_handler_t)devapc_violation_irq, > > + IRQF_TRIGGER_NONE, "devapc", devapc_ctx); > > + if (ret) > > + return ret; > > + > > + return 0; > > +} > > + > > +static int mtk_devapc_remove(struct platform_device *dev) > > +{ > > + return 0; > > +} > > + > > +static const struct of_device_id mtk_devapc_dt_match[] = { > > + { .compatible = "mediatek,mt6779-devapc" }, > > + {}, > > +}; > > + > > +static struct platform_driver mtk_devapc_driver = { > > + .probe = mtk_devapc_probe, > > + .remove = mtk_devapc_remove, > > + .driver = { > > + .name = KBUILD_MODNAME, > > + .of_match_table = mtk_devapc_dt_match, > > + }, > > +}; > > + > > +module_platform_driver(mtk_devapc_driver); > > + > > +MODULE_DESCRIPTION("Mediatek Device APC Driver"); > > +MODULE_AUTHOR("Neal Liu "); > > +MODULE_LICENSE("GPL"); > > diff --git a/drivers/soc/mediatek/mtk-devapc.h b/drivers/soc/mediatek/mtk-devapc.h > > new file mode 100644 > > index 0000000..ab2cb14 > > --- /dev/null > > +++ b/drivers/soc/mediatek/mtk-devapc.h > > @@ -0,0 +1,670 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * Copyright (C) 2020 MediaTek Inc. > > + */ > > + > > +#ifndef __MTK_DEVAPC_H__ > > +#define __MTK_DEVAPC_H__ > > + > > +#define PFX "[DEVAPC]: " > > use dev_err() and friends instead. Okay, I'll remove it. > > > + > > +#define VIO_MASK_STA_REG_GET(m) \ > > +({ \ > > + typeof(m) (_m) = (m); \ > > + reg_index = _m / 32; \ > > + reg_offset = _m % 32; \ > > +}) > > don't do that. no explicit variable assingment in a macro, the macro should > return the value. Okay, I'll revise it in next patches. > > > + > > +enum DEVAPC_PD_REG_TYPE { > > + VIO_MASK = 0, > > + VIO_STA, > > + VIO_DBG0, > > + VIO_DBG1, > > + APC_CON, > > + VIO_SHIFT_STA, > > + VIO_SHIFT_SEL, > > + VIO_SHIFT_CON, > > + PD_REG_TYPE_NUM, > > +}; > > + > > +enum DEVAPC_VIO_DBGS_TYPE { > > + MSTID = 0, > > + DMNID, > > + VIO_W, > > + VIO_R, > > + ADDR_H, > > +}; > > + > > +struct mtk_device_info { > > + int sys_index; > > + int ctrl_index; > > + int vio_index; > > +}; > > + > > +static struct mtk_device_info mtk_devices_infra[] = { > > That's for mt6779, correct? Should be stated in the name. Okay. I have another way to reach the goal without using this struct array. I'll send another patches. > > > + /* sys_idx, ctrl_idx, vio_idx */ > > + /* 0 */ > > + {0, 0, 0}, > > + {0, 1, 1}, > > + {0, 2, 2}, > > + {0, 3, 3}, > > + {0, 4, 4}, > > + {0, 5, 5}, > > + {0, 6, 6}, > > + {0, 7, 7}, > > + {0, 8, 8}, > > + {0, 9, 9}, > > + > > + /* 10 */ > > + {0, 10, 10}, > > + {0, 11, 11}, > > + {0, 12, 12}, > > + {0, 13, 13}, > > + {0, 14, 14}, > > + {0, 15, 15}, > > + {0, 16, 16}, > > + {0, 17, 17}, > > + {0, 18, 18}, > > + {0, 19, 19}, > > + > > + /* 20 */ > > + {0, 20, 20}, > > + {0, 21, 21}, > > + {0, 22, 22}, > > + {0, 23, 23}, > > + {0, 24, 24}, > > + {0, 25, 25}, > > + {0, 26, 26}, > > + {0, 27, 27}, > > + {0, 28, 28}, > > + {0, 29, 29}, > > + > > + /* 30 */ > > + {0, 30, 30}, > > + {0, 31, 31}, > > + {0, 32, 32}, > > + {0, 33, 77}, > > + {0, 34, 78}, > > + {0, 35, 79}, > > + {0, 35, 80}, > > + {0, 37, 37}, > > + {0, 38, 38}, > > + {0, 39, 39}, > > + > > + /* 40 */ > > + {0, 40, 40}, > > + {0, 41, 41}, > > + {0, 42, 42}, > > + {0, 43, 43}, > > + {0, 44, 44}, > > + {0, 45, 45}, > > + {0, 46, 46}, > > + {0, 47, 47}, > > + {0, 48, 48}, > > + {0, 49, 49}, > > + > > + /* 50 */ > > + {0, 50, 50}, > > + {0, 51, 51}, > > + {0, 52, 52}, > > + {0, 53, 53}, > > + {0, 54, 54}, > > + {0, 55, 55}, > > + {0, 56, 56}, > > + {0, 57, 57}, > > + {0, 58, 58}, > > + {0, 59, 59}, > > + > > + /* 60 */ > > + {0, 60, 60}, > > + {0, 61, 61}, > > + {0, 62, 62}, > > + {0, 63, 63}, > > + {0, 64, 64}, > > + {0, 65, 70}, > > + {0, 66, 71}, > > + {0, 67, 72}, > > + {0, 68, 73}, > > + {0, 70, 81}, > > + > > + /* 70 */ > > + {0, 71, 82}, > > + {0, 72, 83}, > > + {0, 73, 84}, > > + {0, 74, 85}, > > + {0, 75, 86}, > > + {0, 76, 87}, > > + {0, 77, 88}, > > + {0, 78, 89}, > > + {0, 79, 90}, > > + {0, 80, 91}, > > + > > + /* 80 */ > > + {0, 81, 92}, > > + {0, 82, 93}, > > + {0, 83, 94}, > > + {0, 84, 95}, > > + {0, 85, 96}, > > + {0, 86, 97}, > > + {0, 87, 98}, > > + {0, 88, 99}, > > + {0, 89, 100}, > > + {0, 90, 101}, > > + > > + /* 90 */ > > + {0, 91, 102}, > > + {0, 92, 103}, > > + {0, 93, 104}, > > + {0, 94, 105}, > > + {0, 95, 106}, > > + {0, 96, 107}, > > + {0, 97, 108}, > > + {0, 98, 109}, > > + {0, 110, 110}, > > + {0, 111, 111}, > > + > > + /* 100 */ > > + {0, 112, 112}, > > + {0, 113, 113}, > > + {0, 114, 114}, > > + {0, 115, 115}, > > + {0, 116, 116}, > > + {0, 117, 117}, > > + {0, 118, 118}, > > + {0, 119, 119}, > > + {0, 120, 120}, > > + {0, 121, 121}, > > + > > + /* 110 */ > > + {0, 122, 122}, > > + {0, 123, 123}, > > + {0, 124, 124}, > > + {0, 125, 125}, > > + {0, 126, 126}, > > + {0, 127, 127}, > > + {0, 128, 128}, > > + {0, 129, 129}, > > + {0, 130, 130}, > > + {0, 131, 131}, > > + > > + /* 120 */ > > + {0, 132, 132}, > > + {0, 133, 133}, > > + {0, 134, 134}, > > + {0, 135, 135}, > > + {0, 136, 136}, > > + {0, 137, 137}, > > + {0, 138, 138}, > > + {0, 139, 139}, > > + {0, 140, 140}, > > + {0, 141, 141}, > > + > > + /* 130 */ > > + {0, 142, 142}, > > + {0, 143, 143}, > > + {0, 144, 144}, > > + {0, 145, 145}, > > + {0, 146, 146}, > > + {0, 147, 147}, > > + {0, 148, 148}, > > + {0, 149, 149}, > > + {0, 150, 150}, > > + {0, 151, 151}, > > + > > + /* 140 */ > > + {0, 152, 152}, > > + {0, 153, 153}, > > + {0, 154, 154}, > > + {0, 155, 155}, > > + {0, 156, 156}, > > + {0, 157, 157}, > > + {0, 158, 158}, > > + {0, 159, 159}, > > + {0, 160, 160}, > > + {0, 161, 161}, > > + > > + /* 150 */ > > + {0, 162, 162}, > > + {0, 163, 163}, > > + {0, 164, 164}, > > + {0, 165, 165}, > > + {0, 166, 166}, > > + {0, 167, 167}, > > + {0, 168, 168}, > > + {0, 169, 169}, > > + {0, 170, 170}, > > + {0, 171, 171}, > > + > > + /* 160 */ > > + {0, 172, 172}, > > + {0, 173, 173}, > > + {0, 174, 174}, > > + {0, 175, 175}, > > + {0, 176, 176}, > > + {0, 177, 177}, > > + {0, 178, 178}, > > + {0, 179, 179}, > > + {0, 180, 180}, > > + {0, 181, 181}, > > + > > + /* 170 */ > > + {0, 182, 182}, > > + {0, 183, 183}, > > + {0, 184, 184}, > > + {0, 185, 185}, > > + {0, 186, 186}, > > + {0, 187, 187}, > > + {0, 188, 188}, > > + {0, 189, 189}, > > + {0, 190, 190}, > > + {0, 191, 191}, > > + > > + /* 180 */ > > + {0, 192, 192}, > > + {0, 193, 193}, > > + {0, 194, 194}, > > + {0, 195, 195}, > > + {0, 196, 196}, > > + {0, 197, 197}, > > + {0, 198, 198}, > > + {0, 199, 199}, > > + {0, 200, 200}, > > + {0, 201, 201}, > > + > > + /* 190 */ > > + {0, 202, 202}, > > + {0, 203, 203}, > > + {0, 204, 204}, > > + {0, 205, 205}, > > + {0, 206, 206}, > > + {0, 207, 207}, > > + {0, 208, 208}, > > + {0, 209, 209}, > > + {0, 210, 210}, > > + {0, 211, 211}, > > + > > + /* 200 */ > > + {0, 212, 212}, > > + {0, 213, 213}, > > + {0, 214, 214}, > > + {0, 215, 215}, > > + {0, 216, 216}, > > + {0, 217, 217}, > > + {0, 218, 218}, > > + {0, 219, 219}, > > + {0, 220, 220}, > > + {0, 221, 221}, > > + > > + /* 210 */ > > + {0, 222, 222}, > > + {0, 223, 223}, > > + {0, 224, 224}, > > + {0, 225, 225}, > > + {0, 226, 226}, > > + {0, 227, 227}, > > + {0, 228, 228}, > > + {0, 229, 229}, > > + {0, 230, 230}, > > + {0, 231, 231}, > > + > > + /* 220 */ > > + {1, 0, 232}, > > + {1, 1, 233}, > > + {1, 2, 234}, > > + {1, 3, 235}, > > + {1, 4, 236}, > > + {1, 5, 237}, > > + {1, 6, 238}, > > + {1, 7, 239}, > > + {1, 8, 240}, > > + {1, 9, 241}, > > + > > + /* 230 */ > > + {1, 10, 242}, > > + {1, 11, 243}, > > + {1, 12, 244}, > > + {1, 13, 245}, > > + {1, 14, 246}, > > + {1, 15, 247}, > > + {1, 16, 248}, > > + {1, 17, 249}, > > + {1, 18, 250}, > > + {1, 19, 251}, > > + > > + /* 240 */ > > + {1, 20, 252}, > > + {1, 21, 253}, > > + {1, 22, 254}, > > + {1, 23, 255}, > > + {1, 24, 256}, > > + {1, 25, 257}, > > + {1, 26, 258}, > > + {1, 27, 259}, > > + {1, 28, 260}, > > + {1, 29, 261}, > > + > > + /* 250 */ > > + {1, 30, 262}, > > + {1, 31, 263}, > > + {1, 32, 264}, > > + {1, 33, 265}, > > + {1, 34, 266}, > > + {1, 35, 267}, > > + {1, 36, 268}, > > + {1, 37, 269}, > > + {1, 38, 270}, > > + {1, 39, 271}, > > + > > + /* 260 */ > > + {1, 40, 272}, > > + {1, 41, 273}, > > + {1, 42, 274}, > > + {1, 43, 275}, > > + {1, 44, 276}, > > + {1, 45, 277}, > > + {1, 46, 278}, > > + {1, 47, 279}, > > + {1, 48, 280}, > > + {1, 49, 281}, > > + > > + /* 270 */ > > + {1, 50, 282}, > > + {1, 51, 283}, > > + {1, 52, 284}, > > + {1, 53, 285}, > > + {1, 54, 286}, > > + {1, 55, 287}, > > + {1, 56, 288}, > > + {1, 57, 289}, > > + {1, 58, 290}, > > + {1, 59, 291}, > > + > > + /* 280 */ > > + {1, 60, 292}, > > + {1, 61, 293}, > > + {1, 62, 294}, > > + {1, 63, 295}, > > + {1, 64, 296}, > > + {1, 65, 297}, > > + {1, 66, 298}, > > + {1, 67, 299}, > > + {1, 68, 300}, > > + {1, 69, 301}, > > + > > + /* 290 */ > > + {1, 70, 302}, > > + {1, 71, 303}, > > + {1, 72, 304}, > > + {1, 73, 305}, > > + {1, 74, 306}, > > + {1, 75, 307}, > > + {1, 76, 308}, > > + {1, 77, 309}, > > + {1, 78, 310}, > > + {1, 79, 311}, > > + > > + /* 300 */ > > + {1, 80, 312}, > > + {1, 81, 313}, > > + {1, 82, 314}, > > + {1, 83, 315}, > > + {1, 84, 316}, > > + {1, 85, 317}, > > + {1, 86, 318}, > > + {1, 87, 319}, > > + {1, 88, 320}, > > + {1, 89, 321}, > > + > > + /* 310 */ > > + {1, 90, 322}, > > + {1, 91, 323}, > > + {1, 92, 324}, > > + {1, 93, 325}, > > + {1, 94, 326}, > > + {1, 95, 327}, > > + {1, 96, 328}, > > + {1, 97, 329}, > > + {1, 98, 330}, > > + {1, 99, 331}, > > + > > + /* 320 */ > > + {1, 100, 332}, > > + {1, 101, 333}, > > + {1, 102, 334}, > > + {1, 103, 335}, > > + {1, 104, 336}, > > + {1, 105, 337}, > > + {1, 106, 338}, > > + {1, 107, 339}, > > + {1, 108, 340}, > > + {1, 109, 341}, > > + > > + /* 330 */ > > + {1, 110, 342}, > > + {1, 111, 343}, > > + {1, 112, 344}, > > + {1, 113, 345}, > > + {1, 114, 346}, > > + {1, 115, 347}, > > + {1, 116, 348}, > > + {1, 117, 349}, > > + {1, 118, 350}, > > + {1, 119, 351}, > > + > > + /* 340 */ > > + {1, 120, 352}, > > + {1, 121, 353}, > > + {1, 122, 354}, > > + {1, 123, 355}, > > + {1, 124, 356}, > > + {1, 125, 357}, > > + {1, 126, 358}, > > + {1, 127, 359}, > > + {1, 128, 360}, > > + {1, 129, 361}, > > + > > + /* 350 */ > > + {1, 130, 362}, > > + {1, 131, 363}, > > + {1, 132, 364}, > > + {1, 133, 365}, > > + {1, 134, 366}, > > + {1, 135, 367}, > > + {1, 136, 368}, > > + {1, 137, 369}, > > + {1, 138, 370}, > > + {1, 139, 371}, > > + > > + /* 360 */ > > + {1, 140, 372}, > > + {1, 141, 373}, > > + {1, 142, 374}, > > + {1, 143, 375}, > > + {1, 144, 376}, > > + {1, 145, 377}, > > + {1, 146, 378}, > > + {1, 147, 379}, > > + {1, 148, 380}, > > + {1, 149, 381}, > > + > > + /* 370 */ > > + {1, 150, 382}, > > + {1, 151, 383}, > > + {1, 152, 384}, > > + {1, 153, 385}, > > + {1, 154, 386}, > > + {1, 155, 387}, > > + {1, 156, 388}, > > + {1, 157, 389}, > > + {1, 158, 390}, > > + {1, 159, 391}, > > + > > + /* 380 */ > > + {1, 160, 392}, > > + {1, 161, 393}, > > + {1, 162, 394}, > > + {1, 163, 395}, > > + {1, 164, 396}, > > + {1, 165, 397}, > > + {1, 166, 398}, > > + {1, 167, 399}, > > + {1, 168, 400}, > > + {1, 169, 401}, > > + > > + /* 390 */ > > + {1, 170, 402}, > > + {1, 171, 403}, > > + {1, 172, 404}, > > + {1, 173, 405}, > > + {1, 174, 406}, > > + {1, 175, 407}, > > + {1, 176, 408}, > > + {1, 177, 409}, > > + {1, 178, 410}, > > + {1, 179, 411}, > > + > > + /* 400 */ > > + {1, 180, 412}, > > + {1, 181, 413}, > > + {1, 182, 414}, > > + {1, 183, 415}, > > + {1, 184, 416}, > > + {1, 185, 417}, > > + {1, 186, 418}, > > + {1, 187, 419}, > > + {1, 188, 420}, > > + {1, 189, 421}, > > + > > + /* 410 */ > > + {1, 190, 422}, > > + {1, 191, 423}, > > + {1, 192, 424}, > > + {1, 193, 425}, > > + {1, 194, 426}, > > + {1, 195, 427}, > > + {1, 196, 428}, > > + {1, 197, 429}, > > + {1, 198, 430}, > > + {1, 199, 431}, > > + > > + /* 420 */ > > + {1, 200, 432}, > > + {1, 201, 433}, > > + {1, 202, 434}, > > + {1, 203, 435}, > > + {1, 204, 436}, > > + {1, 205, 437}, > > + {1, 206, 438}, > > + {1, 207, 439}, > > + {1, 208, 440}, > > + {1, 209, 441}, > > + > > + /* 430 */ > > + {1, 210, 442}, > > + {1, 211, 443}, > > + {1, 212, 444}, > > + {1, 213, 445}, > > + {1, 214, 446}, > > + {1, 215, 447}, > > + {1, 216, 448}, > > + {1, 217, 449}, > > + {1, 218, 450}, > > + {1, 219, 451}, > > + > > + /* 440 */ > > + {1, 220, 452}, > > + {1, 221, 453}, > > + {1, 222, 454}, > > + {1, 223, 455}, > > + {1, 224, 456}, > > + {1, 225, 457}, > > + {1, 226, 458}, > > + {1, 227, 459}, > > + {1, 228, 460}, > > + {1, 229, 461}, > > + > > + /* 450 */ > > + {1, 230, 462}, > > + {1, 231, 463}, > > + {1, 232, 464}, > > + {1, 233, 465}, > > + {1, 234, 466}, > > + {1, 235, 467}, > > + {1, 236, 468}, > > + {1, 237, 469}, > > + {1, 238, 470}, > > + {1, 239, 471}, > > + > > + /* 460 */ > > + {1, 240, 472}, > > + {1, 241, 473}, > > + {1, 242, 474}, > > + {1, 243, 475}, > > + {1, 244, 476}, > > + {1, 245, 477}, > > + {1, 246, 478}, > > + {-1, -1, 479}, > > + {-1, -1, 480}, > > + {-1, -1, 481}, > > + > > + /* 470 */ > > + {-1, -1, 482}, > > + {-1, -1, 483}, > > + {-1, -1, 484}, > > + {-1, -1, 485}, > > + {-1, -1, 486}, > > + {-1, -1, 487}, > > + {-1, -1, 488}, > > + {-1, -1, 489}, > > + {-1, -1, 490}, > > + {-1, -1, 491}, > > + > > + /* 480 */ > > + {-1, -1, 492}, > > + {-1, -1, 493}, > > + {-1, -1, 494}, > > + {-1, -1, 495}, > > + {-1, -1, 496}, > > + {-1, -1, 497}, > > + {-1, -1, 498}, > > + {-1, -1, 499}, > > + {-1, -1, 500}, > > + {-1, -1, 501}, > > + > > + /* 490 */ > > + {-1, -1, 502}, > > + {-1, -1, 503}, > > + {-1, -1, 504}, > > + {-1, -1, 505}, > > + {-1, -1, 506}, > > + {-1, -1, 507}, > > + {-1, -1, 508}, > > + {-1, -1, 509}, > > + {-1, -1, 510}, > > + > > +}; > > + > > +struct mtk_devapc_vio_info { > > + bool read; > > + bool write; > > + u32 vio_addr; > > + u32 vio_addr_high; > > + u32 master_id; > > + u32 domain_id; > > +}; > > + > > +struct mtk_devapc_vio_dbgs_desc { > > + u32 mask; > > + u32 start_bit; > > +}; > > + > > +struct mtk_devapc_context { > > + u8 slave_type_num; > > + void __iomem **devapc_pd_base; > > + const struct mtk_device_info **device_info; > > + struct mtk_devapc_vio_info *vio_info; > > + struct mtk_devapc_vio_dbgs_desc *vio_dbgs_desc; > > + u32 *pds_offset; > > +}; > > + > > Not sure if I get this right: > > struct mtk_devapc_offset { > u32 vio_mask; > u32 vio_sta; > u32 vio_dbg0; > u32 vio_dbg1; > ... > } > > struct mtk_devapc_context { > u8 pd_base_num; > void __iomem **devapc_pd_base; > struct mtk_devapc_offset *offset; > const struct mtk_device_info **device_info; > struct mtk_devapc_vio_info *vio_info; > struct mtk_devapc_vio_dbgs_desc *vio_dbgs_desc; > }; > > With this I think we can get rid of mtk_devapc_pd_get(). > mtk_devapc_pd_get() is used to calculate the vaddr of devapc pd register. It's based on different slave_type, pd_reg_type and reg_idx. I don't think it can be replaced with such simple data structures. > Sorry I'm not able to review the whole driver right now. Please also have a look > on my comments from v1. > > We will have to go little by little to get this into a good state. In case it > makes sense to have this in the kernel at all. > > Regards, > Matthias I'm appreciated for your review. It helps me to write better code and get closer to the kernel. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel