All of lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH 1/4] fdtdec: Add fdtdec_get_mem_size_base()
@ 2020-07-16  3:23 Bin Meng
  2020-07-16  3:23 ` [PATCH 2/4] fdtdec: Update fdtdec_setup_mem_size_base_fdt() to call fdtdec_get_mem_size_base() Bin Meng
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: Bin Meng @ 2020-07-16  3:23 UTC (permalink / raw)
  To: u-boot

From: Bin Meng <bin.meng@windriver.com>

This adds a new API fdtdec_get_mem_size_base() that does similar
thing to fdtdec_setup_mem_size_base_fdt(), but without assigning
gd->ram_size and gd->ram_base.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
---

 include/fdtdec.h | 22 ++++++++++++++++++++++
 lib/fdtdec.c     | 24 ++++++++++++++++++++++++
 2 files changed, 46 insertions(+)

diff --git a/include/fdtdec.h b/include/fdtdec.h
index abd6d42..460d57a 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -909,6 +909,28 @@ int fdtdec_decode_display_timing(const void *blob, int node, int index,
 				 struct display_timing *config);
 
 /**
+ * fdtdec_get_mem_size_base() - decode FDT to get ram size and base
+ *
+ * Decode the /memory 'reg' property to determine the size and start of the
+ * first memory bank, populate the global data with the size and start of the
+ * first bank of memory.
+ *
+ * This function should be called from a boards dram_init(). This helper
+ * function allows for boards to query the device tree for DRAM size and start
+ * address instead of hard coding the value in the case where the memory size
+ * and start address cannot be detected automatically.
+ *
+ * @param blob		FDT blob
+ * @param ram_size	buffer to hold the ram size to set
+ * @param ram_base	buffer to hold the ram base to set
+ *
+ * @return 0 if OK, -EINVAL if the /memory node or reg property is missing or
+ * invalid
+ */
+int fdtdec_get_mem_size_base(const void *blob,
+			     phys_size_t *ram_size, unsigned long *ram_base);
+
+/**
  * fdtdec_setup_mem_size_base_fdt() - decode and setup gd->ram_size and
  * gd->ram_start
  *
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 0dd7ff1..078ff7a 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1030,6 +1030,30 @@ int fdtdec_decode_display_timing(const void *blob, int parent, int index,
 	return ret;
 }
 
+int fdtdec_get_mem_size_base(const void *blob,
+			     phys_size_t *ram_size, unsigned long *ram_base)
+{
+	int ret, mem;
+	struct fdt_resource res;
+
+	mem = fdt_path_offset(blob, "/memory");
+	if (mem < 0) {
+		debug("%s: Missing /memory node\n", __func__);
+		return -EINVAL;
+	}
+
+	ret = fdt_get_resource(blob, mem, "reg", 0, &res);
+	if (ret != 0) {
+		debug("%s: Unable to decode first memory bank\n", __func__);
+		return -EINVAL;
+	}
+
+	*ram_size = (phys_size_t)(res.end - res.start + 1);
+	*ram_base = (unsigned long)res.start;
+
+	return 0;
+}
+
 int fdtdec_setup_mem_size_base_fdt(const void *blob)
 {
 	int ret, mem;
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 6+ messages in thread

* [PATCH 2/4] fdtdec: Update fdtdec_setup_mem_size_base_fdt() to call fdtdec_get_mem_size_base()
  2020-07-16  3:23 [PATCH 1/4] fdtdec: Add fdtdec_get_mem_size_base() Bin Meng
@ 2020-07-16  3:23 ` Bin Meng
  2020-07-16  3:23 ` [PATCH 3/4] riscv: dts: hifive-unleashed-a00: Make memory node available to SPL Bin Meng
  2020-07-16  3:23 ` [PATCH 4/4] ram: sifive: Avoid using hardcoded ram base and size Bin Meng
  2 siblings, 0 replies; 6+ messages in thread
From: Bin Meng @ 2020-07-16  3:23 UTC (permalink / raw)
  To: u-boot

From: Bin Meng <bin.meng@windriver.com>

The only difference betwen fdtdec_setup_mem_size_base_fdt() and
fdtdec_get_mem_size_base() is that the former does the assignment
to gd->ram_size and gd->ram_base.

Simplify the codes to call fdtdec_get_mem_size_base() directly.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
---

 lib/fdtdec.c | 19 ++++---------------
 1 file changed, 4 insertions(+), 15 deletions(-)

diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 078ff7a..015df84 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1056,23 +1056,12 @@ int fdtdec_get_mem_size_base(const void *blob,
 
 int fdtdec_setup_mem_size_base_fdt(const void *blob)
 {
-	int ret, mem;
-	struct fdt_resource res;
-
-	mem = fdt_path_offset(blob, "/memory");
-	if (mem < 0) {
-		debug("%s: Missing /memory node\n", __func__);
-		return -EINVAL;
-	}
+	int ret;
 
-	ret = fdt_get_resource(blob, mem, "reg", 0, &res);
-	if (ret != 0) {
-		debug("%s: Unable to decode first memory bank\n", __func__);
-		return -EINVAL;
-	}
+	ret = fdtdec_get_mem_size_base(blob, &gd->ram_size, &gd->ram_base);
+	if (ret)
+		return ret;
 
-	gd->ram_size = (phys_size_t)(res.end - res.start + 1);
-	gd->ram_base = (unsigned long)res.start;
 	debug("%s: Initial DRAM size %llx\n", __func__,
 	      (unsigned long long)gd->ram_size);
 
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 6+ messages in thread

* [PATCH 3/4] riscv: dts: hifive-unleashed-a00: Make memory node available to SPL
  2020-07-16  3:23 [PATCH 1/4] fdtdec: Add fdtdec_get_mem_size_base() Bin Meng
  2020-07-16  3:23 ` [PATCH 2/4] fdtdec: Update fdtdec_setup_mem_size_base_fdt() to call fdtdec_get_mem_size_base() Bin Meng
@ 2020-07-16  3:23 ` Bin Meng
  2020-07-16  3:23 ` [PATCH 4/4] ram: sifive: Avoid using hardcoded ram base and size Bin Meng
  2 siblings, 0 replies; 6+ messages in thread
From: Bin Meng @ 2020-07-16  3:23 UTC (permalink / raw)
  To: u-boot

From: Bin Meng <bin.meng@windriver.com>

Make memory node available to SPL in prepration to updates to SiFive
DDR RAM driver to read memory information from DT.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
---

 arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
index e037150..ebe8c07 100644
--- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
+++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
@@ -16,6 +16,10 @@
 		spi2 = &qspi2;
 	};
 
+	memory at 80000000 {
+		u-boot,dm-spl;
+	};
+
 	hfclk {
 		u-boot,dm-spl;
 	};
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 6+ messages in thread

* [PATCH 4/4] ram: sifive: Avoid using hardcoded ram base and size
  2020-07-16  3:23 [PATCH 1/4] fdtdec: Add fdtdec_get_mem_size_base() Bin Meng
  2020-07-16  3:23 ` [PATCH 2/4] fdtdec: Update fdtdec_setup_mem_size_base_fdt() to call fdtdec_get_mem_size_base() Bin Meng
  2020-07-16  3:23 ` [PATCH 3/4] riscv: dts: hifive-unleashed-a00: Make memory node available to SPL Bin Meng
@ 2020-07-16  3:23 ` Bin Meng
  2020-07-17  5:58   ` Leo Liang
  2 siblings, 1 reply; 6+ messages in thread
From: Bin Meng @ 2020-07-16  3:23 UTC (permalink / raw)
  To: u-boot

From: Bin Meng <bin.meng@windriver.com>

At present the SiFive FU540 RAM driver uses hard-coded memory base
address and size to initialize the DDR controller. This may not be
true when this driver is used on another board based on FU540.

Update the driver to read the memory information from DT and use
that during the initialization.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
---

 drivers/ram/sifive/fu540_ddr.c | 28 +++++++++++++---------------
 1 file changed, 13 insertions(+), 15 deletions(-)

diff --git a/drivers/ram/sifive/fu540_ddr.c b/drivers/ram/sifive/fu540_ddr.c
index f8f8ca9..2f38023 100644
--- a/drivers/ram/sifive/fu540_ddr.c
+++ b/drivers/ram/sifive/fu540_ddr.c
@@ -8,6 +8,7 @@
 
 #include <common.h>
 #include <dm.h>
+#include <fdtdec.h>
 #include <init.h>
 #include <ram.h>
 #include <regmap.h>
@@ -39,9 +40,6 @@
 #define DENALI_PHY_1152	1152
 #define DENALI_PHY_1214	1214
 
-#define PAYLOAD_DEST	0x80000000
-#define DDR_MEM_SIZE	(8UL * 1024UL * 1024UL * 1024UL)
-
 #define DRAM_CLASS_OFFSET			8
 #define DRAM_CLASS_DDR4				0xA
 #define OPTIMAL_RMODW_EN_OFFSET			0
@@ -65,6 +63,8 @@
 #define PHY_RX_CAL_DQ0_0_OFFSET			0
 #define PHY_RX_CAL_DQ1_0_OFFSET			16
 
+DECLARE_GLOBAL_DATA_PTR;
+
 struct fu540_ddrctl {
 	volatile u32 denali_ctl[265];
 };
@@ -235,8 +235,8 @@ static int fu540_ddr_setup(struct udevice *dev)
 	struct fu540_ddr_params *params = &plat->ddr_params;
 	volatile u32 *denali_ctl =  priv->ctl->denali_ctl;
 	volatile u32 *denali_phy =  priv->phy->denali_phy;
-	const u64 ddr_size = DDR_MEM_SIZE;
-	const u64 ddr_end = PAYLOAD_DEST + ddr_size;
+	const u64 ddr_size = priv->info.size;
+	const u64 ddr_end = priv->info.base + ddr_size;
 	int ret, i;
 	u32 physet;
 
@@ -302,7 +302,7 @@ static int fu540_ddr_setup(struct udevice *dev)
 		     | (1 << MULTIPLE_OUT_OF_RANGE_OFFSET));
 
 	/* set up range protection */
-	fu540_ddr_setup_range_protection(denali_ctl, DDR_MEM_SIZE);
+	fu540_ddr_setup_range_protection(denali_ctl, priv->info.size);
 
 	/* Mask off port command error interrupt DENALI_CTL_136 */
 	setbits_le32(DENALI_CTL_136 + denali_ctl,
@@ -314,14 +314,14 @@ static int fu540_ddr_setup(struct udevice *dev)
 
 	/* check size */
 	priv->info.size = get_ram_size((long *)priv->info.base,
-				       DDR_MEM_SIZE);
+				       ddr_size);
 
 	debug("%s : %lx\n", __func__, priv->info.size);
 
 	/* check memory access for all memory */
-	if (priv->info.size != DDR_MEM_SIZE) {
+	if (priv->info.size != ddr_size) {
 		printf("DDR invalid size : 0x%lx, expected 0x%lx\n",
-		       priv->info.size, DDR_MEM_SIZE);
+		       priv->info.size, (uintptr_t)ddr_size);
 		return -EINVAL;
 	}
 
@@ -333,6 +333,9 @@ static int fu540_ddr_probe(struct udevice *dev)
 {
 	struct fu540_ddr_info *priv = dev_get_priv(dev);
 
+	fdtdec_get_mem_size_base(gd->fdt_blob, (phys_size_t *)&priv->info.size,
+				 (unsigned long *)&priv->info.base);
+
 #if defined(CONFIG_SPL_BUILD)
 	struct regmap *map;
 	int ret;
@@ -368,14 +371,9 @@ static int fu540_ddr_probe(struct udevice *dev)
 	priv->phy = regmap_get_range(map, 1);
 	priv->physical_filter_ctrl = regmap_get_range(map, 2);
 
-	priv->info.base = CONFIG_SYS_SDRAM_BASE;
-
-	priv->info.size = 0;
 	return fu540_ddr_setup(dev);
-#else
-	priv->info.base = CONFIG_SYS_SDRAM_BASE;
-	priv->info.size = DDR_MEM_SIZE;
 #endif
+
 	return 0;
 }
 
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 6+ messages in thread

* [PATCH 4/4] ram: sifive: Avoid using hardcoded ram base and size
  2020-07-16  3:23 ` [PATCH 4/4] ram: sifive: Avoid using hardcoded ram base and size Bin Meng
@ 2020-07-17  5:58   ` Leo Liang
  2020-07-17  6:09     ` Bin Meng
  0 siblings, 1 reply; 6+ messages in thread
From: Leo Liang @ 2020-07-17  5:58 UTC (permalink / raw)
  To: u-boot

Hi Bin,

This whole patch set looks pretty good to me.

Just out of curiosity and as being rather new to the u-boot community,
would the following fix be more direct and avoid modifying general code?

On Wed, Jul 15, 2020 at 08:23:03PM -0700, Bin Meng wrote:
> From: Bin Meng <bin.meng@windriver.com>
> 
> At present the SiFive FU540 RAM driver uses hard-coded memory base
> address and size to initialize the DDR controller. This may not be
> true when this driver is used on another board based on FU540.
> 
> Update the driver to read the memory information from DT and use
> that during the initialization.
> 
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> ---
> 
>  drivers/ram/sifive/fu540_ddr.c | 28 +++++++++++++---------------
>  1 file changed, 13 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/ram/sifive/fu540_ddr.c b/drivers/ram/sifive/fu540_ddr.c
> index f8f8ca9..2f38023 100644
> --- a/drivers/ram/sifive/fu540_ddr.c
> +++ b/drivers/ram/sifive/fu540_ddr.c
> @@ -8,6 +8,7 @@
>  
>  #include <common.h>
>  #include <dm.h>
> +#include <fdtdec.h>
>  #include <init.h>
>  #include <ram.h>
>  #include <regmap.h>
> @@ -39,9 +40,6 @@
>  #define DENALI_PHY_1152	1152
>  #define DENALI_PHY_1214	1214
>  
> -#define PAYLOAD_DEST	0x80000000
> -#define DDR_MEM_SIZE	(8UL * 1024UL * 1024UL * 1024UL)
> -
>  #define DRAM_CLASS_OFFSET			8
>  #define DRAM_CLASS_DDR4				0xA
>  #define OPTIMAL_RMODW_EN_OFFSET			0
> @@ -65,6 +63,8 @@
>  #define PHY_RX_CAL_DQ0_0_OFFSET			0
>  #define PHY_RX_CAL_DQ1_0_OFFSET			16
>  
> +DECLARE_GLOBAL_DATA_PTR;
> +
>  struct fu540_ddrctl {
>  	volatile u32 denali_ctl[265];
>  };
> @@ -235,8 +235,8 @@ static int fu540_ddr_setup(struct udevice *dev)
>  	struct fu540_ddr_params *params = &plat->ddr_params;
>  	volatile u32 *denali_ctl =  priv->ctl->denali_ctl;
>  	volatile u32 *denali_phy =  priv->phy->denali_phy;
> -	const u64 ddr_size = DDR_MEM_SIZE;
> -	const u64 ddr_end = PAYLOAD_DEST + ddr_size;
> +	const u64 ddr_size = priv->info.size;
> +	const u64 ddr_end = priv->info.base + ddr_size;
>  	int ret, i;
>  	u32 physet;
>  
> @@ -302,7 +302,7 @@ static int fu540_ddr_setup(struct udevice *dev)
>  		     | (1 << MULTIPLE_OUT_OF_RANGE_OFFSET));
>  
>  	/* set up range protection */
> -	fu540_ddr_setup_range_protection(denali_ctl, DDR_MEM_SIZE);
> +	fu540_ddr_setup_range_protection(denali_ctl, priv->info.size);
>  
>  	/* Mask off port command error interrupt DENALI_CTL_136 */
>  	setbits_le32(DENALI_CTL_136 + denali_ctl,
> @@ -314,14 +314,14 @@ static int fu540_ddr_setup(struct udevice *dev)
>  
>  	/* check size */
>  	priv->info.size = get_ram_size((long *)priv->info.base,
> -				       DDR_MEM_SIZE);
> +				       ddr_size);
>  
>  	debug("%s : %lx\n", __func__, priv->info.size);
>  
>  	/* check memory access for all memory */
> -	if (priv->info.size != DDR_MEM_SIZE) {
> +	if (priv->info.size != ddr_size) {
>  		printf("DDR invalid size : 0x%lx, expected 0x%lx\n",
> -		       priv->info.size, DDR_MEM_SIZE);
> +		       priv->info.size, (uintptr_t)ddr_size);
>  		return -EINVAL;
>  	}
>  
> @@ -333,6 +333,9 @@ static int fu540_ddr_probe(struct udevice *dev)
>  {
>  	struct fu540_ddr_info *priv = dev_get_priv(dev);
>  
> +	fdtdec_get_mem_size_base(gd->fdt_blob, (phys_size_t *)&priv->info.size,
> +				 (unsigned long *)&priv->info.base);
> +

Instead of introducing new API,
could we do something as such with the existing API?

fdtdec_setup_mem_size_base(gd->blob);
priv->info.base = gd->ram_base;
priv->info.size = gd->ram_size;

>  #if defined(CONFIG_SPL_BUILD)
>  	struct regmap *map;
>  	int ret;
> @@ -368,14 +371,9 @@ static int fu540_ddr_probe(struct udevice *dev)
>  	priv->phy = regmap_get_range(map, 1);
>  	priv->physical_filter_ctrl = regmap_get_range(map, 2);
>  
> -	priv->info.base = CONFIG_SYS_SDRAM_BASE;
> -
> -	priv->info.size = 0;
>  	return fu540_ddr_setup(dev);
> -#else
> -	priv->info.base = CONFIG_SYS_SDRAM_BASE;
> -	priv->info.size = DDR_MEM_SIZE;
>  #endif
> +
>  	return 0;
>  }
>  
> -- 
> 2.7.4
>

Best regards,
Leo

^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH 4/4] ram: sifive: Avoid using hardcoded ram base and size
  2020-07-17  5:58   ` Leo Liang
@ 2020-07-17  6:09     ` Bin Meng
  0 siblings, 0 replies; 6+ messages in thread
From: Bin Meng @ 2020-07-17  6:09 UTC (permalink / raw)
  To: u-boot

Hi Leo,

On Fri, Jul 17, 2020 at 1:58 PM Leo Liang <ycliang@andestech.com> wrote:
>
> Hi Bin,
>
> This whole patch set looks pretty good to me.
>
> Just out of curiosity and as being rather new to the u-boot community,
> would the following fix be more direct and avoid modifying general code?
>
> On Wed, Jul 15, 2020 at 08:23:03PM -0700, Bin Meng wrote:
> > From: Bin Meng <bin.meng@windriver.com>
> >
> > At present the SiFive FU540 RAM driver uses hard-coded memory base
> > address and size to initialize the DDR controller. This may not be
> > true when this driver is used on another board based on FU540.
> >
> > Update the driver to read the memory information from DT and use
> > that during the initialization.
> >
> > Signed-off-by: Bin Meng <bin.meng@windriver.com>
> > ---
> >
> >  drivers/ram/sifive/fu540_ddr.c | 28 +++++++++++++---------------
> >  1 file changed, 13 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/ram/sifive/fu540_ddr.c b/drivers/ram/sifive/fu540_ddr.c
> > index f8f8ca9..2f38023 100644
> > --- a/drivers/ram/sifive/fu540_ddr.c
> > +++ b/drivers/ram/sifive/fu540_ddr.c
> > @@ -8,6 +8,7 @@
> >
> >  #include <common.h>
> >  #include <dm.h>
> > +#include <fdtdec.h>
> >  #include <init.h>
> >  #include <ram.h>
> >  #include <regmap.h>
> > @@ -39,9 +40,6 @@
> >  #define DENALI_PHY_1152      1152
> >  #define DENALI_PHY_1214      1214
> >
> > -#define PAYLOAD_DEST 0x80000000
> > -#define DDR_MEM_SIZE (8UL * 1024UL * 1024UL * 1024UL)
> > -
> >  #define DRAM_CLASS_OFFSET                    8
> >  #define DRAM_CLASS_DDR4                              0xA
> >  #define OPTIMAL_RMODW_EN_OFFSET                      0
> > @@ -65,6 +63,8 @@
> >  #define PHY_RX_CAL_DQ0_0_OFFSET                      0
> >  #define PHY_RX_CAL_DQ1_0_OFFSET                      16
> >
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> >  struct fu540_ddrctl {
> >       volatile u32 denali_ctl[265];
> >  };
> > @@ -235,8 +235,8 @@ static int fu540_ddr_setup(struct udevice *dev)
> >       struct fu540_ddr_params *params = &plat->ddr_params;
> >       volatile u32 *denali_ctl =  priv->ctl->denali_ctl;
> >       volatile u32 *denali_phy =  priv->phy->denali_phy;
> > -     const u64 ddr_size = DDR_MEM_SIZE;
> > -     const u64 ddr_end = PAYLOAD_DEST + ddr_size;
> > +     const u64 ddr_size = priv->info.size;
> > +     const u64 ddr_end = priv->info.base + ddr_size;
> >       int ret, i;
> >       u32 physet;
> >
> > @@ -302,7 +302,7 @@ static int fu540_ddr_setup(struct udevice *dev)
> >                    | (1 << MULTIPLE_OUT_OF_RANGE_OFFSET));
> >
> >       /* set up range protection */
> > -     fu540_ddr_setup_range_protection(denali_ctl, DDR_MEM_SIZE);
> > +     fu540_ddr_setup_range_protection(denali_ctl, priv->info.size);
> >
> >       /* Mask off port command error interrupt DENALI_CTL_136 */
> >       setbits_le32(DENALI_CTL_136 + denali_ctl,
> > @@ -314,14 +314,14 @@ static int fu540_ddr_setup(struct udevice *dev)
> >
> >       /* check size */
> >       priv->info.size = get_ram_size((long *)priv->info.base,
> > -                                    DDR_MEM_SIZE);
> > +                                    ddr_size);
> >
> >       debug("%s : %lx\n", __func__, priv->info.size);
> >
> >       /* check memory access for all memory */
> > -     if (priv->info.size != DDR_MEM_SIZE) {
> > +     if (priv->info.size != ddr_size) {
> >               printf("DDR invalid size : 0x%lx, expected 0x%lx\n",
> > -                    priv->info.size, DDR_MEM_SIZE);
> > +                    priv->info.size, (uintptr_t)ddr_size);
> >               return -EINVAL;
> >       }
> >
> > @@ -333,6 +333,9 @@ static int fu540_ddr_probe(struct udevice *dev)
> >  {
> >       struct fu540_ddr_info *priv = dev_get_priv(dev);
> >
> > +     fdtdec_get_mem_size_base(gd->fdt_blob, (phys_size_t *)&priv->info.size,
> > +                              (unsigned long *)&priv->info.base);
> > +
>
> Instead of introducing new API,
> could we do something as such with the existing API?
>
> fdtdec_setup_mem_size_base(gd->blob);
> priv->info.base = gd->ram_base;
> priv->info.size = gd->ram_size;

Yes, I think that works too. Maybe it's not worth introducing a new
API in fdtdec.

>
> >  #if defined(CONFIG_SPL_BUILD)
> >       struct regmap *map;
> >       int ret;
> > @@ -368,14 +371,9 @@ static int fu540_ddr_probe(struct udevice *dev)
> >       priv->phy = regmap_get_range(map, 1);
> >       priv->physical_filter_ctrl = regmap_get_range(map, 2);
> >
> > -     priv->info.base = CONFIG_SYS_SDRAM_BASE;
> > -
> > -     priv->info.size = 0;
> >       return fu540_ddr_setup(dev);
> > -#else
> > -     priv->info.base = CONFIG_SYS_SDRAM_BASE;
> > -     priv->info.size = DDR_MEM_SIZE;
> >  #endif
> > +
> >       return 0;
> >  }
> >

Regards,
Bin

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2020-07-17  6:09 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-16  3:23 [PATCH 1/4] fdtdec: Add fdtdec_get_mem_size_base() Bin Meng
2020-07-16  3:23 ` [PATCH 2/4] fdtdec: Update fdtdec_setup_mem_size_base_fdt() to call fdtdec_get_mem_size_base() Bin Meng
2020-07-16  3:23 ` [PATCH 3/4] riscv: dts: hifive-unleashed-a00: Make memory node available to SPL Bin Meng
2020-07-16  3:23 ` [PATCH 4/4] ram: sifive: Avoid using hardcoded ram base and size Bin Meng
2020-07-17  5:58   ` Leo Liang
2020-07-17  6:09     ` Bin Meng

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.