From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC43BC433E5 for ; Thu, 16 Jul 2020 13:59:22 +0000 (UTC) Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 602A520787 for ; Thu, 16 Jul 2020 13:59:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 602A520787 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=ellerman.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4B6wpv1NrzzDr3L for ; Thu, 16 Jul 2020 23:59:19 +1000 (AEST) Received: from ozlabs.org (bilbo.ozlabs.org [203.11.71.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4B6vQ26GWQzDqS7 for ; Thu, 16 Jul 2020 22:56:10 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=ellerman.id.au Received: by ozlabs.org (Postfix, from userid 1034) id 4B6vPs1fvFz9sT6; Thu, 16 Jul 2020 22:56:01 +1000 (AEST) From: Michael Ellerman To: Madhavan Srinivasan , mpe@ellerman.id.au In-Reply-To: <20200713144623.508695-1-maddy@linux.ibm.com> References: <20200713144623.508695-1-maddy@linux.ibm.com> Subject: Re: [PATCH v2] powerpc/perf: Add kernel support for new MSR[HV PR] bits in trace-imc Message-Id: <159490401759.3805857.5732304624752324949.b4-ty@ellerman.id.au> Date: Thu, 16 Jul 2020 22:56:01 +1000 (AEST) X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anju T Sudhakar , linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Mon, 13 Jul 2020 20:16:23 +0530, Madhavan Srinivasan wrote: > IMC trace-mode record has MSR[HV PR] bits added in the third DW. > These bits can be used to set the cpumode for the instruction pointer > captured in each sample. > > Add support in kernel to use these bits to set the cpumode for > each sample. Applied to powerpc/next. [1/1] powerpc/perf: Add kernel support for new MSR[HV PR] bits in trace-imc https://git.kernel.org/powerpc/c/77ca3951cc37727ae8361d583a30da7a1b84e427 cheers