From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.4 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,MIME_BASE64_TEXT,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7472C433E3 for ; Tue, 21 Jul 2020 03:59:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 78DB4208E4 for ; Tue, 21 Jul 2020 03:59:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="oZivCz7Z" Received: (majordomo@vger.kernel.org) by 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base64 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org TWVkaWFUZWsgYnVzIGZhYnJpYyBwcm92aWRlcyBUcnVzdFpvbmUgc2VjdXJpdHkgc3VwcG9ydCBh bmQgZGF0YQ0KcHJvdGVjdGlvbiB0byBwcmV2ZW50IHNsYXZlcyBmcm9tIGJlaW5nIGFjY2Vzc2Vk IGJ5IHVuZXhwZWN0ZWQNCm1hc3RlcnMuDQpUaGUgc2VjdXJpdHkgdmlvbGF0aW9uIGlzIGxvZ2dl ZCBhbmQgc2VudCB0byB0aGUgcHJvY2Vzc29yIGZvcg0KZnVydGhlciBhbmFseXNpcyBvciBjb3Vu dGVybWVhc3VyZXMuDQoNCkFueSBvY2N1cnJlbmNlIG9mIHNlY3VyaXR5IHZpb2xhdGlvbiB3b3Vs ZCByYWlzZSBhbiBpbnRlcnJ1cHQsIGFuZA0KaXQgd2lsbCBiZSBoYW5kbGVkIGJ5IG10ay1kZXZh cGMgZHJpdmVyLiBUaGUgdmlvbGF0aW9uDQppbmZvcm1hdGlvbiBpcyBwcmludGVkIGluIG9yZGVy IHRvIGZpbmQgdGhlIG11cmRlcmVyLg0KDQpTaWduZWQtb2ZmLWJ5OiBOZWFsIExpdSA8bmVhbC5s aXVAbWVkaWF0ZWsuY29tPg0KLS0tDQogZHJpdmVycy9zb2MvbWVkaWF0ZWsvS2NvbmZpZyAgICAg IHwgICAgOSArDQogZHJpdmVycy9zb2MvbWVkaWF0ZWsvTWFrZWZpbGUgICAgIHwgICAgMSArDQog ZHJpdmVycy9zb2MvbWVkaWF0ZWsvbXRrLWRldmFwYy5jIHwgIDM3MiArKysrKysrKysrKysrKysr KysrKysrKysrKysrKysrKysrKysrDQogZHJpdmVycy9zb2MvbWVkaWF0ZWsvbXRrLWRldmFwYy5o IHwgICA1NCArKysrKysNCiA0IGZpbGVzIGNoYW5nZWQsIDQzNiBpbnNlcnRpb25zKCspDQogY3Jl YXRlIG1vZGUgMTAwNjQ0IGRyaXZlcnMvc29jL21lZGlhdGVrL210ay1kZXZhcGMuYw0KIGNyZWF0 ZSBtb2RlIDEwMDY0NCBkcml2ZXJzL3NvYy9tZWRpYXRlay9tdGstZGV2YXBjLmgNCg0KZGlmZiAt LWdpdCBhL2RyaXZlcnMvc29jL21lZGlhdGVrL0tjb25maWcgYi9kcml2ZXJzL3NvYy9tZWRpYXRl ay9LY29uZmlnDQppbmRleCA1OWE1NmNkLi4xMTc3Yzk4IDEwMDY0NA0KLS0tIGEvZHJpdmVycy9z b2MvbWVkaWF0ZWsvS2NvbmZpZw0KKysrIGIvZHJpdmVycy9zb2MvbWVkaWF0ZWsvS2NvbmZpZw0K QEAgLTE3LDYgKzE3LDE1IEBAIGNvbmZpZyBNVEtfQ01EUQ0KIAkgIHRpbWUgbGltaXRhdGlvbiwg c3VjaCBhcyB1cGRhdGluZyBkaXNwbGF5IGNvbmZpZ3VyYXRpb24gZHVyaW5nIHRoZQ0KIAkgIHZi bGFuay4NCiANCitjb25maWcgTVRLX0RFVkFQQw0KKwl0cmlzdGF0ZSAiTWVkaWF0ZWsgRGV2aWNl IEFQQyBTdXBwb3J0Ig0KKwloZWxwDQorCSAgU2F5IHllcyBoZXJlIHRvIGVuYWJsZSBzdXBwb3J0 IGZvciBNZWRpYXRlayBEZXZpY2UgQVBDIGRyaXZlci4NCisJICBUaGlzIGRyaXZlciBpcyBtYWlu bHkgdXNlZCB0byBoYW5kbGUgdGhlIHZpb2xhdGlvbiB3aGljaCBjYXRjaGVzDQorCSAgdW5leHBl Y3RlZCB0cmFuc2FjdGlvbi4NCisJICBUaGUgdmlvbGF0aW9uIGluZm9ybWF0aW9uIGlzIGxvZ2dl ZCBmb3IgZnVydGhlciBhbmFseXNpcyBvcg0KKwkgIGNvdW50ZXJtZWFzdXJlcy4NCisNCiBjb25m aWcgTVRLX0lORlJBQ0ZHDQogCWJvb2wgIk1lZGlhVGVrIElORlJBQ0ZHIFN1cHBvcnQiDQogCXNl bGVjdCBSRUdNQVANCmRpZmYgLS1naXQgYS9kcml2ZXJzL3NvYy9tZWRpYXRlay9NYWtlZmlsZSBi L2RyaXZlcnMvc29jL21lZGlhdGVrL01ha2VmaWxlDQppbmRleCAwMWY5Zjg3Li5hYmZkNGJhIDEw MDY0NA0KLS0tIGEvZHJpdmVycy9zb2MvbWVkaWF0ZWsvTWFrZWZpbGUNCisrKyBiL2RyaXZlcnMv c29jL21lZGlhdGVrL01ha2VmaWxlDQpAQCAtMSw1ICsxLDYgQEANCiAjIFNQRFgtTGljZW5zZS1J ZGVudGlmaWVyOiBHUEwtMi4wLW9ubHkNCiBvYmotJChDT05GSUdfTVRLX0NNRFEpICs9IG10ay1j bWRxLWhlbHBlci5vDQorb2JqLSQoQ09ORklHX01US19ERVZBUEMpICs9IG10ay1kZXZhcGMubw0K IG9iai0kKENPTkZJR19NVEtfSU5GUkFDRkcpICs9IG10ay1pbmZyYWNmZy5vDQogb2JqLSQoQ09O RklHX01US19QTUlDX1dSQVApICs9IG10ay1wbWljLXdyYXAubw0KIG9iai0kKENPTkZJR19NVEtf U0NQU1lTKSArPSBtdGstc2Nwc3lzLm8NCmRpZmYgLS1naXQgYS9kcml2ZXJzL3NvYy9tZWRpYXRl ay9tdGstZGV2YXBjLmMgYi9kcml2ZXJzL3NvYy9tZWRpYXRlay9tdGstZGV2YXBjLmMNCm5ldyBm aWxlIG1vZGUgMTAwNjQ0DQppbmRleCAwMDAwMDAwLi4xMzk3ZTk4DQotLS0gL2Rldi9udWxsDQor KysgYi9kcml2ZXJzL3NvYy9tZWRpYXRlay9tdGstZGV2YXBjLmMNCkBAIC0wLDAgKzEsMzcyIEBA DQorLy8gU1BEWC1MaWNlbnNlLUlkZW50aWZpZXI6IEdQTC0yLjANCisvKg0KKyAqIENvcHlyaWdo dCAoQykgMjAyMCBNZWRpYVRlayBJbmMuDQorICovDQorDQorI2luY2x1ZGUgPGxpbnV4L2Nsay5o Pg0KKyNpbmNsdWRlIDxsaW51eC9pbnRlcnJ1cHQuaD4NCisjaW5jbHVkZSA8bGludXgvaW9wb2xs Lmg+DQorI2luY2x1ZGUgPGxpbnV4L21vZHVsZS5oPg0KKyNpbmNsdWRlIDxsaW51eC9wbGF0Zm9y bV9kZXZpY2UuaD4NCisjaW5jbHVkZSA8bGludXgvb2ZfZGV2aWNlLmg+DQorI2luY2x1ZGUgPGxp bnV4L29mX2lycS5oPg0KKyNpbmNsdWRlIDxsaW51eC9vZl9hZGRyZXNzLmg+DQorI2luY2x1ZGUg Im10ay1kZXZhcGMuaCINCisNCitzdGF0aWMgdTMyIGdldF9zaGlmdF9ncm91cChzdHJ1Y3QgbXRr X2RldmFwY19jb250ZXh0ICpjdHgsIHUzMiB2aW9faWR4KQ0KK3sNCisJdTMyIHZpb19zaGlmdF9z dGE7DQorCXZvaWQgX19pb21lbSAqcmVnOw0KKw0KKwlyZWcgPSBjdHgtPmRldmFwY19wZF9iYXNl ICsgY3R4LT5vZmZzZXQtPnZpb19zaGlmdF9zdGE7DQorCXZpb19zaGlmdF9zdGEgPSByZWFkbChy ZWcpOw0KKw0KKwlpZiAodmlvX3NoaWZ0X3N0YSkNCisJCXJldHVybiBfX2Zmcyh2aW9fc2hpZnRf c3RhKTsNCisNCisJcmV0dXJuIDMxOw0KK30NCisNCitzdGF0aWMgaW50IGNoZWNrX3Zpb19tYXNr X3N0YShzdHJ1Y3QgbXRrX2RldmFwY19jb250ZXh0ICpjdHgsIHUzMiBtb2R1bGUsDQorCQkJICAg ICAgdTMyIG9mZnNldCkNCit7DQorCXZvaWQgX19pb21lbSAqcmVnOw0KKwl1MzIgdmFsdWU7DQor DQorCXJlZyA9IGN0eC0+ZGV2YXBjX3BkX2Jhc2UgKyBvZmZzZXQ7DQorCXJlZyArPSAweDQgKiBW SU9fTU9EX1RPX1JFR19JTkQobW9kdWxlKTsNCisNCisJdmFsdWUgPSByZWFkbChyZWcpOw0KKw0K KwlyZXR1cm4gKCh2YWx1ZSA+PiBWSU9fTU9EX1RPX1JFR19PRkYobW9kdWxlKSkgJiAweDEpOw0K K30NCisNCitzdGF0aWMgaW50IGNoZWNrX3Zpb19tYXNrKHN0cnVjdCBtdGtfZGV2YXBjX2NvbnRl eHQgKmN0eCwgdTMyIG1vZHVsZSkNCit7DQorCXJldHVybiBjaGVja192aW9fbWFza19zdGEoY3R4 LCBtb2R1bGUsIGN0eC0+b2Zmc2V0LT52aW9fbWFzayk7DQorfQ0KKw0KK3N0YXRpYyBpbnQgY2hl Y2tfdmlvX3N0YXR1cyhzdHJ1Y3QgbXRrX2RldmFwY19jb250ZXh0ICpjdHgsIHUzMiBtb2R1bGUp DQorew0KKwlyZXR1cm4gY2hlY2tfdmlvX21hc2tfc3RhKGN0eCwgbW9kdWxlLCBjdHgtPm9mZnNl dC0+dmlvX3N0YSk7DQorfQ0KKw0KK3N0YXRpYyB2b2lkIGNsZWFyX3Zpb19zdGF0dXMoc3RydWN0 IG10a19kZXZhcGNfY29udGV4dCAqY3R4LCB1MzIgbW9kdWxlKQ0KK3sNCisJdm9pZCBfX2lvbWVt ICpyZWc7DQorDQorCXJlZyA9IGN0eC0+ZGV2YXBjX3BkX2Jhc2UgKyBjdHgtPm9mZnNldC0+dmlv X3N0YTsNCisJcmVnICs9IDB4NCAqIFZJT19NT0RfVE9fUkVHX0lORChtb2R1bGUpOw0KKw0KKwl3 cml0ZWwoMHgxIDw8IFZJT19NT0RfVE9fUkVHX09GRihtb2R1bGUpLCByZWcpOw0KKw0KKwlpZiAo Y2hlY2tfdmlvX3N0YXR1cyhjdHgsIG1vZHVsZSkpDQorCQlkZXZfZXJyKGN0eC0+ZGV2LCAiJXM6 IENsZWFyIGZhaWxlZCwgbW9kdWxlX2luZGV4OjB4JXhcbiIsDQorCQkJX19mdW5jX18sIG1vZHVs ZSk7DQorfQ0KKw0KK3N0YXRpYyB2b2lkIG1hc2tfbW9kdWxlX2lycShzdHJ1Y3QgbXRrX2RldmFw Y19jb250ZXh0ICpjdHgsIHUzMiBtb2R1bGUsDQorCQkJICAgIGJvb2wgbWFzaykNCit7DQorCXZv aWQgX19pb21lbSAqcmVnOw0KKwl1MzIgdmFsdWU7DQorDQorCXJlZyA9IGN0eC0+ZGV2YXBjX3Bk X2Jhc2UgKyBjdHgtPm9mZnNldC0+dmlvX21hc2s7DQorCXJlZyArPSAweDQgKiBWSU9fTU9EX1RP X1JFR19JTkQobW9kdWxlKTsNCisNCisJdmFsdWUgPSByZWFkbChyZWcpOw0KKwlpZiAobWFzaykN CisJCXZhbHVlIHw9ICgweDEgPDwgVklPX01PRF9UT19SRUdfT0ZGKG1vZHVsZSkpOw0KKwllbHNl DQorCQl2YWx1ZSAmPSB+KDB4MSA8PCBWSU9fTU9EX1RPX1JFR19PRkYobW9kdWxlKSk7DQorDQor CXdyaXRlbCh2YWx1ZSwgcmVnKTsNCit9DQorDQorI2RlZmluZSBQSFlfREVWQVBDX1RJTUVPVVQJ MHgxMDAwMA0KKw0KKy8qDQorICogc3luY192aW9fZGJnIC0gZG8gInNoaWZ0IiBtZWNoYW5zaW0i IHRvIGdldCBmdWxsIHZpb2xhdGlvbiBpbmZvcm1hdGlvbi4NCisgKiAgICAgICAgICAgICAgICBz aGlmdCBtZWNoYW5pc20gaXMgZGVwZW5kcyBvbiBkZXZhcGMgaGFyZHdhcmUgZGVzaWduLg0KKyAq ICAgICAgICAgICAgICAgIE1lZGlhdGVrIGRldmFwYyBzZXQgbXVsdGlwbGUgc2xhdmVzIGFzIGEg Z3JvdXAuIFdoZW4gdmlvbGF0aW9uDQorICogICAgICAgICAgICAgICAgaXMgdHJpZ2dlcmVkLCB2 aW9sYXRpb24gaW5mbyBpcyBrZXB0IGluc2lkZSBkZXZhcGMgaGFyZHdhcmUuDQorICogICAgICAg ICAgICAgICAgRHJpdmVyIHNob3VsZCBkbyBzaGlmdCBtZWNoYW5zaW0gdG8gInNoaWZ0IiBmdWxs IHZpb2xhdGlvbg0KKyAqICAgICAgICAgICAgICAgIGluZm8gdG8gVklPX0RCR3MgcmVnaXN0ZXJz Lg0KKyAqDQorICovDQorc3RhdGljIGludCBzeW5jX3Zpb19kYmcoc3RydWN0IG10a19kZXZhcGNf Y29udGV4dCAqY3R4LCB1MzIgc2hpZnRfYml0KQ0KK3sNCisJdm9pZCBfX2lvbWVtICpwZF92aW9f c2hpZnRfc3RhX3JlZzsNCisJdm9pZCBfX2lvbWVtICpwZF92aW9fc2hpZnRfc2VsX3JlZzsNCisJ dm9pZCBfX2lvbWVtICpwZF92aW9fc2hpZnRfY29uX3JlZzsNCisJaW50IHJldDsNCisJdTMyIHZh bDsNCisNCisJcGRfdmlvX3NoaWZ0X3N0YV9yZWcgPSBjdHgtPmRldmFwY19wZF9iYXNlICsgY3R4 LT5vZmZzZXQtPnZpb19zaGlmdF9zdGE7DQorCXBkX3Zpb19zaGlmdF9zZWxfcmVnID0gY3R4LT5k ZXZhcGNfcGRfYmFzZSArIGN0eC0+b2Zmc2V0LT52aW9fc2hpZnRfc2VsOw0KKwlwZF92aW9fc2hp ZnRfY29uX3JlZyA9IGN0eC0+ZGV2YXBjX3BkX2Jhc2UgKyBjdHgtPm9mZnNldC0+dmlvX3NoaWZ0 X2NvbjsNCisNCisJLyogRW5hYmxlIHNoaWZ0IG1lY2hhbnNpbSAqLw0KKwl3cml0ZWwoMHgxIDw8 IHNoaWZ0X2JpdCwgcGRfdmlvX3NoaWZ0X3NlbF9yZWcpOw0KKwl3cml0ZWwoMHgxLCBwZF92aW9f c2hpZnRfY29uX3JlZyk7DQorDQorCXJldCA9IHJlYWRsX3BvbGxfdGltZW91dChwZF92aW9fc2hp ZnRfY29uX3JlZywgdmFsLCB2YWwgJiAweDMsIDEwMDAsDQorCQkJCSBQSFlfREVWQVBDX1RJTUVP VVQpOw0KKwlpZiAocmV0KQ0KKwkJZGV2X2VycihjdHgtPmRldiwgIiVzOiBTaGlmdCB2aW9sYXRp b24gaW5mbyBmYWlsZWRcbiIsDQorCQkJX19mdW5jX18pOw0KKw0KKwkvKiBEaXNhYmxlIHNoaWZ0 IG1lY2hhbmlzbSAqLw0KKwl3cml0ZWwoMHgwLCBwZF92aW9fc2hpZnRfY29uX3JlZyk7DQorCXdy aXRlbCgweDAsIHBkX3Zpb19zaGlmdF9zZWxfcmVnKTsNCisJd3JpdGVsKDB4MSA8PCBzaGlmdF9i aXQsIHBkX3Zpb19zaGlmdF9zdGFfcmVnKTsNCisNCisJcmV0dXJuIHJldDsNCit9DQorDQorc3Rh dGljIHZvaWQgZGV2YXBjX3Zpb19pbmZvX3ByaW50KHN0cnVjdCBtdGtfZGV2YXBjX2NvbnRleHQg KmN0eCkNCit7DQorCXN0cnVjdCBtdGtfZGV2YXBjX3Zpb19pbmZvICp2aW9faW5mbyA9IGN0eC0+ dmlvX2luZm87DQorDQorCS8qIFByaW50IHZpb2xhdGlvbiBpbmZvcm1hdGlvbiAqLw0KKwlpZiAo dmlvX2luZm8tPndyaXRlKQ0KKwkJZGV2X2luZm8oY3R4LT5kZXYsICJXcml0ZSBWaW9sYXRpb25c biIpOw0KKwllbHNlIGlmICh2aW9faW5mby0+cmVhZCkNCisJCWRldl9pbmZvKGN0eC0+ZGV2LCAi UmVhZCBWaW9sYXRpb25cbiIpOw0KKw0KKwlkZXZfaW5mbyhjdHgtPmRldiwgIlZpbyBBZGRyOjB4 JXgsIEhpZ2g6MHgleCwgQnVzIElEOjB4JXgsIERvbSBJRDoleFxuIiwNCisJCSB2aW9faW5mby0+ dmlvX2FkZHIsIHZpb19pbmZvLT52aW9fYWRkcl9oaWdoLA0KKwkJIHZpb19pbmZvLT5tYXN0ZXJf aWQsIHZpb19pbmZvLT5kb21haW5faWQpOw0KK30NCisNCisvKg0KKyAqIGRldmFwY19leHRyYWN0 X3Zpb19kYmcgLSBleHRyYWN0IGZ1bGwgdmlvbGF0aW9uIGluZm9ybWF0aW9uIGFmdGVyIGRvaW5n DQorICogICAgICAgICAgICAgICAgICAgICAgICAgIHNoaWZ0IG1lY2hhbmlzbS4NCisgKi8NCitz dGF0aWMgdm9pZCBkZXZhcGNfZXh0cmFjdF92aW9fZGJnKHN0cnVjdCBtdGtfZGV2YXBjX2NvbnRl eHQgKmN0eCkNCit7DQorCWNvbnN0IHN0cnVjdCBtdGtfZGV2YXBjX3Zpb19kYmdzICp2aW9fZGJn czsNCisJc3RydWN0IG10a19kZXZhcGNfdmlvX2luZm8gKnZpb19pbmZvOw0KKwl2b2lkIF9faW9t ZW0gKnZpb19kYmcwX3JlZzsNCisJdm9pZCBfX2lvbWVtICp2aW9fZGJnMV9yZWc7DQorCXUzMiBk YmcwOw0KKw0KKwl2aW9fZGJnMF9yZWcgPSBjdHgtPmRldmFwY19wZF9iYXNlICsgY3R4LT5vZmZz ZXQtPnZpb19kYmcwOw0KKwl2aW9fZGJnMV9yZWcgPSBjdHgtPmRldmFwY19wZF9iYXNlICsgY3R4 LT5vZmZzZXQtPnZpb19kYmcxOw0KKw0KKwl2aW9fZGJncyA9IGN0eC0+dmlvX2RiZ3M7DQorCXZp b19pbmZvID0gY3R4LT52aW9faW5mbzsNCisNCisJLyogU3RhcnRzIHRvIGV4dHJhY3QgdmlvbGF0 aW9uIGluZm9ybWF0aW9uICovDQorCWRiZzAgPSByZWFkbCh2aW9fZGJnMF9yZWcpOw0KKwl2aW9f aW5mby0+dmlvX2FkZHIgPSByZWFkbCh2aW9fZGJnMV9yZWcpOw0KKw0KKwl2aW9faW5mby0+bWFz dGVyX2lkID0gKGRiZzAgJiB2aW9fZGJncy0+bXN0aWQubWFzaykgPj4NCisJCQkgICAgICB2aW9f ZGJncy0+bXN0aWQuc3RhcnQ7DQorCXZpb19pbmZvLT5kb21haW5faWQgPSAoZGJnMCAmIHZpb19k YmdzLT5kbW5pZC5tYXNrKSA+Pg0KKwkJCSAgICAgIHZpb19kYmdzLT5kbW5pZC5zdGFydDsNCisJ dmlvX2luZm8tPndyaXRlID0gKChkYmcwICYgdmlvX2RiZ3MtPnZpb193Lm1hc2spID4+DQorCQkJ ICAgIHZpb19kYmdzLT52aW9fdy5zdGFydCkgPT0gMTsNCisJdmlvX2luZm8tPnJlYWQgPSAoKGRi ZzAgJiB2aW9fZGJncy0+dmlvX3IubWFzaykgPj4NCisJCQkgIHZpb19kYmdzLT52aW9fci5zdGFy dCkgPT0gMTsNCisJdmlvX2luZm8tPnZpb19hZGRyX2hpZ2ggPSAoZGJnMCAmIHZpb19kYmdzLT5h ZGRyX2gubWFzaykgPj4NCisJCQkJICB2aW9fZGJncy0+YWRkcl9oLnN0YXJ0Ow0KKw0KKwlkZXZh cGNfdmlvX2luZm9fcHJpbnQoY3R4KTsNCit9DQorDQorLyoNCisgKiBtdGtfZGV2YXBjX2R1bXBf dmlvX2RiZyAtIGdldCB0aGUgdmlvbGF0aW9uIGluZGV4IGFuZCBkdW1wIHRoZSBmdWxsIHZpb2xh dGlvbg0KKyAqICAgICAgICAgICAgICAgICAgICAgICAgICAgZGVidWcgaW5mb3JtYXRpb24uDQor ICovDQorc3RhdGljIGJvb2wgbXRrX2RldmFwY19kdW1wX3Zpb19kYmcoc3RydWN0IG10a19kZXZh cGNfY29udGV4dCAqY3R4LCB1MzIgdmlvX2lkeCkNCit7DQorCXUzMiBzaGlmdF9iaXQ7DQorDQor CWlmIChjaGVja192aW9fbWFzayhjdHgsIHZpb19pZHgpKQ0KKwkJcmV0dXJuIGZhbHNlOw0KKw0K KwlpZiAoIWNoZWNrX3Zpb19zdGF0dXMoY3R4LCB2aW9faWR4KSkNCisJCXJldHVybiBmYWxzZTsN CisNCisJc2hpZnRfYml0ID0gZ2V0X3NoaWZ0X2dyb3VwKGN0eCwgdmlvX2lkeCk7DQorDQorCWlm IChzeW5jX3Zpb19kYmcoY3R4LCBzaGlmdF9iaXQpKQ0KKwkJcmV0dXJuIGZhbHNlOw0KKw0KKwlk ZXZhcGNfZXh0cmFjdF92aW9fZGJnKGN0eCk7DQorDQorCXJldHVybiB0cnVlOw0KK30NCisNCisv Kg0KKyAqIGRldmFwY192aW9sYXRpb25faXJxIC0gdGhlIGRldmFwYyBJbnRlcnJ1cHQgU2Vydmlj ZSBSb3V0aW5lIChJU1IpIHdpbGwgZHVtcA0KKyAqICAgICAgICAgICAgICAgICAgICAgICAgdmlv bGF0aW9uIGluZm9ybWF0aW9uIGluY2x1ZGluZyB3aGljaCBtYXN0ZXIgdmlvbGF0ZXMNCisgKiAg ICAgICAgICAgICAgICAgICAgICAgIGFjY2VzcyBzbGF2ZS4NCisgKi8NCitzdGF0aWMgaXJxcmV0 dXJuX3QgZGV2YXBjX3Zpb2xhdGlvbl9pcnEoaW50IGlycV9udW1iZXIsDQorCQkJCQlzdHJ1Y3Qg bXRrX2RldmFwY19jb250ZXh0ICpjdHgpDQorew0KKwl1MzIgdmlvX2lkeDsNCisNCisJZm9yICh2 aW9faWR4ID0gMDsgdmlvX2lkeCA8IGN0eC0+dmlvX2lkeF9udW07IHZpb19pZHgrKykgew0KKwkJ aWYgKCFtdGtfZGV2YXBjX2R1bXBfdmlvX2RiZyhjdHgsIHZpb19pZHgpKQ0KKwkJCWNvbnRpbnVl Ow0KKw0KKwkJLyogRW5zdXJlIHRoYXQgdmlvbGF0aW9uIGluZm8gYXJlIHdyaXR0ZW4gYmVmb3Jl DQorCQkgKiBmdXJ0aGVyIG9wZXJhdGlvbnMNCisJCSAqLw0KKwkJc21wX21iKCk7DQorDQorCQkv Kg0KKwkJICogTWFzayBzbGF2ZSdzIGlycSBiZWZvcmUgY2xlYXJpbmcgdmlvIHN0YXR1cy4NCisJ CSAqIE11c3QgZG8gaXQgdG8gYXZvaWQgbmVzdGVkIGludGVycnVwdCBhbmQgcHJldmVudA0KKwkJ ICogdW5leHBlY3RlZCBiZWhhdmlvci4NCisJCSAqLw0KKwkJbWFza19tb2R1bGVfaXJxKGN0eCwg dmlvX2lkeCwgdHJ1ZSk7DQorDQorCQljbGVhcl92aW9fc3RhdHVzKGN0eCwgdmlvX2lkeCk7DQor DQorCQltYXNrX21vZHVsZV9pcnEoY3R4LCB2aW9faWR4LCBmYWxzZSk7DQorCX0NCisNCisJcmV0 dXJuIElSUV9IQU5ETEVEOw0KK30NCisNCisvKg0KKyAqIHN0YXJ0X2RldmFwYyAtIGluaXRpYWxp emUgZGV2YXBjIHN0YXR1cyBhbmQgc3RhcnQgcmVjZWl2aW5nIGludGVycnVwdA0KKyAqICAgICAg ICAgICAgICAgIHdoaWxlIGRldmFwYyB2aW9sYXRpb24gaXMgdHJpZ2dlcmVkLg0KKyAqLw0KK3N0 YXRpYyBpbnQgc3RhcnRfZGV2YXBjKHN0cnVjdCBtdGtfZGV2YXBjX2NvbnRleHQgKmN0eCkNCit7 DQorCXZvaWQgX19pb21lbSAqcGRfdmlvX3NoaWZ0X3N0YV9yZWc7DQorCXZvaWQgX19pb21lbSAq cGRfYXBjX2Nvbl9yZWc7DQorCXUzMiB2aW9fc2hpZnRfc3RhOw0KKwl1MzIgdmlvX2lkeDsNCisN CisJcGRfYXBjX2Nvbl9yZWcgPSBjdHgtPmRldmFwY19wZF9iYXNlICsgY3R4LT5vZmZzZXQtPmFw Y19jb247DQorCXBkX3Zpb19zaGlmdF9zdGFfcmVnID0gY3R4LT5kZXZhcGNfcGRfYmFzZSArIGN0 eC0+b2Zmc2V0LT52aW9fc2hpZnRfc3RhOw0KKwlpZiAoIXBkX2FwY19jb25fcmVnIHx8ICFwZF92 aW9fc2hpZnRfc3RhX3JlZykNCisJCXJldHVybiAtRUlOVkFMOw0KKw0KKwkvKiBDbGVhciBkZXZh cGMgdmlvbGF0aW9uIHN0YXR1cyAqLw0KKwl3cml0ZWwoQklUKDMxKSwgcGRfYXBjX2Nvbl9yZWcp Ow0KKw0KKwkvKiBDbGVhciB2aW9sYXRpb24gc2hpZnQgc3RhdHVzICovDQorCXZpb19zaGlmdF9z dGEgPSByZWFkbChwZF92aW9fc2hpZnRfc3RhX3JlZyk7DQorCWlmICh2aW9fc2hpZnRfc3RhKQ0K KwkJd3JpdGVsKHZpb19zaGlmdF9zdGEsIHBkX3Zpb19zaGlmdF9zdGFfcmVnKTsNCisNCisJLyog Q2xlYXIgc2xhdmUgdmlvbGF0aW9uIHN0YXR1cyAqLw0KKwlmb3IgKHZpb19pZHggPSAwOyB2aW9f aWR4IDwgY3R4LT52aW9faWR4X251bTsgdmlvX2lkeCsrKSB7DQorCQljbGVhcl92aW9fc3RhdHVz KGN0eCwgdmlvX2lkeCk7DQorCQltYXNrX21vZHVsZV9pcnEoY3R4LCB2aW9faWR4LCBmYWxzZSk7 DQorCX0NCisNCisJcmV0dXJuIDA7DQorfQ0KKw0KK3N0YXRpYyBjb25zdCBzdHJ1Y3QgbXRrX2Rl dmFwY19wZF9vZmZzZXQgbXQ2Nzc5X3BkX29mZnNldCA9IHsNCisJLnZpb19tYXNrID0gMHgwLA0K KwkudmlvX3N0YSA9IDB4NDAwLA0KKwkudmlvX2RiZzAgPSAweDkwMCwNCisJLnZpb19kYmcxID0g MHg5MDQsDQorCS5hcGNfY29uID0gMHhGMDAsDQorCS52aW9fc2hpZnRfc3RhID0gMHhGMTAsDQor CS52aW9fc2hpZnRfc2VsID0gMHhGMTQsDQorCS52aW9fc2hpZnRfY29uID0gMHhGMjAsDQorfTsN CisNCitzdGF0aWMgY29uc3Qgc3RydWN0IG10a19kZXZhcGNfdmlvX2RiZ3MgbXQ2Nzc5X3Zpb19k YmdzID0gew0KKwkubXN0aWQgPSAgezB4MDAwMEZGRkYsIDB4MH0sDQorCS5kbW5pZCA9ICB7MHgw MDNGMDAwMCwgMHgxMH0sDQorCS52aW9fdyA9ICB7MHgwMDQwMDAwMCwgMHgxNn0sDQorCS52aW9f ciA9ICB7MHgwMDgwMDAwMCwgMHgxN30sDQorCS5hZGRyX2ggPSB7MHgwRjAwMDAwMCwgMHgxOH0s DQorfTsNCisNCitzdGF0aWMgY29uc3Qgc3RydWN0IG10a19kZXZhcGNfY29udGV4dCBkZXZhcGNf bXQ2Nzc5ID0gew0KKwkudmlvX2lkeF9udW0gPSA1MTAsDQorCS5vZmZzZXQgPSAmbXQ2Nzc5X3Bk X29mZnNldCwNCisJLnZpb19kYmdzID0gJm10Njc3OV92aW9fZGJncywNCit9Ow0KKw0KK3N0YXRp YyBjb25zdCBzdHJ1Y3Qgb2ZfZGV2aWNlX2lkIG10a19kZXZhcGNfZHRfbWF0Y2hbXSA9IHsNCisJ ew0KKwkJLmNvbXBhdGlibGUgPSAibWVkaWF0ZWssbXQ2Nzc5LWRldmFwYyIsDQorCQkuZGF0YSA9 ICZkZXZhcGNfbXQ2Nzc5LA0KKwl9LCB7DQorCX0sDQorfTsNCisNCitzdGF0aWMgaW50IG10a19k ZXZhcGNfcHJvYmUoc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRldikNCit7DQorCXN0cnVjdCBk ZXZpY2Vfbm9kZSAqbm9kZSA9IHBkZXYtPmRldi5vZl9ub2RlOw0KKwlzdHJ1Y3QgbXRrX2RldmFw Y19jb250ZXh0ICpjdHg7DQorCXN0cnVjdCBjbGsgKmRldmFwY19pbmZyYV9jbGs7DQorCXUzMiBk ZXZhcGNfaXJxOw0KKwlpbnQgcmV0Ow0KKw0KKwlpZiAoSVNfRVJSKG5vZGUpKQ0KKwkJcmV0dXJu IC1FTk9ERVY7DQorDQorCWN0eCA9IGRldm1fa3phbGxvYygmcGRldi0+ZGV2LCBzaXplb2YoKmN0 eCksIEdGUF9LRVJORUwpOw0KKwlpZiAoIWN0eCkNCisJCXJldHVybiAtRU5PTUVNOw0KKw0KKwlj dHggPSAoc3RydWN0IG10a19kZXZhcGNfY29udGV4dCAqKW9mX2RldmljZV9nZXRfbWF0Y2hfZGF0 YSgmcGRldi0+ZGV2KTsNCisJY3R4LT5kZXYgPSAmcGRldi0+ZGV2Ow0KKw0KKwljdHgtPnZpb19p bmZvID0gZGV2bV9remFsbG9jKCZwZGV2LT5kZXYsDQorCQkJCSAgICAgc2l6ZW9mKHN0cnVjdCBt dGtfZGV2YXBjX3Zpb19pbmZvKSwNCisJCQkJICAgICBHRlBfS0VSTkVMKTsNCisJaWYgKCFjdHgt PnZpb19pbmZvKQ0KKwkJcmV0dXJuIC1FTk9NRU07DQorDQorCWN0eC0+ZGV2YXBjX3BkX2Jhc2Ug PSBvZl9pb21hcChub2RlLCAwKTsNCisJaWYgKCFjdHgtPmRldmFwY19wZF9iYXNlKQ0KKwkJcmV0 dXJuIC1FSU5WQUw7DQorDQorCWRldmFwY19pcnEgPSBpcnFfb2ZfcGFyc2VfYW5kX21hcChub2Rl LCAwKTsNCisJaWYgKCFkZXZhcGNfaXJxKQ0KKwkJcmV0dXJuIC1FSU5WQUw7DQorDQorCWRldmFw Y19pbmZyYV9jbGsgPSBkZXZtX2Nsa19nZXQoJnBkZXYtPmRldiwgImRldmFwYy1pbmZyYS1jbG9j ayIpOw0KKwlpZiAoSVNfRVJSKGRldmFwY19pbmZyYV9jbGspKQ0KKwkJcmV0dXJuIC1FSU5WQUw7 DQorDQorCWlmIChjbGtfcHJlcGFyZV9lbmFibGUoZGV2YXBjX2luZnJhX2NsaykpDQorCQlyZXR1 cm4gLUVJTlZBTDsNCisNCisJcmV0ID0gc3RhcnRfZGV2YXBjKGN0eCk7DQorCWlmIChyZXQpDQor CQlyZXR1cm4gcmV0Ow0KKw0KKwlyZXQgPSBkZXZtX3JlcXVlc3RfaXJxKCZwZGV2LT5kZXYsIGRl dmFwY19pcnEsDQorCQkJICAgICAgIChpcnFfaGFuZGxlcl90KWRldmFwY192aW9sYXRpb25faXJx LA0KKwkJCSAgICAgICBJUlFGX1RSSUdHRVJfTk9ORSwgImRldmFwYyIsIGN0eCk7DQorCWlmIChy ZXQpDQorCQlyZXR1cm4gcmV0Ow0KKw0KKwlyZXR1cm4gMDsNCit9DQorDQorc3RhdGljIGludCBt dGtfZGV2YXBjX3JlbW92ZShzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpkZXYpDQorew0KKwlyZXR1 cm4gMDsNCit9DQorDQorc3RhdGljIHN0cnVjdCBwbGF0Zm9ybV9kcml2ZXIgbXRrX2RldmFwY19k cml2ZXIgPSB7DQorCS5wcm9iZSA9IG10a19kZXZhcGNfcHJvYmUsDQorCS5yZW1vdmUgPSBtdGtf ZGV2YXBjX3JlbW92ZSwNCisJLmRyaXZlciA9IHsNCisJCS5uYW1lID0gS0JVSUxEX01PRE5BTUUs DQorCQkub2ZfbWF0Y2hfdGFibGUgPSBtdGtfZGV2YXBjX2R0X21hdGNoLA0KKwl9LA0KK307DQor DQorbW9kdWxlX3BsYXRmb3JtX2RyaXZlcihtdGtfZGV2YXBjX2RyaXZlcik7DQorDQorTU9EVUxF X0RFU0NSSVBUSU9OKCJNZWRpYXRlayBEZXZpY2UgQVBDIERyaXZlciIpOw0KK01PRFVMRV9BVVRI T1IoIk5lYWwgTGl1IDxuZWFsLmxpdUBtZWRpYXRlay5jb20+Iik7DQorTU9EVUxFX0xJQ0VOU0Uo IkdQTCIpOw0KZGlmZiAtLWdpdCBhL2RyaXZlcnMvc29jL21lZGlhdGVrL210ay1kZXZhcGMuaCBi L2RyaXZlcnMvc29jL21lZGlhdGVrL210ay1kZXZhcGMuaA0KbmV3IGZpbGUgbW9kZSAxMDA2NDQN CmluZGV4IDAwMDAwMDAuLjdiZDdlNjYNCi0tLSAvZGV2L251bGwNCisrKyBiL2RyaXZlcnMvc29j L21lZGlhdGVrL210ay1kZXZhcGMuaA0KQEAgLTAsMCArMSw1NCBAQA0KKy8qIFNQRFgtTGljZW5z ZS1JZGVudGlmaWVyOiBHUEwtMi4wICovDQorLyoNCisgKiBDb3B5cmlnaHQgKEMpIDIwMjAgTWVk aWFUZWsgSW5jLg0KKyAqLw0KKw0KKyNpZm5kZWYgX19NVEtfREVWQVBDX0hfXw0KKyNkZWZpbmUg X19NVEtfREVWQVBDX0hfXw0KKw0KKyNkZWZpbmUgVklPX01PRF9UT19SRUdfSU5EKG0pCSgobSkg LyAzMikNCisjZGVmaW5lIFZJT19NT0RfVE9fUkVHX09GRihtKQkoKG0pICUgMzIpDQorDQorc3Ry dWN0IG10a19kZXZhcGNfcGRfb2Zmc2V0IHsNCisJdTMyIHZpb19tYXNrOw0KKwl1MzIgdmlvX3N0 YTsNCisJdTMyIHZpb19kYmcwOw0KKwl1MzIgdmlvX2RiZzE7DQorCXUzMiBhcGNfY29uOw0KKwl1 MzIgdmlvX3NoaWZ0X3N0YTsNCisJdTMyIHZpb19zaGlmdF9zZWw7DQorCXUzMiB2aW9fc2hpZnRf Y29uOw0KK307DQorDQorc3RydWN0IG10a19kZXZhcGNfdmlvX2RiZ3NfZGVzYyB7DQorCXUzMiBt YXNrOw0KKwl1MzIgc3RhcnQ7DQorfTsNCisNCitzdHJ1Y3QgbXRrX2RldmFwY192aW9fZGJncyB7 DQorCXN0cnVjdCBtdGtfZGV2YXBjX3Zpb19kYmdzX2Rlc2MgbXN0aWQ7DQorCXN0cnVjdCBtdGtf ZGV2YXBjX3Zpb19kYmdzX2Rlc2MgZG1uaWQ7DQorCXN0cnVjdCBtdGtfZGV2YXBjX3Zpb19kYmdz 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, Matthias Brugger Subject: [PATCH v3 2/2] soc: mediatek: add mtk-devapc driver Date: Tue, 21 Jul 2020 11:59:31 +0800 Message-ID: <1595303971-8793-3-git-send-email-neal.liu@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1595303971-8793-1-git-send-email-neal.liu@mediatek.com> References: <1595303971-8793-1-git-send-email-neal.liu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 286DBE0385449444B7ED4DFE2B7ECFEB77A4A0B02E7E3BA5B071D643A490BD2D2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200720_235944_720461_DD0F14BA X-CRM114-Status: GOOD ( 21.26 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, wsd_upstream@mediatek.com, lkml , linux-mediatek@lists.infradead.org, Neal Liu , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org MediaTek bus fabric provides TrustZone security support and data protection to prevent slaves from being accessed by unexpected masters. The security violation is logged and sent to the processor for further analysis or countermeasures. Any occurrence of security violation would raise an interrupt, and it will be handled by mtk-devapc driver. The violation information is printed in order to find the murderer. Signed-off-by: Neal Liu --- drivers/soc/mediatek/Kconfig | 9 + drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mtk-devapc.c | 372 +++++++++++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-devapc.h | 54 ++++++ 4 files changed, 436 insertions(+) create mode 100644 drivers/soc/mediatek/mtk-devapc.c create mode 100644 drivers/soc/mediatek/mtk-devapc.h diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig index 59a56cd..1177c98 100644 --- a/drivers/soc/mediatek/Kconfig +++ b/drivers/soc/mediatek/Kconfig @@ -17,6 +17,15 @@ config MTK_CMDQ time limitation, such as updating display configuration during the vblank. +config MTK_DEVAPC + tristate "Mediatek Device APC Support" + help + Say yes here to enable support for Mediatek Device APC driver. + This driver is mainly used to handle the violation which catches + unexpected transaction. + The violation information is logged for further analysis or + countermeasures. + config MTK_INFRACFG bool "MediaTek INFRACFG Support" select REGMAP diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile index 01f9f87..abfd4ba 100644 --- a/drivers/soc/mediatek/Makefile +++ b/drivers/soc/mediatek/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o +obj-$(CONFIG_MTK_DEVAPC) += mtk-devapc.o obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-devapc.c new file mode 100644 index 0000000..1397e98 --- /dev/null +++ b/drivers/soc/mediatek/mtk-devapc.c @@ -0,0 +1,372 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "mtk-devapc.h" + +static u32 get_shift_group(struct mtk_devapc_context *ctx, u32 vio_idx) +{ + u32 vio_shift_sta; + void __iomem *reg; + + reg = ctx->devapc_pd_base + ctx->offset->vio_shift_sta; + vio_shift_sta = readl(reg); + + if (vio_shift_sta) + return __ffs(vio_shift_sta); + + return 31; +} + +static int check_vio_mask_sta(struct mtk_devapc_context *ctx, u32 module, + u32 offset) +{ + void __iomem *reg; + u32 value; + + reg = ctx->devapc_pd_base + offset; + reg += 0x4 * VIO_MOD_TO_REG_IND(module); + + value = readl(reg); + + return ((value >> VIO_MOD_TO_REG_OFF(module)) & 0x1); +} + +static int check_vio_mask(struct mtk_devapc_context *ctx, u32 module) +{ + return check_vio_mask_sta(ctx, module, ctx->offset->vio_mask); +} + +static int check_vio_status(struct mtk_devapc_context *ctx, u32 module) +{ + return check_vio_mask_sta(ctx, module, ctx->offset->vio_sta); +} + +static void clear_vio_status(struct mtk_devapc_context *ctx, u32 module) +{ + void __iomem *reg; + + reg = ctx->devapc_pd_base + ctx->offset->vio_sta; + reg += 0x4 * VIO_MOD_TO_REG_IND(module); + + writel(0x1 << VIO_MOD_TO_REG_OFF(module), reg); + + if (check_vio_status(ctx, module)) + dev_err(ctx->dev, "%s: Clear failed, module_index:0x%x\n", + __func__, module); +} + +static void mask_module_irq(struct mtk_devapc_context *ctx, u32 module, + bool mask) +{ + void __iomem *reg; + u32 value; + + reg = ctx->devapc_pd_base + ctx->offset->vio_mask; + reg += 0x4 * VIO_MOD_TO_REG_IND(module); + + value = readl(reg); + if (mask) + value |= (0x1 << VIO_MOD_TO_REG_OFF(module)); + else + value &= ~(0x1 << VIO_MOD_TO_REG_OFF(module)); + + writel(value, reg); +} + +#define PHY_DEVAPC_TIMEOUT 0x10000 + +/* + * sync_vio_dbg - do "shift" mechansim" to get full violation information. + * shift mechanism is depends on devapc hardware design. + * Mediatek devapc set multiple slaves as a group. When violation + * is triggered, violation info is kept inside devapc hardware. + * Driver should do shift mechansim to "shift" full violation + * info to VIO_DBGs registers. + * + */ +static int sync_vio_dbg(struct mtk_devapc_context *ctx, u32 shift_bit) +{ + void __iomem *pd_vio_shift_sta_reg; + void __iomem *pd_vio_shift_sel_reg; + void __iomem *pd_vio_shift_con_reg; + int ret; + u32 val; + + pd_vio_shift_sta_reg = ctx->devapc_pd_base + ctx->offset->vio_shift_sta; + pd_vio_shift_sel_reg = ctx->devapc_pd_base + ctx->offset->vio_shift_sel; + pd_vio_shift_con_reg = ctx->devapc_pd_base + ctx->offset->vio_shift_con; + + /* Enable shift mechansim */ + writel(0x1 << shift_bit, pd_vio_shift_sel_reg); + writel(0x1, pd_vio_shift_con_reg); + + ret = readl_poll_timeout(pd_vio_shift_con_reg, val, val & 0x3, 1000, + PHY_DEVAPC_TIMEOUT); + if (ret) + dev_err(ctx->dev, "%s: Shift violation info failed\n", + __func__); + + /* Disable shift mechanism */ + writel(0x0, pd_vio_shift_con_reg); + writel(0x0, pd_vio_shift_sel_reg); + writel(0x1 << shift_bit, pd_vio_shift_sta_reg); + + return ret; +} + +static void devapc_vio_info_print(struct mtk_devapc_context *ctx) +{ + struct mtk_devapc_vio_info *vio_info = ctx->vio_info; + + /* Print violation information */ + if (vio_info->write) + dev_info(ctx->dev, "Write Violation\n"); + else if (vio_info->read) + dev_info(ctx->dev, "Read Violation\n"); + + dev_info(ctx->dev, "Vio Addr:0x%x, High:0x%x, Bus ID:0x%x, Dom ID:%x\n", + vio_info->vio_addr, vio_info->vio_addr_high, + vio_info->master_id, vio_info->domain_id); +} + +/* + * devapc_extract_vio_dbg - extract full violation information after doing + * shift mechanism. + */ +static void devapc_extract_vio_dbg(struct mtk_devapc_context *ctx) +{ + const struct mtk_devapc_vio_dbgs *vio_dbgs; + struct mtk_devapc_vio_info *vio_info; + void __iomem *vio_dbg0_reg; + void __iomem *vio_dbg1_reg; + u32 dbg0; + + vio_dbg0_reg = ctx->devapc_pd_base + ctx->offset->vio_dbg0; + vio_dbg1_reg = ctx->devapc_pd_base + ctx->offset->vio_dbg1; + + vio_dbgs = ctx->vio_dbgs; + vio_info = ctx->vio_info; + + /* Starts to extract violation information */ + dbg0 = readl(vio_dbg0_reg); + vio_info->vio_addr = readl(vio_dbg1_reg); + + vio_info->master_id = (dbg0 & vio_dbgs->mstid.mask) >> + vio_dbgs->mstid.start; + vio_info->domain_id = (dbg0 & vio_dbgs->dmnid.mask) >> + vio_dbgs->dmnid.start; + vio_info->write = ((dbg0 & vio_dbgs->vio_w.mask) >> + vio_dbgs->vio_w.start) == 1; + vio_info->read = ((dbg0 & vio_dbgs->vio_r.mask) >> + vio_dbgs->vio_r.start) == 1; + vio_info->vio_addr_high = (dbg0 & vio_dbgs->addr_h.mask) >> + vio_dbgs->addr_h.start; + + devapc_vio_info_print(ctx); +} + +/* + * mtk_devapc_dump_vio_dbg - get the violation index and dump the full violation + * debug information. + */ +static bool mtk_devapc_dump_vio_dbg(struct mtk_devapc_context *ctx, u32 vio_idx) +{ + u32 shift_bit; + + if (check_vio_mask(ctx, vio_idx)) + return false; + + if (!check_vio_status(ctx, vio_idx)) + return false; + + shift_bit = get_shift_group(ctx, vio_idx); + + if (sync_vio_dbg(ctx, shift_bit)) + return false; + + devapc_extract_vio_dbg(ctx); + + return true; +} + +/* + * devapc_violation_irq - the devapc Interrupt Service Routine (ISR) will dump + * violation information including which master violates + * access slave. + */ +static irqreturn_t devapc_violation_irq(int irq_number, + struct mtk_devapc_context *ctx) +{ + u32 vio_idx; + + for (vio_idx = 0; vio_idx < ctx->vio_idx_num; vio_idx++) { + if (!mtk_devapc_dump_vio_dbg(ctx, vio_idx)) + continue; + + /* Ensure that violation info are written before + * further operations + */ + smp_mb(); + + /* + * Mask slave's irq before clearing vio status. + * Must do it to avoid nested interrupt and prevent + * unexpected behavior. + */ + mask_module_irq(ctx, vio_idx, true); + + clear_vio_status(ctx, vio_idx); + + mask_module_irq(ctx, vio_idx, false); + } + + return IRQ_HANDLED; +} + +/* + * start_devapc - initialize devapc status and start receiving interrupt + * while devapc violation is triggered. + */ +static int start_devapc(struct mtk_devapc_context *ctx) +{ + void __iomem *pd_vio_shift_sta_reg; + void __iomem *pd_apc_con_reg; + u32 vio_shift_sta; + u32 vio_idx; + + pd_apc_con_reg = ctx->devapc_pd_base + ctx->offset->apc_con; + pd_vio_shift_sta_reg = ctx->devapc_pd_base + ctx->offset->vio_shift_sta; + if (!pd_apc_con_reg || !pd_vio_shift_sta_reg) + return -EINVAL; + + /* Clear devapc violation status */ + writel(BIT(31), pd_apc_con_reg); + + /* Clear violation shift status */ + vio_shift_sta = readl(pd_vio_shift_sta_reg); + if (vio_shift_sta) + writel(vio_shift_sta, pd_vio_shift_sta_reg); + + /* Clear slave violation status */ + for (vio_idx = 0; vio_idx < ctx->vio_idx_num; vio_idx++) { + clear_vio_status(ctx, vio_idx); + mask_module_irq(ctx, vio_idx, false); + } + + return 0; +} + +static const struct mtk_devapc_pd_offset mt6779_pd_offset = { + .vio_mask = 0x0, + .vio_sta = 0x400, + .vio_dbg0 = 0x900, + .vio_dbg1 = 0x904, + .apc_con = 0xF00, + .vio_shift_sta = 0xF10, + .vio_shift_sel = 0xF14, + .vio_shift_con = 0xF20, +}; + +static const struct mtk_devapc_vio_dbgs mt6779_vio_dbgs = { + .mstid = {0x0000FFFF, 0x0}, + .dmnid = {0x003F0000, 0x10}, + .vio_w = {0x00400000, 0x16}, + .vio_r = {0x00800000, 0x17}, + .addr_h = {0x0F000000, 0x18}, +}; + +static const struct mtk_devapc_context devapc_mt6779 = { + .vio_idx_num = 510, + .offset = &mt6779_pd_offset, + .vio_dbgs = &mt6779_vio_dbgs, +}; + +static const struct of_device_id mtk_devapc_dt_match[] = { + { + .compatible = "mediatek,mt6779-devapc", + .data = &devapc_mt6779, + }, { + }, +}; + +static int mtk_devapc_probe(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct mtk_devapc_context *ctx; + struct clk *devapc_infra_clk; + u32 devapc_irq; + int ret; + + if (IS_ERR(node)) + return -ENODEV; + + ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx = (struct mtk_devapc_context *)of_device_get_match_data(&pdev->dev); + ctx->dev = &pdev->dev; + + ctx->vio_info = devm_kzalloc(&pdev->dev, + sizeof(struct mtk_devapc_vio_info), + GFP_KERNEL); + if (!ctx->vio_info) + return -ENOMEM; + + ctx->devapc_pd_base = of_iomap(node, 0); + if (!ctx->devapc_pd_base) + return -EINVAL; + + devapc_irq = irq_of_parse_and_map(node, 0); + if (!devapc_irq) + return -EINVAL; + + devapc_infra_clk = devm_clk_get(&pdev->dev, "devapc-infra-clock"); + if (IS_ERR(devapc_infra_clk)) + return -EINVAL; + + if (clk_prepare_enable(devapc_infra_clk)) + return -EINVAL; + + ret = start_devapc(ctx); + if (ret) + return ret; + + ret = devm_request_irq(&pdev->dev, devapc_irq, + (irq_handler_t)devapc_violation_irq, + IRQF_TRIGGER_NONE, "devapc", ctx); + if (ret) + return ret; + + return 0; +} + +static int mtk_devapc_remove(struct platform_device *dev) +{ + return 0; +} + +static struct platform_driver mtk_devapc_driver = { + .probe = mtk_devapc_probe, + .remove = mtk_devapc_remove, + .driver = { + .name = KBUILD_MODNAME, + .of_match_table = mtk_devapc_dt_match, + }, +}; + +module_platform_driver(mtk_devapc_driver); + +MODULE_DESCRIPTION("Mediatek Device APC Driver"); +MODULE_AUTHOR("Neal Liu "); +MODULE_LICENSE("GPL"); diff --git a/drivers/soc/mediatek/mtk-devapc.h b/drivers/soc/mediatek/mtk-devapc.h new file mode 100644 index 0000000..7bd7e66 --- /dev/null +++ b/drivers/soc/mediatek/mtk-devapc.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 MediaTek Inc. + */ + +#ifndef __MTK_DEVAPC_H__ +#define __MTK_DEVAPC_H__ + +#define VIO_MOD_TO_REG_IND(m) ((m) / 32) +#define VIO_MOD_TO_REG_OFF(m) ((m) % 32) + +struct mtk_devapc_pd_offset { + u32 vio_mask; + u32 vio_sta; + u32 vio_dbg0; + u32 vio_dbg1; + u32 apc_con; + u32 vio_shift_sta; + u32 vio_shift_sel; + u32 vio_shift_con; +}; + +struct mtk_devapc_vio_dbgs_desc { + u32 mask; + u32 start; +}; + +struct mtk_devapc_vio_dbgs { + struct mtk_devapc_vio_dbgs_desc mstid; + struct mtk_devapc_vio_dbgs_desc dmnid; + struct mtk_devapc_vio_dbgs_desc vio_w; + struct mtk_devapc_vio_dbgs_desc vio_r; + struct mtk_devapc_vio_dbgs_desc addr_h; +}; + +struct mtk_devapc_vio_info { + bool read; + bool write; + u32 vio_addr; + u32 vio_addr_high; + u32 master_id; + u32 domain_id; +}; + +struct mtk_devapc_context { + struct device *dev; + u32 vio_idx_num; + void __iomem *devapc_pd_base; + struct mtk_devapc_vio_info *vio_info; + const struct mtk_devapc_pd_offset *offset; + const struct mtk_devapc_vio_dbgs *vio_dbgs; +}; + +#endif /* __MTK_DEVAPC_H__ */ -- 1.7.9.5 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7EA7FC433DF for ; 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Tue, 21 Jul 2020 11:59:33 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 21 Jul 2020 11:59:33 +0800 From: Neal Liu To: Rob Herring , Matthias Brugger Subject: [PATCH v3 2/2] soc: mediatek: add mtk-devapc driver Date: Tue, 21 Jul 2020 11:59:31 +0800 Message-ID: <1595303971-8793-3-git-send-email-neal.liu@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1595303971-8793-1-git-send-email-neal.liu@mediatek.com> References: <1595303971-8793-1-git-send-email-neal.liu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 286DBE0385449444B7ED4DFE2B7ECFEB77A4A0B02E7E3BA5B071D643A490BD2D2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200720_235944_720461_DD0F14BA X-CRM114-Status: GOOD ( 21.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, wsd_upstream@mediatek.com, lkml , linux-mediatek@lists.infradead.org, Neal Liu , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org MediaTek bus fabric provides TrustZone security support and data protection to prevent slaves from being accessed by unexpected masters. The security violation is logged and sent to the processor for further analysis or countermeasures. Any occurrence of security violation would raise an interrupt, and it will be handled by mtk-devapc driver. The violation information is printed in order to find the murderer. Signed-off-by: Neal Liu --- drivers/soc/mediatek/Kconfig | 9 + drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mtk-devapc.c | 372 +++++++++++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-devapc.h | 54 ++++++ 4 files changed, 436 insertions(+) create mode 100644 drivers/soc/mediatek/mtk-devapc.c create mode 100644 drivers/soc/mediatek/mtk-devapc.h diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig index 59a56cd..1177c98 100644 --- a/drivers/soc/mediatek/Kconfig +++ b/drivers/soc/mediatek/Kconfig @@ -17,6 +17,15 @@ config MTK_CMDQ time limitation, such as updating display configuration during the vblank. +config MTK_DEVAPC + tristate "Mediatek Device APC Support" + help + Say yes here to enable support for Mediatek Device APC driver. + This driver is mainly used to handle the violation which catches + unexpected transaction. + The violation information is logged for further analysis or + countermeasures. + config MTK_INFRACFG bool "MediaTek INFRACFG Support" select REGMAP diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile index 01f9f87..abfd4ba 100644 --- a/drivers/soc/mediatek/Makefile +++ b/drivers/soc/mediatek/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o +obj-$(CONFIG_MTK_DEVAPC) += mtk-devapc.o obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-devapc.c new file mode 100644 index 0000000..1397e98 --- /dev/null +++ b/drivers/soc/mediatek/mtk-devapc.c @@ -0,0 +1,372 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "mtk-devapc.h" + +static u32 get_shift_group(struct mtk_devapc_context *ctx, u32 vio_idx) +{ + u32 vio_shift_sta; + void __iomem *reg; + + reg = ctx->devapc_pd_base + ctx->offset->vio_shift_sta; + vio_shift_sta = readl(reg); + + if (vio_shift_sta) + return __ffs(vio_shift_sta); + + return 31; +} + +static int check_vio_mask_sta(struct mtk_devapc_context *ctx, u32 module, + u32 offset) +{ + void __iomem *reg; + u32 value; + + reg = ctx->devapc_pd_base + offset; + reg += 0x4 * VIO_MOD_TO_REG_IND(module); + + value = readl(reg); + + return ((value >> VIO_MOD_TO_REG_OFF(module)) & 0x1); +} + +static int check_vio_mask(struct mtk_devapc_context *ctx, u32 module) +{ + return check_vio_mask_sta(ctx, module, ctx->offset->vio_mask); +} + +static int check_vio_status(struct mtk_devapc_context *ctx, u32 module) +{ + return check_vio_mask_sta(ctx, module, ctx->offset->vio_sta); +} + +static void clear_vio_status(struct mtk_devapc_context *ctx, u32 module) +{ + void __iomem *reg; + + reg = ctx->devapc_pd_base + ctx->offset->vio_sta; + reg += 0x4 * VIO_MOD_TO_REG_IND(module); + + writel(0x1 << VIO_MOD_TO_REG_OFF(module), reg); + + if (check_vio_status(ctx, module)) + dev_err(ctx->dev, "%s: Clear failed, module_index:0x%x\n", + __func__, module); +} + +static void mask_module_irq(struct mtk_devapc_context *ctx, u32 module, + bool mask) +{ + void __iomem *reg; + u32 value; + + reg = ctx->devapc_pd_base + ctx->offset->vio_mask; + reg += 0x4 * VIO_MOD_TO_REG_IND(module); + + value = readl(reg); + if (mask) + value |= (0x1 << VIO_MOD_TO_REG_OFF(module)); + else + value &= ~(0x1 << VIO_MOD_TO_REG_OFF(module)); + + writel(value, reg); +} + +#define PHY_DEVAPC_TIMEOUT 0x10000 + +/* + * sync_vio_dbg - do "shift" mechansim" to get full violation information. + * shift mechanism is depends on devapc hardware design. + * Mediatek devapc set multiple slaves as a group. When violation + * is triggered, violation info is kept inside devapc hardware. + * Driver should do shift mechansim to "shift" full violation + * info to VIO_DBGs registers. + * + */ +static int sync_vio_dbg(struct mtk_devapc_context *ctx, u32 shift_bit) +{ + void __iomem *pd_vio_shift_sta_reg; + void __iomem *pd_vio_shift_sel_reg; + void __iomem *pd_vio_shift_con_reg; + int ret; + u32 val; + + pd_vio_shift_sta_reg = ctx->devapc_pd_base + ctx->offset->vio_shift_sta; + pd_vio_shift_sel_reg = ctx->devapc_pd_base + ctx->offset->vio_shift_sel; + pd_vio_shift_con_reg = ctx->devapc_pd_base + ctx->offset->vio_shift_con; + + /* Enable shift mechansim */ + writel(0x1 << shift_bit, pd_vio_shift_sel_reg); + writel(0x1, pd_vio_shift_con_reg); + + ret = readl_poll_timeout(pd_vio_shift_con_reg, val, val & 0x3, 1000, + PHY_DEVAPC_TIMEOUT); + if (ret) + dev_err(ctx->dev, "%s: Shift violation info failed\n", + __func__); + + /* Disable shift mechanism */ + writel(0x0, pd_vio_shift_con_reg); + writel(0x0, pd_vio_shift_sel_reg); + writel(0x1 << shift_bit, pd_vio_shift_sta_reg); + + return ret; +} + +static void devapc_vio_info_print(struct mtk_devapc_context *ctx) +{ + struct mtk_devapc_vio_info *vio_info = ctx->vio_info; + + /* Print violation information */ + if (vio_info->write) + dev_info(ctx->dev, "Write Violation\n"); + else if (vio_info->read) + dev_info(ctx->dev, "Read Violation\n"); + + dev_info(ctx->dev, "Vio Addr:0x%x, High:0x%x, Bus ID:0x%x, Dom ID:%x\n", + vio_info->vio_addr, vio_info->vio_addr_high, + vio_info->master_id, vio_info->domain_id); +} + +/* + * devapc_extract_vio_dbg - extract full violation information after doing + * shift mechanism. + */ +static void devapc_extract_vio_dbg(struct mtk_devapc_context *ctx) +{ + const struct mtk_devapc_vio_dbgs *vio_dbgs; + struct mtk_devapc_vio_info *vio_info; + void __iomem *vio_dbg0_reg; + void __iomem *vio_dbg1_reg; + u32 dbg0; + + vio_dbg0_reg = ctx->devapc_pd_base + ctx->offset->vio_dbg0; + vio_dbg1_reg = ctx->devapc_pd_base + ctx->offset->vio_dbg1; + + vio_dbgs = ctx->vio_dbgs; + vio_info = ctx->vio_info; + + /* Starts to extract violation information */ + dbg0 = readl(vio_dbg0_reg); + vio_info->vio_addr = readl(vio_dbg1_reg); + + vio_info->master_id = (dbg0 & vio_dbgs->mstid.mask) >> + vio_dbgs->mstid.start; + vio_info->domain_id = (dbg0 & vio_dbgs->dmnid.mask) >> + vio_dbgs->dmnid.start; + vio_info->write = ((dbg0 & vio_dbgs->vio_w.mask) >> + vio_dbgs->vio_w.start) == 1; + vio_info->read = ((dbg0 & vio_dbgs->vio_r.mask) >> + vio_dbgs->vio_r.start) == 1; + vio_info->vio_addr_high = (dbg0 & vio_dbgs->addr_h.mask) >> + vio_dbgs->addr_h.start; + + devapc_vio_info_print(ctx); +} + +/* + * mtk_devapc_dump_vio_dbg - get the violation index and dump the full violation + * debug information. + */ +static bool mtk_devapc_dump_vio_dbg(struct mtk_devapc_context *ctx, u32 vio_idx) +{ + u32 shift_bit; + + if (check_vio_mask(ctx, vio_idx)) + return false; + + if (!check_vio_status(ctx, vio_idx)) + return false; + + shift_bit = get_shift_group(ctx, vio_idx); + + if (sync_vio_dbg(ctx, shift_bit)) + return false; + + devapc_extract_vio_dbg(ctx); + + return true; +} + +/* + * devapc_violation_irq - the devapc Interrupt Service Routine (ISR) will dump + * violation information including which master violates + * access slave. + */ +static irqreturn_t devapc_violation_irq(int irq_number, + struct mtk_devapc_context *ctx) +{ + u32 vio_idx; + + for (vio_idx = 0; vio_idx < ctx->vio_idx_num; vio_idx++) { + if (!mtk_devapc_dump_vio_dbg(ctx, vio_idx)) + continue; + + /* Ensure that violation info are written before + * further operations + */ + smp_mb(); + + /* + * Mask slave's irq before clearing vio status. + * Must do it to avoid nested interrupt and prevent + * unexpected behavior. + */ + mask_module_irq(ctx, vio_idx, true); + + clear_vio_status(ctx, vio_idx); + + mask_module_irq(ctx, vio_idx, false); + } + + return IRQ_HANDLED; +} + +/* + * start_devapc - initialize devapc status and start receiving interrupt + * while devapc violation is triggered. + */ +static int start_devapc(struct mtk_devapc_context *ctx) +{ + void __iomem *pd_vio_shift_sta_reg; + void __iomem *pd_apc_con_reg; + u32 vio_shift_sta; + u32 vio_idx; + + pd_apc_con_reg = ctx->devapc_pd_base + ctx->offset->apc_con; + pd_vio_shift_sta_reg = ctx->devapc_pd_base + ctx->offset->vio_shift_sta; + if (!pd_apc_con_reg || !pd_vio_shift_sta_reg) + return -EINVAL; + + /* Clear devapc violation status */ + writel(BIT(31), pd_apc_con_reg); + + /* Clear violation shift status */ + vio_shift_sta = readl(pd_vio_shift_sta_reg); + if (vio_shift_sta) + writel(vio_shift_sta, pd_vio_shift_sta_reg); + + /* Clear slave violation status */ + for (vio_idx = 0; vio_idx < ctx->vio_idx_num; vio_idx++) { + clear_vio_status(ctx, vio_idx); + mask_module_irq(ctx, vio_idx, false); + } + + return 0; +} + +static const struct mtk_devapc_pd_offset mt6779_pd_offset = { + .vio_mask = 0x0, + .vio_sta = 0x400, + .vio_dbg0 = 0x900, + .vio_dbg1 = 0x904, + .apc_con = 0xF00, + .vio_shift_sta = 0xF10, + .vio_shift_sel = 0xF14, + .vio_shift_con = 0xF20, +}; + +static const struct mtk_devapc_vio_dbgs mt6779_vio_dbgs = { + .mstid = {0x0000FFFF, 0x0}, + .dmnid = {0x003F0000, 0x10}, + .vio_w = {0x00400000, 0x16}, + .vio_r = {0x00800000, 0x17}, + .addr_h = {0x0F000000, 0x18}, +}; + +static const struct mtk_devapc_context devapc_mt6779 = { + .vio_idx_num = 510, + .offset = &mt6779_pd_offset, + .vio_dbgs = &mt6779_vio_dbgs, +}; + +static const struct of_device_id mtk_devapc_dt_match[] = { + { + .compatible = "mediatek,mt6779-devapc", + .data = &devapc_mt6779, + }, { + }, +}; + +static int mtk_devapc_probe(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct mtk_devapc_context *ctx; + struct clk *devapc_infra_clk; + u32 devapc_irq; + int ret; + + if (IS_ERR(node)) + return -ENODEV; + + ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx = (struct mtk_devapc_context *)of_device_get_match_data(&pdev->dev); + ctx->dev = &pdev->dev; + + ctx->vio_info = devm_kzalloc(&pdev->dev, + sizeof(struct mtk_devapc_vio_info), + GFP_KERNEL); + if (!ctx->vio_info) + return -ENOMEM; + + ctx->devapc_pd_base = of_iomap(node, 0); + if (!ctx->devapc_pd_base) + return -EINVAL; + + devapc_irq = irq_of_parse_and_map(node, 0); + if (!devapc_irq) + return -EINVAL; + + devapc_infra_clk = devm_clk_get(&pdev->dev, "devapc-infra-clock"); + if (IS_ERR(devapc_infra_clk)) + return -EINVAL; + + if (clk_prepare_enable(devapc_infra_clk)) + return -EINVAL; + + ret = start_devapc(ctx); + if (ret) + return ret; + + ret = devm_request_irq(&pdev->dev, devapc_irq, + (irq_handler_t)devapc_violation_irq, + IRQF_TRIGGER_NONE, "devapc", ctx); + if (ret) + return ret; + + return 0; +} + +static int mtk_devapc_remove(struct platform_device *dev) +{ + return 0; +} + +static struct platform_driver mtk_devapc_driver = { + .probe = mtk_devapc_probe, + .remove = mtk_devapc_remove, + .driver = { + .name = KBUILD_MODNAME, + .of_match_table = mtk_devapc_dt_match, + }, +}; + +module_platform_driver(mtk_devapc_driver); + +MODULE_DESCRIPTION("Mediatek Device APC Driver"); +MODULE_AUTHOR("Neal Liu "); +MODULE_LICENSE("GPL"); diff --git a/drivers/soc/mediatek/mtk-devapc.h b/drivers/soc/mediatek/mtk-devapc.h new file mode 100644 index 0000000..7bd7e66 --- /dev/null +++ b/drivers/soc/mediatek/mtk-devapc.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 MediaTek Inc. + */ + +#ifndef __MTK_DEVAPC_H__ +#define __MTK_DEVAPC_H__ + +#define VIO_MOD_TO_REG_IND(m) ((m) / 32) +#define VIO_MOD_TO_REG_OFF(m) ((m) % 32) + +struct mtk_devapc_pd_offset { + u32 vio_mask; + u32 vio_sta; + u32 vio_dbg0; + u32 vio_dbg1; + u32 apc_con; + u32 vio_shift_sta; + u32 vio_shift_sel; + u32 vio_shift_con; +}; + +struct mtk_devapc_vio_dbgs_desc { + u32 mask; + u32 start; +}; + +struct mtk_devapc_vio_dbgs { + struct mtk_devapc_vio_dbgs_desc mstid; + struct mtk_devapc_vio_dbgs_desc dmnid; + struct mtk_devapc_vio_dbgs_desc vio_w; + struct mtk_devapc_vio_dbgs_desc vio_r; + struct mtk_devapc_vio_dbgs_desc addr_h; +}; + +struct mtk_devapc_vio_info { + bool read; + bool write; + u32 vio_addr; + u32 vio_addr_high; + u32 master_id; + u32 domain_id; +}; + +struct mtk_devapc_context { + struct device *dev; + u32 vio_idx_num; + void __iomem *devapc_pd_base; + struct mtk_devapc_vio_info *vio_info; + const struct mtk_devapc_pd_offset *offset; + const struct mtk_devapc_vio_dbgs *vio_dbgs; +}; + +#endif /* __MTK_DEVAPC_H__ */ -- 1.7.9.5 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel