From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sagar Shrikant Kadam Date: Fri, 24 Jul 2020 01:47:19 -0700 Subject: [PATCH v4 3/5] fu540: dtsi: add reset producer and consumer entries In-Reply-To: <1595580442-25485-1-git-send-email-sagar.kadam@sifive.com> References: <1595580442-25485-1-git-send-email-sagar.kadam@sifive.com> Message-ID: <1595580442-25485-4-git-send-email-sagar.kadam@sifive.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de The resets to DDR and ethernet sub-system are connected to PRCI device reset control register, these reset signals are active low and are held low at power-up. Add these reset producer and consumer details needed by the reset driver. Signed-off-by: Sagar Shrikant Kadam Reviewed-by: Pragnesh Patel Reviewed-by: Bin Meng --- arch/riscv/dts/fu540-c000-u-boot.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi index afdb4f4..5302677 100644 --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi @@ -3,6 +3,8 @@ * (C) Copyright 2019 SiFive, Inc */ +#include + / { cpus { assigned-clocks = <&prci PRCI_CLK_COREPLL>; @@ -59,6 +61,16 @@ reg = <0x0 0x2000000 0x0 0xc0000>; u-boot,dm-spl; }; + prci: clock-controller at 10000000 { + #reset-cells = <1>; + resets = <&prci PRCI_RST_DDR_CTRL_N>, + <&prci PRCI_RST_DDR_AXI_N>, + <&prci PRCI_RST_DDR_AHB_N>, + <&prci PRCI_RST_DDR_PHY_N>, + <&prci PRCI_RST_GEMGXL_N>; + reset-names = "ddr_ctrl", "ddr_axi", "ddr_ahb", + "ddr_phy", "gemgxl_reset"; + }; dmc: dmc at 100b0000 { compatible = "sifive,fu540-c000-ddr"; reg = <0x0 0x100b0000 0x0 0x0800 -- 2.7.4