All of lore.kernel.org
 help / color / mirror / Atom feed
From: Chris Wilson <chris.p.wilson@intel.com>
To: Lionel Landwerlin <lionel.g.landwerlin@intel.com>,
	Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 2/4] drm/i915/perf: Whitelist OA report trigger registers
Date: Fri, 24 Jul 2020 11:23:56 +0100	[thread overview]
Message-ID: <159558623641.21069.2918420188225512985@build.alporthouse.com> (raw)
In-Reply-To: <159558594558.21069.2521382659864870599@build.alporthouse.com>

Quoting Chris Wilson (2020-07-24 11:19:05)
> Quoting Lionel Landwerlin (2020-07-24 11:07:18)
> > On 24/07/2020 12:26, Chris Wilson wrote:
> > > Quoting Umesh Nerlige Ramappa (2020-07-24 01:18:59)
> > >> diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> > >> index febc9e6692ba..3b1d3dbcd477 100644
> > >> --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> > >> +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> > >> @@ -934,6 +934,10 @@ static bool pardon_reg(struct drm_i915_private *i915, i915_reg_t reg)
> > >>          static const struct regmask pardon[] = {
> > >>                  { GEN9_CTX_PREEMPT_REG, INTEL_GEN_MASK(9, 9) },
> > >>                  { GEN8_L3SQCREG4, INTEL_GEN_MASK(9, 9) },
> > >> +               { OAREPORTTRIG2, INTEL_GEN_MASK(8, 11) },
> > >> +               { OAREPORTTRIG6, INTEL_GEN_MASK(8, 11) },
> > >> +               { GEN12_OAG_OAREPORTTRIG2, INTEL_GEN_MASK(12, 12) },
> > >> +               { GEN12_OAG_OAREPORTTRIG6, INTEL_GEN_MASK(12, 12) },
> > > Because we are not making the mistake of exposing more globals, and the
> > > pardon is a list of our past sins, not an excuse for more.
> > 
> > I'm afraid the HW design leave us no choice on Gen12 :(
> 
> The question then is how much mischief can a client get up to if they
> subvert the OA of the privileged user. It's a privilege escalation hole,
> but is there anything dangerous behind it? Or is it just going to disturb
> the data being fed to the privileged client... (Which seems scary enough.)

The other angle is whether the RING_NONPRIV are context saved; I have
vague memories of seeing them in the context image. If they are, we can
add them the to privileged OA client. We still need to respect the
hard limit on the number, but that would close the hole.
-Chris
---------------------------------------------------------------------
Intel Corporation (UK) Limited
Registered No. 1134945 (England)
Registered Office: Pipers Way, Swindon SN3 1RJ
VAT No: 860 2173 47

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2020-07-24 10:24 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-24  0:18 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
2020-07-24  0:18 ` [Intel-gfx] [PATCH 1/4] drm/i915/perf: Ensure observation logic is not clock gated Umesh Nerlige Ramappa
2020-07-24  0:18 ` [Intel-gfx] [PATCH 2/4] drm/i915/perf: Whitelist OA report trigger registers Umesh Nerlige Ramappa
2020-07-24  9:26   ` Chris Wilson
2020-07-24 10:07     ` Lionel Landwerlin
2020-07-24 10:19       ` Chris Wilson
2020-07-24 10:23         ` Chris Wilson [this message]
2020-07-24 10:33           ` Lionel Landwerlin
2020-07-24 11:27             ` Chris Wilson
2020-07-24 10:31         ` Lionel Landwerlin
2020-07-24  0:19 ` [Intel-gfx] [PATCH 3/4] drm/i915/perf: Whitelist OA counter and buffer registers Umesh Nerlige Ramappa
2020-07-24  8:55   ` Chris Wilson
2020-07-27 19:34     ` Umesh Nerlige Ramappa
2020-07-24  0:19 ` [Intel-gfx] [PATCH 4/4] drm/i915/perf: Map OA buffer to user space for gen12 performance query Umesh Nerlige Ramappa
2020-07-24 12:42   ` Chris Wilson
2020-07-24 16:29     ` Umesh Nerlige Ramappa
2020-07-24 16:34       ` Chris Wilson
2020-07-24 18:47         ` Umesh Nerlige Ramappa
2020-07-24 18:55           ` Chris Wilson
2020-07-24 19:35             ` Umesh Nerlige Ramappa
2020-07-24 19:46               ` Chris Wilson
2020-07-24 22:05                 ` Umesh Nerlige Ramappa
2020-07-24  1:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Allow privileged user to map the OA buffer (rev5) Patchwork
2020-07-24  1:44 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2020-08-20 18:01 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
2020-08-20 18:01 ` [Intel-gfx] [PATCH 2/4] drm/i915/perf: Whitelist OA report trigger registers Umesh Nerlige Ramappa
2020-08-04 17:11 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
2020-08-04 17:11 ` [Intel-gfx] [PATCH 2/4] drm/i915/perf: Whitelist OA report trigger registers Umesh Nerlige Ramappa
2020-07-31 23:58 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
2020-07-31 23:58 ` [Intel-gfx] [PATCH 2/4] drm/i915/perf: Whitelist OA report trigger registers Umesh Nerlige Ramappa
2020-07-31 14:46 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
2020-07-31 14:46 ` [Intel-gfx] [PATCH 2/4] drm/i915/perf: Whitelist OA report trigger registers Umesh Nerlige Ramappa
2020-07-31  6:07 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
2020-07-31  6:07 ` [Intel-gfx] [PATCH 2/4] drm/i915/perf: Whitelist OA report trigger registers Umesh Nerlige Ramappa
2020-07-30 23:02 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
2020-07-30 23:02 ` [Intel-gfx] [PATCH 2/4] drm/i915/perf: Whitelist OA report trigger registers Umesh Nerlige Ramappa
2020-07-22  5:55 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
2020-07-22  5:55 ` [Intel-gfx] [PATCH 2/4] drm/i915/perf: Whitelist OA report trigger registers Umesh Nerlige Ramappa
2020-07-21  2:00 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
2020-07-21  2:00 ` [Intel-gfx] [PATCH 2/4] drm/i915/perf: Whitelist OA report trigger registers Umesh Nerlige Ramappa
2020-07-18  0:04 [Intel-gfx] [PATCH 0/4] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
2020-07-18  0:04 ` [Intel-gfx] [PATCH 2/4] drm/i915/perf: Whitelist OA report trigger registers Umesh Nerlige Ramappa
2020-07-18 19:11   ` Lionel Landwerlin

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=159558623641.21069.2918420188225512985@build.alporthouse.com \
    --to=chris.p.wilson@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=lionel.g.landwerlin@intel.com \
    --cc=umesh.nerlige.ramappa@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.