Patch Details
Series:Introduce DG1
URL:https://patchwork.freedesktop.org/series/79863/
State:failure
Details:https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18242/index.html

CI Bug Log - changes from CI_DRM_8786 -> Patchwork_18242

Summary

FAILURE

Serious unknown changes coming with Patchwork_18242 absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18242, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18242/index.html

Possible new issues

Here are the unknown changes that may have been introduced in Patchwork_18242:

IGT changes

Possible regressions

Known issues

Here are the changes found in Patchwork_18242 that come from known issues:

IGT changes

Issues hit

Possible fixes

Warnings

Participating hosts (47 -> 40)

Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus

Build changes

CI-20190529: 20190529
CI_DRM_8786: e9ecbe8de4e7e7c08363c1ecaaee9270b9c6f2ec @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5747: 6980775bcadec862cd5e5affd65928ef79e5b580 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18242: a9a8a114146225c0979ed0f55216e68a4af1445b @ git://anongit.freedesktop.org/gfx-ci/linux

== Linux commits ==

a9a8a1141462 drm/i915/dg1: Change DMC_DEBUG{1, 2} registers
5e4111a18707 drm/i915/dg1: DG1 does not support DC6
f463503a1825 drm/i915/dg1: Add initial DG1 workarounds
2d1e6fca5292 drm/i915/dg1: Load DMC
472d90a048b8 drm/i915/dg1: enable PORT C/D aka D/E
4c68f89318f4 drm/i915/dg1: map/unmap pll clocks
72f10411364c drm/i915/dg1: provide port/phy mapping for vbt
bcab535050e1 drm/i915/dg1: Update voltage swing tables for DP
4933a57b9c0a drm/i915/dg1: Update comp master/slave relationships for PHYs
73800c5e78e4 drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
85111a9da7b5 drm/i915/dg1: Enable first 2 ports for DG1
d24c8e3696f3 drm/i915/dg1: gmbus pin mapping
c0b3de1be1a6 drm/i915/dg1: invert HPD pins
cbbc5366d85e drm/i915/dg1: add hpd interrupt handling
fe51b026ee82 drm/i915/dg1: Enable DPLL for DG1
4b251c381b35 drm/i915/dg1: Add and setup DPLLs for DG1
e18904ffdb23 drm/i915/dg1: Add DPLL macros for DG1
6763f3077f0d drm/i915/dg1: Wait for pcode/uncore handshake at startup
bff25189ad22 drm/i915/dg1: Increase mmio size to 4MB
da0e39cc42f3 drm/i915/dg1: Add DG1 power wells
c2699a393ba3 drm/i915/dg1: Define MOCS table for DG1
8f74e276b41a drm/i915/dg1: Initialize RAWCLK properly