* [PATCH V2 0/5] MIPS: Loongson64: Fix and improve irqchip drivers
@ 2020-07-30 8:51 Huacai Chen
2020-07-30 8:51 ` [PATCH V2 1/5] dt-bindings: interrupt-controller: Update Loongson HTVEC description Huacai Chen
` (5 more replies)
0 siblings, 6 replies; 9+ messages in thread
From: Huacai Chen @ 2020-07-30 8:51 UTC (permalink / raw)
To: Thomas Bogendoerfer, Thomas Gleixner, Jason Cooper, Marc Zyngier,
Rob Herring
Cc: linux-mips, Fuxin Zhang, Huacai Chen, Jiaxun Yang, Huacai Chen
Modernized Loongson64 platforms use a hierarchical interrupt controller
architecture. For LS7A PCH, the hierarchy (from inside to outside) is
CPUINTC --> LIOINTC --> HTVEC --> PCHPIC/PCHMSI. However, the current
status is that there are several bugs in the LIOINTC and PCHPIC drivers,
and the HTVEC driver should be improved to support 8 groups of vectors.
Loonson64C support only 4 groups of HT vectors, and Loongson64G support
as many as 8 groups, so the .dts file and dt-bindings description should
also be updated.
V1 -> V2:
1, Add a cover letter.
2, Add Reviewed-by and Tested-by tags.
3, Improve commit messages by adding Fixes: tags.
Huacai Chen(5):
dt-bindings: interrupt-controller: Update Loongson HTVEC description
MIPS: DTS: Fix number of msi vectors for Loongson64G
irqchip: loongson-liointc: Fix misuse of gc->mask_cache
irqchip: loongson-htvec: Support 8 groups of HT vectors
irqchip: loongson-pch-pic: Fix the misused irq flow handler
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
.../interrupt-controller/loongson,htvec.yaml | 4 ++--
.../boot/dts/loongson/loongson64g_4core_ls7a.dts | 8 ++++++--
drivers/irqchip/irq-loongson-htvec.c | 22 ++++++++++------------
drivers/irqchip/irq-loongson-liointc.c | 10 +++++-----
drivers/irqchip/irq-loongson-pch-pic.c | 15 ++++-----------
5 files changed, 27 insertions(+), 32 deletions(-)
--
2.7.0
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH V2 1/5] dt-bindings: interrupt-controller: Update Loongson HTVEC description
2020-07-30 8:51 [PATCH V2 0/5] MIPS: Loongson64: Fix and improve irqchip drivers Huacai Chen
@ 2020-07-30 8:51 ` Huacai Chen
2020-07-30 8:51 ` [PATCH V2 2/5] MIPS: DTS: Fix number of msi vectors for Loongson64G Huacai Chen
` (4 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Huacai Chen @ 2020-07-30 8:51 UTC (permalink / raw)
To: Thomas Bogendoerfer, Thomas Gleixner, Jason Cooper, Marc Zyngier,
Rob Herring
Cc: linux-mips, Fuxin Zhang, Huacai Chen, Jiaxun Yang, Huacai Chen
Loongson HTVEC support 8 parents interrupts in maximum, so update the
maxItems description.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
.../devicetree/bindings/interrupt-controller/loongson,htvec.yaml | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,htvec.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,htvec.yaml
index e865cd8..87a7455 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/loongson,htvec.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,htvec.yaml
@@ -22,8 +22,8 @@ properties:
interrupts:
minItems: 1
- maxItems: 4
- description: Four parent interrupts that receive chained interrupts.
+ maxItems: 8
+ description: Eight parent interrupts that receive chained interrupts.
interrupt-controller: true
--
2.7.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH V2 2/5] MIPS: DTS: Fix number of msi vectors for Loongson64G
2020-07-30 8:51 [PATCH V2 0/5] MIPS: Loongson64: Fix and improve irqchip drivers Huacai Chen
2020-07-30 8:51 ` [PATCH V2 1/5] dt-bindings: interrupt-controller: Update Loongson HTVEC description Huacai Chen
@ 2020-07-30 8:51 ` Huacai Chen
2020-07-30 20:19 ` Thomas Bogendoerfer
2020-07-30 8:51 ` [PATCH V2 3/5] irqchip: loongson-liointc: Fix misuse of gc->mask_cache Huacai Chen
` (3 subsequent siblings)
5 siblings, 1 reply; 9+ messages in thread
From: Huacai Chen @ 2020-07-30 8:51 UTC (permalink / raw)
To: Thomas Bogendoerfer, Thomas Gleixner, Jason Cooper, Marc Zyngier,
Rob Herring
Cc: linux-mips, Fuxin Zhang, Huacai Chen, Jiaxun Yang, Huacai Chen
HT irqs vectors are 8 groups, each group has 32 irqs, Loongson64C CPUs
can use only 4 groups and Loongson64G CPUs can use all 8 groups. So the
number of msi vectors of Loongson64G is 192 (32*8 - 64 = 192).
Fixes: 24af105962c8004edb9f5bf84 ("MIPS: Loongson64: DeviceTree for LS7A PCH")
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts b/arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts
index bdc911e..c945f85 100644
--- a/arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts
+++ b/arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts
@@ -20,7 +20,11 @@
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
<25 IRQ_TYPE_LEVEL_HIGH>,
<26 IRQ_TYPE_LEVEL_HIGH>,
- <27 IRQ_TYPE_LEVEL_HIGH>;
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <28 IRQ_TYPE_LEVEL_HIGH>,
+ <29 IRQ_TYPE_LEVEL_HIGH>,
+ <30 IRQ_TYPE_LEVEL_HIGH>,
+ <31 IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -31,7 +35,7 @@
interrupt-controller;
msi-controller;
loongson,msi-base-vec = <64>;
- loongson,msi-num-vecs = <128>;
+ loongson,msi-num-vecs = <192>;
interrupt-parent = <&htvec>;
};
};
--
2.7.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH V2 3/5] irqchip: loongson-liointc: Fix misuse of gc->mask_cache
2020-07-30 8:51 [PATCH V2 0/5] MIPS: Loongson64: Fix and improve irqchip drivers Huacai Chen
2020-07-30 8:51 ` [PATCH V2 1/5] dt-bindings: interrupt-controller: Update Loongson HTVEC description Huacai Chen
2020-07-30 8:51 ` [PATCH V2 2/5] MIPS: DTS: Fix number of msi vectors for Loongson64G Huacai Chen
@ 2020-07-30 8:51 ` Huacai Chen
2020-07-30 8:51 ` [PATCH V2 4/5] irqchip: loongson-htvec: Support 8 groups of HT vectors Huacai Chen
` (2 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Huacai Chen @ 2020-07-30 8:51 UTC (permalink / raw)
To: Thomas Bogendoerfer, Thomas Gleixner, Jason Cooper, Marc Zyngier,
Rob Herring
Cc: linux-mips, Fuxin Zhang, Huacai Chen, Jiaxun Yang, Huacai Chen, stable
In gc->mask_cache bits, 1 means enabled and 0 means disabled, but in the
loongson-liointc driver mask_cache is misused by reverting its meaning.
This patch fix the bug and update the comments as well.
Fixes: dbb152267908c4b2c3639492a ("irqchip: Add driver for Loongson I/O Local Interrupt Controller")
Cc: stable@vger.kernel.org
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
drivers/irqchip/irq-loongson-liointc.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
index 63b6147..08165c5 100644
--- a/drivers/irqchip/irq-loongson-liointc.c
+++ b/drivers/irqchip/irq-loongson-liointc.c
@@ -60,7 +60,7 @@ static void liointc_chained_handle_irq(struct irq_desc *desc)
if (!pending) {
/* Always blame LPC IRQ if we have that bug */
if (handler->priv->has_lpc_irq_errata &&
- (handler->parent_int_map & ~gc->mask_cache &
+ (handler->parent_int_map & gc->mask_cache &
BIT(LIOINTC_ERRATA_IRQ)))
pending = BIT(LIOINTC_ERRATA_IRQ);
else
@@ -131,11 +131,11 @@ static void liointc_resume(struct irq_chip_generic *gc)
irq_gc_lock_irqsave(gc, flags);
/* Disable all at first */
writel(0xffffffff, gc->reg_base + LIOINTC_REG_INTC_DISABLE);
- /* Revert map cache */
+ /* Restore map cache */
for (i = 0; i < LIOINTC_CHIP_IRQ; i++)
writeb(priv->map_cache[i], gc->reg_base + i);
- /* Revert mask cache */
- writel(~gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE);
+ /* Restore mask cache */
+ writel(gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE);
irq_gc_unlock_irqrestore(gc, flags);
}
@@ -243,7 +243,7 @@ int __init liointc_of_init(struct device_node *node,
ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
ct->chip.irq_set_type = liointc_set_type;
- gc->mask_cache = 0xffffffff;
+ gc->mask_cache = 0;
priv->gc = gc;
for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
--
2.7.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH V2 4/5] irqchip: loongson-htvec: Support 8 groups of HT vectors
2020-07-30 8:51 [PATCH V2 0/5] MIPS: Loongson64: Fix and improve irqchip drivers Huacai Chen
` (2 preceding siblings ...)
2020-07-30 8:51 ` [PATCH V2 3/5] irqchip: loongson-liointc: Fix misuse of gc->mask_cache Huacai Chen
@ 2020-07-30 8:51 ` Huacai Chen
2020-07-30 8:51 ` [PATCH V2 5/5] irqchip: loongson-pch-pic: Fix the misused irq flow handler Huacai Chen
2020-07-30 12:06 ` [PATCH V2 0/5] MIPS: Loongson64: Fix and improve irqchip drivers Marc Zyngier
5 siblings, 0 replies; 9+ messages in thread
From: Huacai Chen @ 2020-07-30 8:51 UTC (permalink / raw)
To: Thomas Bogendoerfer, Thomas Gleixner, Jason Cooper, Marc Zyngier,
Rob Herring
Cc: linux-mips, Fuxin Zhang, Huacai Chen, Jiaxun Yang, Huacai Chen
The original version can only used by old Loongson-3 which only use 4
groups of HT vectors. Now Loongson-3A R4 can use 8 groups, so improve
the driver to support all 8 groups.
Fixes: 818e915fbac518e8c78e1877a ("irqchip: Add Loongson HyperTransport Vector support")
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
drivers/irqchip/irq-loongson-htvec.c | 22 ++++++++++------------
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/drivers/irqchip/irq-loongson-htvec.c b/drivers/irqchip/irq-loongson-htvec.c
index 1ece933..e7722fa 100644
--- a/drivers/irqchip/irq-loongson-htvec.c
+++ b/drivers/irqchip/irq-loongson-htvec.c
@@ -19,15 +19,14 @@
/* Registers */
#define HTVEC_EN_OFF 0x20
-#define HTVEC_MAX_PARENT_IRQ 4
+#define HTVEC_MAX_PARENT_IRQ 8
#define VEC_COUNT_PER_REG 32
-#define VEC_REG_COUNT 4
-#define VEC_COUNT (VEC_COUNT_PER_REG * VEC_REG_COUNT)
#define VEC_REG_IDX(irq_id) ((irq_id) / VEC_COUNT_PER_REG)
#define VEC_REG_BIT(irq_id) ((irq_id) % VEC_COUNT_PER_REG)
struct htvec {
+ int num_parents;
void __iomem *base;
struct irq_domain *htvec_domain;
raw_spinlock_t htvec_lock;
@@ -43,7 +42,7 @@ static void htvec_irq_dispatch(struct irq_desc *desc)
chained_irq_enter(chip, desc);
- for (i = 0; i < VEC_REG_COUNT; i++) {
+ for (i = 0; i < priv->num_parents; i++) {
pending = readl(priv->base + 4 * i);
while (pending) {
int bit = __ffs(pending);
@@ -147,7 +146,7 @@ static void htvec_reset(struct htvec *priv)
u32 idx;
/* Clear IRQ cause registers, mask all interrupts */
- for (idx = 0; idx < VEC_REG_COUNT; idx++) {
+ for (idx = 0; idx < priv->num_parents; idx++) {
writel_relaxed(0x0, priv->base + HTVEC_EN_OFF + 4 * idx);
writel_relaxed(0xFFFFFFFF, priv->base);
}
@@ -157,7 +156,7 @@ static int htvec_of_init(struct device_node *node,
struct device_node *parent)
{
struct htvec *priv;
- int err, parent_irq[4], num_parents = 0, i;
+ int err, parent_irq[8], i;
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (!priv)
@@ -176,19 +175,18 @@ static int htvec_of_init(struct device_node *node,
if (parent_irq[i] <= 0)
break;
- num_parents++;
+ priv->num_parents++;
}
- if (!num_parents) {
+ if (!priv->num_parents) {
pr_err("Failed to get parent irqs\n");
err = -ENODEV;
goto iounmap_base;
}
priv->htvec_domain = irq_domain_create_linear(of_node_to_fwnode(node),
- VEC_COUNT,
- &htvec_domain_ops,
- priv);
+ (VEC_COUNT_PER_REG * priv->num_parents),
+ &htvec_domain_ops, priv);
if (!priv->htvec_domain) {
pr_err("Failed to create IRQ domain\n");
err = -ENOMEM;
@@ -197,7 +195,7 @@ static int htvec_of_init(struct device_node *node,
htvec_reset(priv);
- for (i = 0; i < num_parents; i++)
+ for (i = 0; i < priv->num_parents; i++)
irq_set_chained_handler_and_data(parent_irq[i],
htvec_irq_dispatch, priv);
--
2.7.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH V2 5/5] irqchip: loongson-pch-pic: Fix the misused irq flow handler
2020-07-30 8:51 [PATCH V2 0/5] MIPS: Loongson64: Fix and improve irqchip drivers Huacai Chen
` (3 preceding siblings ...)
2020-07-30 8:51 ` [PATCH V2 4/5] irqchip: loongson-htvec: Support 8 groups of HT vectors Huacai Chen
@ 2020-07-30 8:51 ` Huacai Chen
2020-07-30 12:06 ` [PATCH V2 0/5] MIPS: Loongson64: Fix and improve irqchip drivers Marc Zyngier
5 siblings, 0 replies; 9+ messages in thread
From: Huacai Chen @ 2020-07-30 8:51 UTC (permalink / raw)
To: Thomas Bogendoerfer, Thomas Gleixner, Jason Cooper, Marc Zyngier,
Rob Herring
Cc: linux-mips, Fuxin Zhang, Huacai Chen, Jiaxun Yang, Huacai Chen
Loongson PCH PIC is a standard level triggered PIC, and it need to clear
interrupt during unmask.
Fixes: ef8c01eb64ca6719da449dab0 ("irqchip: Add Loongson PCH PIC controller")
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
drivers/irqchip/irq-loongson-pch-pic.c | 15 ++++-----------
1 file changed, 4 insertions(+), 11 deletions(-)
diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-loongson-pch-pic.c
index 2a05b93..61d06df 100644
--- a/drivers/irqchip/irq-loongson-pch-pic.c
+++ b/drivers/irqchip/irq-loongson-pch-pic.c
@@ -64,15 +64,6 @@ static void pch_pic_bitclr(struct pch_pic *priv, int offset, int bit)
raw_spin_unlock(&priv->pic_lock);
}
-static void pch_pic_eoi_irq(struct irq_data *d)
-{
- u32 idx = PIC_REG_IDX(d->hwirq);
- struct pch_pic *priv = irq_data_get_irq_chip_data(d);
-
- writel(BIT(PIC_REG_BIT(d->hwirq)),
- priv->base + PCH_PIC_CLR + idx * 4);
-}
-
static void pch_pic_mask_irq(struct irq_data *d)
{
struct pch_pic *priv = irq_data_get_irq_chip_data(d);
@@ -85,6 +76,9 @@ static void pch_pic_unmask_irq(struct irq_data *d)
{
struct pch_pic *priv = irq_data_get_irq_chip_data(d);
+ writel(BIT(PIC_REG_BIT(d->hwirq)),
+ priv->base + PCH_PIC_CLR + PIC_REG_IDX(d->hwirq) * 4);
+
irq_chip_unmask_parent(d);
pch_pic_bitclr(priv, PCH_PIC_MASK, d->hwirq);
}
@@ -124,7 +118,6 @@ static struct irq_chip pch_pic_irq_chip = {
.irq_mask = pch_pic_mask_irq,
.irq_unmask = pch_pic_unmask_irq,
.irq_ack = irq_chip_ack_parent,
- .irq_eoi = pch_pic_eoi_irq,
.irq_set_affinity = irq_chip_set_affinity_parent,
.irq_set_type = pch_pic_set_type,
};
@@ -150,7 +143,7 @@ static int pch_pic_alloc(struct irq_domain *domain, unsigned int virq,
irq_domain_set_info(domain, virq, hwirq,
&pch_pic_irq_chip, priv,
- handle_fasteoi_ack_irq, NULL, NULL);
+ handle_level_irq, NULL, NULL);
irq_set_probe(virq);
return 0;
--
2.7.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH V2 0/5] MIPS: Loongson64: Fix and improve irqchip drivers
2020-07-30 8:51 [PATCH V2 0/5] MIPS: Loongson64: Fix and improve irqchip drivers Huacai Chen
` (4 preceding siblings ...)
2020-07-30 8:51 ` [PATCH V2 5/5] irqchip: loongson-pch-pic: Fix the misused irq flow handler Huacai Chen
@ 2020-07-30 12:06 ` Marc Zyngier
2020-07-30 12:31 ` Thomas Bogendoerfer
5 siblings, 1 reply; 9+ messages in thread
From: Marc Zyngier @ 2020-07-30 12:06 UTC (permalink / raw)
To: Huacai Chen, Thomas Bogendoerfer, Rob Herring, Jason Cooper,
Thomas Gleixner
Cc: linux-mips, Huacai Chen, Jiaxun Yang, Fuxin Zhang
On Thu, 30 Jul 2020 16:51:25 +0800, Huacai Chen wrote:
> Modernized Loongson64 platforms use a hierarchical interrupt controller
> architecture. For LS7A PCH, the hierarchy (from inside to outside) is
> CPUINTC --> LIOINTC --> HTVEC --> PCHPIC/PCHMSI. However, the current
> status is that there are several bugs in the LIOINTC and PCHPIC drivers,
> and the HTVEC driver should be improved to support 8 groups of vectors.
> Loonson64C support only 4 groups of HT vectors, and Loongson64G support
> as many as 8 groups, so the .dts file and dt-bindings description should
> also be updated.
>
> [...]
Applied to irq/irqchip-next, thanks!
[1/5] dt-bindings: interrupt-controller: Update Loongson HTVEC description
commit: 8fea4b2e804ab8ff93bd0d67a3dadee1d1a3e24f
[3/5] irqchip/loongson-liointc: Fix misuse of gc->mask_cache
commit: c9c73a05413ea4a465cae1cb3593b01b190a233f
[4/5] irqchip/loongson-htvec: Support 8 groups of HT vectors
commit: c47e388cfc648421bd821f5d9fda9e76eefe29cd
[5/5] irqchip/loongson-pch-pic: Fix the misused irq flow handler
commit: ac62460c24126eb2442e3653a266ebbf05b004d8
Please note that I haven't taken patch #2, as it doesn't apply on top
of irqchip/next. Please route it via the MIPS tree.
Cheers,
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH V2 0/5] MIPS: Loongson64: Fix and improve irqchip drivers
2020-07-30 12:06 ` [PATCH V2 0/5] MIPS: Loongson64: Fix and improve irqchip drivers Marc Zyngier
@ 2020-07-30 12:31 ` Thomas Bogendoerfer
0 siblings, 0 replies; 9+ messages in thread
From: Thomas Bogendoerfer @ 2020-07-30 12:31 UTC (permalink / raw)
To: Marc Zyngier
Cc: Huacai Chen, Rob Herring, Jason Cooper, Thomas Gleixner,
linux-mips, Huacai Chen, Jiaxun Yang, Fuxin Zhang
On Thu, Jul 30, 2020 at 01:06:03PM +0100, Marc Zyngier wrote:
> On Thu, 30 Jul 2020 16:51:25 +0800, Huacai Chen wrote:
> > Modernized Loongson64 platforms use a hierarchical interrupt controller
> > architecture. For LS7A PCH, the hierarchy (from inside to outside) is
> > CPUINTC --> LIOINTC --> HTVEC --> PCHPIC/PCHMSI. However, the current
> > status is that there are several bugs in the LIOINTC and PCHPIC drivers,
> > and the HTVEC driver should be improved to support 8 groups of vectors.
> > Loonson64C support only 4 groups of HT vectors, and Loongson64G support
> > as many as 8 groups, so the .dts file and dt-bindings description should
> > also be updated.
> >
> > [...]
>
> Applied to irq/irqchip-next, thanks!
>
> [1/5] dt-bindings: interrupt-controller: Update Loongson HTVEC description
> commit: 8fea4b2e804ab8ff93bd0d67a3dadee1d1a3e24f
> [3/5] irqchip/loongson-liointc: Fix misuse of gc->mask_cache
> commit: c9c73a05413ea4a465cae1cb3593b01b190a233f
> [4/5] irqchip/loongson-htvec: Support 8 groups of HT vectors
> commit: c47e388cfc648421bd821f5d9fda9e76eefe29cd
> [5/5] irqchip/loongson-pch-pic: Fix the misused irq flow handler
> commit: ac62460c24126eb2442e3653a266ebbf05b004d8
>
> Please note that I haven't taken patch #2, as it doesn't apply on top
> of irqchip/next. Please route it via the MIPS tree.
I'll take it.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH V2 2/5] MIPS: DTS: Fix number of msi vectors for Loongson64G
2020-07-30 8:51 ` [PATCH V2 2/5] MIPS: DTS: Fix number of msi vectors for Loongson64G Huacai Chen
@ 2020-07-30 20:19 ` Thomas Bogendoerfer
0 siblings, 0 replies; 9+ messages in thread
From: Thomas Bogendoerfer @ 2020-07-30 20:19 UTC (permalink / raw)
To: Huacai Chen
Cc: Thomas Gleixner, Jason Cooper, Marc Zyngier, Rob Herring,
linux-mips, Fuxin Zhang, Huacai Chen, Jiaxun Yang
On Thu, Jul 30, 2020 at 04:51:27PM +0800, Huacai Chen wrote:
> HT irqs vectors are 8 groups, each group has 32 irqs, Loongson64C CPUs
> can use only 4 groups and Loongson64G CPUs can use all 8 groups. So the
> number of msi vectors of Loongson64G is 192 (32*8 - 64 = 192).
>
> Fixes: 24af105962c8004edb9f5bf84 ("MIPS: Loongson64: DeviceTree for LS7A PCH")
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
> ---
> arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
applied to mips-next.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 9+ messages in thread
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2020-07-30 8:51 [PATCH V2 0/5] MIPS: Loongson64: Fix and improve irqchip drivers Huacai Chen
2020-07-30 8:51 ` [PATCH V2 1/5] dt-bindings: interrupt-controller: Update Loongson HTVEC description Huacai Chen
2020-07-30 8:51 ` [PATCH V2 2/5] MIPS: DTS: Fix number of msi vectors for Loongson64G Huacai Chen
2020-07-30 20:19 ` Thomas Bogendoerfer
2020-07-30 8:51 ` [PATCH V2 3/5] irqchip: loongson-liointc: Fix misuse of gc->mask_cache Huacai Chen
2020-07-30 8:51 ` [PATCH V2 4/5] irqchip: loongson-htvec: Support 8 groups of HT vectors Huacai Chen
2020-07-30 8:51 ` [PATCH V2 5/5] irqchip: loongson-pch-pic: Fix the misused irq flow handler Huacai Chen
2020-07-30 12:06 ` [PATCH V2 0/5] MIPS: Loongson64: Fix and improve irqchip drivers Marc Zyngier
2020-07-30 12:31 ` Thomas Bogendoerfer
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