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Fri, 14 Aug 2020 18:41:25 -0800 Received: from MTKMBS31N2.mediatek.inc (172.27.4.87) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 14 Aug 2020 19:31:21 -0700 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 15 Aug 2020 10:31:15 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 15 Aug 2020 10:31:18 +0800 Message-ID: <1597458618.25591.4.camel@mhfsdcap03> Subject: Re: [PATCH v3 2/3] dt-bindings: pinctrl: mt8192: add binding document From: zhiyong tao To: Rob Herring Date: Sat, 15 Aug 2020 10:30:18 +0800 In-Reply-To: <20200812194754.GA2587643@bogus> References: <20200807074905.23468-1-zhiyong.tao@mediatek.com> <20200807074905.23468-3-zhiyong.tao@mediatek.com> <20200812194754.GA2587643@bogus> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: BF560CB03BDBC8D7BE9BBF3B24F554186E71B74FF91E47135E2A884A9A4CDBA92000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200814_224132_910263_4A0F7DC7 X-CRM114-Status: GOOD ( 26.66 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, hui.liu@mediatek.com, srv_heupstream@mediatek.com, chuanjia.liu@mediatek.com, biao.huang@mediatek.com, linus.walleij@linaro.org, sean.wang@kernel.org, seiya.wang@mediatek.com, linux-kernel@vger.kernel.org, sin_jieyang@mediatek.com, hongzhou.yang@mediatek.com, sj.huang@mediatek.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, sean.wang@mediatek.com, linux-gpio@vger.kernel.org, matthias.bgg@gmail.com, eddie.huang@mediatek.com, erin.lo@mediatek.com, jg_poxu@mediatek.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Wed, 2020-08-12 at 13:47 -0600, Rob Herring wrote: > On Fri, Aug 07, 2020 at 03:49:04PM +0800, Zhiyong Tao wrote: > > The commit adds mt8192 compatible node in binding document. > > > > Signed-off-by: Zhiyong Tao > > --- > > .../bindings/pinctrl/pinctrl-mt8192.yaml | 149 ++++++++++++++++++ > > 1 file changed, 149 insertions(+) > > create mode 100755 Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml > > Don't set execute permission. > Dear Rob, Thanks for your suggestion. I will change it in v4. > > > > diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml > > new file mode 100755 > > index 000000000000..3b46bbfa38ec > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml > > @@ -0,0 +1,149 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8192.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Mediatek MT8192 Pin Controller > > + > > +maintainers: > > + - Sean Wang > > + > > +description: | > > + The Mediatek's Pin controller is used to control SoC pins. > > + > > +properties: > > + compatible: > > + const: mediatek,mt8192-pinctrl > > + > > + gpio-controller: true > > + > > + '#gpio-cells': > > + description: | > > + Number of cells in GPIO specifier. Since the generic GPIO binding is used, > > + the amount of cells must be specified as 2. See the below > > + mentioned gpio binding representation for description of particular cells. > > + const: 2 > > + > > + gpio-ranges: > > + description: gpio valid number range. > > + maxItems: 1 > > + > > + reg: > > + description: | > > + Physical address base for gpio base registers. There are 11 GPIO > > + physical address base in mt8192. > > + maxItems: 11 > > + > > + reg-names: > > + description: | > > + Gpio base register names. > > + maxItems: 11 > > + > > + interrupt-controller: true > > + > > + '#interrupt-cells': > > + const: 2 > > + > > + interrupts: > > + description: The interrupt outputs to sysirq. > > + maxItems: 1 > > + > > +#PIN CONFIGURATION NODES > > +patternProperties: > > + '^pins': > > + type: object > > + description: | > > + A pinctrl node should contain at least one subnodes representing the > > + pinctrl groups available on the machine. Each subnode will list the > > + pins it needs, and how they should be configured, with regard to muxer > > + configuration, pullups, drive strength, input enable/disable and > > + input schmitt. > > + An example of using macro: > > + pincontroller { > > + /* GPIO0 set as multifunction GPIO0 */ > > + state_0_node_a { > > + pinmux = ; > > + }; > > + /* GPIO1 set as multifunction PWM */ > > + state_0_node_a { > > + pinmux = ; > > + }; > > + }; > > + properties: > > + pinmux: > > + $ref: "pinmux-node.yaml" > > This is at the wrong level. Should be under '^pins'. ==> I will change it in v4. > > > + description: | > > + Integer array, represents gpio pin number and mux setting. > > + Supported pin number and mux varies for different SoCs, and are defined > > + as macros in dt-bindings/pinctrl/-pinfunc.h directly. > > + > > + drive-strength: > > + description: | > > + It can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See > > + dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10/12/14/16mA in mt8192. > > + enum: [2, 4, 6, 8, 10, 12, 14, 16] > > + > > + bias-pull-down: true > > + > > + bias-pull-up: true > > + > > + bias-disable: true > > + > > + output-high: true > > + > > + output-low: true > > + > > + input-enable: true > > + > > + input-disable: true > > + > > + input-schmitt-enable: true > > + > > + input-schmitt-disable: true > > + > > + required: > > + - pinmux > > + > > + additionalProperties: false > > + > > +required: > > + - compatible > > + - reg > > + - interrupts > > + - interrupt-controller > > + - '#interrupt-cells' > > + - gpio-controller > > + - '#gpio-cells' > > + - gpio-ranges > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include > > + #include > > + pio: pinctrl@10005000 { > > + compatible = "mediatek,mt8192-pinctrl"; > > + reg = <0x10005000 0x1000>, > > + <0x11c20000 0x1000>, > > + <0x11d10000 0x1000>, > > + <0x11d30000 0x1000>, > > + <0x11d40000 0x1000>, > > + <0x11e20000 0x1000>, > > + <0x11e70000 0x1000>, > > + <0x11ea0000 0x1000>, > > + <0x11f20000 0x1000>, > > + <0x11f30000 0x1000>, > > + <0x1000b000 0x1000>; > > + reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", > > + "iocfg_bl", "iocfg_br", "iocfg_lm", > > + "iocfg_lb", "iocfg_rt", "iocfg_lt", > > + "iocfg_tl", "eint"; > > + gpio-controller; > > + #gpio-cells = <2>; > > + gpio-ranges = <&pio 0 0 220>; > > + interrupt-controller; > > + interrupts = ; > > + #interrupt-cells = <2>; > > Would be good to have a pin node here so you can test you've got the > schema correct. ==> I will add a pin node here in v4. > > > + }; > > -- > > 2.18.0 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AEBE8C433E1 for ; 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Sat, 15 Aug 2020 10:31:15 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 15 Aug 2020 10:31:18 +0800 Message-ID: <1597458618.25591.4.camel@mhfsdcap03> Subject: Re: [PATCH v3 2/3] dt-bindings: pinctrl: mt8192: add binding document From: zhiyong tao To: Rob Herring Date: Sat, 15 Aug 2020 10:30:18 +0800 In-Reply-To: <20200812194754.GA2587643@bogus> References: <20200807074905.23468-1-zhiyong.tao@mediatek.com> <20200807074905.23468-3-zhiyong.tao@mediatek.com> <20200812194754.GA2587643@bogus> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: BF560CB03BDBC8D7BE9BBF3B24F554186E71B74FF91E47135E2A884A9A4CDBA92000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200814_224132_910263_4A0F7DC7 X-CRM114-Status: GOOD ( 26.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, hui.liu@mediatek.com, srv_heupstream@mediatek.com, chuanjia.liu@mediatek.com, biao.huang@mediatek.com, linus.walleij@linaro.org, sean.wang@kernel.org, seiya.wang@mediatek.com, linux-kernel@vger.kernel.org, sin_jieyang@mediatek.com, hongzhou.yang@mediatek.com, sj.huang@mediatek.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, sean.wang@mediatek.com, linux-gpio@vger.kernel.org, matthias.bgg@gmail.com, eddie.huang@mediatek.com, erin.lo@mediatek.com, jg_poxu@mediatek.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 2020-08-12 at 13:47 -0600, Rob Herring wrote: > On Fri, Aug 07, 2020 at 03:49:04PM +0800, Zhiyong Tao wrote: > > The commit adds mt8192 compatible node in binding document. > > > > Signed-off-by: Zhiyong Tao > > --- > > .../bindings/pinctrl/pinctrl-mt8192.yaml | 149 ++++++++++++++++++ > > 1 file changed, 149 insertions(+) > > create mode 100755 Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml > > Don't set execute permission. > Dear Rob, Thanks for your suggestion. I will change it in v4. > > > > diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml > > new file mode 100755 > > index 000000000000..3b46bbfa38ec > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml > > @@ -0,0 +1,149 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8192.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Mediatek MT8192 Pin Controller > > + > > +maintainers: > > + - Sean Wang > > + > > +description: | > > + The Mediatek's Pin controller is used to control SoC pins. > > + > > +properties: > > + compatible: > > + const: mediatek,mt8192-pinctrl > > + > > + gpio-controller: true > > + > > + '#gpio-cells': > > + description: | > > + Number of cells in GPIO specifier. Since the generic GPIO binding is used, > > + the amount of cells must be specified as 2. See the below > > + mentioned gpio binding representation for description of particular cells. > > + const: 2 > > + > > + gpio-ranges: > > + description: gpio valid number range. > > + maxItems: 1 > > + > > + reg: > > + description: | > > + Physical address base for gpio base registers. There are 11 GPIO > > + physical address base in mt8192. > > + maxItems: 11 > > + > > + reg-names: > > + description: | > > + Gpio base register names. > > + maxItems: 11 > > + > > + interrupt-controller: true > > + > > + '#interrupt-cells': > > + const: 2 > > + > > + interrupts: > > + description: The interrupt outputs to sysirq. > > + maxItems: 1 > > + > > +#PIN CONFIGURATION NODES > > +patternProperties: > > + '^pins': > > + type: object > > + description: | > > + A pinctrl node should contain at least one subnodes representing the > > + pinctrl groups available on the machine. Each subnode will list the > > + pins it needs, and how they should be configured, with regard to muxer > > + configuration, pullups, drive strength, input enable/disable and > > + input schmitt. > > + An example of using macro: > > + pincontroller { > > + /* GPIO0 set as multifunction GPIO0 */ > > + state_0_node_a { > > + pinmux = ; > > + }; > > + /* GPIO1 set as multifunction PWM */ > > + state_0_node_a { > > + pinmux = ; > > + }; > > + }; > > + properties: > > + pinmux: > > + $ref: "pinmux-node.yaml" > > This is at the wrong level. Should be under '^pins'. ==> I will change it in v4. > > > + description: | > > + Integer array, represents gpio pin number and mux setting. > > + Supported pin number and mux varies for different SoCs, and are defined > > + as macros in dt-bindings/pinctrl/-pinfunc.h directly. > > + > > + drive-strength: > > + description: | > > + It can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See > > + dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10/12/14/16mA in mt8192. > > + enum: [2, 4, 6, 8, 10, 12, 14, 16] > > + > > + bias-pull-down: true > > + > > + bias-pull-up: true > > + > > + bias-disable: true > > + > > + output-high: true > > + > > + output-low: true > > + > > + input-enable: true > > + > > + input-disable: true > > + > > + input-schmitt-enable: true > > + > > + input-schmitt-disable: true > > + > > + required: > > + - pinmux > > + > > + additionalProperties: false > > + > > +required: > > + - compatible > > + - reg > > + - interrupts > > + - interrupt-controller > > + - '#interrupt-cells' > > + - gpio-controller > > + - '#gpio-cells' > > + - gpio-ranges > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include > > + #include > > + pio: pinctrl@10005000 { > > + compatible = "mediatek,mt8192-pinctrl"; > > + reg = <0x10005000 0x1000>, > > + <0x11c20000 0x1000>, > > + <0x11d10000 0x1000>, > > + <0x11d30000 0x1000>, > > + <0x11d40000 0x1000>, > > + <0x11e20000 0x1000>, > > + <0x11e70000 0x1000>, > > + <0x11ea0000 0x1000>, > > + <0x11f20000 0x1000>, > > + <0x11f30000 0x1000>, > > + <0x1000b000 0x1000>; > > + reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", > > + "iocfg_bl", "iocfg_br", "iocfg_lm", > > + "iocfg_lb", "iocfg_rt", "iocfg_lt", > > + "iocfg_tl", "eint"; > > + gpio-controller; > > + #gpio-cells = <2>; > > + gpio-ranges = <&pio 0 0 220>; > > + interrupt-controller; > > + interrupts = ; > > + #interrupt-cells = <2>; > > Would be good to have a pin node here so you can test you've got the > schema correct. ==> I will add a pin node here in v4. > > > + }; > > -- > > 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel