Patch Details
Series:drm/i915/tgl+: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev2)
URL:https://patchwork.freedesktop.org/series/79486/
State:success
Details:https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18365/index.html

CI Bug Log - changes from CI_DRM_8891 -> Patchwork_18365

Summary

WARNING

Minor unknown changes coming with Patchwork_18365 need to be verified
manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18365, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18365/index.html

Possible new issues

Here are the unknown changes that may have been introduced in Patchwork_18365:

IGT changes

Warnings

Known issues

Here are the changes found in Patchwork_18365 that come from known issues:

IGT changes

Possible fixes

Warnings

Participating hosts (41 -> 35)

Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus

Build changes

CI-20190529: 20190529
CI_DRM_8891: f01d54256ca8735663c14ccf0525777fea682e8a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5769: 4e5f76be680b65780204668e302026cf638decc9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18365: d27f4a1c75b10bc42abc5e52438eb67171e4107d @ git://anongit.freedesktop.org/gfx-ci/linux

== Linux commits ==

d27f4a1c75b1 drm/i915/tgl+: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock