From mboxrd@z Thu Jan  1 00:00:00 1970
From: Chunfeng Yun <chunfeng.yun@mediatek.com>
Date: Wed, 19 Aug 2020 16:54:28 +0800
Subject: [PATCH v2 09/11] arm: dts: mt7622: add sata- and asm_sel nodes
In-Reply-To: <20200819080225.4267-10-linux@fw-web.de>
References: <20200819080225.4267-1-linux@fw-web.de>
 <20200819080225.4267-10-linux@fw-web.de>
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On Wed, 2020-08-19 at 10:02 +0200, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w@public-files.de>
> 
> asm_sel is for switching between sata and pcie mode
> on r64 there is GPIO90 connected to ASM1480 which
> switches RX/TX pairs to PCIe/SATA connector
> output-low means sata-controller is active
> 
> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> ---
>  arch/arm/dts/mt7622-bananapi-bpi-r64.dts |  9 +++++++
>  arch/arm/dts/mt7622.dtsi                 | 31 ++++++++++++++++++++++++
>  2 files changed, 40 insertions(+)
> 
> diff --git a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
> index 768f15bc2c..c36ec8f8d0 100644
> --- a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
> +++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
> @@ -204,3 +204,12 @@
>  		full-duplex;
>  	};
>  };
> +
> +&gpio {
> +	/*gpio 90 for setting mode to sata*/
> +	asm_sel {
> +		gpio-hog;
> +		gpios = <90 GPIO_ACTIVE_HIGH>;
> +		output-low;
> +	};
> +};
> diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi
> index fec071643e..6b4260407e 100644
> --- a/arch/arm/dts/mt7622.dtsi
> +++ b/arch/arm/dts/mt7622.dtsi
> @@ -10,6 +10,7 @@
>  #include <dt-bindings/power/mt7629-power.h>
>  #include <dt-bindings/reset/mt7629-reset.h>
>  #include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/phy/phy.h>
>  
>  / {
>  	compatible = "mediatek,mt7622";
> @@ -270,6 +271,36 @@
>  		};
>  	};
>  
> +	sata: sata at 1a200000 {
> +		compatible = "mediatek,mtk-ahci";
> +		reg = <0x1a200000 0x1100>;
> +		resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
> +			<&pciesys MT7622_SATA_PHY_SW_RST>,
> +			<&pciesys MT7622_SATA_PHY_REG_RST>;
> +		reset-names = "axi", "sw", "reg";
> +		mediatek,phy-mode = <&pciesys>;
> +		ports-implemented = <0x1>;
> +		phys = <&sata_port PHY_TYPE_SATA>;
> +		phy-names = "sata-phy";
> +		status = "okay";
> +	};
> +
> +	sata_phy: sata-phy at 1a243000 {
> +		compatible = "mediatek,generic-tphy-v1";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
we can use ranges with parameters if you send next version, otherwise no
change is also fine to me.

ranges=<0 0x1a243000 0x100>;
> +		status = "okay";
> +
> +		sata_port: sata-phy at 1a243000 {
> +			reg = <0x1a243000 0x0100>;
sata_port: sata-phy at 0 {
	reg = <0x0 0x0100>;
> +			clocks = <&topckgen CLK_TOP_ETH_500M>;
> +			clock-names = "ref";
> +			#phy-cells = <1>;
> +			status = "okay";
> +		};
> +	};
For phy part,
Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com>

thanks

> +
>  	ethsys: syscon at 1b000000 {
>  		compatible = "mediatek,mt7622-ethsys", "syscon";
>  		reg = <0x1b000000 0x1000>;