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Fri, 28 Aug 2020 11:13:46 +0000 From: "Robert Chiras (OSS)" To: Rob Herring , Andrzej Hajda , Neil Armstrong , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Sam Ravnborg , =?UTF-8?q?Guido=20G=C3=BCnther?= , Fabio Estevam , Ondrej Jirman Cc: David Airlie , Daniel Vetter , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-imx@nxp.com Subject: [PATCH 3/5] drm/bridge: nwl-dsi: Add support for clock-drop-level Date: Fri, 28 Aug 2020 14:13:30 +0300 Message-Id: <1598613212-1113-4-git-send-email-robert.chiras@oss.nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1598613212-1113-1-git-send-email-robert.chiras@oss.nxp.com> References: <1598613212-1113-1-git-send-email-robert.chiras@oss.nxp.com> Content-Type: text/plain X-ClientProxiedBy: AM3PR07CA0114.eurprd07.prod.outlook.com (2603:10a6:207:7::24) To DB6PR0401MB2598.eurprd04.prod.outlook.com (2603:10a6:4:39::7) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from fsr-ub1664-120.ea.freescale.net (83.217.231.2) by AM3PR07CA0114.eurprd07.prod.outlook.com (2603:10a6:207:7::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3348.7 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: AL3bSPx4NGF+UEGe6B1gAJJSplBnl1qT9dSAtOy/FD9mXx45eFhfYb7tem/VVuD/VocYwOYKc8cdSBRiaG7+Dz115SzY0i6Ac7GdBihgDD5yqKdMfUAfMxZDeAwmJhVX+tZLmdvuaHPFpnZqVNeXfCwmkfeM4tZj6LUYzCX5XtnTok2+kSb3cPDT1q3JDPl6tgc24u2CsLFc2xKO+WXITYAuxm6oOf0j3ZloQh8bdnzWt7WZCKevXOJdgbogOSzjbQXF8jdyRHA0i7j69YkvO8gSb03Qb5Zd7TnU04SZYRZqWzMqUxrmiIMC4mm1i+WZ/RNdp2fYaIWGHpov4eQnMb8p2F8bWFsJm3ltfxDwa2piNGRLZ9VtBxtGFTdDz5dgbL6g7xE1QHjT2jiFD33GSgJ9G1K8AjikUenPj6LosjyOQXuE0rsujkP8LXARMHRyDQBqnMDwcgu1Gy7ivSeyARkDDEVF89irwNrPyiFLzSzRHvZclDQ8DlVEExt1jv0CD92I+s6XPL9AETZLB9OCl+1PBx9jsVcZX6d4xdeF7tiobvbKxI48dxmwuQ1eriZnxugVnoWNJymBB9ChQT/8GP0M1zHqoRpKQ5BNEy9wo4Qq+ZYJtSwW71s4Fydr7kAz7xWWHKmwhrR/BWqYydoLcg== X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7a3e804a-7c66-44df-6d25-08d84b436e63 X-MS-Exchange-CrossTenant-AuthSource: DB6PR0401MB2598.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Aug 2020 11:13:46.1676 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: zSW0s7AS1AgxxbCj5oEbOds5FERTjwISSoD9fjGrBjxCdxqq5i3YcF2JWiI2pN2pf5KZLPiIQCeOO4396IAh3g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR04MB7413 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Robert Chiras The clock-drop-level is needed in order to add more blanking space needed by DSI panels when sending DSI commands. One level is the equivalent of phy_ref rate from the PLL rate. Since the PLL rate is targeted as highest possible, each level should not get the crtc_clock too low, compared to the actual clock. Example for a clock of 132M, with "clock-drop-level = <1>" in dts file will result in a crtc_clock of 129M, using the following logic: - video_pll rate to provide both phy_ref rate of 24M and pixel-clock of 132M is 1056M (divisor /43 for phy_ref and /8 for pixel-clock) - from this rate, we subtract the equivalent of phy_ref (24M) but keep the same divisor. This way, the video_pll rate will be 1056 - 24 = 1032M. - new pixel-clock will be: 1032 / 8 = 129M For a "clock-drop-level = <2>", new pixel-clock will be: (1056 - (24 * 2)) / 8 = 1008 / 8 = 126M Signed-off-by: Robert Chiras --- drivers/gpu/drm/bridge/nwl-dsi.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c index 1228466..ac4aa0a 100644 --- a/drivers/gpu/drm/bridge/nwl-dsi.c +++ b/drivers/gpu/drm/bridge/nwl-dsi.c @@ -142,6 +142,7 @@ struct nwl_dsi { struct nwl_dsi_transfer *xfer; struct list_head valid_modes; + u32 clk_drop_lvl; }; static const struct regmap_config nwl_dsi_regmap_config = { @@ -842,13 +843,14 @@ static unsigned long nwl_dsi_get_lcm(unsigned long a, unsigned long b) return ((unsigned long long)a * b) / gcf; } - /* * This function tries to adjust the crtc_clock for a DSI device in such a way * that the video pll will be able to satisfy both Display Controller pixel * clock (feeding out DPI interface) and our input phy_ref clock. + * Also, the DC pixel clock must be lower than the actual clock in order to + * have enough blanking space to send DSI commands, if the device is a panel. */ -static void nwl_dsi_setup_pll_config(struct mode_config *config) +static void nwl_dsi_setup_pll_config(struct mode_config *config, u32 lvl) { unsigned long pll_rate; int div; @@ -908,7 +910,6 @@ static void nwl_dsi_setup_pll_config(struct mode_config *config) } } - /* * This function will try the required phy speed for current mode * If the phy speed can be achieved, the phy will save the speed @@ -1103,7 +1104,7 @@ nwl_dsi_bridge_mode_valid(struct drm_bridge *bridge, pll_rate = config->pll_rates[config->phy_rate_idx]; if (dsi->pll_clk && !pll_rate) - nwl_dsi_setup_pll_config(config); + nwl_dsi_setup_pll_config(config, dsi->clk_drop_lvl); return MODE_OK; } @@ -1248,6 +1249,7 @@ static const struct drm_bridge_funcs nwl_dsi_bridge_funcs = { static int nwl_dsi_parse_dt(struct nwl_dsi *dsi) { struct platform_device *pdev = to_platform_device(dsi->dev); + struct device_node *np = dsi->dev->of_node; struct clk *clk; void __iomem *base; int ret; @@ -1364,6 +1366,8 @@ static int nwl_dsi_parse_dt(struct nwl_dsi *dsi) return PTR_ERR(dsi->rst_dpi); } + of_property_read_u32(np, "fsl,clock-drop-level", &dsi->clk_drop_lvl); + INIT_LIST_HEAD(&dsi->valid_modes); return 0; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Robert Chiras The clock-drop-level is needed in order to add more blanking space needed by DSI panels when sending DSI commands. One level is the equivalent of phy_ref rate from the PLL rate. Since the PLL rate is targeted as highest possible, each level should not get the crtc_clock too low, compared to the actual clock. Example for a clock of 132M, with "clock-drop-level = <1>" in dts file will result in a crtc_clock of 129M, using the following logic: - video_pll rate to provide both phy_ref rate of 24M and pixel-clock of 132M is 1056M (divisor /43 for phy_ref and /8 for pixel-clock) - from this rate, we subtract the equivalent of phy_ref (24M) but keep the same divisor. This way, the video_pll rate will be 1056 - 24 = 1032M. - new pixel-clock will be: 1032 / 8 = 129M For a "clock-drop-level = <2>", new pixel-clock will be: (1056 - (24 * 2)) / 8 = 1008 / 8 = 126M Signed-off-by: Robert Chiras --- drivers/gpu/drm/bridge/nwl-dsi.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c index 1228466..ac4aa0a 100644 --- a/drivers/gpu/drm/bridge/nwl-dsi.c +++ b/drivers/gpu/drm/bridge/nwl-dsi.c @@ -142,6 +142,7 @@ struct nwl_dsi { struct nwl_dsi_transfer *xfer; struct list_head valid_modes; + u32 clk_drop_lvl; }; static const struct regmap_config nwl_dsi_regmap_config = { @@ -842,13 +843,14 @@ static unsigned long nwl_dsi_get_lcm(unsigned long a, unsigned long b) return ((unsigned long long)a * b) / gcf; } - /* * This function tries to adjust the crtc_clock for a DSI device in such a way * that the video pll will be able to satisfy both Display Controller pixel * clock (feeding out DPI interface) and our input phy_ref clock. + * Also, the DC pixel clock must be lower than the actual clock in order to + * have enough blanking space to send DSI commands, if the device is a panel. */ -static void nwl_dsi_setup_pll_config(struct mode_config *config) +static void nwl_dsi_setup_pll_config(struct mode_config *config, u32 lvl) { unsigned long pll_rate; int div; @@ -908,7 +910,6 @@ static void nwl_dsi_setup_pll_config(struct mode_config *config) } } - /* * This function will try the required phy speed for current mode * If the phy speed can be achieved, the phy will save the speed @@ -1103,7 +1104,7 @@ nwl_dsi_bridge_mode_valid(struct drm_bridge *bridge, pll_rate = config->pll_rates[config->phy_rate_idx]; if (dsi->pll_clk && !pll_rate) - nwl_dsi_setup_pll_config(config); + nwl_dsi_setup_pll_config(config, dsi->clk_drop_lvl); return MODE_OK; } @@ -1248,6 +1249,7 @@ static const struct drm_bridge_funcs nwl_dsi_bridge_funcs = { static int nwl_dsi_parse_dt(struct nwl_dsi *dsi) { struct platform_device *pdev = to_platform_device(dsi->dev); + struct device_node *np = dsi->dev->of_node; struct clk *clk; void __iomem *base; int ret; @@ -1364,6 +1366,8 @@ static int nwl_dsi_parse_dt(struct nwl_dsi *dsi) return PTR_ERR(dsi->rst_dpi); } + of_property_read_u32(np, "fsl,clock-drop-level", &dsi->clk_drop_lvl); + INIT_LIST_HEAD(&dsi->valid_modes); return 0; -- 2.7.4 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel