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From: "Souza, Jose" <jose.souza@intel.com>
To: "Roper, Matthew D" <matthew.d.roper@intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Cc: "De Marchi, Lucas" <lucas.demarchi@intel.com>
Subject: Re: [PATCH] drm/i915: Add 324mhz and 326.4mhz cdclks for gen11+
Date: Fri, 23 Aug 2019 17:47:58 +0000	[thread overview]
Message-ID: <15eb5dcc645d4a1003b930f71bfa660eaa355c14.camel@intel.com> (raw)
In-Reply-To: <20190822163133.27587-1-matthew.d.roper@intel.com>

On Thu, 2019-08-22 at 09:31 -0700, Matt Roper wrote:
> The bspec was recently updated with these new cdclk values for ICL,
> EHL,
> and TGL.
> 
> Bspec: 20598
> Bspec: 49201

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index d0bc42e5039c..0be137a9129a 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1748,8 +1748,10 @@ static void cnl_sanitize_cdclk(struct
> drm_i915_private *dev_priv)
>  
>  static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
>  {
> -	static const int ranges_24[] = { 180000, 192000, 312000,
> 552000, 648000 };
> -	static const int ranges_19_38[] = { 172800, 192000, 307200,
> 556800, 652800 };
> +	static const int ranges_24[] = { 180000, 192000, 312000,
> 324000,
> +					 552000, 648000 };
> +	static const int ranges_19_38[] = { 172800, 192000, 307200,
> 326400,
> +					    556800, 652800 };
>  	const int *ranges;
>  	int len, i;
>  
> @@ -1790,6 +1792,7 @@ static int icl_calc_cdclk_pll_vco(struct
> drm_i915_private *dev_priv, int cdclk)
>  		/* fall through */
>  	case 172800:
>  	case 307200:
> +	case 326400:
>  	case 556800:
>  	case 652800:
>  		WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
> @@ -1797,6 +1800,7 @@ static int icl_calc_cdclk_pll_vco(struct
> drm_i915_private *dev_priv, int cdclk)
>  		break;
>  	case 180000:
>  	case 312000:
> +	case 324000:
>  	case 552000:
>  	case 648000:
>  		WARN_ON(dev_priv->cdclk.hw.ref != 24000);
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  parent reply	other threads:[~2019-08-23 17:47 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-22 16:31 [PATCH] drm/i915: Add 324mhz and 326.4mhz cdclks for gen11+ Matt Roper
2019-08-23 13:26 ` ✓ Fi.CI.BAT: success for " Patchwork
2019-08-23 17:47 ` Souza, Jose [this message]
2019-08-23 22:17 ` [PATCH] " Matt Roper
2019-08-24 10:42 ` ✓ Fi.CI.IGT: success for " Patchwork

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