From mboxrd@z Thu Jan 1 00:00:00 1970 From: Wasim Khan Date: Mon, 28 Sep 2020 16:26:14 +0530 Subject: [PATCH v2 12/12] pci: ls_pcie_g4: Add size check for config resource In-Reply-To: <1601290574-20151-1-git-send-email-wasim.khan@nxp.com> References: <1601290574-20151-1-git-send-email-wasim.khan@nxp.com> Message-ID: <1601290574-20151-13-git-send-email-wasim.khan@nxp.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de resource "config" is required to have minimum 4KB space to access all config space of PCI Express EP. Signed-off-by: Wasim Khan --- Changes in V2: - Updated commit description - Fix CheckPatch issue - Change size check to 4KB to access PCIe config space Changes in V3: - No Change drivers/pci/pcie_layerscape_gen4.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c index 0226bde..6e71173 100644 --- a/drivers/pci/pcie_layerscape_gen4.c +++ b/drivers/pci/pcie_layerscape_gen4.c @@ -455,6 +455,7 @@ static int ls_pcie_g4_probe(struct udevice *dev) u32 link_ctrl_sta; u32 val; int ret; + fdt_size_t cfg_size; pcie->bus = dev; @@ -488,6 +489,13 @@ static int ls_pcie_g4_probe(struct udevice *dev) return ret; } + cfg_size = fdt_resource_size(&pcie->cfg_res); + if (cfg_size < SZ_4K) { + printf("PCIe%d: %s Invalid size(0x%llx) for resource \"config\",expected minimum 0x%x\n", + PCIE_SRDS_PRTCL(pcie->idx), dev->name, cfg_size, SZ_4K); + return 0; + } + pcie->cfg = map_physmem(pcie->cfg_res.start, fdt_resource_size(&pcie->cfg_res), MAP_NOCACHE); -- 2.7.4