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From: Taylor Simpson <tsimpson@quicinc.com>
To: tsimpson@quicinc.com
Cc: "open list:All patches CC here" <qemu-devel@nongnu.org>
Subject: [RFC PATCH v4 12/29] Hexagon (target/hexagon) instruction attributes
Date: Mon, 28 Sep 2020 07:36:31 -0500	[thread overview]
Message-ID: <1601296608-29390-13-git-send-email-tsimpson@quicinc.com> (raw)
In-Reply-To: <1601296608-29390-1-git-send-email-tsimpson@quicinc.com>

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
---
 target/hexagon/attribs.h     | 32 +++++++++++++++
 target/hexagon/attribs_def.h | 98 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 130 insertions(+)
 create mode 100644 target/hexagon/attribs.h
 create mode 100644 target/hexagon/attribs_def.h

diff --git a/target/hexagon/attribs.h b/target/hexagon/attribs.h
new file mode 100644
index 0000000..d35af0c
--- /dev/null
+++ b/target/hexagon/attribs.h
@@ -0,0 +1,32 @@
+/*
+ *  Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HEXAGON_ATTRIBS_H
+#define HEXAGON_ATTRIBS_H
+
+enum {
+#define DEF_ATTRIB(NAME, ...) A_##NAME,
+#include "attribs_def.h"
+#undef DEF_ATTRIB
+};
+
+#define ATTRIB_WIDTH 32
+#define GET_ATTRIB(opcode, attrib) \
+    (((opcode_attribs[opcode][attrib / ATTRIB_WIDTH])\
+    >> (attrib % ATTRIB_WIDTH)) & 0x1)
+
+#endif /* ATTRIBS_H */
diff --git a/target/hexagon/attribs_def.h b/target/hexagon/attribs_def.h
new file mode 100644
index 0000000..d024176
--- /dev/null
+++ b/target/hexagon/attribs_def.h
@@ -0,0 +1,98 @@
+/*
+ *  Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Keep this as the first attribute: */
+DEF_ATTRIB(AA_DUMMY, "Dummy Zeroth Attribute", "", "")
+
+/* Misc */
+DEF_ATTRIB(EXTENSION, "Extension instruction", "", "")
+
+DEF_ATTRIB(PRIV, "Not available in user or guest mode", "", "")
+DEF_ATTRIB(GUEST, "Not available in user mode", "", "")
+
+DEF_ATTRIB(FPOP, "Floating Point Operation", "", "")
+
+DEF_ATTRIB(EXTENDABLE, "Immediate may be extended", "", "")
+
+DEF_ATTRIB(ARCHV2, "V2 architecture", "", "")
+DEF_ATTRIB(ARCHV3, "V3 architecture", "", "")
+DEF_ATTRIB(ARCHV4, "V4 architecture", "", "")
+DEF_ATTRIB(ARCHV5, "V5 architecture", "", "")
+
+DEF_ATTRIB(SUBINSN, "sub-instruction", "", "")
+
+/* Load and Store attributes */
+DEF_ATTRIB(LOAD, "Loads from memory", "", "")
+DEF_ATTRIB(STORE, "Stores to memory", "", "")
+DEF_ATTRIB(MEMLIKE, "Memory-like instruction", "", "")
+DEF_ATTRIB(MEMLIKE_PACKET_RULES, "follows Memory-like packet rules", "", "")
+
+
+/* Change-of-flow attributes */
+DEF_ATTRIB(JUMP, "Jump-type instruction", "", "")
+DEF_ATTRIB(INDIRECT, "Absolute register jump", "", "")
+DEF_ATTRIB(CALL, "Function call instruction", "", "")
+DEF_ATTRIB(COF, "Change-of-flow instruction", "", "")
+DEF_ATTRIB(CONDEXEC, "May be cancelled by a predicate", "", "")
+DEF_ATTRIB(DOTNEWVALUE, "Uses a register value generated in this pkt", "", "")
+DEF_ATTRIB(NEWCMPJUMP, "Compound compare and jump", "", "")
+
+/* access to implicit registers */
+DEF_ATTRIB(IMPLICIT_WRITES_LR, "Writes the link register", "", "UREG.LR")
+DEF_ATTRIB(IMPLICIT_WRITES_PC, "Writes the program counter", "", "UREG.PC")
+DEF_ATTRIB(IMPLICIT_WRITES_SP, "Writes the stack pointer", "", "UREG.SP")
+DEF_ATTRIB(IMPLICIT_WRITES_FP, "Writes the frame pointer", "", "UREG.FP")
+DEF_ATTRIB(IMPLICIT_WRITES_GP, "Writes the GP register", "", "UREG.GP")
+DEF_ATTRIB(IMPLICIT_WRITES_LC0, "Writes loop count for loop 0", "", "UREG.LC0")
+DEF_ATTRIB(IMPLICIT_WRITES_LC1, "Writes loop count for loop 1", "", "UREG.LC1")
+DEF_ATTRIB(IMPLICIT_WRITES_SA0, "Writes start addr for loop 0", "", "UREG.SA0")
+DEF_ATTRIB(IMPLICIT_WRITES_SA1, "Writes start addr for loop 1", "", "UREG.SA1")
+DEF_ATTRIB(IMPLICIT_WRITES_P0, "Writes Predicate 0", "", "UREG.P0")
+DEF_ATTRIB(IMPLICIT_WRITES_P1, "Writes Predicate 1", "", "UREG.P1")
+DEF_ATTRIB(IMPLICIT_WRITES_P2, "Writes Predicate 1", "", "UREG.P2")
+DEF_ATTRIB(IMPLICIT_WRITES_P3, "May write Predicate 3", "", "UREG.P3")
+
+DEF_ATTRIB(CRSLOT23, "Can execute in slot 2 or slot 3 (CR)", "", "")
+DEF_ATTRIB(IT_NOP, "nop instruction", "", "")
+DEF_ATTRIB(IT_EXTENDER, "constant extender instruction", "", "")
+
+
+/* Restrictions to make note of */
+DEF_ATTRIB(RESTRICT_SLOT0ONLY, "Must execute on slot0", "", "")
+DEF_ATTRIB(RESTRICT_SLOT1ONLY, "Must execute on slot1", "", "")
+DEF_ATTRIB(RESTRICT_SLOT2ONLY, "Must execute on slot2", "", "")
+DEF_ATTRIB(RESTRICT_SLOT3ONLY, "Must execute on slot3", "", "")
+DEF_ATTRIB(RESTRICT_NOSLOT1, "No slot 1 instruction in parallel", "", "")
+DEF_ATTRIB(RESTRICT_PREFERSLOT0, "Try to encode into slot 0", "", "")
+
+DEF_ATTRIB(ICOP, "Instruction cache op", "", "")
+
+DEF_ATTRIB(HWLOOP0_END, "Ends HW loop0", "", "")
+DEF_ATTRIB(HWLOOP1_END, "Ends HW loop1", "", "")
+DEF_ATTRIB(DCZEROA, "dczeroa type", "", "")
+DEF_ATTRIB(ICFLUSHOP, "icflush op type", "", "")
+DEF_ATTRIB(DCFLUSHOP, "dcflush op type", "", "")
+DEF_ATTRIB(DCFETCH, "dcfetch type", "", "")
+
+DEF_ATTRIB(L2FETCH, "Instruction is l2fetch type", "", "")
+
+DEF_ATTRIB(ICINVA, "icinva", "", "")
+DEF_ATTRIB(DCCLEANINVA, "dccleaninva", "", "")
+
+/* Keep this as the last attribute: */
+DEF_ATTRIB(ZZ_LASTATTRIB, "Last attribute in the file", "", "")
+
-- 
2.7.4


  parent reply	other threads:[~2020-09-28 12:49 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <1601296608-29390-1-git-send-email-tsimpson@quicinc.com>
2020-09-28 12:36 ` [RFC PATCH v4 01/29] Hexagon Update MAINTAINERS file Taylor Simpson
2020-09-28 12:36 ` [RFC PATCH v4 02/29] Hexagon (target/hexagon) README Taylor Simpson
2020-09-28 12:36 ` [RFC PATCH v4 03/29] Hexagon (include/elf.h) ELF machine definition Taylor Simpson
2020-09-28 12:36 ` [RFC PATCH v4 04/29] Hexagon (target/hexagon) scalar core definition Taylor Simpson
2020-09-28 12:36 ` [RFC PATCH v4 05/29] Hexagon (disas) disassembler Taylor Simpson
2020-09-28 12:36 ` [RFC PATCH v4 06/29] Hexagon (target/hexagon) register names Taylor Simpson
2020-09-28 12:36 ` [RFC PATCH v4 07/29] Hexagon (target/hexagon) scalar core helpers Taylor Simpson
2020-09-28 12:36 ` [RFC PATCH v4 08/29] Hexagon (target/hexagon) GDB Stub Taylor Simpson
2020-09-28 12:36 ` [RFC PATCH v4 09/29] Hexagon (target/hexagon) architecture types Taylor Simpson
2020-09-28 12:36 ` [RFC PATCH v4 10/29] Hexagon (target/hexagon) instruction and packet types Taylor Simpson
2020-09-28 12:36 ` [RFC PATCH v4 11/29] Hexagon (target/hexagon) register fields Taylor Simpson
2020-09-28 12:36 ` Taylor Simpson [this message]
2020-09-28 12:36 ` [RFC PATCH v4 13/29] Hexagon (target/hexagon) instruction/packet decode Taylor Simpson
2020-09-28 12:36 ` [RFC PATCH v4 14/29] Hexagon (target/hexagon) instruction printing Taylor Simpson
2020-09-28 12:36 ` [RFC PATCH v4 15/29] Hexagon (target/hexagon) utility functions Taylor Simpson
2020-09-28 12:36 ` [RFC PATCH v4 16/29] Hexagon (target/hexagon/imported) arch import Taylor Simpson
2020-09-28 12:36 ` [RFC PATCH v4 17/29] Hexagon (target/hexagon) generator phase 1 - C preprocessor for semantics Taylor Simpson
2020-09-28 12:36 ` [RFC PATCH v4 18/29] Hexagon (target/hexagon) generator phase 2 - generate header files Taylor Simpson
2020-09-28 12:36 ` [RFC PATCH v4 19/29] Hexagon (target/hexagon) generator phase 3 - C preprocessor for decode tree Taylor Simpson
2020-09-28 12:36 ` [RFC PATCH v4 20/29] Hexagon (target/hexagon) generater phase 4 - " Taylor Simpson
2020-09-28 12:36 ` [RFC PATCH v4 21/29] Hexagon (target/hexagon) opcode data structures Taylor Simpson
2020-09-28 12:36 ` [RFC PATCH v4 22/29] Hexagon (target/hexagon) macros Taylor Simpson
2020-09-28 12:36 ` [RFC PATCH v4 23/29] Hexagon (target/hexagon) instruction classes Taylor Simpson
2020-09-28 12:36 ` [RFC PATCH v4 24/29] Hexagon (target/hexagon) TCG generation Taylor Simpson
2020-09-28 12:36 ` [RFC PATCH v4 25/29] Hexagon (target/hexagon) TCG for instructions with multiple definitions Taylor Simpson
2020-09-28 12:36 ` [RFC PATCH v4 26/29] Hexagon (target/hexagon) translation Taylor Simpson
2020-09-28 12:36 ` [RFC PATCH v4 27/29] Hexagon (linux-user/hexagon) Linux user emulation Taylor Simpson
2020-09-28 12:36 ` [RFC PATCH v4 28/29] Hexagon (tests/tcg/hexagon) TCG tests Taylor Simpson
2020-09-28 12:36 ` [RFC PATCH v4 29/29] Hexagon build infrastructure Taylor Simpson
2020-09-28 17:28 [RFC PATCH v4 00/29] Hexagon patch series Taylor Simpson
2020-09-28 17:28 ` [RFC PATCH v4 12/29] Hexagon (target/hexagon) instruction attributes Taylor Simpson

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