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From: Patchwork <patchwork@emeril.freedesktop.org>
To: "Lucas De Marchi" <lucas.demarchi@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1
Date: Wed, 30 Sep 2020 07:25:10 -0000	[thread overview]
Message-ID: <160145071097.17416.917015014930953761@emeril.freedesktop.org> (raw)
In-Reply-To: <20200930064234.85769-1-lucas.demarchi@intel.com>

== Series Details ==

Series: Introduce DG1
URL   : https://patchwork.freedesktop.org/series/82241/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
2ab727864817 drm/i915/dg1: add more PCI ids
02a93e492718 drm/i915/dg1: Initialize RAWCLK properly
90eb98d91e8e drm/i915/dg1: Define MOCS table for DG1
44b1fb34d9e6 drm/i915/dg1: Add DG1 power wells
af7964472d1d drm/i915/dg1: Increase mmio size to 4MB
313e894b5c43 drm/i915/dg1: Wait for pcode/uncore handshake at startup
46ba3b109500 drm/i915/dg1: Add DPLL macros for DG1
802098453f92 drm/i915/dg1: Add and setup DPLLs for DG1
fc9e91e510d5 drm/i915/dg1: Enable DPLL for DG1
4caa7e8d99ff drm/i915/dg1: add hpd interrupt handling
1556d9b840f8 drm/i915/dg1: invert HPD pins
ed7812a70681 drm/i915/dg1: gmbus pin mapping
b5634537768e drm/i915/dg1: Enable first 2 ports for DG1
a96cb47a46d4 drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
e764c35d3b9e drm/i915/dg1: Update comp master/slave relationships for PHYs
dc3f763d7b05 drm/i915/dg1: Update voltage swing tables for DP
d0727f32e9ec drm/i915/dg1: provide port/phy mapping for vbt
3056c7ce001a drm/i915/dg1: map/unmap pll clocks
-:244: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'phy' - possible side-effects?
#244: FILE: drivers/gpu/drm/i915/i915_reg.h:10320:
+#define   DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_VAL_TO_ID(val, phy) \
+	  ((((val) & DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)) >> ((phy % 2) * 2)) + (2 * (phy / 2)))

total: 0 errors, 0 warnings, 1 checks, 204 lines checked
571405def6c9 drm/i915/dg1: enable PORT C/D aka D/E
f5c37ea500ef drm/i915/dg1: Load DMC
01007b9c648c drm/i915/dg1: Add initial DG1 workarounds
9034c09bbbdf drm/i915/dg1: DG1 does not support DC6
648249c6dd8b drm/i915/dg1: Change DMC_DEBUG{1, 2} registers
b609cfe8808b drm/i915/dgfx: define llc and snooping behaviour


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  parent reply	other threads:[~2020-09-30  7:25 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-30  6:42 [Intel-gfx] [PATCH v6 00/24] Introduce DG1 Lucas De Marchi
2020-09-30  6:42 ` [Intel-gfx] [PATCH v6 01/24] drm/i915/dg1: add more PCI ids Lucas De Marchi
2020-09-30 14:00   ` Matt Roper
2020-09-30  6:42 ` [Intel-gfx] [PATCH v6 02/24] drm/i915/dg1: Initialize RAWCLK properly Lucas De Marchi
2020-09-30  6:42 ` [Intel-gfx] [PATCH v6 03/24] drm/i915/dg1: Define MOCS table for DG1 Lucas De Marchi
2020-09-30  6:42 ` [Intel-gfx] [PATCH v6 04/24] drm/i915/dg1: Add DG1 power wells Lucas De Marchi
2020-09-30 15:44   ` Matt Roper
2020-09-30  6:42 ` [Intel-gfx] [PATCH v6 05/24] drm/i915/dg1: Increase mmio size to 4MB Lucas De Marchi
2020-09-30  6:42 ` [Intel-gfx] [PATCH v6 06/24] drm/i915/dg1: Wait for pcode/uncore handshake at startup Lucas De Marchi
2020-09-30  6:42 ` [Intel-gfx] [PATCH v6 07/24] drm/i915/dg1: Add DPLL macros for DG1 Lucas De Marchi
2020-09-30  6:42 ` [Intel-gfx] [PATCH v6 08/24] drm/i915/dg1: Add and setup DPLLs " Lucas De Marchi
2020-09-30  6:42 ` [Intel-gfx] [PATCH v6 09/24] drm/i915/dg1: Enable DPLL " Lucas De Marchi
2020-09-30  6:42 ` [Intel-gfx] [PATCH v6 10/24] drm/i915/dg1: add hpd interrupt handling Lucas De Marchi
2020-09-30  6:42 ` [Intel-gfx] [PATCH v6 11/24] drm/i915/dg1: invert HPD pins Lucas De Marchi
2020-09-30  6:42 ` [Intel-gfx] [PATCH v6 12/24] drm/i915/dg1: gmbus pin mapping Lucas De Marchi
2020-09-30 16:17   ` Matt Roper
2020-09-30  6:42 ` [Intel-gfx] [PATCH v6 13/24] drm/i915/dg1: Enable first 2 ports for DG1 Lucas De Marchi
2020-09-30  6:42 ` [Intel-gfx] [PATCH v6 14/24] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D Lucas De Marchi
2020-09-30  6:42 ` [Intel-gfx] [PATCH v6 15/24] drm/i915/dg1: Update comp master/slave relationships for PHYs Lucas De Marchi
2020-09-30  6:42 ` [Intel-gfx] [PATCH v6 16/24] drm/i915/dg1: Update voltage swing tables for DP Lucas De Marchi
2020-09-30  6:42 ` [Intel-gfx] [PATCH v6 17/24] drm/i915/dg1: provide port/phy mapping for vbt Lucas De Marchi
2020-09-30  6:42 ` [Intel-gfx] [PATCH v6 18/24] drm/i915/dg1: map/unmap pll clocks Lucas De Marchi
2020-09-30  6:42 ` [Intel-gfx] [PATCH v6 19/24] drm/i915/dg1: enable PORT C/D aka D/E Lucas De Marchi
2020-09-30 17:33   ` Matt Roper
2020-09-30  6:42 ` [Intel-gfx] [PATCH v6 20/24] drm/i915/dg1: Load DMC Lucas De Marchi
2020-09-30 16:10   ` Matt Roper
2020-09-30 16:18     ` Lucas De Marchi
2020-09-30  6:42 ` [Intel-gfx] [PATCH v6 21/24] drm/i915/dg1: Add initial DG1 workarounds Lucas De Marchi
2020-09-30  6:42 ` [Intel-gfx] [PATCH v6 22/24] drm/i915/dg1: DG1 does not support DC6 Lucas De Marchi
2020-09-30 16:50   ` Matt Roper
2020-10-08  4:20     ` Lucas De Marchi
2020-09-30  6:42 ` [Intel-gfx] [PATCH v6 23/24] drm/i915/dg1: Change DMC_DEBUG{1, 2} registers Lucas De Marchi
2020-09-30 17:20   ` Matt Roper
2020-10-01  5:16     ` Lucas De Marchi
2020-10-01 14:51       ` Matt Roper
2020-09-30  6:42 ` [Intel-gfx] [PATCH v6 24/24] drm/i915/dgfx: define llc and snooping behaviour Lucas De Marchi
2020-09-30  7:25 ` Patchwork [this message]
2020-09-30  7:26 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Introduce DG1 Patchwork
2020-09-30  7:44 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-09-30  8:01   ` Lucas De Marchi
2020-09-30  9:14     ` Matthew Auld
  -- strict thread matches above, loose matches on Subject: below --
2020-10-12 21:29 [Intel-gfx] [PATCH v7 00/15] " Lucas De Marchi
2020-10-12 21:52 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2020-07-24 21:38 [Intel-gfx] [PATCH v5 00/22] " Lucas De Marchi
2020-07-24 21:45 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2020-05-21  0:37 [Intel-gfx] [PATCH 00/37] " Lucas De Marchi
2020-05-21  1:05 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork

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