From: "tip-bot2 for Mike Travis" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: Mike Travis <mike.travis@hpe.com>, Borislav Petkov <bp@suse.de>,
Dimitri Sivanich <dimitri.sivanich@hpe.com>,
Steve Wahl <steve.wahl@hpe.com>, x86 <x86@kernel.org>,
LKML <linux-kernel@vger.kernel.org>
Subject: [tip: x86/platform] x86/platform/uv: Update for UV5 NMI MMR changes
Date: Wed, 07 Oct 2020 07:12:00 -0000 [thread overview]
Message-ID: <160205472033.7002.14164903565017374344.tip-bot2@tip-bot2> (raw)
In-Reply-To: <20201005203929.148656-13-mike.travis@hpe.com>
The following commit has been merged into the x86/platform branch of tip:
Commit-ID: ae5f8ce3c247b8d937782e76802a9036c09998ad
Gitweb: https://git.kernel.org/tip/ae5f8ce3c247b8d937782e76802a9036c09998ad
Author: Mike Travis <mike.travis@hpe.com>
AuthorDate: Mon, 05 Oct 2020 15:39:28 -05:00
Committer: Borislav Petkov <bp@suse.de>
CommitterDate: Wed, 07 Oct 2020 09:09:50 +02:00
x86/platform/uv: Update for UV5 NMI MMR changes
The UV NMI MMR addresses and fields moved between UV4 and UV5
necessitating a rewrite of the UV NMI handler. Adjust references
to accommodate those changes.
Signed-off-by: Mike Travis <mike.travis@hpe.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Dimitri Sivanich <dimitri.sivanich@hpe.com>
Reviewed-by: Steve Wahl <steve.wahl@hpe.com>
Link: https://lkml.kernel.org/r/20201005203929.148656-13-mike.travis@hpe.com
---
arch/x86/include/asm/uv/uv_hub.h | 13 +------
arch/x86/platform/uv/uv_nmi.c | 64 ++++++++++++++++++++++++++-----
2 files changed, 54 insertions(+), 23 deletions(-)
diff --git a/arch/x86/include/asm/uv/uv_hub.h b/arch/x86/include/asm/uv/uv_hub.h
index 07079b5..610bda2 100644
--- a/arch/x86/include/asm/uv/uv_hub.h
+++ b/arch/x86/include/asm/uv/uv_hub.h
@@ -734,19 +734,6 @@ extern void uv_nmi_setup_hubless(void);
#define UVH_NMI_MMR_SHIFT 63
#define UVH_NMI_MMR_TYPE "SCRATCH5"
-/* Newer SMM NMI handler, not present in all systems */
-#define UVH_NMI_MMRX UVH_EVENT_OCCURRED0
-#define UVH_NMI_MMRX_CLEAR UVH_EVENT_OCCURRED0_ALIAS
-#define UVH_NMI_MMRX_SHIFT UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT
-#define UVH_NMI_MMRX_TYPE "EXTIO_INT0"
-
-/* Non-zero indicates newer SMM NMI handler present */
-#define UVH_NMI_MMRX_SUPPORTED UVH_EXTIO_INT0_BROADCAST
-
-/* Indicates to BIOS that we want to use the newer SMM NMI handler */
-#define UVH_NMI_MMRX_REQ UVH_BIOS_KERNEL_MMR_ALIAS_2
-#define UVH_NMI_MMRX_REQ_SHIFT 62
-
struct uv_hub_nmi_s {
raw_spinlock_t nmi_lock;
atomic_t in_nmi; /* flag this node in UV NMI IRQ */
diff --git a/arch/x86/platform/uv/uv_nmi.c b/arch/x86/platform/uv/uv_nmi.c
index 9d08ff5..eac26fe 100644
--- a/arch/x86/platform/uv/uv_nmi.c
+++ b/arch/x86/platform/uv/uv_nmi.c
@@ -2,8 +2,8 @@
/*
* SGI NMI support routines
*
- * Copyright (c) 2009-2013 Silicon Graphics, Inc. All Rights Reserved.
- * Copyright (c) Mike Travis
+ * Copyright (C) 2007-2017 Silicon Graphics, Inc. All rights reserved.
+ * Copyright (c) Mike Travis
*/
#include <linux/cpu.h>
@@ -54,6 +54,20 @@ static struct uv_hub_nmi_s **uv_hub_nmi_list;
DEFINE_PER_CPU(struct uv_cpu_nmi_s, uv_cpu_nmi);
+/* Newer SMM NMI handler, not present in all systems */
+static unsigned long uvh_nmi_mmrx; /* UVH_EVENT_OCCURRED0/1 */
+static unsigned long uvh_nmi_mmrx_clear; /* UVH_EVENT_OCCURRED0/1_ALIAS */
+static int uvh_nmi_mmrx_shift; /* UVH_EVENT_OCCURRED0/1_EXTIO_INT0_SHFT */
+static int uvh_nmi_mmrx_mask; /* UVH_EVENT_OCCURRED0/1_EXTIO_INT0_MASK */
+static char *uvh_nmi_mmrx_type; /* "EXTIO_INT0" */
+
+/* Non-zero indicates newer SMM NMI handler present */
+static unsigned long uvh_nmi_mmrx_supported; /* UVH_EXTIO_INT0_BROADCAST */
+
+/* Indicates to BIOS that we want to use the newer SMM NMI handler */
+static unsigned long uvh_nmi_mmrx_req; /* UVH_BIOS_KERNEL_MMR_ALIAS_2 */
+static int uvh_nmi_mmrx_req_shift; /* 62 */
+
/* UV hubless values */
#define NMI_CONTROL_PORT 0x70
#define NMI_DUMMY_PORT 0x71
@@ -227,13 +241,43 @@ static inline bool uv_nmi_action_is(const char *action)
/* Setup which NMI support is present in system */
static void uv_nmi_setup_mmrs(void)
{
- if (uv_read_local_mmr(UVH_NMI_MMRX_SUPPORTED)) {
- uv_write_local_mmr(UVH_NMI_MMRX_REQ,
- 1UL << UVH_NMI_MMRX_REQ_SHIFT);
- nmi_mmr = UVH_NMI_MMRX;
- nmi_mmr_clear = UVH_NMI_MMRX_CLEAR;
- nmi_mmr_pending = 1UL << UVH_NMI_MMRX_SHIFT;
- pr_info("UV: SMI NMI support: %s\n", UVH_NMI_MMRX_TYPE);
+ /* First determine arch specific MMRs to handshake with BIOS */
+ if (UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK) {
+ uvh_nmi_mmrx = UVH_EVENT_OCCURRED0;
+ uvh_nmi_mmrx_clear = UVH_EVENT_OCCURRED0_ALIAS;
+ uvh_nmi_mmrx_shift = UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT;
+ uvh_nmi_mmrx_mask = UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK;
+ uvh_nmi_mmrx_type = "OCRD0-EXTIO_INT0";
+
+ uvh_nmi_mmrx_supported = UVH_EXTIO_INT0_BROADCAST;
+ uvh_nmi_mmrx_req = UVH_BIOS_KERNEL_MMR_ALIAS_2;
+ uvh_nmi_mmrx_req_shift = 62;
+
+ } else if (UVH_EVENT_OCCURRED1_EXTIO_INT0_MASK) {
+ uvh_nmi_mmrx = UVH_EVENT_OCCURRED1;
+ uvh_nmi_mmrx_clear = UVH_EVENT_OCCURRED1_ALIAS;
+ uvh_nmi_mmrx_shift = UVH_EVENT_OCCURRED1_EXTIO_INT0_SHFT;
+ uvh_nmi_mmrx_mask = UVH_EVENT_OCCURRED1_EXTIO_INT0_MASK;
+ uvh_nmi_mmrx_type = "OCRD1-EXTIO_INT0";
+
+ uvh_nmi_mmrx_supported = UVH_EXTIO_INT0_BROADCAST;
+ uvh_nmi_mmrx_req = UVH_BIOS_KERNEL_MMR_ALIAS_2;
+ uvh_nmi_mmrx_req_shift = 62;
+
+ } else {
+ pr_err("UV:%s:cannot find EVENT_OCCURRED*_EXTIO_INT0\n",
+ __func__);
+ return;
+ }
+
+ /* Then find out if new NMI is supported */
+ if (likely(uv_read_local_mmr(uvh_nmi_mmrx_supported))) {
+ uv_write_local_mmr(uvh_nmi_mmrx_req,
+ 1UL << uvh_nmi_mmrx_req_shift);
+ nmi_mmr = uvh_nmi_mmrx;
+ nmi_mmr_clear = uvh_nmi_mmrx_clear;
+ nmi_mmr_pending = 1UL << uvh_nmi_mmrx_shift;
+ pr_info("UV: SMI NMI support: %s\n", uvh_nmi_mmrx_type);
} else {
nmi_mmr = UVH_NMI_MMR;
nmi_mmr_clear = UVH_NMI_MMR_CLEAR;
@@ -1049,5 +1093,5 @@ void __init uv_nmi_setup_hubless(void)
/* Ensure NMI enabled in Processor Interface Reg: */
uv_reassert_nmi();
uv_register_nmi_notifier();
- pr_info("UV: Hubless NMI enabled\n");
+ pr_info("UV: PCH NMI enabled\n");
}
next prev parent reply other threads:[~2020-10-07 7:12 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-05 20:39 [PATCH v4 00/13] x86/platform/uv: Updates for UV5 Architecture Mike Travis
2020-10-05 20:39 ` [PATCH v4 01/13] x86/platform/uv: Remove UV BAU TLB Shootdown Handler Mike Travis
2020-10-07 7:12 ` [tip: x86/platform] " tip-bot2 for Mike Travis
2020-10-05 20:39 ` [PATCH v4 02/13] x86/platform/uv: Remove SCIR MMR references for UVY systems Mike Travis
2020-10-06 13:16 ` Borislav Petkov
2020-10-07 1:11 ` Mike Travis
2020-10-07 6:44 ` Borislav Petkov
2020-10-07 7:12 ` [tip: x86/platform] x86/platform/uv: Remove SCIR MMR references for UV systems tip-bot2 for Mike Travis
2020-10-05 20:39 ` [PATCH v4 03/13] x86/platform/uv: Adjust references in UV kernel modules Mike Travis
2020-10-05 21:16 ` Borislav Petkov
2020-10-05 21:32 ` Mike Travis
2020-10-06 13:10 ` Borislav Petkov
2020-10-07 6:57 ` Borislav Petkov
2020-10-07 7:12 ` [tip: x86/platform] drivers/misc/sgi-xp: " tip-bot2 for Mike Travis
2020-10-05 20:39 ` [PATCH v4 04/13] x86/platform/uv: Update UV MMRs for UV5 Mike Travis
2020-10-07 7:12 ` [tip: x86/platform] " tip-bot2 for Mike Travis
2020-10-05 20:39 ` [PATCH v4 05/13] x86/platform/uv: Add UV5 direct references Mike Travis
2020-10-07 7:12 ` [tip: x86/platform] " tip-bot2 for Mike Travis
2020-10-05 20:39 ` [PATCH v4 06/13] x86/platform/uv: Add and Decode Arch Type in UVsystab Mike Travis
2020-10-05 21:21 ` Borislav Petkov
2020-10-05 21:35 ` Mike Travis
2020-10-06 15:19 ` Borislav Petkov
2020-10-07 1:21 ` Mike Travis
2020-10-07 7:05 ` Borislav Petkov
2020-10-07 7:12 ` [tip: x86/platform] x86/platform/uv: Add and decode " tip-bot2 for Mike Travis
2020-10-05 20:39 ` [PATCH v4 07/13] x86/platform/uv: Update MMIOH references based on new UV5 MMRs Mike Travis
2020-10-07 7:12 ` [tip: x86/platform] " tip-bot2 for Mike Travis
2020-10-05 20:39 ` [PATCH v4 08/13] x86/platform/uv: Adjust GAM MMR references affected by UV5 updates Mike Travis
2020-10-07 7:12 ` [tip: x86/platform] " tip-bot2 for Mike Travis
2020-10-05 20:39 ` [PATCH v4 09/13] x86/platform/uv: Update UV5 MMR references in UV GRU Mike Travis
2020-10-07 7:12 ` [tip: x86/platform] " tip-bot2 for Mike Travis
2020-10-05 20:39 ` [PATCH v4 10/13] x86/platform/uv: Update Node Present Counting Mike Travis
2020-10-07 7:12 ` [tip: x86/platform] x86/platform/uv: Update node present counting tip-bot2 for Mike Travis
2020-10-05 20:39 ` [PATCH v4 11/13] x86/platform/uv: Update UV5 TSC Checking Mike Travis
2020-10-07 7:12 ` [tip: x86/platform] x86/platform/uv: Update UV5 TSC checking tip-bot2 for Mike Travis
2020-10-05 20:39 ` [PATCH v4 12/13] x86/platform/uv: Update for UV5 NMI MMR changes Mike Travis
2020-10-07 7:12 ` tip-bot2 for Mike Travis [this message]
2020-10-05 20:39 ` [PATCH v4 13/13] x86/platform/uv: Update Copyrights to conform to HPE standards Mike Travis
2020-10-07 7:11 ` [tip: x86/platform] " tip-bot2 for Mike Travis
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=160205472033.7002.14164903565017374344.tip-bot2@tip-bot2 \
--to=tip-bot2@linutronix.de \
--cc=bp@suse.de \
--cc=dimitri.sivanich@hpe.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-tip-commits@vger.kernel.org \
--cc=mike.travis@hpe.com \
--cc=steve.wahl@hpe.com \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.