From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.3 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3FF12C433DF for ; Wed, 14 Oct 2020 13:30:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A8EE52222C for ; Wed, 14 Oct 2020 13:30:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="ao36OYAF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731221AbgJNNaQ (ORCPT ); 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Wed, 14 Oct 2020 21:30:04 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 14 Oct 2020 21:30:03 +0800 Message-ID: <1602682204.14806.53.camel@mhfsdcap03> Subject: Re: [v6,1/3] dt-binding: reset-controller: mediatek: add YAML schemas From: Crystal Guo To: "p.zabel@pengutronix.de" , "robh+dt@kernel.org" , "matthias.bgg@gmail.com" CC: srv_heupstream , "linux-mediatek@lists.infradead.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "s-anna@ti.com" , Seiya Wang =?UTF-8?Q?=28=E7=8E=8B=E8=BF=BA=E5=90=9B=29?= , Stanley Chu =?UTF-8?Q?=28=E6=9C=B1=E5=8E=9F=E9=99=9E=29?= , Yingjoe Chen =?UTF-8?Q?=28=E9=99=B3=E8=8B=B1=E6=B4=B2=29?= , Fan Chen =?UTF-8?Q?=28=E9=99=B3=E5=87=A1=29?= , "Yong Liang =?UTF-8?Q?=28=E6=A2=81=E5=8B=87=29?=" Date: Wed, 14 Oct 2020 21:30:04 +0800 In-Reply-To: <20200930022159.5559-2-crystal.guo@mediatek.com> References: <20200930022159.5559-1-crystal.guo@mediatek.com> <20200930022159.5559-2-crystal.guo@mediatek.com> Content-Type: text/plain; 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Wed, 14 Oct 2020 21:30:04 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 14 Oct 2020 21:30:03 +0800 Message-ID: <1602682204.14806.53.camel@mhfsdcap03> Subject: Re: [v6,1/3] dt-binding: reset-controller: mediatek: add YAML schemas From: Crystal Guo To: "p.zabel@pengutronix.de" , "robh+dt@kernel.org" , "matthias.bgg@gmail.com" Date: Wed, 14 Oct 2020 21:30:04 +0800 In-Reply-To: <20200930022159.5559-2-crystal.guo@mediatek.com> References: <20200930022159.5559-1-crystal.guo@mediatek.com> <20200930022159.5559-2-crystal.guo@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 41791D005C9335D5F39C2B4293C82C0E7193625AFD810F4D058E601C57B8D2622000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201014_093015_928190_C16134D1 X-CRM114-Status: GOOD ( 16.68 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "devicetree@vger.kernel.org" , Yong Liang =?UTF-8?Q?=28=E6=A2=81=E5=8B=87=29?= , Stanley Chu =?UTF-8?Q?=28=E6=9C=B1=E5=8E=9F=E9=99=9E=29?= , srv_heupstream , Seiya Wang =?UTF-8?Q?=28=E7=8E=8B=E8=BF=BA=E5=90=9B=29?= , "linux-kernel@vger.kernel.org" , Fan Chen =?UTF-8?Q?=28=E9=99=B3=E5=87=A1=29?= , "linux-mediatek@lists.infradead.org" , Yingjoe Chen =?UTF-8?Q?=28=E9=99=B3=E8=8B=B1=E6=B4=B2=29?= , "s-anna@ti.com" , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Hi Maintainers, Gentle ping for this patch set. Many thanks Crystal On Wed, 2020-09-30 at 10:21 +0800, Crystal Guo wrote: > Add a YAML documentation for Mediatek, which uses ti reset-controller > driver directly. The TI reset controller provides a common reset > management, and is suitable for Mediatek SoCs. > > Signed-off-by: Crystal Guo > --- > .../bindings/reset/mediatek-syscon-reset.yaml | 51 +++++++++++++++++++ > 1 file changed, 51 insertions(+) > create mode 100644 Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml > > diff --git a/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml > new file mode 100644 > index 000000000000..7871550c3c69 > --- /dev/null > +++ b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml > @@ -0,0 +1,51 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/reset/mediatek-syscon-reset.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Mediatek Reset Controller > + > +maintainers: > + - Crystal Guo > + > +description: > + The bindings describe the reset-controller for Mediatek SoCs, > + which is based on TI reset controller. For more detail, please > + visit Documentation/devicetree/bindings/reset/ti-syscon-reset.txt. > + > +properties: > + compatible: > + const: mediatek,syscon-reset > + > + '#reset-cells': > + const: 1 > + > + mediatek,reset-bits: > + description: > > + Contains the reset control register information, please refer to > + Documentation/devicetree/bindings/reset/ti-syscon-reset.txt. > + > +required: > + - compatible > + - '#reset-cells' > + - mediatek,reset-bits > + > +additionalProperties: false > + > +examples: > + - | > + #include > + infracfg: infracfg@10001000 { > + compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd"; > + reg = <0 0x10001000>; > + #clock-cells = <1>; > + > + infracfg_rst: reset-controller { > + compatible = "mediatek,syscon-reset"; > + #reset-cells = <1>; > + mediatek,reset-bits = < > + 0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) > + >; > + }; > + }; _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64354C433DF for ; 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Wed, 14 Oct 2020 21:30:04 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 14 Oct 2020 21:30:03 +0800 Message-ID: <1602682204.14806.53.camel@mhfsdcap03> Subject: Re: [v6,1/3] dt-binding: reset-controller: mediatek: add YAML schemas From: Crystal Guo To: "p.zabel@pengutronix.de" , "robh+dt@kernel.org" , "matthias.bgg@gmail.com" Date: Wed, 14 Oct 2020 21:30:04 +0800 In-Reply-To: <20200930022159.5559-2-crystal.guo@mediatek.com> References: <20200930022159.5559-1-crystal.guo@mediatek.com> <20200930022159.5559-2-crystal.guo@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 41791D005C9335D5F39C2B4293C82C0E7193625AFD810F4D058E601C57B8D2622000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201014_093015_928190_C16134D1 X-CRM114-Status: GOOD ( 16.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "devicetree@vger.kernel.org" , Yong Liang =?UTF-8?Q?=28=E6=A2=81=E5=8B=87=29?= , Stanley Chu =?UTF-8?Q?=28=E6=9C=B1=E5=8E=9F=E9=99=9E=29?= , srv_heupstream , Seiya Wang =?UTF-8?Q?=28=E7=8E=8B=E8=BF=BA=E5=90=9B=29?= , "linux-kernel@vger.kernel.org" , Fan Chen =?UTF-8?Q?=28=E9=99=B3=E5=87=A1=29?= , "linux-mediatek@lists.infradead.org" , Yingjoe Chen =?UTF-8?Q?=28=E9=99=B3=E8=8B=B1=E6=B4=B2=29?= , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Maintainers, Gentle ping for this patch set. Many thanks Crystal On Wed, 2020-09-30 at 10:21 +0800, Crystal Guo wrote: > Add a YAML documentation for Mediatek, which uses ti reset-controller > driver directly. The TI reset controller provides a common reset > management, and is suitable for Mediatek SoCs. > > Signed-off-by: Crystal Guo > --- > .../bindings/reset/mediatek-syscon-reset.yaml | 51 +++++++++++++++++++ > 1 file changed, 51 insertions(+) > create mode 100644 Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml > > diff --git a/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml > new file mode 100644 > index 000000000000..7871550c3c69 > --- /dev/null > +++ b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml > @@ -0,0 +1,51 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/reset/mediatek-syscon-reset.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Mediatek Reset Controller > + > +maintainers: > + - Crystal Guo > + > +description: > + The bindings describe the reset-controller for Mediatek SoCs, > + which is based on TI reset controller. For more detail, please > + visit Documentation/devicetree/bindings/reset/ti-syscon-reset.txt. > + > +properties: > + compatible: > + const: mediatek,syscon-reset > + > + '#reset-cells': > + const: 1 > + > + mediatek,reset-bits: > + description: > > + Contains the reset control register information, please refer to > + Documentation/devicetree/bindings/reset/ti-syscon-reset.txt. > + > +required: > + - compatible > + - '#reset-cells' > + - mediatek,reset-bits > + > +additionalProperties: false > + > +examples: > + - | > + #include > + infracfg: infracfg@10001000 { > + compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd"; > + reg = <0 0x10001000>; > + #clock-cells = <1>; > + > + infracfg_rst: reset-controller { > + compatible = "mediatek,syscon-reset"; > + #reset-cells = <1>; > + mediatek,reset-bits = < > + 0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) > + >; > + }; > + }; _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel