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Fri, 16 Oct 2020 07:39:46 +0000 From: Sanjay R Mehta To: vkoul@kernel.org Cc: gregkh@linuxfoundation.org, dan.j.williams@intel.com, Thomas.Lendacky@amd.com, Shyam-sundar.S-k@amd.com, Nehal-bakulchandra.Shah@amd.com, robh@kernel.org, mchehab+samsung@kernel.org, davem@davemloft.net, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, Sanjay R Mehta Subject: [PATCH v7 0/3] Add support for AMD PTDMA controller driver Date: Fri, 16 Oct 2020 02:39:04 -0500 Message-Id: <1602833947-82021-1-git-send-email-Sanju.Mehta@amd.com> X-Mailer: git-send-email 2.7.4 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit X-Originating-IP: [165.204.156.251] X-ClientProxiedBy: MAXPR01CA0101.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:5d::19) To BN8PR12MB3540.namprd12.prod.outlook.com (2603:10b6:408:6c::33) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sanjuamdntb2.amd.com (165.204.156.251) by MAXPR01CA0101.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:5d::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3477.21 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: 8nxfA8UwMopAAwCFrhYQJzAgZsv0yku1fZNBFngWrLXE5AHPVpny9zIIxrCI8RdjyvD6jQ1oG/wpHdT12oY82wfjwNv47atSLOToJKlfycxWpIUbQ5w+3UKlm8ygBy7/gSDM5CuPfjnwCnhcAVXf+PkPonYS1XQtOu5NEu7KjxMXP1TeKanASK+HZznoE8IPQgec+bdRkxML9mgbkYD2hK4kuWyTz8bvgyH1V2CycAl8CSalX1iOdxOHW5ohLOLEyeHl2ot0V9f2d/Q86yNJEzbTLdNa0n7RArujr9CY22MKeSQbEtYTIDGEJ4RwI1GFZJYaox5SUvB1/+Qmjbc7HJgMwzc5oKRw3X5sNqfH3PiG+jNznpDwOCa4af0SxDgg4G7v7jTRaUOs7DjfHcnyFmwtAXsJf7j7X2cbinOwTJdOfyFOiq8F051vbTPF7+JAJ9ArNnRwn0qep2s+cCoAFKT+SdGQTpj8OxkorycBFQGIgvxgyuM+cdj3DVuZFmDWyXqs/ALGnd4gVf0bL+fTbmHyUwQO0UH2t2ktYT3XfgwTJ4crbl79dM26KySiENkhWpRxN2P+BffE8B5q5zeMeCTg9eSQ5TSsax9q0FCzAmCI1iWRmkx4Pe+MCUziGtOt5WPIT6QwpLnBkbkJBKiOfw== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2ffaf3c3-ac54-4749-14e0-08d871a6a746 X-MS-Exchange-CrossTenant-AuthSource: BN8PR12MB3540.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2020 07:39:46.2280 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 96sAjkjz5ZpzXoFN9WwqtLBTw+cXbVsaVHtdEZubQXpiY/OwZXTSL3j8yLBfxlImBqDCCwqUx22lETCm8QL/nQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR1201MB0212 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org From: Sanjay R Mehta This patch series adds support for AMD PTDMA controller which performs high bandwidth memory-to-memory and IO copy operation, performs DMA transfer through queue based descriptor management. AMD Processor has multiple ptdma device instances with each controller having single queue. The driver also adds support for for multiple PTDMA instances, each device will get an unique identifier and uniquely named resources. v7: - Fixed module warnings reported ( by kernel test robot ). v6: - Removed debug artifacts and made the suggested cosmetic changes. - implemented and used to_pt_chan and to_pt_desc inline functions. - Removed src and dst address check as framework does this. - Removed devm_kcalloc() usage and used devm_kzalloc() api. - Using framework debugfs directory to store dma info. v5: - modified code to submit next tranction in ISR itself and removed the tasklet. - implemented .device_synchronize API. - converted debugfs code by using DEFINE_SHOW_ATTRIBUTE() - using dbg_dev_root for debugfs root directory. - removed dma_status from pt_dma_chan - removed module parameter cmd_queue_lenght. - removed global device list for multiple devics. - removed code related to dynamic adding/deleting to device list - removed pt_add_device and pt_del_device functions v4: - modified DMA channel and descriptor management using virt-dma layer instead of list based management. - return only status of the cookie from pt_tx_status - copyright year changed from 2019 to 2020 - removed dummy code for suspend & resume - used bitmask and genmask v3: - Fixed the sparse warnings. v2: - Added controller description in cover letter - Removed "default m" from Kconfig - Replaced low_address() and high_address() functions with kernel API's lower_32_bits & upper_32_bits(). - Removed the BH handler function pt_core_irq_bh() and instead handling transaction in irq handler itself. - Moved presetting of command queue registers into new function "init_cmdq_regs()" - Removed the kernel thread dependency to submit transaction. - Increased the hardware command queue size to 32 and adding it as a module parameter. - Removed backlog command queue handling mechanism. - Removed software command queue handling and instead submitting transaction command directly to hardware command queue. - Added tasklet structure variable in "struct pt_device". This is used to invoke pt_do_cmd_complete() upon receiving interrupt for command completion. - pt_core_perform_passthru() function parameters are modified and it is now used to submit command directly to hardware from dmaengine framew - Removed below structures, enums, macros and functions, as these value constants. Making command submission simple, - Removed "union pt_function" and several macros like PT_VERSION, PT_BYTESWAP, PT_CMD_* etc.. - enum pt_passthru_bitwise, enum pt_passthru_byteswap, enum pt_memty struct pt_dma_info, struct pt_data, struct pt_mem, struct pt_passt struct pt_op, Links of the review comments for v5: 1. https://lkml.org/lkml/2020/7/3/154 2. https://lkml.org/lkml/2020/8/25/431 3. https://lkml.org/lkml/2020/7/3/177 4. https://lkml.org/lkml/2020/7/3/186 Links of the review comments for v5: 1. https://lkml.org/lkml/2020/5/4/42 2. https://lkml.org/lkml/2020/5/4/45 3. https://lkml.org/lkml/2020/5/4/38 4. https://lkml.org/lkml/2020/5/26/70 Links of the review comments for v4: 1. https://lkml.org/lkml/2020/1/24/12 2. https://lkml.org/lkml/2020/1/24/17 Links of the review comments for v2: 1https://lkml.org/lkml/2019/12/27/630 2. https://lkml.org/lkml/2020/1/3/23 3. https://lkml.org/lkml/2020/1/3/314 4. https://lkml.org/lkml/2020/1/10/100 Links of the review comments for v1: 1. https://lkml.org/lkml/2019/9/24/490 2. https://lkml.org/lkml/2019/9/24/399 3. https://lkml.org/lkml/2019/9/24/862 4. https://lkml.org/lkml/2019/9/24/122 Sanjay R Mehta (3): dmaengine: ptdma: Initial driver for the AMD PTDMA dmaengine: ptdma: register PTDMA controller as a DMA resource dmaengine: ptdma: Add debugfs entries for PTDMA information MAINTAINERS | 6 + drivers/dma/Kconfig | 2 + drivers/dma/Makefile | 1 + drivers/dma/ptdma/Kconfig | 13 + drivers/dma/ptdma/Makefile | 10 + drivers/dma/ptdma/ptdma-debugfs.c | 115 ++++++++ drivers/dma/ptdma/ptdma-dev.c | 333 ++++++++++++++++++++++ drivers/dma/ptdma/ptdma-dmaengine.c | 554 ++++++++++++++++++++++++++++++++++++ drivers/dma/ptdma/ptdma-pci.c | 252 ++++++++++++++++ drivers/dma/ptdma/ptdma.h | 352 +++++++++++++++++++++++ 10 files changed, 1638 insertions(+) create mode 100644 drivers/dma/ptdma/Kconfig create mode 100644 drivers/dma/ptdma/Makefile create mode 100644 drivers/dma/ptdma/ptdma-debugfs.c create mode 100644 drivers/dma/ptdma/ptdma-dev.c create mode 100644 drivers/dma/ptdma/ptdma-dmaengine.c create mode 100644 drivers/dma/ptdma/ptdma-pci.c create mode 100644 drivers/dma/ptdma/ptdma.h -- 2.7.4