From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E71C9C2D0A3 for ; Sat, 17 Oct 2020 19:03:43 +0000 (UTC) Received: from dpdk.org (dpdk.org [92.243.14.124]) by mail.kernel.org (Postfix) with ESMTP id 513612073A for ; Sat, 17 Oct 2020 19:03:43 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 513612073A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=dev-bounces@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 894D8CA54; Sat, 17 Oct 2020 21:02:29 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id B656CA90A for ; Sat, 17 Oct 2020 21:02:22 +0200 (CEST) IronPort-SDR: AZcXsTVoHyAVjb/wT/7v84I8I3b/ePmgpS+LQcuQSVFE1NJHRUHDMLIBrhbTxaY+xqVXnGxrzO HTjz5ERk+juw== X-IronPort-AV: E=McAfee;i="6000,8403,9777"; a="166946640" X-IronPort-AV: E=Sophos;i="5.77,387,1596524400"; d="scan'208";a="166946640" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Oct 2020 12:02:20 -0700 IronPort-SDR: TeM62RGMsSllpuSw+g0vUwSxNQW6xgayA4qahPlb93OKXjKna7nTTkn+sw7LuePk8coAhcw0CL tsyi9opUyxuw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,387,1596524400"; d="scan'208";a="532137369" Received: from txasoft-yocto.an.intel.com ([10.123.72.192]) by orsmga005.jf.intel.com with ESMTP; 17 Oct 2020 12:02:19 -0700 From: Timothy McDaniel To: Cc: dev@dpdk.org, erik.g.carrillo@intel.com, gage.eads@intel.com, harry.van.haaren@intel.com, jerinj@marvell.com Date: Sat, 17 Oct 2020 14:03:59 -0500 Message-Id: <1602961456-17392-6-git-send-email-timothy.mcdaniel@intel.com> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1602961456-17392-1-git-send-email-timothy.mcdaniel@intel.com> References: <1596138614-17409-2-git-send-email-timothy.mcdaniel@intel.com> <1602961456-17392-1-git-send-email-timothy.mcdaniel@intel.com> Subject: [dpdk-dev] [PATCH v5 05/22] event/dlb: add inline functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add miscellaneous inline functions that may be called from multiple files. These functions include inline assembly of new x86 instructions, such as movdir64b, since they are not available as builtin functions in the minimum supported GCC version. Signed-off-by: Timothy McDaniel Reviewed-by: Gage Eads --- drivers/event/dlb/dlb_inline_fns.h | 79 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 drivers/event/dlb/dlb_inline_fns.h diff --git a/drivers/event/dlb/dlb_inline_fns.h b/drivers/event/dlb/dlb_inline_fns.h new file mode 100644 index 0000000..1aa5449 --- /dev/null +++ b/drivers/event/dlb/dlb_inline_fns.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2016-2020 Intel Corporation + */ + +#include "rte_memcpy.h" +#include "rte_io.h" + +/* Inline functions required in more than one source file. */ + +static inline struct dlb_eventdev * +dlb_pmd_priv(const struct rte_eventdev *eventdev) +{ + return eventdev->data->dev_private; +} + +static inline void +dlb_umonitor(volatile void *addr) +{ + asm volatile(".byte 0xf3, 0x0f, 0xae, 0xf7\t\n" + : + : "D" (addr)); +} + +static inline void +dlb_umwait(int state, uint64_t timeout) +{ + uint32_t eax = timeout & UINT32_MAX; + uint32_t edx = timeout >> 32; + + asm volatile(".byte 0xf2, 0x0f, 0xae, 0xf7\t\n" + : + : "D" (state), "a" (eax), "d" (edx)); +} + +static inline void +dlb_movntdq(void *dest, void *src) +{ + /* Move entire 64B cache line of QEs, 128 bits (16B) at a time. */ + long long *_src = (long long *)src; + __v2di src_data0 = (__v2di){_src[0], _src[1]}; + __v2di src_data1 = (__v2di){_src[2], _src[3]}; + __v2di src_data2 = (__v2di){_src[4], _src[5]}; + __v2di src_data3 = (__v2di){_src[6], _src[7]}; + + __builtin_ia32_movntdq((__v2di *)dest + 0, (__v2di)src_data0); + rte_wmb(); + __builtin_ia32_movntdq((__v2di *)dest + 1, (__v2di)src_data1); + rte_wmb(); + __builtin_ia32_movntdq((__v2di *)dest + 2, (__v2di)src_data2); + rte_wmb(); + __builtin_ia32_movntdq((__v2di *)dest + 3, (__v2di)src_data3); + rte_wmb(); +} + +static inline void +dlb_movntdq_single(void *dest, void *src) +{ + long long *_src = (long long *)src; + __v2di src_data0 = (__v2di){_src[0], _src[1]}; + + __builtin_ia32_movntdq((__v2di *)dest, (__v2di)src_data0); +} + +static inline void +dlb_cldemote(void *addr) +{ + /* Load addr into RSI, then demote the cache line of the address + * contained in that register. + */ + asm volatile(".byte 0x0f, 0x1c, 0x06" :: "S" (addr)); +} + +static inline void +dlb_movdir64b(void *dest, void *src) +{ + asm volatile(".byte 0x66, 0x0f, 0x38, 0xf8, 0x02" + : + : "a" (dest), "d" (src)); +} -- 2.6.4