From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.3 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0264CC56201 for ; Tue, 27 Oct 2020 08:06:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 597B121D24 for ; Tue, 27 Oct 2020 08:06:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="kkXTjUIK" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2508731AbgJ0IEs (ORCPT ); Tue, 27 Oct 2020 04:04:48 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:41693 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2508690AbgJ0IDs (ORCPT ); Tue, 27 Oct 2020 04:03:48 -0400 X-UUID: 171b9c2476154cc28e2145d477d9573f-20201027 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=JyBsc+Y4sIJPtk0rE227nArOS2YDqslqxM8kl64ZCIc=; b=kkXTjUIK0rGUK7P6ezJ+4KrgcWlLSccGSZ/OPX+QQxrrPcexsxKzt5zM8PzvvslSsP50fJyLfIK3WC003Yp+8h66D9fspD8Lu+UykEDCRM0sPTqB+IkEoN359mrr9dxHDaz3G4B+GcVNIuEJxxpaM8gY+5awywmDT+aKmUaO5kQ=; X-UUID: 171b9c2476154cc28e2145d477d9573f-20201027 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1402063274; Tue, 27 Oct 2020 16:03:45 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 27 Oct 2020 16:03:43 +0800 Received: from [172.21.77.33] (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 27 Oct 2020 16:03:43 +0800 Message-ID: <1603785824.12492.11.camel@mtkswgap22> Subject: Re: [PATCH v2 2/4] arm: mm: reordering memory type table From: Miles Chen To: Russell King - ARM Linux admin CC: Catalin Marinas , Minchan Kim , , , , , Will Deacon , Steve Capper , Simon Horman , "Suren Baghdasaryan" Date: Tue, 27 Oct 2020 16:03:44 +0800 In-Reply-To: <20201023101640.GA1551@shell.armlinux.org.uk> References: <20201023091437.8225-1-miles.chen@mediatek.com> <20201023091437.8225-3-miles.chen@mediatek.com> <20201023101640.GA1551@shell.armlinux.org.uk> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 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merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kXJxT-0007Hu-Mc; Tue, 27 Oct 2020 08:03:57 +0000 X-UUID: df790220eafc403ca9cefce440529bb1-20201027 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=JyBsc+Y4sIJPtk0rE227nArOS2YDqslqxM8kl64ZCIc=; b=kkXTjUIK0rGUK7P6ezJ+4KrgcWlLSccGSZ/OPX+QQxrrPcexsxKzt5zM8PzvvslSsP50fJyLfIK3WC003Yp+8h66D9fspD8Lu+UykEDCRM0sPTqB+IkEoN359mrr9dxHDaz3G4B+GcVNIuEJxxpaM8gY+5awywmDT+aKmUaO5kQ=; X-UUID: df790220eafc403ca9cefce440529bb1-20201027 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2060379035; Tue, 27 Oct 2020 00:03:53 -0800 Received: from MTKMBS01N1.mediatek.inc (172.21.101.68) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 27 Oct 2020 01:03:51 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 27 Oct 2020 16:03:43 +0800 Received: from [172.21.77.33] (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 27 Oct 2020 16:03:43 +0800 Message-ID: <1603785824.12492.11.camel@mtkswgap22> Subject: Re: [PATCH v2 2/4] arm: mm: reordering memory type table From: Miles Chen To: Russell King - ARM Linux admin Date: Tue, 27 Oct 2020 16:03:44 +0800 In-Reply-To: <20201023101640.GA1551@shell.armlinux.org.uk> References: <20201023091437.8225-1-miles.chen@mediatek.com> <20201023091437.8225-3-miles.chen@mediatek.com> <20201023101640.GA1551@shell.armlinux.org.uk> X-Mailer: Evolution 3.2.3-0ubuntu6 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201027_040356_014961_2F5E2765 X-CRM114-Status: GOOD ( 30.18 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Steve Capper , wsd_upstream@mediatek.com, Catalin Marinas , Will Deacon , linux-kernel@vger.kernel.org, Minchan Kim , Simon Horman , linux-mediatek@lists.infradead.org, Suren Baghdasaryan , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Fri, 2020-10-23 at 11:16 +0100, Russell King - ARM Linux admin wrote: > On Fri, Oct 23, 2020 at 05:14:35PM +0800, Miles Chen wrote: > > From: Minchan Kim > > > > To use bit 5 in page table as L_PTE_SPECIAL, we need a room for that. > > It seems we don't need 4 bits for the memory type with ARMv6+. > > If it's true, let's reorder bits to make bit 5 free. > > > > We will use the bit for L_PTE_SPECIAL in next patch. > > > > A note from Catalin in [1]: > > " > > > Anyway, on ARMv7 or ARMv6+LPAE, the non-shared device gets mapped to > > > shared device in hardware. Looking through the arm32 code, it seems that > > > MT_DEVICE_NONSHARED is used by arch/arm/mach-shmobile/setup-r8a7779.c > > > and IIUC that's a v7 platform (R-Car H1, Cortex-A9). I think the above > > > should be defined to L_PTE_MT_DEV_SHARED, unless I miss any place where > > > DEV_NONSHARED is relevant on ARMv6 (adding Simon to confirm on shmbile). > > " > > > > [1] https://lore.kernel.org/patchwork/patch/986574/ > > > > Cc: Russell King > > Cc: Catalin Marinas > > Cc: Will Deacon > > Cc: Steve Capper > > Cc: Simon Horman > > Cc: Minchan Kim > > Cc: Suren Baghdasaryan > > Signed-off-by: Minchan Kim > > Signed-off-by: Miles Chen > > --- > > arch/arm/include/asm/pgtable-2level.h | 21 +++++++++++++++++---- > > arch/arm/mm/proc-macros.S | 4 ++-- > > 2 files changed, 19 insertions(+), 6 deletions(-) > > > > diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h > > index 27a8635abea0..cdcd55cca37d 100644 > > --- a/arch/arm/include/asm/pgtable-2level.h > > +++ b/arch/arm/include/asm/pgtable-2level.h > > @@ -161,14 +161,27 @@ > > #define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 0x01) << 2) /* 0001 */ > > #define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 0x02) << 2) /* 0010 */ > > #define L_PTE_MT_WRITEBACK (_AT(pteval_t, 0x03) << 2) /* 0011 */ > > +#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */ > > +#define L_PTE_MT_VECTORS (_AT(pteval_t, 0x05) << 2) /* 0101 */ > > #define L_PTE_MT_MINICACHE (_AT(pteval_t, 0x06) << 2) /* 0110 (sa1100, xscale) */ > > #define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 0x07) << 2) /* 0111 */ > > -#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */ > > -#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */ > > Sorry, no, this isn't going to work. > > The lower two bits of this (bits 2 and 3) are explicitly designed to fit > the C and B bits used in older architectures. Changing L_PTE_MT_VECTORS > from having value '11' to '01' changes the functionality on older CPUs. > thanks for the comment. Is is possible to find other order to fit this? e.g., +#define L_PTE_MT_VECTORS (_AT(pteval_t, 0x07) << 2) /* 0111 */ #define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 0x05) << 2) /* 0101 */ or only allow this types for the new CPUs? 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Tue, 27 Oct 2020 16:03:43 +0800 Message-ID: <1603785824.12492.11.camel@mtkswgap22> Subject: Re: [PATCH v2 2/4] arm: mm: reordering memory type table From: Miles Chen To: Russell King - ARM Linux admin Date: Tue, 27 Oct 2020 16:03:44 +0800 In-Reply-To: <20201023101640.GA1551@shell.armlinux.org.uk> References: <20201023091437.8225-1-miles.chen@mediatek.com> <20201023091437.8225-3-miles.chen@mediatek.com> <20201023101640.GA1551@shell.armlinux.org.uk> X-Mailer: Evolution 3.2.3-0ubuntu6 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201027_040356_014961_2F5E2765 X-CRM114-Status: GOOD ( 30.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Steve Capper , wsd_upstream@mediatek.com, Catalin Marinas , Will Deacon , linux-kernel@vger.kernel.org, Minchan Kim , Simon Horman , linux-mediatek@lists.infradead.org, Suren Baghdasaryan , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 2020-10-23 at 11:16 +0100, Russell King - ARM Linux admin wrote: > On Fri, Oct 23, 2020 at 05:14:35PM +0800, Miles Chen wrote: > > From: Minchan Kim > > > > To use bit 5 in page table as L_PTE_SPECIAL, we need a room for that. > > It seems we don't need 4 bits for the memory type with ARMv6+. > > If it's true, let's reorder bits to make bit 5 free. > > > > We will use the bit for L_PTE_SPECIAL in next patch. > > > > A note from Catalin in [1]: > > " > > > Anyway, on ARMv7 or ARMv6+LPAE, the non-shared device gets mapped to > > > shared device in hardware. Looking through the arm32 code, it seems that > > > MT_DEVICE_NONSHARED is used by arch/arm/mach-shmobile/setup-r8a7779.c > > > and IIUC that's a v7 platform (R-Car H1, Cortex-A9). I think the above > > > should be defined to L_PTE_MT_DEV_SHARED, unless I miss any place where > > > DEV_NONSHARED is relevant on ARMv6 (adding Simon to confirm on shmbile). > > " > > > > [1] https://lore.kernel.org/patchwork/patch/986574/ > > > > Cc: Russell King > > Cc: Catalin Marinas > > Cc: Will Deacon > > Cc: Steve Capper > > Cc: Simon Horman > > Cc: Minchan Kim > > Cc: Suren Baghdasaryan > > Signed-off-by: Minchan Kim > > Signed-off-by: Miles Chen > > --- > > arch/arm/include/asm/pgtable-2level.h | 21 +++++++++++++++++---- > > arch/arm/mm/proc-macros.S | 4 ++-- > > 2 files changed, 19 insertions(+), 6 deletions(-) > > > > diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h > > index 27a8635abea0..cdcd55cca37d 100644 > > --- a/arch/arm/include/asm/pgtable-2level.h > > +++ b/arch/arm/include/asm/pgtable-2level.h > > @@ -161,14 +161,27 @@ > > #define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 0x01) << 2) /* 0001 */ > > #define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 0x02) << 2) /* 0010 */ > > #define L_PTE_MT_WRITEBACK (_AT(pteval_t, 0x03) << 2) /* 0011 */ > > +#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */ > > +#define L_PTE_MT_VECTORS (_AT(pteval_t, 0x05) << 2) /* 0101 */ > > #define L_PTE_MT_MINICACHE (_AT(pteval_t, 0x06) << 2) /* 0110 (sa1100, xscale) */ > > #define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 0x07) << 2) /* 0111 */ > > -#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */ > > -#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */ > > Sorry, no, this isn't going to work. > > The lower two bits of this (bits 2 and 3) are explicitly designed to fit > the C and B bits used in older architectures. Changing L_PTE_MT_VECTORS > from having value '11' to '01' changes the functionality on older CPUs. > thanks for the comment. Is is possible to find other order to fit this? e.g., +#define L_PTE_MT_VECTORS (_AT(pteval_t, 0x07) << 2) /* 0111 */ #define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 0x05) << 2) /* 0101 */ or only allow this types for the new CPUs? Miles _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel