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Date: Wed, 11 Nov 2020 14:49:47 +1000
From: Nicholas Piggin <npiggin@gmail.com>
Subject: Re: [RFC PATCH 0/9] powerpc/64s: fast interrupt exit
To: Christophe Leroy <christophe.leroy@csgroup.eu>,
 linuxppc-dev@lists.ozlabs.org
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Excerpts from Christophe Leroy's message of November 10, 2020 9:31 pm:
>=20
>=20
> Le 10/11/2020 =C3=A0 09:49, Nicholas Piggin a =C3=A9crit=C2=A0:
>> Excerpts from Christophe Leroy's message of November 7, 2020 8:35 pm:
>>>
>>>
>>> Le 06/11/2020 =C3=A0 16:59, Nicholas Piggin a =C3=A9crit=C2=A0:
>>>> This series attempts to improve the speed of interrupts and system cal=
ls
>>>> in two major ways.
>>>>
>>>> Firstly, the SRR/HSRR registers do not need to be reloaded if they wer=
e
>>>> not used or clobbered fur the duration of the interrupt.
>>>>
>>>> Secondly, an alternate return location facility is added for soft-mask=
ed
>>>> asynchronous interrupts and then that's used to set everything up for
>>>> return without having to disable MSR RI or EE.
>>>>
>>>> After this series, the entire system call / interrupt handler fast pat=
h
>>>> executes no mtsprs and one mtmsrd to enable interrupts initially, and
>>>> the system call vectored path doesn't even need to do that.
>>>
>>> Interesting series.
>>>
>>> Unfortunately, can't be done on PPC32 (at least on non bookE), because =
it would mean mapping kernel
>>> at 0 instead of 0xC0000000. Not sure libc would like it, and anyway it =
would be an issue for
>>> catching NULL pointer dereferencing, unless we use page tables instead =
of BATs to map kernel mem,
>>> which would be serious performance cut.
>>=20
>> Hmm, why would you have to map at 0?
>=20
> In real mode, physical mem is at 0. If we want to switch from real to vir=
tual mode by just writing=20
> to MSR, then we need virtuel addresses match with real addresses ?

Ah that's what I missed.

64s real mode masks out the top 2 bits of the address which is how that=20
works. But I don't usually think about that path anyway because most
iterrupts arrive with MMU on.

> We could play with chip selects to put RAM at 0xc0000000, but then we'd h=
ave a problem with=20
> exception as they have to be at 0. Or we could play with MSR[IP] and get =
the exceptions at=20
> 0xfff00000, but that would not be so easy I guess.
>=20
>>=20
>> PPC32 doesn't have soft mask interrupts, but you could still test all
>> MSR[PR]=3D0 interrupts to see if they land inside some region to see if
>> they hit in the restart table I think?
>=20
> Yes and this is already what is done at exit for the ones that handle MSR=
[RI] I think.

Interesting, I'll have to check that out.

>>=20
>> Could PPC32 skip the SRR reload at least? That's simpler.
>=20
> I think that would only be possible if real addresses where matching virt=
ual addresses, or am I=20
> missing something ?

No you're right, I was missing something.

Thanks,
Nick