From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.2 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F1AFC433FE for ; Tue, 8 Dec 2020 02:01:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 01247238E9 for ; Tue, 8 Dec 2020 02:01:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727702AbgLHCBX (ORCPT ); Mon, 7 Dec 2020 21:01:23 -0500 Received: from Mailgw01.mediatek.com ([1.203.163.78]:51429 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725877AbgLHCBX (ORCPT ); Mon, 7 Dec 2020 21:01:23 -0500 X-UUID: 8a664c262b164f2bb78d63554f53e19a-20201208 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=AnfMsxCsqIaWPXAofU2Qh3nt/yEpA1Nncyh3grmr2Hs=; b=a2h/GOb3tMmj4tVWWW0Z8TUR3FBZ3HuPCXErjJgQio5LqJUJMEZR1tVd2u1BuMDPlmDLv2O+NDJZ8PcqVt24FAPKEqv1uNg6UFJa56TTUYvo2315Fqbm9h8UgU9F6hHw+HODvloC9Xj/ab+g8IgGqFF1/2dzNy25Nb0tHM+TMbc=; X-UUID: 8a664c262b164f2bb78d63554f53e19a-20201208 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1168966895; Tue, 08 Dec 2020 10:00:35 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS31DR.mediatek.inc (172.27.6.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 8 Dec 2020 10:00:23 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 8 Dec 2020 10:00:26 +0800 Message-ID: <1607392825.23328.5.camel@mhfsdcap03> Subject: Re: [PATCH v3 07/11] dt-bindings: phy: convert MIP DSI PHY binding to YAML schema From: Chunfeng Yun To: Rob Herring CC: Serge Semin , Chun-Kuang Hu , Philipp Zabel , "David Airlie" , Daniel Vetter , "David S . Miller" , Jakub Kicinski , "Kishon Vijay Abraham I" , Vinod Koul , "Matthias Brugger" , Greg Kroah-Hartman , Stanley Chu , "Min Guo" , , , , , , , Date: Tue, 8 Dec 2020 10:00:25 +0800 In-Reply-To: <20201207211920.GA841059@robh.at.kernel.org> References: <20201118082126.42701-1-chunfeng.yun@mediatek.com> <20201118082126.42701-7-chunfeng.yun@mediatek.com> <20201207211920.GA841059@robh.at.kernel.org> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: BA25879DABC571C822341F4AC2ABA120CA9AACE0D97F7DEA60AC1AC6A1D432792000:8 X-MTK: N Content-Transfer-Encoding: base64 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org T24gTW9uLCAyMDIwLTEyLTA3IGF0IDE1OjE5IC0wNjAwLCBSb2IgSGVycmluZyB3cm90ZToNCj4g T24gV2VkLCBOb3YgMTgsIDIwMjAgYXQgMDQ6MjE6MjJQTSArMDgwMCwgQ2h1bmZlbmcgWXVuIHdy b3RlOg0KPiA+IENvbnZlcnQgTUlQSSBEU0kgUEhZIGJpbmRpbmcgdG8gWUFNTCBzY2hlbWEgbWVk aWF0ZWssZHNpLXBoeS55YW1sDQo+ID4gDQo+ID4gQ2M6IENodW4tS3VhbmcgSHUgPGNodW5rdWFu Zy5odUBrZXJuZWwub3JnPg0KPiA+IFNpZ25lZC1vZmYtYnk6IENodW5mZW5nIFl1biA8Y2h1bmZl bmcueXVuQG1lZGlhdGVrLmNvbT4NCj4gPiAtLS0NCj4gPiB2MzogbmV3IHBhdGNoDQo+ID4gLS0t DQo+ID4gIC4uLi9kaXNwbGF5L21lZGlhdGVrL21lZGlhdGVrLGRzaS50eHQgICAgICAgICB8IDE4 ICstLS0NCj4gPiAgLi4uL2JpbmRpbmdzL3BoeS9tZWRpYXRlayxkc2ktcGh5LnlhbWwgICAgICAg IHwgODMgKysrKysrKysrKysrKysrKysrKw0KPiA+ICAyIGZpbGVzIGNoYW5nZWQsIDg0IGluc2Vy dGlvbnMoKyksIDE3IGRlbGV0aW9ucygtKQ0KPiA+ICBjcmVhdGUgbW9kZSAxMDA2NDQgRG9jdW1l bnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL3BoeS9tZWRpYXRlayxkc2ktcGh5LnlhbWwNCj4g PiANCj4gPiBkaWZmIC0tZ2l0IGEvRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL2Rp c3BsYXkvbWVkaWF0ZWsvbWVkaWF0ZWssZHNpLnR4dCBiL0RvY3VtZW50YXRpb24vZGV2aWNldHJl ZS9iaW5kaW5ncy9kaXNwbGF5L21lZGlhdGVrL21lZGlhdGVrLGRzaS50eHQNCj4gPiBpbmRleCBm MDZmMjRkNDA1YTUuLjgyMzhhODY2ODZiZSAxMDA2NDQNCj4gPiAtLS0gYS9Eb2N1bWVudGF0aW9u L2RldmljZXRyZWUvYmluZGluZ3MvZGlzcGxheS9tZWRpYXRlay9tZWRpYXRlayxkc2kudHh0DQo+ ID4gKysrIGIvRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL2Rpc3BsYXkvbWVkaWF0 ZWsvbWVkaWF0ZWssZHNpLnR4dA0KPiA+IEBAIC0yMiwyMyArMjIsNyBAQCBSZXF1aXJlZCBwcm9w ZXJ0aWVzOg0KPiA+ICBNSVBJIFRYIENvbmZpZ3VyYXRpb24gTW9kdWxlDQo+ID4gID09PT09PT09 PT09PT09PT09PT09PT09PT09PT0NCj4gPiAgDQo+ID4gLVRoZSBNSVBJIFRYIGNvbmZpZ3VyYXRp b24gbW9kdWxlIGNvbnRyb2xzIHRoZSBNSVBJIEQtUEhZLg0KPiA+IC0NCj4gPiAtUmVxdWlyZWQg cHJvcGVydGllczoNCj4gPiAtLSBjb21wYXRpYmxlOiAibWVkaWF0ZWssPGNoaXA+LW1pcGktdHgi DQo+ID4gLS0gdGhlIHN1cHBvcnRlZCBjaGlwcyBhcmUgbXQyNzAxLCA3NjIzLCBtdDgxNzMgYW5k IG10ODE4My4NCj4gPiAtLSByZWc6IFBoeXNpY2FsIGJhc2UgYWRkcmVzcyBhbmQgbGVuZ3RoIG9m IHRoZSBjb250cm9sbGVyJ3MgcmVnaXN0ZXJzDQo+ID4gLS0gY2xvY2tzOiBQTEwgcmVmZXJlbmNl IGNsb2NrDQo+ID4gLS0gY2xvY2stb3V0cHV0LW5hbWVzOiBuYW1lIG9mIHRoZSBvdXRwdXQgY2xv Y2sgbGluZSB0byB0aGUgRFNJIGVuY29kZXINCj4gPiAtLSAjY2xvY2stY2VsbHM6IG11c3QgYmUg PDA+Ow0KPiA+IC0tICNwaHktY2VsbHM6IG11c3QgYmUgPDA+Lg0KPiA+IC0NCj4gPiAtT3B0aW9u YWwgcHJvcGVydGllczoNCj4gPiAtLSBkcml2ZS1zdHJlbmd0aC1taWNyb2FtcDogYWRqdXN0IGRy aXZpbmcgY3VycmVudCwgc2hvdWxkIGJlIDMwMDAgfiA2MDAwLiBBbmQNCj4gPiAtCQkJCQkJICAg dGhlIHN0ZXAgaXMgMjAwLg0KPiA+IC0tIG52bWVtLWNlbGxzOiBBIHBoYW5kbGUgdG8gdGhlIGNh bGlicmF0aW9uIGRhdGEgcHJvdmlkZWQgYnkgYSBudm1lbSBkZXZpY2UuIElmDQo+ID4gLSAgICAg ICAgICAgICAgIHVuc3BlY2lmaWVkIGRlZmF1bHQgdmFsdWVzIHNoYWxsIGJlIHVzZWQuDQo+ID4g LS0gbnZtZW0tY2VsbC1uYW1lczogU2hvdWxkIGJlICJjYWxpYnJhdGlvbi1kYXRhIg0KPiA+ICtT ZWUgcGh5L21lZGlhdGVrLGRzaS1waHkueWFtbA0KPiA+ICANCj4gPiAgRXhhbXBsZToNCj4gPiAg DQo+ID4gZGlmZiAtLWdpdCBhL0RvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9waHkv bWVkaWF0ZWssZHNpLXBoeS55YW1sIGIvRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdz L3BoeS9tZWRpYXRlayxkc2ktcGh5LnlhbWwNCj4gPiBuZXcgZmlsZSBtb2RlIDEwMDY0NA0KPiA+ IGluZGV4IDAwMDAwMDAwMDAwMC4uODdmOGRmMjUxYWIwDQo+ID4gLS0tIC9kZXYvbnVsbA0KPiA+ ICsrKyBiL0RvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9waHkvbWVkaWF0ZWssZHNp LXBoeS55YW1sDQo+ID4gQEAgLTAsMCArMSw4MyBAQA0KPiA+ICsjIFNQRFgtTGljZW5zZS1JZGVu dGlmaWVyOiAoR1BMLTIuMC1vbmx5IE9SIEJTRC0yLUNsYXVzZSkNCj4gPiArIyBDb3B5cmlnaHQg KGMpIDIwMjAgTWVkaWFUZWsNCj4gPiArJVlBTUwgMS4yDQo+ID4gKy0tLQ0KPiA+ICskaWQ6IGh0 dHA6Ly9kZXZpY2V0cmVlLm9yZy9zY2hlbWFzL3BoeS9tZWRpYXRlayxkc2ktcGh5LnlhbWwjDQo+ ID4gKyRzY2hlbWE6IGh0dHA6Ly9kZXZpY2V0cmVlLm9yZy9tZXRhLXNjaGVtYXMvY29yZS55YW1s Iw0KPiA+ICsNCj4gPiArdGl0bGU6IE1lZGlhVGVrIE1JUEkgRGlzcGxheSBTZXJpYWwgSW50ZXJm YWNlIChEU0kpIFBIWSBiaW5kaW5nDQo+ID4gKw0KPiA+ICttYWludGFpbmVyczoNCj4gPiArICAt IENodW4tS3VhbmcgSHUgPGNodW5rdWFuZy5odUBrZXJuZWwub3JnPg0KPiA+ICsgIC0gQ2h1bmZl bmcgWXVuIDxjaHVuZmVuZy55dW5AbWVkaWF0ZWsuY29tPg0KPiA+ICsNCj4gPiArZGVzY3JpcHRp b246IFRoZSBNSVBJIERTSSBQSFkgc3VwcG9ydHMgdXAgdG8gNC1sYW5lIG91dHB1dC4NCj4gPiAr DQo+ID4gK3Byb3BlcnRpZXM6DQo+ID4gKyAgJG5vZGVuYW1lOg0KPiA+ICsgICAgcGF0dGVybjog Il5kc2ktcGh5QFswLTlhLWZdKyQiDQo+ID4gKw0KPiA+ICsgIGNvbXBhdGlibGU6DQo+ID4gKyAg ICBlbnVtOg0KPiA+ICsgICAgICAtIG1lZGlhdGVrLG10MjcwMS1taXBpLXR4DQo+ID4gKyAgICAg IC0gbWVkaWF0ZWssbXQ3NjIzLW1pcGktdHgNCj4gPiArICAgICAgLSBtZWRpYXRlayxtdDgxNzMt bWlwaS10eA0KPiA+ICsNCj4gPiArICByZWc6DQo+ID4gKyAgICBtYXhJdGVtczogMQ0KPiA+ICsN Cj4gPiArICBjbG9ja3M6DQo+ID4gKyAgICBpdGVtczoNCj4gPiArICAgICAgLSBkZXNjcmlwdGlv bjogUExMIHJlZmVyZW5jZSBjbG9jaw0KPiA+ICsNCj4gPiArICBjbG9jay1vdXRwdXQtbmFtZXM6 DQo+ID4gKyAgICBtYXhJdGVtczogMQ0KPiA+ICsNCj4gPiArICAiI3BoeS1jZWxscyI6DQo+ID4g KyAgICBjb25zdDogMA0KPiA+ICsNCj4gPiArICAiI2Nsb2NrLWNlbGxzIjoNCj4gPiArICAgIGNv bnN0OiAwDQo+ID4gKw0KPiA+ICsgIG52bWVtLWNlbGxzOg0KPiA+ICsgICAgbWF4SXRlbXM6IDEN Cj4gPiArICAgIGRlc2NyaXB0aW9uOiBBIHBoYW5kbGUgdG8gdGhlIGNhbGlicmF0aW9uIGRhdGEg cHJvdmlkZWQgYnkgYSBudm1lbSBkZXZpY2UsDQo+ID4gKyAgICAgIGlmIHVuc3BlY2lmaWVkLCBk ZWZhdWx0IHZhbHVlcyBzaGFsbCBiZSB1c2VkLg0KPiA+ICsNCj4gPiArICBudm1lbS1jZWxsLW5h bWVzOg0KPiA+ICsgICAgaXRlbXM6DQo+ID4gKyAgICAgIC0gY29uc3Q6IGNhbGlicmF0aW9uLWRh dGENCj4gPiArDQo+ID4gKyAgZHJpdmUtc3RyZW5ndGgtbWljcm9hbXA6DQo+ID4gKyAgICBkZXNj cmlwdGlvbjogYWRqdXN0IGRyaXZpbmcgY3VycmVudCwgdGhlIHN0ZXAgaXMgMjAwLg0KPiANCj4g bXVsdGlwbGVPZjogMjAwDQpHb3QgaXQuDQo+IA0KPiA+ICsgICAgJHJlZjogL3NjaGVtYXMvdHlw ZXMueWFtbCMvZGVmaW5pdGlvbnMvdWludDMyDQo+IA0KPiBDYW4gZHJvcC4gU3RhbmRhcmQgdW5p dCBzdWZmaXhlcyBoYXZlIGEgdHlwZSBhbHJlYWR5Lg0KT2ssIHRoYW5rcyBhIGxvdA0KDQo+IA0K PiA+ICsgICAgbWluaW11bTogMjAwMA0KPiA+ICsgICAgbWF4aW11bTogNjAwMA0KPiA+ICsgICAg ZGVmYXVsdDogNDYwMA0KPiA+ICsNCj4gPiArcmVxdWlyZWQ6DQo+ID4gKyAgLSBjb21wYXRpYmxl DQo+ID4gKyAgLSByZWcNCj4gPiArICAtIGNsb2Nrcw0KPiA+ICsgIC0gY2xvY2stb3V0cHV0LW5h bWVzDQo+ID4gKyAgLSAiI3BoeS1jZWxscyINCj4gPiArICAtICIjY2xvY2stY2VsbHMiDQo+ID4g Kw0KPiA+ICthZGRpdGlvbmFsUHJvcGVydGllczogZmFsc2UNCj4gPiArDQo+ID4gK2V4YW1wbGVz Og0KPiA+ICsgIC0gfA0KPiA+ICsgICAgI2luY2x1ZGUgPGR0LWJpbmRpbmdzL2Nsb2NrL210ODE3 My1jbGsuaD4NCj4gPiArICAgIGRzaS1waHlAMTAyMTUwMDAgew0KPiA+ICsgICAgICAgIGNvbXBh dGlibGUgPSAibWVkaWF0ZWssbXQ4MTczLW1pcGktdHgiOw0KPiA+ICsgICAgICAgIHJlZyA9IDww eDEwMjE1MDAwIDB4MTAwMD47DQo+ID4gKyAgICAgICAgY2xvY2tzID0gPCZjbGsyNm0+Ow0KPiA+ ICsgICAgICAgIGNsb2NrLW91dHB1dC1uYW1lcyA9ICJtaXBpX3R4MF9wbGwiOw0KPiA+ICsgICAg ICAgIGRyaXZlLXN0cmVuZ3RoLW1pY3JvYW1wID0gPDQwMDA+Ow0KPiA+ICsgICAgICAgIG52bWVt LWNlbGxzPSA8Jm1pcGlfdHhfY2FsaWJyYXRpb24+Ow0KPiA+ICsgICAgICAgIG52bWVtLWNlbGwt bmFtZXMgPSAiY2FsaWJyYXRpb24tZGF0YSI7DQo+ID4gKyAgICAgICAgI2Nsb2NrLWNlbGxzID0g PDA+Ow0KPiA+ICsgICAgICAgICNwaHktY2VsbHMgPSA8MD47DQo+ID4gKyAgICB9Ow0KPiA+ICsN Cj4gPiArLi4uDQo+ID4gLS0gDQo+ID4gMi4xOC4wDQo+ID4gDQoNCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BBF5EC4361B for ; Tue, 8 Dec 2020 02:10:54 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 36BF423A1E for ; Tue, 8 Dec 2020 02:10:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 36BF423A1E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Date:To:From: Subject:Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=cdvPNmSh9e7qq0QsBvB4DXae30uOyZAnQvXpxCbafWc=; b=jVEee4JCPhUDuUG5ZspCH6fIY kvwQN4sId5PjFj8SE+wBCN2+DeunvDOlREB52IL/f7NrImfv8mDNZkca+iqcrnDx5cvtZ0E8fHvTG NsiH+g+fH0IB415j4o17bRpRwfk55e5KO+1m9xXao1pqnvhqZrJCjcCY7mQQhEaZjDY9WbLIF6AS8 /IvwfUCd0vrN6UAdmgYOx4IZNFIvgd+2/STNjXz9+KkZFnHdrbsocromTUrbLe7HT4ZUPAO1BbbW1 3D77w8QtE7wGJs+2IEAp9+7aoa46HZHgc1LGVLhobTN55DnW4pycIb6zPXqYLV+K+VnSfaPxL47mW 0oGWuSHJQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kmSSj-0000MB-Ld; Tue, 08 Dec 2020 02:10:45 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kmSSg-0000Lg-EE; Tue, 08 Dec 2020 02:10:43 +0000 X-UUID: a0fd30be59064ca0ba85c96f28a01f2e-20201207 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=AnfMsxCsqIaWPXAofU2Qh3nt/yEpA1Nncyh3grmr2Hs=; b=a2h/GOb3tMmj4tVWWW0Z8TUR3FBZ3HuPCXErjJgQio5LqJUJMEZR1tVd2u1BuMDPlmDLv2O+NDJZ8PcqVt24FAPKEqv1uNg6UFJa56TTUYvo2315Fqbm9h8UgU9F6hHw+HODvloC9Xj/ab+g8IgGqFF1/2dzNy25Nb0tHM+TMbc=; X-UUID: a0fd30be59064ca0ba85c96f28a01f2e-20201207 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1902848928; Mon, 07 Dec 2020 18:10:40 -0800 Received: from MTKMBS31DR.mediatek.inc (172.27.6.102) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 7 Dec 2020 18:00:35 -0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS31DR.mediatek.inc (172.27.6.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 8 Dec 2020 10:00:23 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 8 Dec 2020 10:00:26 +0800 Message-ID: <1607392825.23328.5.camel@mhfsdcap03> Subject: Re: [PATCH v3 07/11] dt-bindings: phy: convert MIP DSI PHY binding to YAML schema From: Chunfeng Yun To: Rob Herring Date: Tue, 8 Dec 2020 10:00:25 +0800 In-Reply-To: <20201207211920.GA841059@robh.at.kernel.org> References: <20201118082126.42701-1-chunfeng.yun@mediatek.com> <20201118082126.42701-7-chunfeng.yun@mediatek.com> <20201207211920.GA841059@robh.at.kernel.org> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: BA25879DABC571C822341F4AC2ABA120CA9AACE0D97F7DEA60AC1AC6A1D432792000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201207_211042_698688_A4D8E517 X-CRM114-Status: GOOD ( 24.11 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Chun-Kuang Hu , Min Guo , Philipp Zabel , devicetree@vger.kernel.org, David Airlie , Greg Kroah-Hartman , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Kishon Vijay Abraham I , Serge Semin , Vinod Koul , linux-mediatek@lists.infradead.org, Daniel Vetter , netdev@vger.kernel.org, Matthias Brugger , Jakub Kicinski , Stanley Chu , "David S . Miller" , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Mon, 2020-12-07 at 15:19 -0600, Rob Herring wrote: > On Wed, Nov 18, 2020 at 04:21:22PM +0800, Chunfeng Yun wrote: > > Convert MIPI DSI PHY binding to YAML schema mediatek,dsi-phy.yaml > > > > Cc: Chun-Kuang Hu > > Signed-off-by: Chunfeng Yun > > --- > > v3: new patch > > --- > > .../display/mediatek/mediatek,dsi.txt | 18 +--- > > .../bindings/phy/mediatek,dsi-phy.yaml | 83 +++++++++++++++++++ > > 2 files changed, 84 insertions(+), 17 deletions(-) > > create mode 100644 Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml > > > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > > index f06f24d405a5..8238a86686be 100644 > > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > > @@ -22,23 +22,7 @@ Required properties: > > MIPI TX Configuration Module > > ============================ > > > > -The MIPI TX configuration module controls the MIPI D-PHY. > > - > > -Required properties: > > -- compatible: "mediatek,-mipi-tx" > > -- the supported chips are mt2701, 7623, mt8173 and mt8183. > > -- reg: Physical base address and length of the controller's registers > > -- clocks: PLL reference clock > > -- clock-output-names: name of the output clock line to the DSI encoder > > -- #clock-cells: must be <0>; > > -- #phy-cells: must be <0>. > > - > > -Optional properties: > > -- drive-strength-microamp: adjust driving current, should be 3000 ~ 6000. And > > - the step is 200. > > -- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If > > - unspecified default values shall be used. > > -- nvmem-cell-names: Should be "calibration-data" > > +See phy/mediatek,dsi-phy.yaml > > > > Example: > > > > diff --git a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml > > new file mode 100644 > > index 000000000000..87f8df251ab0 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml > > @@ -0,0 +1,83 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +# Copyright (c) 2020 MediaTek > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: MediaTek MIPI Display Serial Interface (DSI) PHY binding > > + > > +maintainers: > > + - Chun-Kuang Hu > > + - Chunfeng Yun > > + > > +description: The MIPI DSI PHY supports up to 4-lane output. > > + > > +properties: > > + $nodename: > > + pattern: "^dsi-phy@[0-9a-f]+$" > > + > > + compatible: > > + enum: > > + - mediatek,mt2701-mipi-tx > > + - mediatek,mt7623-mipi-tx > > + - mediatek,mt8173-mipi-tx > > + > > + reg: > > + maxItems: 1 > > + > > + clocks: > > + items: > > + - description: PLL reference clock > > + > > + clock-output-names: > > + maxItems: 1 > > + > > + "#phy-cells": > > + const: 0 > > + > > + "#clock-cells": > > + const: 0 > > + > > + nvmem-cells: > > + maxItems: 1 > > + description: A phandle to the calibration data provided by a nvmem device, > > + if unspecified, default values shall be used. > > + > > + nvmem-cell-names: > > + items: > > + - const: calibration-data > > + > > + drive-strength-microamp: > > + description: adjust driving current, the step is 200. > > multipleOf: 200 Got it. > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > Can drop. Standard unit suffixes have a type already. Ok, thanks a lot > > > + minimum: 2000 > > + maximum: 6000 > > + default: 4600 > > + > > +required: > > + - compatible > > + - reg > > + - clocks > > + - clock-output-names > > + - "#phy-cells" > > + - "#clock-cells" > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include > > + dsi-phy@10215000 { > > + compatible = "mediatek,mt8173-mipi-tx"; > > + reg = <0x10215000 0x1000>; > > + clocks = <&clk26m>; > > + clock-output-names = "mipi_tx0_pll"; > > + drive-strength-microamp = <4000>; > > + nvmem-cells= <&mipi_tx_calibration>; > > + nvmem-cell-names = "calibration-data"; > > + #clock-cells = <0>; > > + #phy-cells = <0>; > > + }; > > + > > +... > > -- > > 2.18.0 > > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8953EC433FE for ; Tue, 8 Dec 2020 02:12:15 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3273423A55 for ; Tue, 8 Dec 2020 02:12:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3273423A55 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Date:To:From: Subject:Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=cu+rO1UE+xXuHh+ioXkGTf/alGufx0w5IKiDvfHhW6o=; b=jtVsp76/NWnSRQvdR0vx8MU0r 2V+6MIp3OsU0SLBf6PURQcPbZsDlajsGQV+AEiLQ6VBtuE/JdQoMD3WYY4YMAnfhRFPW3pobDM7DA qzewi2NDCi8Q+vDFWxsOFm1PAoKaTOOhKUiSHMUBtAcBRtLsuxj7h6K/flKSuiLopkSmP4lbdimRg eF+8h3+mFS7c+x5wWkcCt2aHRX9u9ug9wm6TU5DM5xO1MlXPcMwKZDyC/s/l+uEOZH8uigKFd7Ps+ +a71+mamuP55+3mwCHfEeJDzLjULD50lAqxVDwLasSQp3Jb7r1rs4uZJh/ORWSoZx8F5xpaZ/IFKB +Bl1AV7nA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kmSSk-0000MJ-Fb; Tue, 08 Dec 2020 02:10:46 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kmSSg-0000Lg-EE; Tue, 08 Dec 2020 02:10:43 +0000 X-UUID: a0fd30be59064ca0ba85c96f28a01f2e-20201207 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=AnfMsxCsqIaWPXAofU2Qh3nt/yEpA1Nncyh3grmr2Hs=; b=a2h/GOb3tMmj4tVWWW0Z8TUR3FBZ3HuPCXErjJgQio5LqJUJMEZR1tVd2u1BuMDPlmDLv2O+NDJZ8PcqVt24FAPKEqv1uNg6UFJa56TTUYvo2315Fqbm9h8UgU9F6hHw+HODvloC9Xj/ab+g8IgGqFF1/2dzNy25Nb0tHM+TMbc=; X-UUID: a0fd30be59064ca0ba85c96f28a01f2e-20201207 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1902848928; Mon, 07 Dec 2020 18:10:40 -0800 Received: from MTKMBS31DR.mediatek.inc (172.27.6.102) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 7 Dec 2020 18:00:35 -0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS31DR.mediatek.inc (172.27.6.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 8 Dec 2020 10:00:23 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 8 Dec 2020 10:00:26 +0800 Message-ID: <1607392825.23328.5.camel@mhfsdcap03> Subject: Re: [PATCH v3 07/11] dt-bindings: phy: convert MIP DSI PHY binding to YAML schema From: Chunfeng Yun To: Rob Herring Date: Tue, 8 Dec 2020 10:00:25 +0800 In-Reply-To: <20201207211920.GA841059@robh.at.kernel.org> References: <20201118082126.42701-1-chunfeng.yun@mediatek.com> <20201118082126.42701-7-chunfeng.yun@mediatek.com> <20201207211920.GA841059@robh.at.kernel.org> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: BA25879DABC571C822341F4AC2ABA120CA9AACE0D97F7DEA60AC1AC6A1D432792000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201207_211042_698688_A4D8E517 X-CRM114-Status: GOOD ( 24.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Chun-Kuang Hu , Min Guo , Philipp Zabel , devicetree@vger.kernel.org, David Airlie , Greg Kroah-Hartman , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Kishon Vijay Abraham I , Serge Semin , Vinod Koul , linux-mediatek@lists.infradead.org, Daniel Vetter , netdev@vger.kernel.org, Matthias Brugger , Jakub Kicinski , Stanley Chu , "David S . Miller" , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 2020-12-07 at 15:19 -0600, Rob Herring wrote: > On Wed, Nov 18, 2020 at 04:21:22PM +0800, Chunfeng Yun wrote: > > Convert MIPI DSI PHY binding to YAML schema mediatek,dsi-phy.yaml > > > > Cc: Chun-Kuang Hu > > Signed-off-by: Chunfeng Yun > > --- > > v3: new patch > > --- > > .../display/mediatek/mediatek,dsi.txt | 18 +--- > > .../bindings/phy/mediatek,dsi-phy.yaml | 83 +++++++++++++++++++ > > 2 files changed, 84 insertions(+), 17 deletions(-) > > create mode 100644 Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml > > > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > > index f06f24d405a5..8238a86686be 100644 > > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > > @@ -22,23 +22,7 @@ Required properties: > > MIPI TX Configuration Module > > ============================ > > > > -The MIPI TX configuration module controls the MIPI D-PHY. > > - > > -Required properties: > > -- compatible: "mediatek,-mipi-tx" > > -- the supported chips are mt2701, 7623, mt8173 and mt8183. > > -- reg: Physical base address and length of the controller's registers > > -- clocks: PLL reference clock > > -- clock-output-names: name of the output clock line to the DSI encoder > > -- #clock-cells: must be <0>; > > -- #phy-cells: must be <0>. > > - > > -Optional properties: > > -- drive-strength-microamp: adjust driving current, should be 3000 ~ 6000. And > > - the step is 200. > > -- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If > > - unspecified default values shall be used. > > -- nvmem-cell-names: Should be "calibration-data" > > +See phy/mediatek,dsi-phy.yaml > > > > Example: > > > > diff --git a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml > > new file mode 100644 > > index 000000000000..87f8df251ab0 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml > > @@ -0,0 +1,83 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +# Copyright (c) 2020 MediaTek > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: MediaTek MIPI Display Serial Interface (DSI) PHY binding > > + > > +maintainers: > > + - Chun-Kuang Hu > > + - Chunfeng Yun > > + > > +description: The MIPI DSI PHY supports up to 4-lane output. > > + > > +properties: > > + $nodename: > > + pattern: "^dsi-phy@[0-9a-f]+$" > > + > > + compatible: > > + enum: > > + - mediatek,mt2701-mipi-tx > > + - mediatek,mt7623-mipi-tx > > + - mediatek,mt8173-mipi-tx > > + > > + reg: > > + maxItems: 1 > > + > > + clocks: > > + items: > > + - description: PLL reference clock > > + > > + clock-output-names: > > + maxItems: 1 > > + > > + "#phy-cells": > > + const: 0 > > + > > + "#clock-cells": > > + const: 0 > > + > > + nvmem-cells: > > + maxItems: 1 > > + description: A phandle to the calibration data provided by a nvmem device, > > + if unspecified, default values shall be used. > > + > > + nvmem-cell-names: > > + items: > > + - const: calibration-data > > + > > + drive-strength-microamp: > > + description: adjust driving current, the step is 200. > > multipleOf: 200 Got it. > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > Can drop. Standard unit suffixes have a type already. Ok, thanks a lot > > > + minimum: 2000 > > + maximum: 6000 > > + default: 4600 > > + > > +required: > > + - compatible > > + - reg > > + - clocks > > + - clock-output-names > > + - "#phy-cells" > > + - "#clock-cells" > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include > > + dsi-phy@10215000 { > > + compatible = "mediatek,mt8173-mipi-tx"; > > + reg = <0x10215000 0x1000>; > > + clocks = <&clk26m>; > > + clock-output-names = "mipi_tx0_pll"; > > + drive-strength-microamp = <4000>; > > + nvmem-cells= <&mipi_tx_calibration>; > > + nvmem-cell-names = "calibration-data"; > > + #clock-cells = <0>; > > + #phy-cells = <0>; > > + }; > > + > > +... > > -- > > 2.18.0 > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.0 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7EE67C4361B for ; Tue, 8 Dec 2020 08:33:49 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 24B9E233EE for ; Tue, 8 Dec 2020 08:33:49 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 24B9E233EE Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 697556E989; Tue, 8 Dec 2020 08:32:21 +0000 (UTC) Received: from mailgw01.mediatek.com (unknown [1.203.163.78]) by gabe.freedesktop.org (Postfix) with ESMTP id 1A4F26E8C7 for ; Tue, 8 Dec 2020 02:05:56 +0000 (UTC) X-UUID: 8a664c262b164f2bb78d63554f53e19a-20201208 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=AnfMsxCsqIaWPXAofU2Qh3nt/yEpA1Nncyh3grmr2Hs=; b=a2h/GOb3tMmj4tVWWW0Z8TUR3FBZ3HuPCXErjJgQio5LqJUJMEZR1tVd2u1BuMDPlmDLv2O+NDJZ8PcqVt24FAPKEqv1uNg6UFJa56TTUYvo2315Fqbm9h8UgU9F6hHw+HODvloC9Xj/ab+g8IgGqFF1/2dzNy25Nb0tHM+TMbc=; X-UUID: 8a664c262b164f2bb78d63554f53e19a-20201208 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1168966895; Tue, 08 Dec 2020 10:00:35 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS31DR.mediatek.inc (172.27.6.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 8 Dec 2020 10:00:23 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 8 Dec 2020 10:00:26 +0800 Message-ID: <1607392825.23328.5.camel@mhfsdcap03> Subject: Re: [PATCH v3 07/11] dt-bindings: phy: convert MIP DSI PHY binding to YAML schema From: Chunfeng Yun To: Rob Herring Date: Tue, 8 Dec 2020 10:00:25 +0800 In-Reply-To: <20201207211920.GA841059@robh.at.kernel.org> References: <20201118082126.42701-1-chunfeng.yun@mediatek.com> <20201118082126.42701-7-chunfeng.yun@mediatek.com> <20201207211920.GA841059@robh.at.kernel.org> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: BA25879DABC571C822341F4AC2ABA120CA9AACE0D97F7DEA60AC1AC6A1D432792000:8 X-MTK: N X-Mailman-Approved-At: Tue, 08 Dec 2020 08:32:06 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Chun-Kuang Hu , Min Guo , devicetree@vger.kernel.org, David Airlie , Greg Kroah-Hartman , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Kishon Vijay Abraham I , Serge Semin , Vinod Koul , linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, Matthias Brugger , Jakub Kicinski , Stanley Chu , "David S . Miller" , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Mon, 2020-12-07 at 15:19 -0600, Rob Herring wrote: > On Wed, Nov 18, 2020 at 04:21:22PM +0800, Chunfeng Yun wrote: > > Convert MIPI DSI PHY binding to YAML schema mediatek,dsi-phy.yaml > > > > Cc: Chun-Kuang Hu > > Signed-off-by: Chunfeng Yun > > --- > > v3: new patch > > --- > > .../display/mediatek/mediatek,dsi.txt | 18 +--- > > .../bindings/phy/mediatek,dsi-phy.yaml | 83 +++++++++++++++++++ > > 2 files changed, 84 insertions(+), 17 deletions(-) > > create mode 100644 Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml > > > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > > index f06f24d405a5..8238a86686be 100644 > > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > > @@ -22,23 +22,7 @@ Required properties: > > MIPI TX Configuration Module > > ============================ > > > > -The MIPI TX configuration module controls the MIPI D-PHY. > > - > > -Required properties: > > -- compatible: "mediatek,-mipi-tx" > > -- the supported chips are mt2701, 7623, mt8173 and mt8183. > > -- reg: Physical base address and length of the controller's registers > > -- clocks: PLL reference clock > > -- clock-output-names: name of the output clock line to the DSI encoder > > -- #clock-cells: must be <0>; > > -- #phy-cells: must be <0>. > > - > > -Optional properties: > > -- drive-strength-microamp: adjust driving current, should be 3000 ~ 6000. And > > - the step is 200. > > -- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If > > - unspecified default values shall be used. > > -- nvmem-cell-names: Should be "calibration-data" > > +See phy/mediatek,dsi-phy.yaml > > > > Example: > > > > diff --git a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml > > new file mode 100644 > > index 000000000000..87f8df251ab0 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml > > @@ -0,0 +1,83 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +# Copyright (c) 2020 MediaTek > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: MediaTek MIPI Display Serial Interface (DSI) PHY binding > > + > > +maintainers: > > + - Chun-Kuang Hu > > + - Chunfeng Yun > > + > > +description: The MIPI DSI PHY supports up to 4-lane output. > > + > > +properties: > > + $nodename: > > + pattern: "^dsi-phy@[0-9a-f]+$" > > + > > + compatible: > > + enum: > > + - mediatek,mt2701-mipi-tx > > + - mediatek,mt7623-mipi-tx > > + - mediatek,mt8173-mipi-tx > > + > > + reg: > > + maxItems: 1 > > + > > + clocks: > > + items: > > + - description: PLL reference clock > > + > > + clock-output-names: > > + maxItems: 1 > > + > > + "#phy-cells": > > + const: 0 > > + > > + "#clock-cells": > > + const: 0 > > + > > + nvmem-cells: > > + maxItems: 1 > > + description: A phandle to the calibration data provided by a nvmem device, > > + if unspecified, default values shall be used. > > + > > + nvmem-cell-names: > > + items: > > + - const: calibration-data > > + > > + drive-strength-microamp: > > + description: adjust driving current, the step is 200. > > multipleOf: 200 Got it. > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > Can drop. Standard unit suffixes have a type already. Ok, thanks a lot > > > + minimum: 2000 > > + maximum: 6000 > > + default: 4600 > > + > > +required: > > + - compatible > > + - reg > > + - clocks > > + - clock-output-names > > + - "#phy-cells" > > + - "#clock-cells" > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include > > + dsi-phy@10215000 { > > + compatible = "mediatek,mt8173-mipi-tx"; > > + reg = <0x10215000 0x1000>; > > + clocks = <&clk26m>; > > + clock-output-names = "mipi_tx0_pll"; > > + drive-strength-microamp = <4000>; > > + nvmem-cells= <&mipi_tx_calibration>; > > + nvmem-cell-names = "calibration-data"; > > + #clock-cells = <0>; > > + #phy-cells = <0>; > > + }; > > + > > +... > > -- > > 2.18.0 > > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel