* [Intel-gfx] [PATCH 1/3] drm/i915/gt: stop ignoring read with wa_masked_field_set
@ 2020-12-09 4:52 Lucas De Marchi
2020-12-09 4:52 ` [Intel-gfx] [PATCH 2/3] drm/i915/gt: rename wa_write_masked_or() Lucas De Marchi
` (4 more replies)
0 siblings, 5 replies; 8+ messages in thread
From: Lucas De Marchi @ 2020-12-09 4:52 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
When using masked registers, there is nothing to clear since a masked
register has the mask in the upper 16b: we can just write to the
location we want and use the mask to control what bits we are writing
to.
However that doesn't mean we don't want to read back the register and
check the value actually matched what we wanted to write, i.e. that
the WA stick. That should be an explicit opt-out for registers that are
either write-only or that are affected by hardware misbehavior.
Moreover both wa_masked_en() and wa_masked_dis() check the WA stick, so
skipping the check just because the field is more than 1 bit is
surprising and error-prone.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 2db1e68d7464..70d4ca2776a3 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -233,7 +233,7 @@ static void
wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg,
u32 mask, u32 val)
{
- wa_write_masked_or(wal, reg, 0, _MASKED_FIELD(mask, val));
+ wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask);
}
static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine,
--
2.29.2
_______________________________________________
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915/gt: rename wa_write_masked_or()
2020-12-09 4:52 [Intel-gfx] [PATCH 1/3] drm/i915/gt: stop ignoring read with wa_masked_field_set Lucas De Marchi
@ 2020-12-09 4:52 ` Lucas De Marchi
2020-12-09 11:34 ` Chris Wilson
2020-12-09 4:52 ` [Intel-gfx] [PATCH 3/3] drm/i915/gt: document masked registers Lucas De Marchi
` (3 subsequent siblings)
4 siblings, 1 reply; 8+ messages in thread
From: Lucas De Marchi @ 2020-12-09 4:52 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
The use of "masked" in this function is due to its history. Once upon a
time it received a mask and a value as parameter. Since
commit eeec73f8a4a4 ("drm/i915/gt: Skip rmw for masked registers")
that is not true anymore and now there is a clear and a set parameter.
Depending on the case, that can still be thought as a mask and value,
but there are some subtle differences: what we clear doesn't need to be
the same bits we are setting, particularly when we are using masked
registers.
The fact that we also have "masked registers", i.e. registers whose mask
is stored in the upper 16 bits of the register, makes it even more
confusing, because "masked" in wa_write_masked_or() has little to do
with masked registers, but rather refers to the old mask parameter the
function received (that can also, but not exclusively, be used to write
to masked register).
Avoid the ambiguity and misnomer by renaming it to something else,
hopefully less confusing: wa_write_clr_set(), to designate that we are
doing both clr and set operations in the register.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 88 ++++++++++-----------
1 file changed, 44 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 70d4ca2776a3..fec099f6ae76 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -194,7 +194,7 @@ static void wa_add(struct i915_wa_list *wal, i915_reg_t reg,
}
static void
-wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set)
+wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set)
{
wa_add(wal, reg, clear, set, clear);
}
@@ -202,19 +202,19 @@ wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set)
static void
wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
{
- wa_write_masked_or(wal, reg, ~0, set);
+ wa_write_clr_set(wal, reg, ~0, set);
}
static void
wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
{
- wa_write_masked_or(wal, reg, set, set);
+ wa_write_clr_set(wal, reg, set, set);
}
static void
wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)
{
- wa_write_masked_or(wal, reg, clr, 0);
+ wa_write_clr_set(wal, reg, clr, 0);
}
static void
@@ -603,10 +603,10 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
/* WaEnableFloatBlendOptimization:icl */
- wa_write_masked_or(wal,
- GEN10_CACHE_MODE_SS,
- 0, /* write-only, so skip validation */
- _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE));
+ wa_write_clr_set(wal,
+ GEN10_CACHE_MODE_SS,
+ 0, /* write-only, so skip validation */
+ _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE));
/* WaDisableGPGPUMidThreadPreemption:icl */
wa_masked_field_set(wal, GEN8_CS_CHICKEN1,
@@ -619,9 +619,9 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
/* Wa_1604278689:icl,ehl */
wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID);
- wa_write_masked_or(wal, IVB_FBC_RT_BASE_UPPER,
- 0, /* write-only register; skip validation */
- 0xFFFFFFFF);
+ wa_write_clr_set(wal, IVB_FBC_RT_BASE_UPPER,
+ 0, /* write-only register; skip validation */
+ 0xFFFFFFFF);
/* Wa_1406306137:icl,ehl */
wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);
@@ -881,11 +881,11 @@ ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
* This actually overrides the dispatch
* mode for all thread types.
*/
- wa_write_masked_or(wal, GEN7_FF_THREAD_MODE,
- GEN7_FF_SCHED_MASK,
- GEN7_FF_TS_SCHED_HW |
- GEN7_FF_VS_SCHED_HW |
- GEN7_FF_DS_SCHED_HW);
+ wa_write_clr_set(wal, GEN7_FF_THREAD_MODE,
+ GEN7_FF_SCHED_MASK,
+ GEN7_FF_TS_SCHED_HW |
+ GEN7_FF_VS_SCHED_HW |
+ GEN7_FF_DS_SCHED_HW);
if (0) { /* causes HiZ corruption on ivb:gt1 */
/* enable HiZ Raw Stall Optimization */
@@ -933,12 +933,12 @@ vlv_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
* This actually overrides the dispatch
* mode for all thread types.
*/
- wa_write_masked_or(wal,
- GEN7_FF_THREAD_MODE,
- GEN7_FF_SCHED_MASK,
- GEN7_FF_TS_SCHED_HW |
- GEN7_FF_VS_SCHED_HW |
- GEN7_FF_DS_SCHED_HW);
+ wa_write_clr_set(wal,
+ GEN7_FF_THREAD_MODE,
+ GEN7_FF_SCHED_MASK,
+ GEN7_FF_TS_SCHED_HW |
+ GEN7_FF_VS_SCHED_HW |
+ GEN7_FF_DS_SCHED_HW);
/*
* BSpec says this must be set, even though
@@ -1172,7 +1172,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
drm_dbg(&i915->drm, "MCR slice/subslice = %x\n", mcr);
- wa_write_masked_or(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);
+ wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);
}
static void
@@ -1197,10 +1197,10 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
/* WaModifyGamTlbPartitioning:icl */
- wa_write_masked_or(wal,
- GEN11_GACB_PERF_CTRL,
- GEN11_HASH_CTRL_MASK,
- GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4);
+ wa_write_clr_set(wal,
+ GEN11_GACB_PERF_CTRL,
+ GEN11_HASH_CTRL_MASK,
+ GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4);
/* Wa_1405766107:icl
* Formerly known as WaCL2SFHalfMaxAlloc
@@ -1844,14 +1844,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
* Wa_1604223664:icl
* Formerly known as WaL3BankAddressHashing
*/
- wa_write_masked_or(wal,
- GEN8_GARBCNTL,
- GEN11_HASH_CTRL_EXCL_MASK,
- GEN11_HASH_CTRL_EXCL_BIT0);
- wa_write_masked_or(wal,
- GEN11_GLBLINVL,
- GEN11_BANK_HASH_ADDR_EXCL_MASK,
- GEN11_BANK_HASH_ADDR_EXCL_BIT0);
+ wa_write_clr_set(wal,
+ GEN8_GARBCNTL,
+ GEN11_HASH_CTRL_EXCL_MASK,
+ GEN11_HASH_CTRL_EXCL_BIT0);
+ wa_write_clr_set(wal,
+ GEN11_GLBLINVL,
+ GEN11_BANK_HASH_ADDR_EXCL_MASK,
+ GEN11_BANK_HASH_ADDR_EXCL_BIT0);
/*
* Wa_1405733216:icl
@@ -1880,10 +1880,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
GEN7_DISABLE_SAMPLER_PREFETCH);
/* Wa_1409178092:icl */
- wa_write_masked_or(wal,
- GEN11_SCRATCH2,
- GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE,
- 0);
+ wa_write_clr_set(wal,
+ GEN11_SCRATCH2,
+ GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE,
+ 0);
/* WaEnable32PlaneMode:icl */
wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS,
@@ -1957,11 +1957,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
/* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
if (IS_GEN9_LP(i915))
- wa_write_masked_or(wal,
- GEN8_L3SQCREG1,
- L3_PRIO_CREDITS_MASK,
- L3_GENERAL_PRIO_CREDITS(62) |
- L3_HIGH_PRIO_CREDITS(2));
+ wa_write_clr_set(wal,
+ GEN8_L3SQCREG1,
+ L3_PRIO_CREDITS_MASK,
+ L3_GENERAL_PRIO_CREDITS(62) |
+ L3_HIGH_PRIO_CREDITS(2));
/* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
wa_write_or(wal,
--
2.29.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Intel-gfx] [PATCH 3/3] drm/i915/gt: document masked registers
2020-12-09 4:52 [Intel-gfx] [PATCH 1/3] drm/i915/gt: stop ignoring read with wa_masked_field_set Lucas De Marchi
2020-12-09 4:52 ` [Intel-gfx] [PATCH 2/3] drm/i915/gt: rename wa_write_masked_or() Lucas De Marchi
@ 2020-12-09 4:52 ` Lucas De Marchi
2020-12-09 11:36 ` Chris Wilson
2020-12-09 6:00 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/gt: stop ignoring read with wa_masked_field_set Patchwork
` (2 subsequent siblings)
4 siblings, 1 reply; 8+ messages in thread
From: Lucas De Marchi @ 2020-12-09 4:52 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
Document what a masked register is according to bspec so we avoid
developers using the wrong functions to implement WAs.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index fec099f6ae76..b5339a36d256 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -217,6 +217,17 @@ wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)
wa_write_clr_set(wal, reg, clr, 0);
}
+/*
+ * WA operations on "masked register". A masked register has the upper 16 bits
+ * documented as "masked" in b-spec. Its purpose is to allow writing to just a
+ * portion of the register without a rmw: you simply write in the upper 16 bits
+ * the mask of bits you are going to modify.
+ *
+ * The wa_masked_* family of functions already does the necessary operations to
+ * calculate the mask based on the parameters passed, so user only has to
+ * provide the lower 16 bits of that register.
+ */
+
static void
wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
{
--
2.29.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/gt: stop ignoring read with wa_masked_field_set
2020-12-09 4:52 [Intel-gfx] [PATCH 1/3] drm/i915/gt: stop ignoring read with wa_masked_field_set Lucas De Marchi
2020-12-09 4:52 ` [Intel-gfx] [PATCH 2/3] drm/i915/gt: rename wa_write_masked_or() Lucas De Marchi
2020-12-09 4:52 ` [Intel-gfx] [PATCH 3/3] drm/i915/gt: document masked registers Lucas De Marchi
@ 2020-12-09 6:00 ` Patchwork
2020-12-09 7:41 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-12-09 11:31 ` [Intel-gfx] [PATCH 1/3] " Chris Wilson
4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2020-12-09 6:00 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 4486 bytes --]
== Series Details ==
Series: series starting with [1/3] drm/i915/gt: stop ignoring read with wa_masked_field_set
URL : https://patchwork.freedesktop.org/series/84714/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9463 -> Patchwork_19087
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/index.html
New tests
---------
New tests have been introduced between CI_DRM_9463 and Patchwork_19087:
### New CI tests (1) ###
* boot:
- Statuses : 1 fail(s) 39 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_19087 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@semaphore:
- fi-icl-y: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/fi-icl-y/igt@amdgpu/amd_basic@semaphore.html
* igt@debugfs_test@read_all_entries:
- fi-tgl-y: [PASS][2] -> [DMESG-WARN][3] ([i915#402]) +2 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/fi-tgl-y/igt@debugfs_test@read_all_entries.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/fi-tgl-y/igt@debugfs_test@read_all_entries.html
* igt@i915_pm_rpm@module-reload:
- fi-cml-s: [PASS][4] -> [INCOMPLETE][5] ([i915#2405])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/fi-cml-s/igt@i915_pm_rpm@module-reload.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/fi-cml-s/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@active:
- fi-bsw-kefka: [PASS][6] -> [DMESG-FAIL][7] ([i915#2675] / [i915#541])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/fi-bsw-kefka/igt@i915_selftest@live@active.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/fi-bsw-kefka/igt@i915_selftest@live@active.html
* igt@runner@aborted:
- fi-cml-s: NOTRUN -> [FAIL][8] ([i915#1814] / [i915#2295] / [i915#2722])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/fi-cml-s/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_flink_basic@double-flink:
- fi-tgl-y: [DMESG-WARN][9] ([i915#402]) -> [PASS][10] +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/fi-tgl-y/igt@gem_flink_basic@double-flink.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/fi-tgl-y/igt@gem_flink_basic@double-flink.html
* igt@i915_selftest@live@execlists:
- fi-icl-y: [INCOMPLETE][11] ([i915#1037] / [i915#2276]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/fi-icl-y/igt@i915_selftest@live@execlists.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/fi-icl-y/igt@i915_selftest@live@execlists.html
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#1037]: https://gitlab.freedesktop.org/drm/intel/issues/1037
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#2276]: https://gitlab.freedesktop.org/drm/intel/issues/2276
[i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
[i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405
[i915#2675]: https://gitlab.freedesktop.org/drm/intel/issues/2675
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Participating hosts (43 -> 40)
------------------------------
Missing (3): fi-ilk-m540 fi-bdw-samus fi-hsw-4200u
Build changes
-------------
* Linux: CI_DRM_9463 -> Patchwork_19087
CI-20190529: 20190529
CI_DRM_9463: 1c64d5d72bcd4e6ccf2d0ba6e6ab3644497846b5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5885: d99f644b1868b9c92435b05ebfafa230721cd677 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19087: 59710d2bf306145e3d257386510dcb4fa22ba631 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
59710d2bf306 drm/i915/gt: document masked registers
296a91cbc4bb drm/i915/gt: rename wa_write_masked_or()
6678587b6bad drm/i915/gt: stop ignoring read with wa_masked_field_set
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/index.html
[-- Attachment #1.2: Type: text/html, Size: 5357 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/gt: stop ignoring read with wa_masked_field_set
2020-12-09 4:52 [Intel-gfx] [PATCH 1/3] drm/i915/gt: stop ignoring read with wa_masked_field_set Lucas De Marchi
` (2 preceding siblings ...)
2020-12-09 6:00 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/gt: stop ignoring read with wa_masked_field_set Patchwork
@ 2020-12-09 7:41 ` Patchwork
2020-12-09 11:31 ` [Intel-gfx] [PATCH 1/3] " Chris Wilson
4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2020-12-09 7:41 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 18739 bytes --]
== Series Details ==
Series: series starting with [1/3] drm/i915/gt: stop ignoring read with wa_masked_field_set
URL : https://patchwork.freedesktop.org/series/84714/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9463_full -> Patchwork_19087_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
New tests
---------
New tests have been introduced between CI_DRM_9463_full and Patchwork_19087_full:
### New CI tests (1) ###
* boot:
- Statuses : 199 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_19087_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_reloc@basic-wide-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][1] ([i915#2389])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-iclb4/igt@gem_exec_reloc@basic-wide-active@vcs1.html
* igt@gem_exec_schedule@smoketest-all:
- shard-glk: [PASS][2] -> [DMESG-WARN][3] ([i915#118] / [i915#95])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-glk8/igt@gem_exec_schedule@smoketest-all.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-glk3/igt@gem_exec_schedule@smoketest-all.html
* igt@i915_pm_rpm@gem-execbuf-stress-pc8:
- shard-hsw: NOTRUN -> [SKIP][4] ([fdo#109271]) +53 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-hsw4/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-skl: [PASS][5] -> [DMESG-FAIL][6] ([i915#2291] / [i915#541])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-skl8/igt@i915_selftest@live@gt_heartbeat.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-skl7/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_async_flips@test-time-stamp:
- shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2597])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-tglb5/igt@kms_async_flips@test-time-stamp.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-tglb2/igt@kms_async_flips@test-time-stamp.html
* igt@kms_chamelium@hdmi-crc-nonplanar-formats:
- shard-hsw: NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-hsw4/igt@kms_chamelium@hdmi-crc-nonplanar-formats.html
* igt@kms_color@pipe-b-ctm-red-to-blue:
- shard-skl: [PASS][10] -> [DMESG-WARN][11] ([i915#1982])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-skl3/igt@kms_color@pipe-b-ctm-red-to-blue.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-skl2/igt@kms_color@pipe-b-ctm-red-to-blue.html
* igt@kms_color_chamelium@pipe-a-gamma:
- shard-skl: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-skl7/igt@kms_color_chamelium@pipe-a-gamma.html
* igt@kms_cursor_crc@pipe-a-cursor-128x128-random:
- shard-skl: [PASS][13] -> [FAIL][14] ([i915#54]) +4 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-skl3/igt@kms_cursor_crc@pipe-a-cursor-128x128-random.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-skl2/igt@kms_cursor_crc@pipe-a-cursor-128x128-random.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [PASS][15] -> [FAIL][16] ([i915#72])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-glk5/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-glk7/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-glk: [PASS][17] -> [FAIL][18] ([i915#2346])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [PASS][19] -> [FAIL][20] ([i915#79])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-skl8/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-skl: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#2672])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-skl7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-snb: [PASS][22] -> [DMESG-WARN][23] ([i915#42])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-snb7/igt@kms_frontbuffer_tracking@fbc-suspend.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-snb7/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-render:
- shard-skl: NOTRUN -> [SKIP][24] ([fdo#109271]) +23 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-skl3/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-render.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][25] -> [FAIL][26] ([i915#1188])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-skl2/igt@kms_hdr@bpc-switch-dpms.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-skl4/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
- shard-skl: NOTRUN -> [FAIL][27] ([fdo#108145] / [i915#265])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][28] -> [FAIL][29] ([fdo#108145] / [i915#265]) +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [PASS][30] -> [SKIP][31] ([fdo#109441]) +2 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-iclb1/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@perf@polling-parameterized:
- shard-skl: [PASS][32] -> [FAIL][33] ([i915#1542])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-skl2/igt@perf@polling-parameterized.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-skl4/igt@perf@polling-parameterized.html
#### Possible fixes ####
* igt@gem_exec_whisper@basic-contexts:
- shard-glk: [DMESG-WARN][34] ([i915#118] / [i915#95]) -> [PASS][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-glk3/igt@gem_exec_whisper@basic-contexts.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-glk4/igt@gem_exec_whisper@basic-contexts.html
* igt@gem_userptr_blits@huge-split:
- shard-hsw: [FAIL][36] -> [PASS][37]
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-hsw2/igt@gem_userptr_blits@huge-split.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-hsw8/igt@gem_userptr_blits@huge-split.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen:
- shard-skl: [FAIL][38] ([i915#54]) -> [PASS][39] +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-skl4/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-skl4/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-hsw: [FAIL][40] ([i915#96]) -> [PASS][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-hsw8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-hsw2/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-tglb: [FAIL][42] ([i915#2346]) -> [PASS][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-tglb3/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-tglb5/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][44] ([i915#79]) -> [PASS][45]
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-vga1-hdmi-a1:
- shard-hsw: [FAIL][46] ([i915#2122]) -> [PASS][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-hsw6/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-vga1-hdmi-a1.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-hsw8/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-vga1-hdmi-a1.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [FAIL][48] ([i915#1188]) -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-skl10/igt@kms_hdr@bpc-switch-suspend.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-skl8/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-skl: [INCOMPLETE][50] ([i915#198]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-skl9/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-skl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [FAIL][52] ([fdo#108145] / [i915#265]) -> [PASS][53]
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [SKIP][54] ([fdo#109642] / [fdo#111068]) -> [PASS][55]
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-iclb5/igt@kms_psr2_su@page_flip.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-iclb2/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_cursor_mmap_gtt:
- shard-iclb: [SKIP][56] ([fdo#109441]) -> [PASS][57]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-iclb7/igt@kms_psr@psr2_cursor_mmap_gtt.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_gtt.html
#### Warnings ####
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][58] ([i915#588]) -> [SKIP][59] ([i915#658])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-iclb8/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [DMESG-WARN][60] ([i915#1226]) -> [SKIP][61] ([fdo#109349])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-iclb1/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-kbl: [DMESG-WARN][62] ([i915#1602]) -> [INCOMPLETE][63] ([i915#155] / [i915#2405])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-kbl7/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-kbl3/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
- shard-glk: [DMESG-WARN][64] ([i915#2635]) -> [DMESG-WARN][65] ([i915#1602] / [i915#2635])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-glk3/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-glk4/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
- shard-apl: [DMESG-WARN][66] ([i915#2635]) -> [DMESG-WARN][67] ([i915#1602] / [i915#2635])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-apl1/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-apl4/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][68], [FAIL][69]) ([i915#1814] / [i915#2295] / [i915#2722] / [i915#483] / [i915#602]) -> [FAIL][70] ([i915#2295] / [i915#2722])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-kbl1/igt@runner@aborted.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-kbl7/igt@runner@aborted.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-kbl7/igt@runner@aborted.html
- shard-iclb: ([FAIL][71], [FAIL][72]) ([i915#1814] / [i915#2295] / [i915#2722] / [i915#483]) -> ([FAIL][73], [FAIL][74]) ([i915#1814] / [i915#2295] / [i915#2722] / [i915#2724] / [i915#483])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-iclb3/igt@runner@aborted.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-iclb1/igt@runner@aborted.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-iclb1/igt@runner@aborted.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-iclb1/igt@runner@aborted.html
- shard-glk: ([FAIL][75], [FAIL][76]) ([i915#1814] / [i915#2295] / [i915#2722] / [i915#483] / [k.org#202321]) -> ([FAIL][77], [FAIL][78]) ([i915#1814] / [i915#2295] / [i915#2722] / [k.org#202321])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-glk2/igt@runner@aborted.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-glk3/igt@runner@aborted.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-glk8/igt@runner@aborted.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/shard-glk4/igt@runner@aborted.html
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
[i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405
[i915#2597]: https://gitlab.freedesktop.org/drm/intel/issues/2597
[i915#2635]: https://gitlab.freedesktop.org/drm/intel/issues/2635
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#2724]: https://gitlab.freedesktop.org/drm/intel/issues/2724
[i915#42]: https://gitlab.freedesktop.org/drm/intel/issues/42
[i915#483]: https://gitlab.freedesktop.org/drm/intel/issues/483
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#602]: https://gitlab.freedesktop.org/drm/intel/issues/602
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[i915#96]: https://gitlab.freedesktop.org/drm/intel/issues/96
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_9463 -> Patchwork_19087
CI-20190529: 20190529
CI_DRM_9463: 1c64d5d72bcd4e6ccf2d0ba6e6ab3644497846b5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5885: d99f644b1868b9c92435b05ebfafa230721cd677 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19087: 59710d2bf306145e3d257386510dcb4fa22ba631 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19087/index.html
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915/gt: stop ignoring read with wa_masked_field_set
2020-12-09 4:52 [Intel-gfx] [PATCH 1/3] drm/i915/gt: stop ignoring read with wa_masked_field_set Lucas De Marchi
` (3 preceding siblings ...)
2020-12-09 7:41 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2020-12-09 11:31 ` Chris Wilson
4 siblings, 0 replies; 8+ messages in thread
From: Chris Wilson @ 2020-12-09 11:31 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx
Quoting Lucas De Marchi (2020-12-09 04:52:44)
> When using masked registers, there is nothing to clear since a masked
> register has the mask in the upper 16b: we can just write to the
> location we want and use the mask to control what bits we are writing
> to.
>
> However that doesn't mean we don't want to read back the register and
> check the value actually matched what we wanted to write, i.e. that
> the WA stick. That should be an explicit opt-out for registers that are
> either write-only or that are affected by hardware misbehavior.
>
> Moreover both wa_masked_en() and wa_masked_dis() check the WA stick, so
> skipping the check just because the field is more than 1 bit is
> surprising and error-prone.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 2db1e68d7464..70d4ca2776a3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -233,7 +233,7 @@ static void
> wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg,
> u32 mask, u32 val)
> {
> - wa_write_masked_or(wal, reg, 0, _MASKED_FIELD(mask, val));
> + wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask);
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/gt: rename wa_write_masked_or()
2020-12-09 4:52 ` [Intel-gfx] [PATCH 2/3] drm/i915/gt: rename wa_write_masked_or() Lucas De Marchi
@ 2020-12-09 11:34 ` Chris Wilson
0 siblings, 0 replies; 8+ messages in thread
From: Chris Wilson @ 2020-12-09 11:34 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx
Quoting Lucas De Marchi (2020-12-09 04:52:45)
> The use of "masked" in this function is due to its history. Once upon a
> time it received a mask and a value as parameter. Since
> commit eeec73f8a4a4 ("drm/i915/gt: Skip rmw for masked registers")
> that is not true anymore and now there is a clear and a set parameter.
> Depending on the case, that can still be thought as a mask and value,
> but there are some subtle differences: what we clear doesn't need to be
> the same bits we are setting, particularly when we are using masked
> registers.
>
> The fact that we also have "masked registers", i.e. registers whose mask
> is stored in the upper 16 bits of the register, makes it even more
> confusing, because "masked" in wa_write_masked_or() has little to do
> with masked registers, but rather refers to the old mask parameter the
> function received (that can also, but not exclusively, be used to write
> to masked register).
>
> Avoid the ambiguity and misnomer by renaming it to something else,
> hopefully less confusing: wa_write_clr_set(), to designate that we are
> doing both clr and set operations in the register.
Seems reasonable; both name and use.
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH 3/3] drm/i915/gt: document masked registers
2020-12-09 4:52 ` [Intel-gfx] [PATCH 3/3] drm/i915/gt: document masked registers Lucas De Marchi
@ 2020-12-09 11:36 ` Chris Wilson
0 siblings, 0 replies; 8+ messages in thread
From: Chris Wilson @ 2020-12-09 11:36 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx
Quoting Lucas De Marchi (2020-12-09 04:52:46)
> Document what a masked register is according to bspec so we avoid
> developers using the wrong functions to implement WAs.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index fec099f6ae76..b5339a36d256 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -217,6 +217,17 @@ wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)
> wa_write_clr_set(wal, reg, clr, 0);
> }
>
> +/*
> + * WA operations on "masked register". A masked register has the upper 16 bits
> + * documented as "masked" in b-spec. Its purpose is to allow writing to just a
> + * portion of the register without a rmw: you simply write in the upper 16 bits
> + * the mask of bits you are going to modify.
> + *
> + * The wa_masked_* family of functions already does the necessary operations to
> + * calculate the mask based on the parameters passed, so user only has to
> + * provide the lower 16 bits of that register.
> + */
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-12-09 11:36 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-12-09 4:52 [Intel-gfx] [PATCH 1/3] drm/i915/gt: stop ignoring read with wa_masked_field_set Lucas De Marchi
2020-12-09 4:52 ` [Intel-gfx] [PATCH 2/3] drm/i915/gt: rename wa_write_masked_or() Lucas De Marchi
2020-12-09 11:34 ` Chris Wilson
2020-12-09 4:52 ` [Intel-gfx] [PATCH 3/3] drm/i915/gt: document masked registers Lucas De Marchi
2020-12-09 11:36 ` Chris Wilson
2020-12-09 6:00 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/gt: stop ignoring read with wa_masked_field_set Patchwork
2020-12-09 7:41 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-12-09 11:31 ` [Intel-gfx] [PATCH 1/3] " Chris Wilson
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