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Thu, 10 Dec 2020 05:36:06 +0000 From: Liu Ying To: linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, laurentiu.palcu@oss.nxp.com, guido.gunther@puri.sm Subject: [PATCH v4 1/6] dt-bindings: display: imx: Add i.MX8qxp/qm DPU binding Date: Thu, 10 Dec 2020 13:27:26 +0800 Message-Id: <1607578052-4316-2-git-send-email-victor.liu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1607578052-4316-1-git-send-email-victor.liu@nxp.com> References: <1607578052-4316-1-git-send-email-victor.liu@nxp.com> Content-Type: text/plain X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: SG2PR01CA0102.apcprd01.prod.exchangelabs.com (2603:1096:3:15::28) To VI1PR04MB3983.eurprd04.prod.outlook.com (2603:10a6:803:4c::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.66) by SG2PR01CA0102.apcprd01.prod.exchangelabs.com (2603:1096:3:15::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3654.12 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: =?us-ascii?Q?Xb/1yZQ986jCa09FsVXPrGJ03i55iy5xQsgZ24Tsus917A6p2ZM63lFsAIa6?= =?us-ascii?Q?VYtcsjj2nlcc0d70wJCfJ7+xisBvxCNsR7hGiu4RNJY84c/ig2wpfAQ/bQzw?= =?us-ascii?Q?G8yTxgGzKqbrwHDPqVAZVtH4vsZNwJdZ/HgDsJs8JB+F9z9eoffd+E2hohUH?= =?us-ascii?Q?SCxqbW+h9gqlkP47MrJ462a3y1Va2tk9fiOMxVgkB1PILzlrY80bn9DSv87v?= =?us-ascii?Q?KboKOHcq4rq/ijUxWXAZBs+DE2ls4SLwW8GSuX26WADwi2GJO2HvlX8UJIx1?= =?us-ascii?Q?glCvp7menYvZ3hy2NnIeNmN6Vwg1e034OIvpKmTOCO8GoaGyLT/k2EyaxhtA?= =?us-ascii?Q?dnhmlKME6Uu40bqywrVVpsuj1QUGj2L6amdbw0xlZMgh7YVyxcJEp/ZwheP5?= =?us-ascii?Q?wHdSyRWwfQQNKOa2VfAaFQr32L+nnpaLh3RvS/P4B76SsUoWTvbG75VWRpT7?= =?us-ascii?Q?Ii9Y0NFkfDJG93ENu4Gzyg127zDMP3XqHF1JOKHbDaDHee84R5Ys2PsfvkWH?= =?us-ascii?Q?c5lCdO+VC0JN//xde4nnyadhCdBDDSKepnR08+kw/ve3I9ueDYI7g/eIkDRC?= =?us-ascii?Q?sYj6EZRmyYNt9+MDw8EPoBipAX+a0ExP0F+p2JceJd1mxGqF4faCpWyMClcb?= =?us-ascii?Q?3Y6pu7s6XAwfVUeptsvPqbCWcis2tnk303m+bhM57nrlxhSDo5jSOoJ7/wOh?= =?us-ascii?Q?z+//3hi/ccKwxWjXDB0HddgVlMxlWmfr5AxbaAGkBI94a93yREKr6M0usq5x?= =?us-ascii?Q?31IW0FdR3t9cf16TXTTvNVyJD/yisrmyjIY0hgXiaqaRGq4F2G7KUpeLrvph?= =?us-ascii?Q?DH/X0eh+EJ85mmWSL0dw/o7to8A0mB/ztQYf3545p9tsKm5T0WgsF6cteMQY?= =?us-ascii?Q?v1u/f32gyipAKlpOiu6gfX54TpaWfBqFjL8PNsDXr1t33bVskml8jN5EyBBs?= =?us-ascii?Q?1zLet9sGsmkLss0sbESb/cEMKR9htqWv91bpM/OIO0OHNvB4GBrV0LOq58BW?= =?us-ascii?Q?hMsm?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB3983.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Dec 2020 05:36:06.3635 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-Network-Message-Id: 6d4ed0b4-f2d0-4d11-d9d2-08d89ccd7db7 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 6tJTcHI4XwxEq1zG/hM/JVgHFcaFKhfeUYX1cdPfpwcbhQROxDDSDUEYOaHwuynsL+J6QleoFcjJCyYddjE5NQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB5454 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds bindings for i.MX8qxp/qm Display Processing Unit. Reviewed-by: Rob Herring Signed-off-by: Liu Ying --- Note that this depends on the 'two cell binding' clock patch set which has already landed in Shawn's i.MX clk/imx git branch. Otherwise, imx8-lpcg.h won't be found. v3->v4: * Improve compatible property by using enum instead of oneOf+const. (Rob) * Add Rob's R-b tag. v2->v3: * No change. v1->v2: * Fix yamllint warnings. * Require bypass0 and bypass1 clocks for both i.MX8qxp and i.MX8qm, as the display controller subsystem spec does say that they exist. * Use new dt binding way to add clocks in the example. * Trivial tweaks for the example. .../bindings/display/imx/fsl,imx8qxp-dpu.yaml | 416 +++++++++++++++++++++ 1 file changed, 416 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml new file mode 100644 index 00000000..817c7f3 --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml @@ -0,0 +1,416 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8qm/qxp Display Processing Unit + +maintainers: + - Liu Ying + +description: | + The Freescale i.MX8qm/qxp Display Processing Unit(DPU) is comprised of two + main components that include a blit engine for 2D graphics accelerations + and a display controller for display output processing, as well as a command + sequencer. + +properties: + compatible: + enum: + - fsl,imx8qxp-dpu + - fsl,imx8qm-dpu + + reg: + maxItems: 1 + + interrupts: + items: + - description: | + store9 shadow load interrupt(blit engine) + - description: | + store9 frame complete interrupt(blit engine) + - description: | + store9 sequence complete interrupt(blit engine) + - description: | + extdst0 shadow load interrupt + (display controller, content stream 0) + - description: | + extdst0 frame complete interrupt + (display controller, content stream 0) + - description: | + extdst0 sequence complete interrupt + (display controller, content stream 0) + - description: | + extdst4 shadow load interrupt + (display controller, safety stream 0) + - description: | + extdst4 frame complete interrupt + (display controller, safety stream 0) + - description: | + extdst4 sequence complete interrupt + (display controller, safety stream 0) + - description: | + extdst1 shadow load interrupt + (display controller, content stream 1) + - description: | + extdst1 frame complete interrupt + (display controller, content stream 1) + - description: | + extdst1 sequence complete interrupt + (display controller, content stream 1) + - description: | + extdst5 shadow load interrupt + (display controller, safety stream 1) + - description: | + extdst5 frame complete interrupt + (display controller, safety stream 1) + - description: | + extdst5 sequence complete interrupt + (display controller, safety stream 1) + - description: | + disengcfg0 shadow load interrupt + (display controller, display stream 0) + - description: | + disengcfg0 frame complete interrupt + (display controller, display stream 0) + - description: | + disengcfg0 sequence complete interrupt + (display controller, display stream 0) + - description: | + framegen0 programmable interrupt0 + (display controller, display stream 0) + - description: | + framegen0 programmable interrupt1 + (display controller, display stream 0) + - description: | + framegen0 programmable interrupt2 + (display controller, display stream 0) + - description: | + framegen0 programmable interrupt3 + (display controller, display stream 0) + - description: | + signature0 shadow load interrupt + (display controller, display stream 0) + - description: | + signature0 measurement valid interrupt + (display controller, display stream 0) + - description: | + signature0 error condition interrupt + (display controller, display stream 0) + - description: | + disengcfg1 shadow load interrupt + (display controller, display stream 1) + - description: | + disengcfg1 frame complete interrupt + (display controller, display stream 1) + - description: | + disengcfg1 sequence complete interrupt + (display controller, display stream 1) + - description: | + framegen1 programmable interrupt0 + (display controller, display stream 1) + - description: | + framegen1 programmable interrupt1 + (display controller, display stream 1) + - description: | + framegen1 programmable interrupt2 + (display controller, display stream 1) + - description: | + framegen1 programmable interrupt3 + (display controller, display stream 1) + - description: | + signature1 shadow load interrupt + (display controller, display stream 1) + - description: | + signature1 measurement valid interrupt + (display controller, display stream 1) + - description: | + signature1 error condition interrupt + (display controller, display stream 1) + - description: | + command sequencer error condition interrupt(command sequencer) + - description: | + common control software interrupt0(common control) + - description: | + common control software interrupt1(common control) + - description: | + common control software interrupt2(common control) + - description: | + common control software interrupt3(common control) + - description: | + framegen0 sychronization status activated interrupt + (display controller, safety stream 0) + - description: | + framegen0 sychronization status deactivated interrupt + (display controller, safety stream 0) + - description: | + framegen0 sychronization status activated interrupt + (display controller, content stream 0) + - description: | + framegen0 sychronization status deactivated interrupt + (display controller, content stream 0) + - description: | + framegen1 sychronization status activated interrupt + (display controller, safety stream 1) + - description: | + framegen1 sychronization status deactivated interrupt + (display controller, safety stream 1) + - description: | + framegen1 sychronization status activated interrupt + (display controller, content stream 1) + - description: | + framegen1 sychronization status deactivated interrupt + (display controller, content stream 1) + + interrupt-names: + items: + - const: store9_shdload + - const: store9_framecomplete + - const: store9_seqcomplete + - const: extdst0_shdload + - const: extdst0_framecomplete + - const: extdst0_seqcomplete + - const: extdst4_shdload + - const: extdst4_framecomplete + - const: extdst4_seqcomplete + - const: extdst1_shdload + - const: extdst1_framecomplete + - const: extdst1_seqcomplete + - const: extdst5_shdload + - const: extdst5_framecomplete + - const: extdst5_seqcomplete + - const: disengcfg_shdload0 + - const: disengcfg_framecomplete0 + - const: disengcfg_seqcomplete0 + - const: framegen0_int0 + - const: framegen0_int1 + - const: framegen0_int2 + - const: framegen0_int3 + - const: sig0_shdload + - const: sig0_valid + - const: sig0_error + - const: disengcfg_shdload1 + - const: disengcfg_framecomplete1 + - const: disengcfg_seqcomplete1 + - const: framegen1_int0 + - const: framegen1_int1 + - const: framegen1_int2 + - const: framegen1_int3 + - const: sig1_shdload + - const: sig1_valid + - const: sig1_error + - const: cmdseq_error + - const: comctrl_sw0 + - const: comctrl_sw1 + - const: comctrl_sw2 + - const: comctrl_sw3 + - const: framegen0_primsync_on + - const: framegen0_primsync_off + - const: framegen0_secsync_on + - const: framegen0_secsync_off + - const: framegen1_primsync_on + - const: framegen1_primsync_off + - const: framegen1_secsync_on + - const: framegen1_secsync_off + + clocks: + maxItems: 8 + + clock-names: + items: + - const: axi + - const: cfg + - const: pll0 + - const: pll1 + - const: bypass0 + - const: bypass1 + - const: disp0 + - const: disp1 + + power-domains: + items: + - description: DC power-domain + - description: PLL0 power-domain + - description: PLL1 power-domain + + power-domain-names: + items: + - const: dc + - const: pll0 + - const: pll1 + + fsl,dpr-channels: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + List of phandle which points to DPR channels associated with + this DPU instance. + + ports: + type: object + description: | + A node containing DPU output port nodes with endpoint definitions + as documented in + Documentation/devicetree/bindings/media/video-interfaces.txt + Documentation/devicetree/bindings/graph.txt + + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + port@0: + type: object + description: The DPU output port node from display stream0. + + properties: + reg: + const: 0 + + required: + - reg + + port@1: + type: object + description: The DPU output port node from display stream1. + + properties: + reg: + const: 1 + + required: + - reg + + required: + - "#address-cells" + - "#size-cells" + - port@0 + - port@1 + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + - power-domain-names + - fsl,dpr-channels + - ports + +additionalProperties: false + +examples: + - | + #include + #include + dpu@56180000 { + compatible = "fsl,imx8qxp-dpu"; + reg = <0x56180000 0x40000>; + interrupt-parent = <&dc0_irqsteer>; + interrupts = <448>, <449>, <450>, <64>, + <65>, <66>, <67>, <68>, + <69>, <70>, <193>, <194>, + <195>, <196>, <197>, <72>, + <73>, <74>, <75>, <76>, + <77>, <78>, <79>, <80>, + <81>, <199>, <200>, <201>, + <202>, <203>, <204>, <205>, + <206>, <207>, <208>, <0>, + <1>, <2>, <3>, <4>, + <82>, <83>, <84>, <85>, + <209>, <210>, <211>, <212>; + interrupt-names = "store9_shdload", + "store9_framecomplete", + "store9_seqcomplete", + "extdst0_shdload", + "extdst0_framecomplete", + "extdst0_seqcomplete", + "extdst4_shdload", + "extdst4_framecomplete", + "extdst4_seqcomplete", + "extdst1_shdload", + "extdst1_framecomplete", + "extdst1_seqcomplete", + "extdst5_shdload", + "extdst5_framecomplete", + "extdst5_seqcomplete", + "disengcfg_shdload0", + "disengcfg_framecomplete0", + "disengcfg_seqcomplete0", + "framegen0_int0", + "framegen0_int1", + "framegen0_int2", + "framegen0_int3", + "sig0_shdload", + "sig0_valid", + "sig0_error", + "disengcfg_shdload1", + "disengcfg_framecomplete1", + "disengcfg_seqcomplete1", + "framegen1_int0", + "framegen1_int1", + "framegen1_int2", + "framegen1_int3", + "sig1_shdload", + "sig1_valid", + "sig1_error", + "cmdseq_error", + "comctrl_sw0", + "comctrl_sw1", + "comctrl_sw2", + "comctrl_sw3", + "framegen0_primsync_on", + "framegen0_primsync_off", + "framegen0_secsync_on", + "framegen0_secsync_off", + "framegen1_primsync_on", + "framegen1_primsync_off", + "framegen1_secsync_on", + "framegen1_secsync_off"; + clocks = <&dc0_dpu_lpcg IMX_LPCG_CLK_5>, + <&dc0_dpu_lpcg IMX_LPCG_CLK_4>, + <&clk IMX_SC_R_DC_0_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_0_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_0_VIDEO0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_DC_0_VIDEO1 IMX_SC_PM_CLK_BYPASS>, + <&dc0_disp_lpcg IMX_LPCG_CLK_0>, + <&dc0_disp_lpcg IMX_LPCG_CLK_1>; + clock-names = "axi", "cfg", + "pll0", "pll1", "bypass0", "bypass1", + "disp0", "disp1"; + power-domains = <&pd IMX_SC_R_DC_0>, + <&pd IMX_SC_R_DC_0_PLL_0>, + <&pd IMX_SC_R_DC_0_PLL_1>; + power-domain-names = "dc", "pll0", "pll1"; + fsl,dpr-channels = <&dc0_dpr1_channel1>, + <&dc0_dpr1_channel2>, + <&dc0_dpr1_channel3>, + <&dc0_dpr2_channel1>, + <&dc0_dpr2_channel2>, + <&dc0_dpr2_channel3>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu0_disp0_pixel_combiner0_ch0: endpoint { + remote-endpoint = <&pixel_combiner0_ch0_dpu0_disp0>; + }; + }; + + port@1 { + reg = <1>; + dpu0_disp1_pixel_combiner0_ch1: endpoint { + remote-endpoint = <&pixel_combiner0_ch1_dpu0_disp1>; + }; + }; + }; + }; -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, 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guido.gunther@puri.sm, shawnguo@kernel.org, kernel@pengutronix.de Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch adds bindings for i.MX8qxp/qm Display Processing Unit. Reviewed-by: Rob Herring Signed-off-by: Liu Ying --- Note that this depends on the 'two cell binding' clock patch set which has already landed in Shawn's i.MX clk/imx git branch. Otherwise, imx8-lpcg.h won't be found. v3->v4: * Improve compatible property by using enum instead of oneOf+const. (Rob) * Add Rob's R-b tag. v2->v3: * No change. v1->v2: * Fix yamllint warnings. * Require bypass0 and bypass1 clocks for both i.MX8qxp and i.MX8qm, as the display controller subsystem spec does say that they exist. * Use new dt binding way to add clocks in the example. * Trivial tweaks for the example. .../bindings/display/imx/fsl,imx8qxp-dpu.yaml | 416 +++++++++++++++++++++ 1 file changed, 416 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml new file mode 100644 index 00000000..817c7f3 --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml @@ -0,0 +1,416 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8qm/qxp Display Processing Unit + +maintainers: + - Liu Ying + +description: | + The Freescale i.MX8qm/qxp Display Processing Unit(DPU) is comprised of two + main components that include a blit engine for 2D graphics accelerations + and a display controller for display output processing, as well as a command + sequencer. + +properties: + compatible: + enum: + - fsl,imx8qxp-dpu + - fsl,imx8qm-dpu + + reg: + maxItems: 1 + + interrupts: + items: + - description: | + store9 shadow load interrupt(blit engine) + - description: | + store9 frame complete interrupt(blit engine) + - description: | + store9 sequence complete interrupt(blit engine) + - description: | + extdst0 shadow load interrupt + (display controller, content stream 0) + - description: | + extdst0 frame complete interrupt + (display controller, content stream 0) + - description: | + extdst0 sequence complete interrupt + (display controller, content stream 0) + - description: | + extdst4 shadow load interrupt + (display controller, safety stream 0) + - description: | + extdst4 frame complete interrupt + (display controller, safety stream 0) + - description: | + extdst4 sequence complete interrupt + (display controller, safety stream 0) + - description: | + extdst1 shadow load interrupt + (display controller, content stream 1) + - description: | + extdst1 frame complete interrupt + (display controller, content stream 1) + - description: | + extdst1 sequence complete interrupt + (display controller, content stream 1) + - description: | + extdst5 shadow load interrupt + (display controller, safety stream 1) + - description: | + extdst5 frame complete interrupt + (display controller, safety stream 1) + - description: | + extdst5 sequence complete interrupt + (display controller, safety stream 1) + - description: | + disengcfg0 shadow load interrupt + (display controller, display stream 0) + - description: | + disengcfg0 frame complete interrupt + (display controller, display stream 0) + - description: | + disengcfg0 sequence complete interrupt + (display controller, display stream 0) + - description: | + framegen0 programmable interrupt0 + (display controller, display stream 0) + - description: | + framegen0 programmable interrupt1 + (display controller, display stream 0) + - description: | + framegen0 programmable interrupt2 + (display controller, display stream 0) + - description: | + framegen0 programmable interrupt3 + (display controller, display stream 0) + - description: | + signature0 shadow load interrupt + (display controller, display stream 0) + - description: | + signature0 measurement valid interrupt + (display controller, display stream 0) + - description: | + signature0 error condition interrupt + (display controller, display stream 0) + - description: | + disengcfg1 shadow load interrupt + (display controller, display stream 1) + - description: | + disengcfg1 frame complete interrupt + (display controller, display stream 1) + - description: | + disengcfg1 sequence complete interrupt + (display controller, display stream 1) + - description: | + framegen1 programmable interrupt0 + (display controller, display stream 1) + - description: | + framegen1 programmable interrupt1 + (display controller, display stream 1) + - description: | + framegen1 programmable interrupt2 + (display controller, display stream 1) + - description: | + framegen1 programmable interrupt3 + (display controller, display stream 1) + - description: | + signature1 shadow load interrupt + (display controller, display stream 1) + - description: | + signature1 measurement valid interrupt + (display controller, display stream 1) + - description: | + signature1 error condition interrupt + (display controller, display stream 1) + - description: | + command sequencer error condition interrupt(command sequencer) + - description: | + common control software interrupt0(common control) + - description: | + common control software interrupt1(common control) + - description: | + common control software interrupt2(common control) + - description: | + common control software interrupt3(common control) + - description: | + framegen0 sychronization status activated interrupt + (display controller, safety stream 0) + - description: | + framegen0 sychronization status deactivated interrupt + (display controller, safety stream 0) + - description: | + framegen0 sychronization status activated interrupt + (display controller, content stream 0) + - description: | + framegen0 sychronization status deactivated interrupt + (display controller, content stream 0) + - description: | + framegen1 sychronization status activated interrupt + (display controller, safety stream 1) + - description: | + framegen1 sychronization status deactivated interrupt + (display controller, safety stream 1) + - description: | + framegen1 sychronization status activated interrupt + (display controller, content stream 1) + - description: | + framegen1 sychronization status deactivated interrupt + (display controller, content stream 1) + + interrupt-names: + items: + - const: store9_shdload + - const: store9_framecomplete + - const: store9_seqcomplete + - const: extdst0_shdload + - const: extdst0_framecomplete + - const: extdst0_seqcomplete + - const: extdst4_shdload + - const: extdst4_framecomplete + - const: extdst4_seqcomplete + - const: extdst1_shdload + - const: extdst1_framecomplete + - const: extdst1_seqcomplete + - const: extdst5_shdload + - const: extdst5_framecomplete + - const: extdst5_seqcomplete + - const: disengcfg_shdload0 + - const: disengcfg_framecomplete0 + - const: disengcfg_seqcomplete0 + - const: framegen0_int0 + - const: framegen0_int1 + - const: framegen0_int2 + - const: framegen0_int3 + - const: sig0_shdload + - const: sig0_valid + - const: sig0_error + - const: disengcfg_shdload1 + - const: disengcfg_framecomplete1 + - const: disengcfg_seqcomplete1 + - const: framegen1_int0 + - const: framegen1_int1 + - const: framegen1_int2 + - const: framegen1_int3 + - const: sig1_shdload + - const: sig1_valid + - const: sig1_error + - const: cmdseq_error + - const: comctrl_sw0 + - const: comctrl_sw1 + - const: comctrl_sw2 + - const: comctrl_sw3 + - const: framegen0_primsync_on + - const: framegen0_primsync_off + - const: framegen0_secsync_on + - const: framegen0_secsync_off + - const: framegen1_primsync_on + - const: framegen1_primsync_off + - const: framegen1_secsync_on + - const: framegen1_secsync_off + + clocks: + maxItems: 8 + + clock-names: + items: + - const: axi + - const: cfg + - const: pll0 + - const: pll1 + - const: bypass0 + - const: bypass1 + - const: disp0 + - const: disp1 + + power-domains: + items: + - description: DC power-domain + - description: PLL0 power-domain + - description: PLL1 power-domain + + power-domain-names: + items: + - const: dc + - const: pll0 + - const: pll1 + + fsl,dpr-channels: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + List of phandle which points to DPR channels associated with + this DPU instance. + + ports: + type: object + description: | + A node containing DPU output port nodes with endpoint definitions + as documented in + Documentation/devicetree/bindings/media/video-interfaces.txt + Documentation/devicetree/bindings/graph.txt + + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + port@0: + type: object + description: The DPU output port node from display stream0. + + properties: + reg: + const: 0 + + required: + - reg + + port@1: + type: object + description: The DPU output port node from display stream1. + + properties: + reg: + const: 1 + + required: + - reg + + required: + - "#address-cells" + - "#size-cells" + - port@0 + - port@1 + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + - power-domain-names + - fsl,dpr-channels + - ports + +additionalProperties: false + +examples: + - | + #include + #include + dpu@56180000 { + compatible = "fsl,imx8qxp-dpu"; + reg = <0x56180000 0x40000>; + interrupt-parent = <&dc0_irqsteer>; + interrupts = <448>, <449>, <450>, <64>, + <65>, <66>, <67>, <68>, + <69>, <70>, <193>, <194>, + <195>, <196>, <197>, <72>, + <73>, <74>, <75>, <76>, + <77>, <78>, <79>, <80>, + <81>, <199>, <200>, <201>, + <202>, <203>, <204>, <205>, + <206>, <207>, <208>, <0>, + <1>, <2>, <3>, <4>, + <82>, <83>, <84>, <85>, + <209>, <210>, <211>, <212>; + interrupt-names = "store9_shdload", + "store9_framecomplete", + "store9_seqcomplete", + "extdst0_shdload", + "extdst0_framecomplete", + "extdst0_seqcomplete", + "extdst4_shdload", + "extdst4_framecomplete", + "extdst4_seqcomplete", + "extdst1_shdload", + "extdst1_framecomplete", + "extdst1_seqcomplete", + "extdst5_shdload", + "extdst5_framecomplete", + "extdst5_seqcomplete", + "disengcfg_shdload0", + "disengcfg_framecomplete0", + "disengcfg_seqcomplete0", + "framegen0_int0", + "framegen0_int1", + "framegen0_int2", + "framegen0_int3", + "sig0_shdload", + "sig0_valid", + "sig0_error", + "disengcfg_shdload1", + "disengcfg_framecomplete1", + "disengcfg_seqcomplete1", + "framegen1_int0", + "framegen1_int1", + "framegen1_int2", + "framegen1_int3", + "sig1_shdload", + "sig1_valid", + "sig1_error", + "cmdseq_error", + "comctrl_sw0", + "comctrl_sw1", + "comctrl_sw2", + "comctrl_sw3", + "framegen0_primsync_on", + "framegen0_primsync_off", + "framegen0_secsync_on", + "framegen0_secsync_off", + "framegen1_primsync_on", + "framegen1_primsync_off", + "framegen1_secsync_on", + "framegen1_secsync_off"; + clocks = <&dc0_dpu_lpcg IMX_LPCG_CLK_5>, + <&dc0_dpu_lpcg IMX_LPCG_CLK_4>, + <&clk IMX_SC_R_DC_0_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_0_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_0_VIDEO0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_DC_0_VIDEO1 IMX_SC_PM_CLK_BYPASS>, + <&dc0_disp_lpcg IMX_LPCG_CLK_0>, + <&dc0_disp_lpcg IMX_LPCG_CLK_1>; + clock-names = "axi", "cfg", + "pll0", "pll1", "bypass0", "bypass1", + "disp0", "disp1"; + power-domains = <&pd IMX_SC_R_DC_0>, + <&pd IMX_SC_R_DC_0_PLL_0>, + <&pd IMX_SC_R_DC_0_PLL_1>; + power-domain-names = "dc", "pll0", "pll1"; + fsl,dpr-channels = <&dc0_dpr1_channel1>, + <&dc0_dpr1_channel2>, + <&dc0_dpr1_channel3>, + <&dc0_dpr2_channel1>, + <&dc0_dpr2_channel2>, + <&dc0_dpr2_channel3>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu0_disp0_pixel_combiner0_ch0: endpoint { + remote-endpoint = <&pixel_combiner0_ch0_dpu0_disp0>; + }; + }; + + port@1 { + reg = <1>; + dpu0_disp1_pixel_combiner0_ch1: endpoint { + remote-endpoint = <&pixel_combiner0_ch1_dpu0_disp1>; + }; + }; + }; + }; -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on 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Sender: "dri-devel" This patch adds bindings for i.MX8qxp/qm Display Processing Unit. Reviewed-by: Rob Herring Signed-off-by: Liu Ying --- Note that this depends on the 'two cell binding' clock patch set which has already landed in Shawn's i.MX clk/imx git branch. Otherwise, imx8-lpcg.h won't be found. v3->v4: * Improve compatible property by using enum instead of oneOf+const. (Rob) * Add Rob's R-b tag. v2->v3: * No change. v1->v2: * Fix yamllint warnings. * Require bypass0 and bypass1 clocks for both i.MX8qxp and i.MX8qm, as the display controller subsystem spec does say that they exist. * Use new dt binding way to add clocks in the example. * Trivial tweaks for the example. .../bindings/display/imx/fsl,imx8qxp-dpu.yaml | 416 +++++++++++++++++++++ 1 file changed, 416 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml new file mode 100644 index 00000000..817c7f3 --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml @@ -0,0 +1,416 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8qm/qxp Display Processing Unit + +maintainers: + - Liu Ying + +description: | + The Freescale i.MX8qm/qxp Display Processing Unit(DPU) is comprised of two + main components that include a blit engine for 2D graphics accelerations + and a display controller for display output processing, as well as a command + sequencer. + +properties: + compatible: + enum: + - fsl,imx8qxp-dpu + - fsl,imx8qm-dpu + + reg: + maxItems: 1 + + interrupts: + items: + - description: | + store9 shadow load interrupt(blit engine) + - description: | + store9 frame complete interrupt(blit engine) + - description: | + store9 sequence complete interrupt(blit engine) + - description: | + extdst0 shadow load interrupt + (display controller, content stream 0) + - description: | + extdst0 frame complete interrupt + (display controller, content stream 0) + - description: | + extdst0 sequence complete interrupt + (display controller, content stream 0) + - description: | + extdst4 shadow load interrupt + (display controller, safety stream 0) + - description: | + extdst4 frame complete interrupt + (display controller, safety stream 0) + - description: | + extdst4 sequence complete interrupt + (display controller, safety stream 0) + - description: | + extdst1 shadow load interrupt + (display controller, content stream 1) + - description: | + extdst1 frame complete interrupt + (display controller, content stream 1) + - description: | + extdst1 sequence complete interrupt + (display controller, content stream 1) + - description: | + extdst5 shadow load interrupt + (display controller, safety stream 1) + - description: | + extdst5 frame complete interrupt + (display controller, safety stream 1) + - description: | + extdst5 sequence complete interrupt + (display controller, safety stream 1) + - description: | + disengcfg0 shadow load interrupt + (display controller, display stream 0) + - description: | + disengcfg0 frame complete interrupt + (display controller, display stream 0) + - description: | + disengcfg0 sequence complete interrupt + (display controller, display stream 0) + - description: | + framegen0 programmable interrupt0 + (display controller, display stream 0) + - description: | + framegen0 programmable interrupt1 + (display controller, display stream 0) + - description: | + framegen0 programmable interrupt2 + (display controller, display stream 0) + - description: | + framegen0 programmable interrupt3 + (display controller, display stream 0) + - description: | + signature0 shadow load interrupt + (display controller, display stream 0) + - description: | + signature0 measurement valid interrupt + (display controller, display stream 0) + - description: | + signature0 error condition interrupt + (display controller, display stream 0) + - description: | + disengcfg1 shadow load interrupt + (display controller, display stream 1) + - description: | + disengcfg1 frame complete interrupt + (display controller, display stream 1) + - description: | + disengcfg1 sequence complete interrupt + (display controller, display stream 1) + - description: | + framegen1 programmable interrupt0 + (display controller, display stream 1) + - description: | + framegen1 programmable interrupt1 + (display controller, display stream 1) + - description: | + framegen1 programmable interrupt2 + (display controller, display stream 1) + - description: | + framegen1 programmable interrupt3 + (display controller, display stream 1) + - description: | + signature1 shadow load interrupt + (display controller, display stream 1) + - description: | + signature1 measurement valid interrupt + (display controller, display stream 1) + - description: | + signature1 error condition interrupt + (display controller, display stream 1) + - description: | + command sequencer error condition interrupt(command sequencer) + - description: | + common control software interrupt0(common control) + - description: | + common control software interrupt1(common control) + - description: | + common control software interrupt2(common control) + - description: | + common control software interrupt3(common control) + - description: | + framegen0 sychronization status activated interrupt + (display controller, safety stream 0) + - description: | + framegen0 sychronization status deactivated interrupt + (display controller, safety stream 0) + - description: | + framegen0 sychronization status activated interrupt + (display controller, content stream 0) + - description: | + framegen0 sychronization status deactivated interrupt + (display controller, content stream 0) + - description: | + framegen1 sychronization status activated interrupt + (display controller, safety stream 1) + - description: | + framegen1 sychronization status deactivated interrupt + (display controller, safety stream 1) + - description: | + framegen1 sychronization status activated interrupt + (display controller, content stream 1) + - description: | + framegen1 sychronization status deactivated interrupt + (display controller, content stream 1) + + interrupt-names: + items: + - const: store9_shdload + - const: store9_framecomplete + - const: store9_seqcomplete + - const: extdst0_shdload + - const: extdst0_framecomplete + - const: extdst0_seqcomplete + - const: extdst4_shdload + - const: extdst4_framecomplete + - const: extdst4_seqcomplete + - const: extdst1_shdload + - const: extdst1_framecomplete + - const: extdst1_seqcomplete + - const: extdst5_shdload + - const: extdst5_framecomplete + - const: extdst5_seqcomplete + - const: disengcfg_shdload0 + - const: disengcfg_framecomplete0 + - const: disengcfg_seqcomplete0 + - const: framegen0_int0 + - const: framegen0_int1 + - const: framegen0_int2 + - const: framegen0_int3 + - const: sig0_shdload + - const: sig0_valid + - const: sig0_error + - const: disengcfg_shdload1 + - const: disengcfg_framecomplete1 + - const: disengcfg_seqcomplete1 + - const: framegen1_int0 + - const: framegen1_int1 + - const: framegen1_int2 + - const: framegen1_int3 + - const: sig1_shdload + - const: sig1_valid + - const: sig1_error + - const: cmdseq_error + - const: comctrl_sw0 + - const: comctrl_sw1 + - const: comctrl_sw2 + - const: comctrl_sw3 + - const: framegen0_primsync_on + - const: framegen0_primsync_off + - const: framegen0_secsync_on + - const: framegen0_secsync_off + - const: framegen1_primsync_on + - const: framegen1_primsync_off + - const: framegen1_secsync_on + - const: framegen1_secsync_off + + clocks: + maxItems: 8 + + clock-names: + items: + - const: axi + - const: cfg + - const: pll0 + - const: pll1 + - const: bypass0 + - const: bypass1 + - const: disp0 + - const: disp1 + + power-domains: + items: + - description: DC power-domain + - description: PLL0 power-domain + - description: PLL1 power-domain + + power-domain-names: + items: + - const: dc + - const: pll0 + - const: pll1 + + fsl,dpr-channels: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + List of phandle which points to DPR channels associated with + this DPU instance. + + ports: + type: object + description: | + A node containing DPU output port nodes with endpoint definitions + as documented in + Documentation/devicetree/bindings/media/video-interfaces.txt + Documentation/devicetree/bindings/graph.txt + + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + port@0: + type: object + description: The DPU output port node from display stream0. + + properties: + reg: + const: 0 + + required: + - reg + + port@1: + type: object + description: The DPU output port node from display stream1. + + properties: + reg: + const: 1 + + required: + - reg + + required: + - "#address-cells" + - "#size-cells" + - port@0 + - port@1 + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + - power-domain-names + - fsl,dpr-channels + - ports + +additionalProperties: false + +examples: + - | + #include + #include + dpu@56180000 { + compatible = "fsl,imx8qxp-dpu"; + reg = <0x56180000 0x40000>; + interrupt-parent = <&dc0_irqsteer>; + interrupts = <448>, <449>, <450>, <64>, + <65>, <66>, <67>, <68>, + <69>, <70>, <193>, <194>, + <195>, <196>, <197>, <72>, + <73>, <74>, <75>, <76>, + <77>, <78>, <79>, <80>, + <81>, <199>, <200>, <201>, + <202>, <203>, <204>, <205>, + <206>, <207>, <208>, <0>, + <1>, <2>, <3>, <4>, + <82>, <83>, <84>, <85>, + <209>, <210>, <211>, <212>; + interrupt-names = "store9_shdload", + "store9_framecomplete", + "store9_seqcomplete", + "extdst0_shdload", + "extdst0_framecomplete", + "extdst0_seqcomplete", + "extdst4_shdload", + "extdst4_framecomplete", + "extdst4_seqcomplete", + "extdst1_shdload", + "extdst1_framecomplete", + "extdst1_seqcomplete", + "extdst5_shdload", + "extdst5_framecomplete", + "extdst5_seqcomplete", + "disengcfg_shdload0", + "disengcfg_framecomplete0", + "disengcfg_seqcomplete0", + "framegen0_int0", + "framegen0_int1", + "framegen0_int2", + "framegen0_int3", + "sig0_shdload", + "sig0_valid", + "sig0_error", + "disengcfg_shdload1", + "disengcfg_framecomplete1", + "disengcfg_seqcomplete1", + "framegen1_int0", + "framegen1_int1", + "framegen1_int2", + "framegen1_int3", + "sig1_shdload", + "sig1_valid", + "sig1_error", + "cmdseq_error", + "comctrl_sw0", + "comctrl_sw1", + "comctrl_sw2", + "comctrl_sw3", + "framegen0_primsync_on", + "framegen0_primsync_off", + "framegen0_secsync_on", + "framegen0_secsync_off", + "framegen1_primsync_on", + "framegen1_primsync_off", + "framegen1_secsync_on", + "framegen1_secsync_off"; + clocks = <&dc0_dpu_lpcg IMX_LPCG_CLK_5>, + <&dc0_dpu_lpcg IMX_LPCG_CLK_4>, + <&clk IMX_SC_R_DC_0_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_0_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_0_VIDEO0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_DC_0_VIDEO1 IMX_SC_PM_CLK_BYPASS>, + <&dc0_disp_lpcg IMX_LPCG_CLK_0>, + <&dc0_disp_lpcg IMX_LPCG_CLK_1>; + clock-names = "axi", "cfg", + "pll0", "pll1", "bypass0", "bypass1", + "disp0", "disp1"; + power-domains = <&pd IMX_SC_R_DC_0>, + <&pd IMX_SC_R_DC_0_PLL_0>, + <&pd IMX_SC_R_DC_0_PLL_1>; + power-domain-names = "dc", "pll0", "pll1"; + fsl,dpr-channels = <&dc0_dpr1_channel1>, + <&dc0_dpr1_channel2>, + <&dc0_dpr1_channel3>, + <&dc0_dpr2_channel1>, + <&dc0_dpr2_channel2>, + <&dc0_dpr2_channel3>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu0_disp0_pixel_combiner0_ch0: endpoint { + remote-endpoint = <&pixel_combiner0_ch0_dpu0_disp0>; + }; + }; + + port@1 { + reg = <1>; + dpu0_disp1_pixel_combiner0_ch1: endpoint { + remote-endpoint = <&pixel_combiner0_ch1_dpu0_disp1>; + }; + }; + }; + }; -- 2.7.4 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel