From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 736B0C4361B for ; Thu, 10 Dec 2020 09:09:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3FEA522C7D for ; Thu, 10 Dec 2020 09:09:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731802AbgLJJIq (ORCPT ); Thu, 10 Dec 2020 04:08:46 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:41680 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1730371AbgLJJIf (ORCPT ); Thu, 10 Dec 2020 04:08:35 -0500 X-UUID: a1c1bd23ace44675936efed2d0295c06-20201210 X-UUID: a1c1bd23ace44675936efed2d0295c06-20201210 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1826352770; Thu, 10 Dec 2020 17:07:48 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 10 Dec 2020 17:07:46 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 10 Dec 2020 17:07:45 +0800 From: Yongqiang Niu To: CK Hu , Philipp Zabel , Rob Herring , Matthias Brugger CC: David Airlie , Daniel Vetter , Mark Rutland , , , , , , Yongqiang Niu Subject: [PATCH v8, 3/6] soc: mediatek: mmsys: add mt8183 function call for setting the routing registers Date: Thu, 10 Dec 2020 17:07:39 +0800 Message-ID: <1607591262-21736-4-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1607591262-21736-1-git-send-email-yongqiang.niu@mediatek.com> References: <1607591262-21736-1-git-send-email-yongqiang.niu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org add mt8183 function call for setting the routing registers Signed-off-by: Yongqiang Niu --- drivers/soc/mediatek/mmsys/Makefile | 1 + drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 90 +++++++++++++++++++++++++++++++ drivers/soc/mediatek/mmsys/mtk-mmsys.c | 1 + include/linux/soc/mediatek/mtk-mmsys.h | 1 + 4 files changed, 93 insertions(+) create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile index ac03025..25eeb9e5 100644 --- a/drivers/soc/mediatek/mmsys/Makefile +++ b/drivers/soc/mediatek/mmsys/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o +obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o diff --git a/drivers/soc/mediatek/mmsys/mt8183-mmsys.c b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c new file mode 100644 index 0000000..192b4ab --- /dev/null +++ b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2020 MediaTek Inc. + +#include +#include +#include +#include +#include + +#define DISP_OVL0_MOUT_EN 0xf00 +#define DISP_OVL0_2L_MOUT_EN 0xf04 +#define DISP_OVL1_2L_MOUT_EN 0xf08 +#define DISP_DITHER0_MOUT_EN 0xf0c +#define DISP_PATH0_SEL_IN 0xf24 +#define DISP_DSI0_SEL_IN 0xf2c +#define DISP_DPI0_SEL_IN 0xf30 +#define DISP_RDMA0_SOUT_SEL_IN 0xf50 +#define DISP_RDMA1_SOUT_SEL_IN 0xf54 + +#define OVL0_MOUT_EN_OVL0_2L BIT(4) +#define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0) +#define OVL1_2L_MOUT_EN_RDMA1 BIT(4) +#define DITHER0_MOUT_IN_DSI0 BIT(0) +#define DISP_PATH0_SEL_IN_OVL0_2L 0x1 +#define DSI0_SEL_IN_RDMA0 0x1 +#define DSI0_SEL_IN_RDMA1 0x3 +#define DPI0_SEL_IN_RDMA0 0x1 +#define DPI0_SEL_IN_RDMA1 0x2 +#define RDMA0_SOUT_COLOR0 0x1 +#define RDMA1_SOUT_DSI0 0x1 + +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0) { + *addr = DISP_OVL0_MOUT_EN; + value = OVL0_MOUT_EN_OVL0_2L; + } else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_OVL0_2L_MOUT_EN; + value = OVL0_2L_MOUT_EN_DISP_PATH0; + } else if (cur == DDP_COMPONENT_OVL_2L1 && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_OVL1_2L_MOUT_EN; + value = OVL1_2L_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) { + *addr = DISP_DITHER0_MOUT_EN; + value = DITHER0_MOUT_IN_DSI0; + } else { + value = 0; + } + + return value; +} + +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_PATH0_SEL_IN; + value = DISP_PATH0_SEL_IN_OVL0_2L; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_DPI0_SEL_IN; + value = DPI0_SEL_IN_RDMA1; + } else { + value = 0; + } + + return value; +} + +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) { + writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + DISP_RDMA0_SOUT_SEL_IN); + } +} + +struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs = { + .mout_en = mtk_mmsys_ddp_mout_en, + .sel_in = mtk_mmsys_ddp_sel_in, + .sout_sel = mtk_mmsys_ddp_sout_sel, +}; diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c index 9d6a3e9..63e1a63 100644 --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c @@ -42,6 +42,7 @@ struct mtk_mmsys_driver_data { static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .clk_driver = "clk-mt8183-mm", + .funcs = &mt8183_mmsys_funcs, }; struct mtk_mmsys { diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 17e8b91..4b6c514 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -55,6 +55,7 @@ struct mtk_mmsys_conn_funcs { }; extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs; +extern struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs; void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, -- 1.8.1.1.dirty From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06656C4361B for ; Thu, 10 Dec 2020 09:08:09 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9DBAA23B99 for ; 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Thu, 10 Dec 2020 01:07:50 -0800 Received: from mtkmbs05n2.mediatek.inc (172.21.101.140) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 10 Dec 2020 01:07:48 -0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 10 Dec 2020 17:07:46 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 10 Dec 2020 17:07:45 +0800 From: Yongqiang Niu To: CK Hu , Philipp Zabel , "Rob Herring" , Matthias Brugger Subject: [PATCH v8, 3/6] soc: mediatek: mmsys: add mt8183 function call for setting the routing registers Date: Thu, 10 Dec 2020 17:07:39 +0800 Message-ID: <1607591262-21736-4-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1607591262-21736-1-git-send-email-yongqiang.niu@mediatek.com> References: <1607591262-21736-1-git-send-email-yongqiang.niu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201210_040754_849862_B163E018 X-CRM114-Status: GOOD ( 20.89 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Yongqiang Niu , David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, Daniel Vetter , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org add mt8183 function call for setting the routing registers Signed-off-by: Yongqiang Niu --- drivers/soc/mediatek/mmsys/Makefile | 1 + drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 90 +++++++++++++++++++++++++++++++ drivers/soc/mediatek/mmsys/mtk-mmsys.c | 1 + include/linux/soc/mediatek/mtk-mmsys.h | 1 + 4 files changed, 93 insertions(+) create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile index ac03025..25eeb9e5 100644 --- a/drivers/soc/mediatek/mmsys/Makefile +++ b/drivers/soc/mediatek/mmsys/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o +obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o diff --git a/drivers/soc/mediatek/mmsys/mt8183-mmsys.c b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c new file mode 100644 index 0000000..192b4ab --- /dev/null +++ b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2020 MediaTek Inc. + +#include +#include +#include +#include +#include + +#define DISP_OVL0_MOUT_EN 0xf00 +#define DISP_OVL0_2L_MOUT_EN 0xf04 +#define DISP_OVL1_2L_MOUT_EN 0xf08 +#define DISP_DITHER0_MOUT_EN 0xf0c +#define DISP_PATH0_SEL_IN 0xf24 +#define DISP_DSI0_SEL_IN 0xf2c +#define DISP_DPI0_SEL_IN 0xf30 +#define DISP_RDMA0_SOUT_SEL_IN 0xf50 +#define DISP_RDMA1_SOUT_SEL_IN 0xf54 + +#define OVL0_MOUT_EN_OVL0_2L BIT(4) +#define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0) +#define OVL1_2L_MOUT_EN_RDMA1 BIT(4) +#define DITHER0_MOUT_IN_DSI0 BIT(0) +#define DISP_PATH0_SEL_IN_OVL0_2L 0x1 +#define DSI0_SEL_IN_RDMA0 0x1 +#define DSI0_SEL_IN_RDMA1 0x3 +#define DPI0_SEL_IN_RDMA0 0x1 +#define DPI0_SEL_IN_RDMA1 0x2 +#define RDMA0_SOUT_COLOR0 0x1 +#define RDMA1_SOUT_DSI0 0x1 + +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0) { + *addr = DISP_OVL0_MOUT_EN; + value = OVL0_MOUT_EN_OVL0_2L; + } else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_OVL0_2L_MOUT_EN; + value = OVL0_2L_MOUT_EN_DISP_PATH0; + } else if (cur == DDP_COMPONENT_OVL_2L1 && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_OVL1_2L_MOUT_EN; + value = OVL1_2L_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) { + *addr = DISP_DITHER0_MOUT_EN; + value = DITHER0_MOUT_IN_DSI0; + } else { + value = 0; + } + + return value; +} + +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_PATH0_SEL_IN; + value = DISP_PATH0_SEL_IN_OVL0_2L; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_DPI0_SEL_IN; + value = DPI0_SEL_IN_RDMA1; + } else { + value = 0; + } + + return value; +} + +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) { + writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + DISP_RDMA0_SOUT_SEL_IN); + } +} + +struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs = { + .mout_en = mtk_mmsys_ddp_mout_en, + .sel_in = mtk_mmsys_ddp_sel_in, + .sout_sel = mtk_mmsys_ddp_sout_sel, +}; diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c index 9d6a3e9..63e1a63 100644 --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c @@ -42,6 +42,7 @@ struct mtk_mmsys_driver_data { static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .clk_driver = "clk-mt8183-mm", + .funcs = &mt8183_mmsys_funcs, }; struct mtk_mmsys { diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 17e8b91..4b6c514 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -55,6 +55,7 @@ struct mtk_mmsys_conn_funcs { }; extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs; +extern struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs; void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, -- 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25499C4361B for ; Thu, 10 Dec 2020 09:09:29 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CBF3222C7D for ; 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Thu, 10 Dec 2020 01:07:50 -0800 Received: from mtkmbs05n2.mediatek.inc (172.21.101.140) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 10 Dec 2020 01:07:48 -0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 10 Dec 2020 17:07:46 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 10 Dec 2020 17:07:45 +0800 From: Yongqiang Niu To: CK Hu , Philipp Zabel , "Rob Herring" , Matthias Brugger Subject: [PATCH v8, 3/6] soc: mediatek: mmsys: add mt8183 function call for setting the routing registers Date: Thu, 10 Dec 2020 17:07:39 +0800 Message-ID: <1607591262-21736-4-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1607591262-21736-1-git-send-email-yongqiang.niu@mediatek.com> References: <1607591262-21736-1-git-send-email-yongqiang.niu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201210_040754_849862_B163E018 X-CRM114-Status: GOOD ( 20.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Yongqiang Niu , David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, Daniel Vetter , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org add mt8183 function call for setting the routing registers Signed-off-by: Yongqiang Niu --- drivers/soc/mediatek/mmsys/Makefile | 1 + drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 90 +++++++++++++++++++++++++++++++ drivers/soc/mediatek/mmsys/mtk-mmsys.c | 1 + include/linux/soc/mediatek/mtk-mmsys.h | 1 + 4 files changed, 93 insertions(+) create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile index ac03025..25eeb9e5 100644 --- a/drivers/soc/mediatek/mmsys/Makefile +++ b/drivers/soc/mediatek/mmsys/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o +obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o diff --git a/drivers/soc/mediatek/mmsys/mt8183-mmsys.c b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c new file mode 100644 index 0000000..192b4ab --- /dev/null +++ b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2020 MediaTek Inc. + +#include +#include +#include +#include +#include + +#define DISP_OVL0_MOUT_EN 0xf00 +#define DISP_OVL0_2L_MOUT_EN 0xf04 +#define DISP_OVL1_2L_MOUT_EN 0xf08 +#define DISP_DITHER0_MOUT_EN 0xf0c +#define DISP_PATH0_SEL_IN 0xf24 +#define DISP_DSI0_SEL_IN 0xf2c +#define DISP_DPI0_SEL_IN 0xf30 +#define DISP_RDMA0_SOUT_SEL_IN 0xf50 +#define DISP_RDMA1_SOUT_SEL_IN 0xf54 + +#define OVL0_MOUT_EN_OVL0_2L BIT(4) +#define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0) +#define OVL1_2L_MOUT_EN_RDMA1 BIT(4) +#define DITHER0_MOUT_IN_DSI0 BIT(0) +#define DISP_PATH0_SEL_IN_OVL0_2L 0x1 +#define DSI0_SEL_IN_RDMA0 0x1 +#define DSI0_SEL_IN_RDMA1 0x3 +#define DPI0_SEL_IN_RDMA0 0x1 +#define DPI0_SEL_IN_RDMA1 0x2 +#define RDMA0_SOUT_COLOR0 0x1 +#define RDMA1_SOUT_DSI0 0x1 + +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0) { + *addr = DISP_OVL0_MOUT_EN; + value = OVL0_MOUT_EN_OVL0_2L; + } else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_OVL0_2L_MOUT_EN; + value = OVL0_2L_MOUT_EN_DISP_PATH0; + } else if (cur == DDP_COMPONENT_OVL_2L1 && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_OVL1_2L_MOUT_EN; + value = OVL1_2L_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) { + *addr = DISP_DITHER0_MOUT_EN; + value = DITHER0_MOUT_IN_DSI0; + } else { + value = 0; + } + + return value; +} + +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_PATH0_SEL_IN; + value = DISP_PATH0_SEL_IN_OVL0_2L; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_DPI0_SEL_IN; + value = DPI0_SEL_IN_RDMA1; + } else { + value = 0; + } + + return value; +} + +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) { + writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + DISP_RDMA0_SOUT_SEL_IN); + } +} + +struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs = { + .mout_en = mtk_mmsys_ddp_mout_en, + .sel_in = mtk_mmsys_ddp_sel_in, + .sout_sel = mtk_mmsys_ddp_sout_sel, +}; diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c index 9d6a3e9..63e1a63 100644 --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c @@ -42,6 +42,7 @@ struct mtk_mmsys_driver_data { static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .clk_driver = "clk-mt8183-mm", + .funcs = &mt8183_mmsys_funcs, }; struct mtk_mmsys { diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 17e8b91..4b6c514 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -55,6 +55,7 @@ struct mtk_mmsys_conn_funcs { }; extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs; +extern struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs; void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, -- 1.8.1.1.dirty _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF2EFC433FE for ; Thu, 10 Dec 2020 14:48:30 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7739123D22 for ; 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Thu, 10 Dec 2020 17:07:46 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 10 Dec 2020 17:07:45 +0800 From: Yongqiang Niu To: CK Hu , Philipp Zabel , Rob Herring , Matthias Brugger Subject: [PATCH v8, 3/6] soc: mediatek: mmsys: add mt8183 function call for setting the routing registers Date: Thu, 10 Dec 2020 17:07:39 +0800 Message-ID: <1607591262-21736-4-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1607591262-21736-1-git-send-email-yongqiang.niu@mediatek.com> References: <1607591262-21736-1-git-send-email-yongqiang.niu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Mailman-Approved-At: Thu, 10 Dec 2020 14:48:10 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Yongqiang Niu , David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" add mt8183 function call for setting the routing registers Signed-off-by: Yongqiang Niu --- drivers/soc/mediatek/mmsys/Makefile | 1 + drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 90 +++++++++++++++++++++++++++++++ drivers/soc/mediatek/mmsys/mtk-mmsys.c | 1 + include/linux/soc/mediatek/mtk-mmsys.h | 1 + 4 files changed, 93 insertions(+) create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile index ac03025..25eeb9e5 100644 --- a/drivers/soc/mediatek/mmsys/Makefile +++ b/drivers/soc/mediatek/mmsys/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o +obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o diff --git a/drivers/soc/mediatek/mmsys/mt8183-mmsys.c b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c new file mode 100644 index 0000000..192b4ab --- /dev/null +++ b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2020 MediaTek Inc. + +#include +#include +#include +#include +#include + +#define DISP_OVL0_MOUT_EN 0xf00 +#define DISP_OVL0_2L_MOUT_EN 0xf04 +#define DISP_OVL1_2L_MOUT_EN 0xf08 +#define DISP_DITHER0_MOUT_EN 0xf0c +#define DISP_PATH0_SEL_IN 0xf24 +#define DISP_DSI0_SEL_IN 0xf2c +#define DISP_DPI0_SEL_IN 0xf30 +#define DISP_RDMA0_SOUT_SEL_IN 0xf50 +#define DISP_RDMA1_SOUT_SEL_IN 0xf54 + +#define OVL0_MOUT_EN_OVL0_2L BIT(4) +#define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0) +#define OVL1_2L_MOUT_EN_RDMA1 BIT(4) +#define DITHER0_MOUT_IN_DSI0 BIT(0) +#define DISP_PATH0_SEL_IN_OVL0_2L 0x1 +#define DSI0_SEL_IN_RDMA0 0x1 +#define DSI0_SEL_IN_RDMA1 0x3 +#define DPI0_SEL_IN_RDMA0 0x1 +#define DPI0_SEL_IN_RDMA1 0x2 +#define RDMA0_SOUT_COLOR0 0x1 +#define RDMA1_SOUT_DSI0 0x1 + +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0) { + *addr = DISP_OVL0_MOUT_EN; + value = OVL0_MOUT_EN_OVL0_2L; + } else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_OVL0_2L_MOUT_EN; + value = OVL0_2L_MOUT_EN_DISP_PATH0; + } else if (cur == DDP_COMPONENT_OVL_2L1 && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_OVL1_2L_MOUT_EN; + value = OVL1_2L_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) { + *addr = DISP_DITHER0_MOUT_EN; + value = DITHER0_MOUT_IN_DSI0; + } else { + value = 0; + } + + return value; +} + +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_PATH0_SEL_IN; + value = DISP_PATH0_SEL_IN_OVL0_2L; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_DPI0_SEL_IN; + value = DPI0_SEL_IN_RDMA1; + } else { + value = 0; + } + + return value; +} + +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) { + writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + DISP_RDMA0_SOUT_SEL_IN); + } +} + +struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs = { + .mout_en = mtk_mmsys_ddp_mout_en, + .sel_in = mtk_mmsys_ddp_sel_in, + .sout_sel = mtk_mmsys_ddp_sout_sel, +}; diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c index 9d6a3e9..63e1a63 100644 --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c @@ -42,6 +42,7 @@ struct mtk_mmsys_driver_data { static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .clk_driver = "clk-mt8183-mm", + .funcs = &mt8183_mmsys_funcs, }; struct mtk_mmsys { diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 17e8b91..4b6c514 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -55,6 +55,7 @@ struct mtk_mmsys_conn_funcs { }; extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs; +extern struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs; void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, -- 1.8.1.1.dirty _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel