From: Chris Wilson <chris@chris-wilson.co.uk>
To: Rodrigo Vivi <rodrigo.vivi@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg1: Fix power gate sequence.
Date: Fri, 18 Dec 2020 19:07:15 +0000 [thread overview]
Message-ID: <160831843596.11872.1356902011285772230@build.alporthouse.com> (raw)
In-Reply-To: <20201218152412.185886-1-rodrigo.vivi@intel.com>
Quoting Rodrigo Vivi (2020-12-18 15:24:12)
> sub-pipe PG is not present on DG1. Setting these bits can disable
> other power gates and cause GPU hangs on video playbacks.
Hmm, all I see is "not valid for pre-gen12".
> Fixes: 85a12d7eb8fe ("drm/i915/tgl: Fix Media power gate sequence.")
> Cc: Dale B Stimson <dale.b.stimson@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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next prev parent reply other threads:[~2020-12-18 19:07 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-18 15:24 [Intel-gfx] [PATCH] drm/i915/dg1: Fix power gate sequence Rodrigo Vivi
2020-12-18 16:18 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2020-12-18 19:07 ` Chris Wilson [this message]
2020-12-18 19:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-07-21 7:59 [Intel-gfx] [PATCH] " Rodrigo Vivi
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