* [PATCH v4, 00/10] soc: mediatek: mmsys: Use function call for setting the routing registers
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Yongqiang Niu
The following series are intended to prepare the mtk-mmsys driver to
allow different DDP (Data Display Path) function call per SoC.
base 5.11-rc1
change since v3:
- move register operation into mmsys path select function
Yongqiang Niu (10):
soc: mediatek: mmsys: create mmsys folder
soc: mediatek: mmsys: Create struct mtk_mmsys to store context data
soc: mediatek: mmsys: move register operation into mmsys path select
function
soc: mediatek: mmsys: Use function call for setting the routing
registers
soc: mediatek: mmsys: add mt8183 function call for setting the routing
registers
soc: mediatek: mmsys: add component OVL_2L2
soc: mediatek: mmsys: add component POSTMASK
soc: mediatek: mmsys: add component RDMA4
soc: mediatek: mmsys: Use function call for setting mmsys ovl mout
register
soc: mediatek: mmsys: add mt8192 mmsys support
drivers/soc/mediatek/Makefile | 2 +-
drivers/soc/mediatek/mmsys/Makefile | 5 +
drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 254 ++++++++++++++++++++
drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 110 +++++++++
drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 149 ++++++++++++
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 180 ++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 373 ------------------------------
include/linux/soc/mediatek/mtk-mmsys.h | 25 ++
8 files changed, 724 insertions(+), 374 deletions(-)
create mode 100644 drivers/soc/mediatek/mmsys/Makefile
create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c
create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c
create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c
create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c
delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c
--
1.8.1.1.dirty
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4, 00/10] soc: mediatek: mmsys: Use function call for setting the routing registers
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, Daniel Vetter, linux-arm-kernel
The following series are intended to prepare the mtk-mmsys driver to
allow different DDP (Data Display Path) function call per SoC.
base 5.11-rc1
change since v3:
- move register operation into mmsys path select function
Yongqiang Niu (10):
soc: mediatek: mmsys: create mmsys folder
soc: mediatek: mmsys: Create struct mtk_mmsys to store context data
soc: mediatek: mmsys: move register operation into mmsys path select
function
soc: mediatek: mmsys: Use function call for setting the routing
registers
soc: mediatek: mmsys: add mt8183 function call for setting the routing
registers
soc: mediatek: mmsys: add component OVL_2L2
soc: mediatek: mmsys: add component POSTMASK
soc: mediatek: mmsys: add component RDMA4
soc: mediatek: mmsys: Use function call for setting mmsys ovl mout
register
soc: mediatek: mmsys: add mt8192 mmsys support
drivers/soc/mediatek/Makefile | 2 +-
drivers/soc/mediatek/mmsys/Makefile | 5 +
drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 254 ++++++++++++++++++++
drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 110 +++++++++
drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 149 ++++++++++++
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 180 ++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 373 ------------------------------
include/linux/soc/mediatek/mtk-mmsys.h | 25 ++
8 files changed, 724 insertions(+), 374 deletions(-)
create mode 100644 drivers/soc/mediatek/mmsys/Makefile
create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c
create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c
create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c
create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c
delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c
--
1.8.1.1.dirty
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4, 00/10] soc: mediatek: mmsys: Use function call for setting the routing registers
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, Daniel Vetter, linux-arm-kernel
The following series are intended to prepare the mtk-mmsys driver to
allow different DDP (Data Display Path) function call per SoC.
base 5.11-rc1
change since v3:
- move register operation into mmsys path select function
Yongqiang Niu (10):
soc: mediatek: mmsys: create mmsys folder
soc: mediatek: mmsys: Create struct mtk_mmsys to store context data
soc: mediatek: mmsys: move register operation into mmsys path select
function
soc: mediatek: mmsys: Use function call for setting the routing
registers
soc: mediatek: mmsys: add mt8183 function call for setting the routing
registers
soc: mediatek: mmsys: add component OVL_2L2
soc: mediatek: mmsys: add component POSTMASK
soc: mediatek: mmsys: add component RDMA4
soc: mediatek: mmsys: Use function call for setting mmsys ovl mout
register
soc: mediatek: mmsys: add mt8192 mmsys support
drivers/soc/mediatek/Makefile | 2 +-
drivers/soc/mediatek/mmsys/Makefile | 5 +
drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 254 ++++++++++++++++++++
drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 110 +++++++++
drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 149 ++++++++++++
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 180 ++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 373 ------------------------------
include/linux/soc/mediatek/mtk-mmsys.h | 25 ++
8 files changed, 724 insertions(+), 374 deletions(-)
create mode 100644 drivers/soc/mediatek/mmsys/Makefile
create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c
create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c
create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c
create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c
delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c
--
1.8.1.1.dirty
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4, 00/10] soc: mediatek: mmsys: Use function call for setting the routing registers
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, linux-arm-kernel
The following series are intended to prepare the mtk-mmsys driver to
allow different DDP (Data Display Path) function call per SoC.
base 5.11-rc1
change since v3:
- move register operation into mmsys path select function
Yongqiang Niu (10):
soc: mediatek: mmsys: create mmsys folder
soc: mediatek: mmsys: Create struct mtk_mmsys to store context data
soc: mediatek: mmsys: move register operation into mmsys path select
function
soc: mediatek: mmsys: Use function call for setting the routing
registers
soc: mediatek: mmsys: add mt8183 function call for setting the routing
registers
soc: mediatek: mmsys: add component OVL_2L2
soc: mediatek: mmsys: add component POSTMASK
soc: mediatek: mmsys: add component RDMA4
soc: mediatek: mmsys: Use function call for setting mmsys ovl mout
register
soc: mediatek: mmsys: add mt8192 mmsys support
drivers/soc/mediatek/Makefile | 2 +-
drivers/soc/mediatek/mmsys/Makefile | 5 +
drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 254 ++++++++++++++++++++
drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 110 +++++++++
drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 149 ++++++++++++
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 180 ++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 373 ------------------------------
include/linux/soc/mediatek/mtk-mmsys.h | 25 ++
8 files changed, 724 insertions(+), 374 deletions(-)
create mode 100644 drivers/soc/mediatek/mmsys/Makefile
create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c
create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c
create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c
create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c
delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c
--
1.8.1.1.dirty
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4, 01/10] soc: mediatek: mmsys: create mmsys folder
2021-01-05 3:06 ` Yongqiang Niu
(?)
(?)
@ 2021-01-05 3:06 ` Yongqiang Niu
-1 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Yongqiang Niu
the mmsys will more and more complicated after support
more and more SoCs, add an independent folder will be
more clear
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/soc/mediatek/Makefile | 2 +-
drivers/soc/mediatek/mmsys/Makefile | 2 +
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 373 +++++++++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 373 ---------------------------------
4 files changed, 376 insertions(+), 374 deletions(-)
create mode 100644 drivers/soc/mediatek/mmsys/Makefile
create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c
delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index b6908db..eca9774 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -5,4 +5,4 @@ obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
obj-$(CONFIG_MTK_SCPSYS_PM_DOMAINS) += mtk-pm-domains.o
-obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
+obj-$(CONFIG_MTK_MMSYS) += mmsys/
diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
new file mode 100644
index 0000000..f44eadc
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
new file mode 100644
index 0000000..18f9397
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -0,0 +1,373 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: James Liao <jamesjj.liao@mediatek.com>
+ */
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+
+#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
+#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
+#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
+#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
+#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
+#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
+#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
+#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
+#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
+#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
+#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
+#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
+#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
+#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
+
+#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
+#define DISP_REG_CONFIG_OUT_SEL 0x04c
+#define DISP_REG_CONFIG_DSI_SEL 0x050
+#define DISP_REG_CONFIG_DPI_SEL 0x064
+
+#define OVL0_MOUT_EN_COLOR0 0x1
+#define OD_MOUT_EN_RDMA0 0x1
+#define OD1_MOUT_EN_RDMA1 BIT(16)
+#define UFOE_MOUT_EN_DSI0 0x1
+#define COLOR0_SEL_IN_OVL0 0x1
+#define OVL1_MOUT_EN_COLOR1 0x1
+#define GAMMA_MOUT_EN_RDMA1 0x1
+#define RDMA0_SOUT_DPI0 0x2
+#define RDMA0_SOUT_DPI1 0x3
+#define RDMA0_SOUT_DSI1 0x1
+#define RDMA0_SOUT_DSI2 0x4
+#define RDMA0_SOUT_DSI3 0x5
+#define RDMA1_SOUT_DPI0 0x2
+#define RDMA1_SOUT_DPI1 0x3
+#define RDMA1_SOUT_DSI1 0x1
+#define RDMA1_SOUT_DSI2 0x4
+#define RDMA1_SOUT_DSI3 0x5
+#define RDMA2_SOUT_DPI0 0x2
+#define RDMA2_SOUT_DPI1 0x3
+#define RDMA2_SOUT_DSI1 0x1
+#define RDMA2_SOUT_DSI2 0x4
+#define RDMA2_SOUT_DSI3 0x5
+#define DPI0_SEL_IN_RDMA1 0x1
+#define DPI0_SEL_IN_RDMA2 0x3
+#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
+#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
+#define DSI0_SEL_IN_RDMA1 0x1
+#define DSI0_SEL_IN_RDMA2 0x4
+#define DSI1_SEL_IN_RDMA1 0x1
+#define DSI1_SEL_IN_RDMA2 0x4
+#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
+#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
+#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
+#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
+#define COLOR1_SEL_IN_OVL1 0x1
+
+#define OVL_MOUT_EN_RDMA 0x1
+#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
+#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
+#define DSI_SEL_IN_BLS 0x0
+#define DPI_SEL_IN_BLS 0x0
+#define DSI_SEL_IN_RDMA 0x1
+
+struct mtk_mmsys_driver_data {
+ const char *clk_driver;
+};
+
+static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
+ .clk_driver = "clk-mt2701-mm",
+};
+
+static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
+ .clk_driver = "clk-mt2712-mm",
+};
+
+static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
+ .clk_driver = "clk-mt6779-mm",
+};
+
+static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
+ .clk_driver = "clk-mt6797-mm",
+};
+
+static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
+ .clk_driver = "clk-mt8173-mm",
+};
+
+static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
+ .clk_driver = "clk-mt8183-mm",
+};
+
+static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ unsigned int *addr)
+{
+ unsigned int value;
+
+ if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
+ *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
+ value = OVL0_MOUT_EN_COLOR0;
+ } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
+ *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
+ value = OVL_MOUT_EN_RDMA;
+ } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
+ *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+ value = OD_MOUT_EN_RDMA0;
+ } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
+ *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
+ value = UFOE_MOUT_EN_DSI0;
+ } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
+ *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
+ value = OVL1_MOUT_EN_COLOR1;
+ } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
+ *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
+ value = GAMMA_MOUT_EN_RDMA1;
+ } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
+ *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+ value = OD1_MOUT_EN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DPI0;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DPI1;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DSI1;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DSI2;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DSI3;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DSI1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DSI2;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DSI3;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DPI0;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DPI1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DPI0;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DPI1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DSI1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DSI2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DSI3;
+ } else {
+ value = 0;
+ }
+
+ return value;
+}
+
+static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ unsigned int *addr)
+{
+ unsigned int value;
+
+ if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
+ *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
+ value = COLOR0_SEL_IN_OVL0;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
+ *addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ value = DPI0_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
+ *addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ value = DPI1_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
+ *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI0_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
+ *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ value = DSI1_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
+ *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI2_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
+ *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ value = DSI3_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
+ *addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ value = DPI0_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
+ *addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ value = DPI1_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
+ *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI0_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
+ *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ value = DSI1_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
+ *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI2_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
+ *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI3_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
+ *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
+ value = COLOR1_SEL_IN_OVL1;
+ } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
+ *addr = DISP_REG_CONFIG_DSI_SEL;
+ value = DSI_SEL_IN_BLS;
+ } else {
+ value = 0;
+ }
+
+ return value;
+}
+
+static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next)
+{
+ if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
+ writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
+ config_regs + DISP_REG_CONFIG_OUT_SEL);
+ } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
+ writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
+ config_regs + DISP_REG_CONFIG_OUT_SEL);
+ writel_relaxed(DSI_SEL_IN_RDMA,
+ config_regs + DISP_REG_CONFIG_DSI_SEL);
+ writel_relaxed(DPI_SEL_IN_BLS,
+ config_regs + DISP_REG_CONFIG_DPI_SEL);
+ }
+}
+
+void mtk_mmsys_ddp_connect(struct device *dev,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next)
+{
+ void __iomem *config_regs = dev_get_drvdata(dev);
+ unsigned int addr, value, reg;
+
+ value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
+ if (value) {
+ reg = readl_relaxed(config_regs + addr) | value;
+ writel_relaxed(reg, config_regs + addr);
+ }
+
+ mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
+
+ value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
+ if (value) {
+ reg = readl_relaxed(config_regs + addr) | value;
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
+
+void mtk_mmsys_ddp_disconnect(struct device *dev,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next)
+{
+ void __iomem *config_regs = dev_get_drvdata(dev);
+ unsigned int addr, value, reg;
+
+ value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
+ if (value) {
+ reg = readl_relaxed(config_regs + addr) & ~value;
+ writel_relaxed(reg, config_regs + addr);
+ }
+
+ value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
+ if (value) {
+ reg = readl_relaxed(config_regs + addr) & ~value;
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
+
+static int mtk_mmsys_probe(struct platform_device *pdev)
+{
+ const struct mtk_mmsys_driver_data *data;
+ struct device *dev = &pdev->dev;
+ struct platform_device *clks;
+ struct platform_device *drm;
+ void __iomem *config_regs;
+ int ret;
+
+ config_regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(config_regs)) {
+ ret = PTR_ERR(config_regs);
+ dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
+ return ret;
+ }
+
+ platform_set_drvdata(pdev, config_regs);
+
+ data = of_device_get_match_data(&pdev->dev);
+
+ clks = platform_device_register_data(&pdev->dev, data->clk_driver,
+ PLATFORM_DEVID_AUTO, NULL, 0);
+ if (IS_ERR(clks))
+ return PTR_ERR(clks);
+
+ drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
+ PLATFORM_DEVID_AUTO, NULL, 0);
+ if (IS_ERR(drm)) {
+ platform_device_unregister(clks);
+ return PTR_ERR(drm);
+ }
+
+ return 0;
+}
+
+static const struct of_device_id of_match_mtk_mmsys[] = {
+ {
+ .compatible = "mediatek,mt2701-mmsys",
+ .data = &mt2701_mmsys_driver_data,
+ },
+ {
+ .compatible = "mediatek,mt2712-mmsys",
+ .data = &mt2712_mmsys_driver_data,
+ },
+ {
+ .compatible = "mediatek,mt6779-mmsys",
+ .data = &mt6779_mmsys_driver_data,
+ },
+ {
+ .compatible = "mediatek,mt6797-mmsys",
+ .data = &mt6797_mmsys_driver_data,
+ },
+ {
+ .compatible = "mediatek,mt8173-mmsys",
+ .data = &mt8173_mmsys_driver_data,
+ },
+ {
+ .compatible = "mediatek,mt8183-mmsys",
+ .data = &mt8183_mmsys_driver_data,
+ },
+ { }
+};
+
+static struct platform_driver mtk_mmsys_drv = {
+ .driver = {
+ .name = "mtk-mmsys",
+ .of_match_table = of_match_mtk_mmsys,
+ },
+ .probe = mtk_mmsys_probe,
+};
+
+builtin_platform_driver(mtk_mmsys_drv);
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
deleted file mode 100644
index 18f9397..0000000
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ /dev/null
@@ -1,373 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2014 MediaTek Inc.
- * Author: James Liao <jamesjj.liao@mediatek.com>
- */
-
-#include <linux/device.h>
-#include <linux/io.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include <linux/soc/mediatek/mtk-mmsys.h>
-
-#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
-#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
-#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
-#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
-#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
-#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
-#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
-#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
-#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
-#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
-#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
-#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
-#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
-#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
-
-#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
-#define DISP_REG_CONFIG_OUT_SEL 0x04c
-#define DISP_REG_CONFIG_DSI_SEL 0x050
-#define DISP_REG_CONFIG_DPI_SEL 0x064
-
-#define OVL0_MOUT_EN_COLOR0 0x1
-#define OD_MOUT_EN_RDMA0 0x1
-#define OD1_MOUT_EN_RDMA1 BIT(16)
-#define UFOE_MOUT_EN_DSI0 0x1
-#define COLOR0_SEL_IN_OVL0 0x1
-#define OVL1_MOUT_EN_COLOR1 0x1
-#define GAMMA_MOUT_EN_RDMA1 0x1
-#define RDMA0_SOUT_DPI0 0x2
-#define RDMA0_SOUT_DPI1 0x3
-#define RDMA0_SOUT_DSI1 0x1
-#define RDMA0_SOUT_DSI2 0x4
-#define RDMA0_SOUT_DSI3 0x5
-#define RDMA1_SOUT_DPI0 0x2
-#define RDMA1_SOUT_DPI1 0x3
-#define RDMA1_SOUT_DSI1 0x1
-#define RDMA1_SOUT_DSI2 0x4
-#define RDMA1_SOUT_DSI3 0x5
-#define RDMA2_SOUT_DPI0 0x2
-#define RDMA2_SOUT_DPI1 0x3
-#define RDMA2_SOUT_DSI1 0x1
-#define RDMA2_SOUT_DSI2 0x4
-#define RDMA2_SOUT_DSI3 0x5
-#define DPI0_SEL_IN_RDMA1 0x1
-#define DPI0_SEL_IN_RDMA2 0x3
-#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
-#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
-#define DSI0_SEL_IN_RDMA1 0x1
-#define DSI0_SEL_IN_RDMA2 0x4
-#define DSI1_SEL_IN_RDMA1 0x1
-#define DSI1_SEL_IN_RDMA2 0x4
-#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
-#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
-#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
-#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
-#define COLOR1_SEL_IN_OVL1 0x1
-
-#define OVL_MOUT_EN_RDMA 0x1
-#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
-#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
-#define DSI_SEL_IN_BLS 0x0
-#define DPI_SEL_IN_BLS 0x0
-#define DSI_SEL_IN_RDMA 0x1
-
-struct mtk_mmsys_driver_data {
- const char *clk_driver;
-};
-
-static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
- .clk_driver = "clk-mt2701-mm",
-};
-
-static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
- .clk_driver = "clk-mt2712-mm",
-};
-
-static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
- .clk_driver = "clk-mt6779-mm",
-};
-
-static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
- .clk_driver = "clk-mt6797-mm",
-};
-
-static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
- .clk_driver = "clk-mt8173-mm",
-};
-
-static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
- .clk_driver = "clk-mt8183-mm",
-};
-
-static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next,
- unsigned int *addr)
-{
- unsigned int value;
-
- if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
- *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
- value = OVL0_MOUT_EN_COLOR0;
- } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
- *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
- value = OVL_MOUT_EN_RDMA;
- } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
- *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
- value = OD_MOUT_EN_RDMA0;
- } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
- *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
- value = UFOE_MOUT_EN_DSI0;
- } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
- *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
- value = OVL1_MOUT_EN_COLOR1;
- } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
- *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
- value = GAMMA_MOUT_EN_RDMA1;
- } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
- *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
- value = OD1_MOUT_EN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DPI0;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DPI1;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DSI1;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DSI2;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DSI3;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DSI1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DSI2;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DSI3;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DPI0;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DPI1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DPI0;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DPI1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DSI1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DSI2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DSI3;
- } else {
- value = 0;
- }
-
- return value;
-}
-
-static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next,
- unsigned int *addr)
-{
- unsigned int value;
-
- if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
- *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
- value = COLOR0_SEL_IN_OVL0;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI0_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI1_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI0_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
- value = DSI1_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI2_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
- value = DSI3_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI0_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI1_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI0_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
- value = DSI1_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI2_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI3_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
- *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
- value = COLOR1_SEL_IN_OVL1;
- } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
- *addr = DISP_REG_CONFIG_DSI_SEL;
- value = DSI_SEL_IN_BLS;
- } else {
- value = 0;
- }
-
- return value;
-}
-
-static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
- enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next)
-{
- if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
- writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
- config_regs + DISP_REG_CONFIG_OUT_SEL);
- } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
- writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
- config_regs + DISP_REG_CONFIG_OUT_SEL);
- writel_relaxed(DSI_SEL_IN_RDMA,
- config_regs + DISP_REG_CONFIG_DSI_SEL);
- writel_relaxed(DPI_SEL_IN_BLS,
- config_regs + DISP_REG_CONFIG_DPI_SEL);
- }
-}
-
-void mtk_mmsys_ddp_connect(struct device *dev,
- enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next)
-{
- void __iomem *config_regs = dev_get_drvdata(dev);
- unsigned int addr, value, reg;
-
- value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
- if (value) {
- reg = readl_relaxed(config_regs + addr) | value;
- writel_relaxed(reg, config_regs + addr);
- }
-
- mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
-
- value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
- if (value) {
- reg = readl_relaxed(config_regs + addr) | value;
- writel_relaxed(reg, config_regs + addr);
- }
-}
-EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
-
-void mtk_mmsys_ddp_disconnect(struct device *dev,
- enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next)
-{
- void __iomem *config_regs = dev_get_drvdata(dev);
- unsigned int addr, value, reg;
-
- value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
- if (value) {
- reg = readl_relaxed(config_regs + addr) & ~value;
- writel_relaxed(reg, config_regs + addr);
- }
-
- value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
- if (value) {
- reg = readl_relaxed(config_regs + addr) & ~value;
- writel_relaxed(reg, config_regs + addr);
- }
-}
-EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
-
-static int mtk_mmsys_probe(struct platform_device *pdev)
-{
- const struct mtk_mmsys_driver_data *data;
- struct device *dev = &pdev->dev;
- struct platform_device *clks;
- struct platform_device *drm;
- void __iomem *config_regs;
- int ret;
-
- config_regs = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(config_regs)) {
- ret = PTR_ERR(config_regs);
- dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
- return ret;
- }
-
- platform_set_drvdata(pdev, config_regs);
-
- data = of_device_get_match_data(&pdev->dev);
-
- clks = platform_device_register_data(&pdev->dev, data->clk_driver,
- PLATFORM_DEVID_AUTO, NULL, 0);
- if (IS_ERR(clks))
- return PTR_ERR(clks);
-
- drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
- PLATFORM_DEVID_AUTO, NULL, 0);
- if (IS_ERR(drm)) {
- platform_device_unregister(clks);
- return PTR_ERR(drm);
- }
-
- return 0;
-}
-
-static const struct of_device_id of_match_mtk_mmsys[] = {
- {
- .compatible = "mediatek,mt2701-mmsys",
- .data = &mt2701_mmsys_driver_data,
- },
- {
- .compatible = "mediatek,mt2712-mmsys",
- .data = &mt2712_mmsys_driver_data,
- },
- {
- .compatible = "mediatek,mt6779-mmsys",
- .data = &mt6779_mmsys_driver_data,
- },
- {
- .compatible = "mediatek,mt6797-mmsys",
- .data = &mt6797_mmsys_driver_data,
- },
- {
- .compatible = "mediatek,mt8173-mmsys",
- .data = &mt8173_mmsys_driver_data,
- },
- {
- .compatible = "mediatek,mt8183-mmsys",
- .data = &mt8183_mmsys_driver_data,
- },
- { }
-};
-
-static struct platform_driver mtk_mmsys_drv = {
- .driver = {
- .name = "mtk-mmsys",
- .of_match_table = of_match_mtk_mmsys,
- },
- .probe = mtk_mmsys_probe,
-};
-
-builtin_platform_driver(mtk_mmsys_drv);
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 01/10] soc: mediatek: mmsys: create mmsys folder
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, Daniel Vetter, linux-arm-kernel
the mmsys will more and more complicated after support
more and more SoCs, add an independent folder will be
more clear
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/soc/mediatek/Makefile | 2 +-
drivers/soc/mediatek/mmsys/Makefile | 2 +
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 373 +++++++++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 373 ---------------------------------
4 files changed, 376 insertions(+), 374 deletions(-)
create mode 100644 drivers/soc/mediatek/mmsys/Makefile
create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c
delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index b6908db..eca9774 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -5,4 +5,4 @@ obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
obj-$(CONFIG_MTK_SCPSYS_PM_DOMAINS) += mtk-pm-domains.o
-obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
+obj-$(CONFIG_MTK_MMSYS) += mmsys/
diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
new file mode 100644
index 0000000..f44eadc
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
new file mode 100644
index 0000000..18f9397
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -0,0 +1,373 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: James Liao <jamesjj.liao@mediatek.com>
+ */
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+
+#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
+#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
+#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
+#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
+#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
+#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
+#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
+#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
+#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
+#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
+#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
+#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
+#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
+#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
+
+#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
+#define DISP_REG_CONFIG_OUT_SEL 0x04c
+#define DISP_REG_CONFIG_DSI_SEL 0x050
+#define DISP_REG_CONFIG_DPI_SEL 0x064
+
+#define OVL0_MOUT_EN_COLOR0 0x1
+#define OD_MOUT_EN_RDMA0 0x1
+#define OD1_MOUT_EN_RDMA1 BIT(16)
+#define UFOE_MOUT_EN_DSI0 0x1
+#define COLOR0_SEL_IN_OVL0 0x1
+#define OVL1_MOUT_EN_COLOR1 0x1
+#define GAMMA_MOUT_EN_RDMA1 0x1
+#define RDMA0_SOUT_DPI0 0x2
+#define RDMA0_SOUT_DPI1 0x3
+#define RDMA0_SOUT_DSI1 0x1
+#define RDMA0_SOUT_DSI2 0x4
+#define RDMA0_SOUT_DSI3 0x5
+#define RDMA1_SOUT_DPI0 0x2
+#define RDMA1_SOUT_DPI1 0x3
+#define RDMA1_SOUT_DSI1 0x1
+#define RDMA1_SOUT_DSI2 0x4
+#define RDMA1_SOUT_DSI3 0x5
+#define RDMA2_SOUT_DPI0 0x2
+#define RDMA2_SOUT_DPI1 0x3
+#define RDMA2_SOUT_DSI1 0x1
+#define RDMA2_SOUT_DSI2 0x4
+#define RDMA2_SOUT_DSI3 0x5
+#define DPI0_SEL_IN_RDMA1 0x1
+#define DPI0_SEL_IN_RDMA2 0x3
+#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
+#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
+#define DSI0_SEL_IN_RDMA1 0x1
+#define DSI0_SEL_IN_RDMA2 0x4
+#define DSI1_SEL_IN_RDMA1 0x1
+#define DSI1_SEL_IN_RDMA2 0x4
+#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
+#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
+#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
+#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
+#define COLOR1_SEL_IN_OVL1 0x1
+
+#define OVL_MOUT_EN_RDMA 0x1
+#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
+#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
+#define DSI_SEL_IN_BLS 0x0
+#define DPI_SEL_IN_BLS 0x0
+#define DSI_SEL_IN_RDMA 0x1
+
+struct mtk_mmsys_driver_data {
+ const char *clk_driver;
+};
+
+static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
+ .clk_driver = "clk-mt2701-mm",
+};
+
+static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
+ .clk_driver = "clk-mt2712-mm",
+};
+
+static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
+ .clk_driver = "clk-mt6779-mm",
+};
+
+static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
+ .clk_driver = "clk-mt6797-mm",
+};
+
+static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
+ .clk_driver = "clk-mt8173-mm",
+};
+
+static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
+ .clk_driver = "clk-mt8183-mm",
+};
+
+static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ unsigned int *addr)
+{
+ unsigned int value;
+
+ if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
+ *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
+ value = OVL0_MOUT_EN_COLOR0;
+ } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
+ *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
+ value = OVL_MOUT_EN_RDMA;
+ } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
+ *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+ value = OD_MOUT_EN_RDMA0;
+ } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
+ *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
+ value = UFOE_MOUT_EN_DSI0;
+ } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
+ *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
+ value = OVL1_MOUT_EN_COLOR1;
+ } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
+ *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
+ value = GAMMA_MOUT_EN_RDMA1;
+ } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
+ *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+ value = OD1_MOUT_EN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DPI0;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DPI1;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DSI1;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DSI2;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DSI3;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DSI1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DSI2;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DSI3;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DPI0;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DPI1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DPI0;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DPI1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DSI1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DSI2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DSI3;
+ } else {
+ value = 0;
+ }
+
+ return value;
+}
+
+static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ unsigned int *addr)
+{
+ unsigned int value;
+
+ if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
+ *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
+ value = COLOR0_SEL_IN_OVL0;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
+ *addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ value = DPI0_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
+ *addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ value = DPI1_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
+ *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI0_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
+ *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ value = DSI1_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
+ *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI2_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
+ *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ value = DSI3_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
+ *addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ value = DPI0_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
+ *addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ value = DPI1_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
+ *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI0_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
+ *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ value = DSI1_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
+ *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI2_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
+ *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI3_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
+ *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
+ value = COLOR1_SEL_IN_OVL1;
+ } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
+ *addr = DISP_REG_CONFIG_DSI_SEL;
+ value = DSI_SEL_IN_BLS;
+ } else {
+ value = 0;
+ }
+
+ return value;
+}
+
+static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next)
+{
+ if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
+ writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
+ config_regs + DISP_REG_CONFIG_OUT_SEL);
+ } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
+ writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
+ config_regs + DISP_REG_CONFIG_OUT_SEL);
+ writel_relaxed(DSI_SEL_IN_RDMA,
+ config_regs + DISP_REG_CONFIG_DSI_SEL);
+ writel_relaxed(DPI_SEL_IN_BLS,
+ config_regs + DISP_REG_CONFIG_DPI_SEL);
+ }
+}
+
+void mtk_mmsys_ddp_connect(struct device *dev,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next)
+{
+ void __iomem *config_regs = dev_get_drvdata(dev);
+ unsigned int addr, value, reg;
+
+ value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
+ if (value) {
+ reg = readl_relaxed(config_regs + addr) | value;
+ writel_relaxed(reg, config_regs + addr);
+ }
+
+ mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
+
+ value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
+ if (value) {
+ reg = readl_relaxed(config_regs + addr) | value;
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
+
+void mtk_mmsys_ddp_disconnect(struct device *dev,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next)
+{
+ void __iomem *config_regs = dev_get_drvdata(dev);
+ unsigned int addr, value, reg;
+
+ value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
+ if (value) {
+ reg = readl_relaxed(config_regs + addr) & ~value;
+ writel_relaxed(reg, config_regs + addr);
+ }
+
+ value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
+ if (value) {
+ reg = readl_relaxed(config_regs + addr) & ~value;
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
+
+static int mtk_mmsys_probe(struct platform_device *pdev)
+{
+ const struct mtk_mmsys_driver_data *data;
+ struct device *dev = &pdev->dev;
+ struct platform_device *clks;
+ struct platform_device *drm;
+ void __iomem *config_regs;
+ int ret;
+
+ config_regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(config_regs)) {
+ ret = PTR_ERR(config_regs);
+ dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
+ return ret;
+ }
+
+ platform_set_drvdata(pdev, config_regs);
+
+ data = of_device_get_match_data(&pdev->dev);
+
+ clks = platform_device_register_data(&pdev->dev, data->clk_driver,
+ PLATFORM_DEVID_AUTO, NULL, 0);
+ if (IS_ERR(clks))
+ return PTR_ERR(clks);
+
+ drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
+ PLATFORM_DEVID_AUTO, NULL, 0);
+ if (IS_ERR(drm)) {
+ platform_device_unregister(clks);
+ return PTR_ERR(drm);
+ }
+
+ return 0;
+}
+
+static const struct of_device_id of_match_mtk_mmsys[] = {
+ {
+ .compatible = "mediatek,mt2701-mmsys",
+ .data = &mt2701_mmsys_driver_data,
+ },
+ {
+ .compatible = "mediatek,mt2712-mmsys",
+ .data = &mt2712_mmsys_driver_data,
+ },
+ {
+ .compatible = "mediatek,mt6779-mmsys",
+ .data = &mt6779_mmsys_driver_data,
+ },
+ {
+ .compatible = "mediatek,mt6797-mmsys",
+ .data = &mt6797_mmsys_driver_data,
+ },
+ {
+ .compatible = "mediatek,mt8173-mmsys",
+ .data = &mt8173_mmsys_driver_data,
+ },
+ {
+ .compatible = "mediatek,mt8183-mmsys",
+ .data = &mt8183_mmsys_driver_data,
+ },
+ { }
+};
+
+static struct platform_driver mtk_mmsys_drv = {
+ .driver = {
+ .name = "mtk-mmsys",
+ .of_match_table = of_match_mtk_mmsys,
+ },
+ .probe = mtk_mmsys_probe,
+};
+
+builtin_platform_driver(mtk_mmsys_drv);
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
deleted file mode 100644
index 18f9397..0000000
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ /dev/null
@@ -1,373 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2014 MediaTek Inc.
- * Author: James Liao <jamesjj.liao@mediatek.com>
- */
-
-#include <linux/device.h>
-#include <linux/io.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include <linux/soc/mediatek/mtk-mmsys.h>
-
-#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
-#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
-#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
-#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
-#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
-#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
-#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
-#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
-#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
-#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
-#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
-#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
-#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
-#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
-
-#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
-#define DISP_REG_CONFIG_OUT_SEL 0x04c
-#define DISP_REG_CONFIG_DSI_SEL 0x050
-#define DISP_REG_CONFIG_DPI_SEL 0x064
-
-#define OVL0_MOUT_EN_COLOR0 0x1
-#define OD_MOUT_EN_RDMA0 0x1
-#define OD1_MOUT_EN_RDMA1 BIT(16)
-#define UFOE_MOUT_EN_DSI0 0x1
-#define COLOR0_SEL_IN_OVL0 0x1
-#define OVL1_MOUT_EN_COLOR1 0x1
-#define GAMMA_MOUT_EN_RDMA1 0x1
-#define RDMA0_SOUT_DPI0 0x2
-#define RDMA0_SOUT_DPI1 0x3
-#define RDMA0_SOUT_DSI1 0x1
-#define RDMA0_SOUT_DSI2 0x4
-#define RDMA0_SOUT_DSI3 0x5
-#define RDMA1_SOUT_DPI0 0x2
-#define RDMA1_SOUT_DPI1 0x3
-#define RDMA1_SOUT_DSI1 0x1
-#define RDMA1_SOUT_DSI2 0x4
-#define RDMA1_SOUT_DSI3 0x5
-#define RDMA2_SOUT_DPI0 0x2
-#define RDMA2_SOUT_DPI1 0x3
-#define RDMA2_SOUT_DSI1 0x1
-#define RDMA2_SOUT_DSI2 0x4
-#define RDMA2_SOUT_DSI3 0x5
-#define DPI0_SEL_IN_RDMA1 0x1
-#define DPI0_SEL_IN_RDMA2 0x3
-#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
-#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
-#define DSI0_SEL_IN_RDMA1 0x1
-#define DSI0_SEL_IN_RDMA2 0x4
-#define DSI1_SEL_IN_RDMA1 0x1
-#define DSI1_SEL_IN_RDMA2 0x4
-#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
-#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
-#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
-#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
-#define COLOR1_SEL_IN_OVL1 0x1
-
-#define OVL_MOUT_EN_RDMA 0x1
-#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
-#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
-#define DSI_SEL_IN_BLS 0x0
-#define DPI_SEL_IN_BLS 0x0
-#define DSI_SEL_IN_RDMA 0x1
-
-struct mtk_mmsys_driver_data {
- const char *clk_driver;
-};
-
-static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
- .clk_driver = "clk-mt2701-mm",
-};
-
-static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
- .clk_driver = "clk-mt2712-mm",
-};
-
-static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
- .clk_driver = "clk-mt6779-mm",
-};
-
-static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
- .clk_driver = "clk-mt6797-mm",
-};
-
-static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
- .clk_driver = "clk-mt8173-mm",
-};
-
-static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
- .clk_driver = "clk-mt8183-mm",
-};
-
-static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next,
- unsigned int *addr)
-{
- unsigned int value;
-
- if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
- *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
- value = OVL0_MOUT_EN_COLOR0;
- } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
- *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
- value = OVL_MOUT_EN_RDMA;
- } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
- *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
- value = OD_MOUT_EN_RDMA0;
- } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
- *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
- value = UFOE_MOUT_EN_DSI0;
- } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
- *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
- value = OVL1_MOUT_EN_COLOR1;
- } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
- *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
- value = GAMMA_MOUT_EN_RDMA1;
- } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
- *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
- value = OD1_MOUT_EN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DPI0;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DPI1;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DSI1;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DSI2;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DSI3;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DSI1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DSI2;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DSI3;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DPI0;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DPI1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DPI0;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DPI1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DSI1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DSI2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DSI3;
- } else {
- value = 0;
- }
-
- return value;
-}
-
-static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next,
- unsigned int *addr)
-{
- unsigned int value;
-
- if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
- *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
- value = COLOR0_SEL_IN_OVL0;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI0_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI1_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI0_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
- value = DSI1_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI2_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
- value = DSI3_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI0_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI1_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI0_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
- value = DSI1_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI2_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI3_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
- *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
- value = COLOR1_SEL_IN_OVL1;
- } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
- *addr = DISP_REG_CONFIG_DSI_SEL;
- value = DSI_SEL_IN_BLS;
- } else {
- value = 0;
- }
-
- return value;
-}
-
-static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
- enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next)
-{
- if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
- writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
- config_regs + DISP_REG_CONFIG_OUT_SEL);
- } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
- writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
- config_regs + DISP_REG_CONFIG_OUT_SEL);
- writel_relaxed(DSI_SEL_IN_RDMA,
- config_regs + DISP_REG_CONFIG_DSI_SEL);
- writel_relaxed(DPI_SEL_IN_BLS,
- config_regs + DISP_REG_CONFIG_DPI_SEL);
- }
-}
-
-void mtk_mmsys_ddp_connect(struct device *dev,
- enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next)
-{
- void __iomem *config_regs = dev_get_drvdata(dev);
- unsigned int addr, value, reg;
-
- value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
- if (value) {
- reg = readl_relaxed(config_regs + addr) | value;
- writel_relaxed(reg, config_regs + addr);
- }
-
- mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
-
- value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
- if (value) {
- reg = readl_relaxed(config_regs + addr) | value;
- writel_relaxed(reg, config_regs + addr);
- }
-}
-EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
-
-void mtk_mmsys_ddp_disconnect(struct device *dev,
- enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next)
-{
- void __iomem *config_regs = dev_get_drvdata(dev);
- unsigned int addr, value, reg;
-
- value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
- if (value) {
- reg = readl_relaxed(config_regs + addr) & ~value;
- writel_relaxed(reg, config_regs + addr);
- }
-
- value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
- if (value) {
- reg = readl_relaxed(config_regs + addr) & ~value;
- writel_relaxed(reg, config_regs + addr);
- }
-}
-EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
-
-static int mtk_mmsys_probe(struct platform_device *pdev)
-{
- const struct mtk_mmsys_driver_data *data;
- struct device *dev = &pdev->dev;
- struct platform_device *clks;
- struct platform_device *drm;
- void __iomem *config_regs;
- int ret;
-
- config_regs = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(config_regs)) {
- ret = PTR_ERR(config_regs);
- dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
- return ret;
- }
-
- platform_set_drvdata(pdev, config_regs);
-
- data = of_device_get_match_data(&pdev->dev);
-
- clks = platform_device_register_data(&pdev->dev, data->clk_driver,
- PLATFORM_DEVID_AUTO, NULL, 0);
- if (IS_ERR(clks))
- return PTR_ERR(clks);
-
- drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
- PLATFORM_DEVID_AUTO, NULL, 0);
- if (IS_ERR(drm)) {
- platform_device_unregister(clks);
- return PTR_ERR(drm);
- }
-
- return 0;
-}
-
-static const struct of_device_id of_match_mtk_mmsys[] = {
- {
- .compatible = "mediatek,mt2701-mmsys",
- .data = &mt2701_mmsys_driver_data,
- },
- {
- .compatible = "mediatek,mt2712-mmsys",
- .data = &mt2712_mmsys_driver_data,
- },
- {
- .compatible = "mediatek,mt6779-mmsys",
- .data = &mt6779_mmsys_driver_data,
- },
- {
- .compatible = "mediatek,mt6797-mmsys",
- .data = &mt6797_mmsys_driver_data,
- },
- {
- .compatible = "mediatek,mt8173-mmsys",
- .data = &mt8173_mmsys_driver_data,
- },
- {
- .compatible = "mediatek,mt8183-mmsys",
- .data = &mt8183_mmsys_driver_data,
- },
- { }
-};
-
-static struct platform_driver mtk_mmsys_drv = {
- .driver = {
- .name = "mtk-mmsys",
- .of_match_table = of_match_mtk_mmsys,
- },
- .probe = mtk_mmsys_probe,
-};
-
-builtin_platform_driver(mtk_mmsys_drv);
--
1.8.1.1.dirty
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^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 01/10] soc: mediatek: mmsys: create mmsys folder
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, Daniel Vetter, linux-arm-kernel
the mmsys will more and more complicated after support
more and more SoCs, add an independent folder will be
more clear
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/soc/mediatek/Makefile | 2 +-
drivers/soc/mediatek/mmsys/Makefile | 2 +
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 373 +++++++++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 373 ---------------------------------
4 files changed, 376 insertions(+), 374 deletions(-)
create mode 100644 drivers/soc/mediatek/mmsys/Makefile
create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c
delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index b6908db..eca9774 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -5,4 +5,4 @@ obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
obj-$(CONFIG_MTK_SCPSYS_PM_DOMAINS) += mtk-pm-domains.o
-obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
+obj-$(CONFIG_MTK_MMSYS) += mmsys/
diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
new file mode 100644
index 0000000..f44eadc
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
new file mode 100644
index 0000000..18f9397
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -0,0 +1,373 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: James Liao <jamesjj.liao@mediatek.com>
+ */
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+
+#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
+#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
+#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
+#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
+#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
+#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
+#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
+#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
+#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
+#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
+#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
+#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
+#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
+#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
+
+#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
+#define DISP_REG_CONFIG_OUT_SEL 0x04c
+#define DISP_REG_CONFIG_DSI_SEL 0x050
+#define DISP_REG_CONFIG_DPI_SEL 0x064
+
+#define OVL0_MOUT_EN_COLOR0 0x1
+#define OD_MOUT_EN_RDMA0 0x1
+#define OD1_MOUT_EN_RDMA1 BIT(16)
+#define UFOE_MOUT_EN_DSI0 0x1
+#define COLOR0_SEL_IN_OVL0 0x1
+#define OVL1_MOUT_EN_COLOR1 0x1
+#define GAMMA_MOUT_EN_RDMA1 0x1
+#define RDMA0_SOUT_DPI0 0x2
+#define RDMA0_SOUT_DPI1 0x3
+#define RDMA0_SOUT_DSI1 0x1
+#define RDMA0_SOUT_DSI2 0x4
+#define RDMA0_SOUT_DSI3 0x5
+#define RDMA1_SOUT_DPI0 0x2
+#define RDMA1_SOUT_DPI1 0x3
+#define RDMA1_SOUT_DSI1 0x1
+#define RDMA1_SOUT_DSI2 0x4
+#define RDMA1_SOUT_DSI3 0x5
+#define RDMA2_SOUT_DPI0 0x2
+#define RDMA2_SOUT_DPI1 0x3
+#define RDMA2_SOUT_DSI1 0x1
+#define RDMA2_SOUT_DSI2 0x4
+#define RDMA2_SOUT_DSI3 0x5
+#define DPI0_SEL_IN_RDMA1 0x1
+#define DPI0_SEL_IN_RDMA2 0x3
+#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
+#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
+#define DSI0_SEL_IN_RDMA1 0x1
+#define DSI0_SEL_IN_RDMA2 0x4
+#define DSI1_SEL_IN_RDMA1 0x1
+#define DSI1_SEL_IN_RDMA2 0x4
+#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
+#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
+#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
+#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
+#define COLOR1_SEL_IN_OVL1 0x1
+
+#define OVL_MOUT_EN_RDMA 0x1
+#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
+#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
+#define DSI_SEL_IN_BLS 0x0
+#define DPI_SEL_IN_BLS 0x0
+#define DSI_SEL_IN_RDMA 0x1
+
+struct mtk_mmsys_driver_data {
+ const char *clk_driver;
+};
+
+static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
+ .clk_driver = "clk-mt2701-mm",
+};
+
+static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
+ .clk_driver = "clk-mt2712-mm",
+};
+
+static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
+ .clk_driver = "clk-mt6779-mm",
+};
+
+static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
+ .clk_driver = "clk-mt6797-mm",
+};
+
+static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
+ .clk_driver = "clk-mt8173-mm",
+};
+
+static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
+ .clk_driver = "clk-mt8183-mm",
+};
+
+static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ unsigned int *addr)
+{
+ unsigned int value;
+
+ if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
+ *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
+ value = OVL0_MOUT_EN_COLOR0;
+ } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
+ *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
+ value = OVL_MOUT_EN_RDMA;
+ } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
+ *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+ value = OD_MOUT_EN_RDMA0;
+ } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
+ *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
+ value = UFOE_MOUT_EN_DSI0;
+ } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
+ *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
+ value = OVL1_MOUT_EN_COLOR1;
+ } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
+ *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
+ value = GAMMA_MOUT_EN_RDMA1;
+ } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
+ *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+ value = OD1_MOUT_EN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DPI0;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DPI1;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DSI1;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DSI2;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DSI3;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DSI1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DSI2;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DSI3;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DPI0;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DPI1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DPI0;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DPI1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DSI1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DSI2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DSI3;
+ } else {
+ value = 0;
+ }
+
+ return value;
+}
+
+static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ unsigned int *addr)
+{
+ unsigned int value;
+
+ if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
+ *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
+ value = COLOR0_SEL_IN_OVL0;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
+ *addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ value = DPI0_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
+ *addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ value = DPI1_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
+ *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI0_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
+ *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ value = DSI1_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
+ *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI2_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
+ *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ value = DSI3_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
+ *addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ value = DPI0_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
+ *addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ value = DPI1_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
+ *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI0_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
+ *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ value = DSI1_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
+ *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI2_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
+ *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI3_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
+ *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
+ value = COLOR1_SEL_IN_OVL1;
+ } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
+ *addr = DISP_REG_CONFIG_DSI_SEL;
+ value = DSI_SEL_IN_BLS;
+ } else {
+ value = 0;
+ }
+
+ return value;
+}
+
+static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next)
+{
+ if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
+ writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
+ config_regs + DISP_REG_CONFIG_OUT_SEL);
+ } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
+ writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
+ config_regs + DISP_REG_CONFIG_OUT_SEL);
+ writel_relaxed(DSI_SEL_IN_RDMA,
+ config_regs + DISP_REG_CONFIG_DSI_SEL);
+ writel_relaxed(DPI_SEL_IN_BLS,
+ config_regs + DISP_REG_CONFIG_DPI_SEL);
+ }
+}
+
+void mtk_mmsys_ddp_connect(struct device *dev,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next)
+{
+ void __iomem *config_regs = dev_get_drvdata(dev);
+ unsigned int addr, value, reg;
+
+ value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
+ if (value) {
+ reg = readl_relaxed(config_regs + addr) | value;
+ writel_relaxed(reg, config_regs + addr);
+ }
+
+ mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
+
+ value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
+ if (value) {
+ reg = readl_relaxed(config_regs + addr) | value;
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
+
+void mtk_mmsys_ddp_disconnect(struct device *dev,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next)
+{
+ void __iomem *config_regs = dev_get_drvdata(dev);
+ unsigned int addr, value, reg;
+
+ value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
+ if (value) {
+ reg = readl_relaxed(config_regs + addr) & ~value;
+ writel_relaxed(reg, config_regs + addr);
+ }
+
+ value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
+ if (value) {
+ reg = readl_relaxed(config_regs + addr) & ~value;
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
+
+static int mtk_mmsys_probe(struct platform_device *pdev)
+{
+ const struct mtk_mmsys_driver_data *data;
+ struct device *dev = &pdev->dev;
+ struct platform_device *clks;
+ struct platform_device *drm;
+ void __iomem *config_regs;
+ int ret;
+
+ config_regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(config_regs)) {
+ ret = PTR_ERR(config_regs);
+ dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
+ return ret;
+ }
+
+ platform_set_drvdata(pdev, config_regs);
+
+ data = of_device_get_match_data(&pdev->dev);
+
+ clks = platform_device_register_data(&pdev->dev, data->clk_driver,
+ PLATFORM_DEVID_AUTO, NULL, 0);
+ if (IS_ERR(clks))
+ return PTR_ERR(clks);
+
+ drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
+ PLATFORM_DEVID_AUTO, NULL, 0);
+ if (IS_ERR(drm)) {
+ platform_device_unregister(clks);
+ return PTR_ERR(drm);
+ }
+
+ return 0;
+}
+
+static const struct of_device_id of_match_mtk_mmsys[] = {
+ {
+ .compatible = "mediatek,mt2701-mmsys",
+ .data = &mt2701_mmsys_driver_data,
+ },
+ {
+ .compatible = "mediatek,mt2712-mmsys",
+ .data = &mt2712_mmsys_driver_data,
+ },
+ {
+ .compatible = "mediatek,mt6779-mmsys",
+ .data = &mt6779_mmsys_driver_data,
+ },
+ {
+ .compatible = "mediatek,mt6797-mmsys",
+ .data = &mt6797_mmsys_driver_data,
+ },
+ {
+ .compatible = "mediatek,mt8173-mmsys",
+ .data = &mt8173_mmsys_driver_data,
+ },
+ {
+ .compatible = "mediatek,mt8183-mmsys",
+ .data = &mt8183_mmsys_driver_data,
+ },
+ { }
+};
+
+static struct platform_driver mtk_mmsys_drv = {
+ .driver = {
+ .name = "mtk-mmsys",
+ .of_match_table = of_match_mtk_mmsys,
+ },
+ .probe = mtk_mmsys_probe,
+};
+
+builtin_platform_driver(mtk_mmsys_drv);
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
deleted file mode 100644
index 18f9397..0000000
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ /dev/null
@@ -1,373 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2014 MediaTek Inc.
- * Author: James Liao <jamesjj.liao@mediatek.com>
- */
-
-#include <linux/device.h>
-#include <linux/io.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include <linux/soc/mediatek/mtk-mmsys.h>
-
-#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
-#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
-#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
-#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
-#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
-#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
-#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
-#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
-#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
-#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
-#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
-#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
-#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
-#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
-
-#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
-#define DISP_REG_CONFIG_OUT_SEL 0x04c
-#define DISP_REG_CONFIG_DSI_SEL 0x050
-#define DISP_REG_CONFIG_DPI_SEL 0x064
-
-#define OVL0_MOUT_EN_COLOR0 0x1
-#define OD_MOUT_EN_RDMA0 0x1
-#define OD1_MOUT_EN_RDMA1 BIT(16)
-#define UFOE_MOUT_EN_DSI0 0x1
-#define COLOR0_SEL_IN_OVL0 0x1
-#define OVL1_MOUT_EN_COLOR1 0x1
-#define GAMMA_MOUT_EN_RDMA1 0x1
-#define RDMA0_SOUT_DPI0 0x2
-#define RDMA0_SOUT_DPI1 0x3
-#define RDMA0_SOUT_DSI1 0x1
-#define RDMA0_SOUT_DSI2 0x4
-#define RDMA0_SOUT_DSI3 0x5
-#define RDMA1_SOUT_DPI0 0x2
-#define RDMA1_SOUT_DPI1 0x3
-#define RDMA1_SOUT_DSI1 0x1
-#define RDMA1_SOUT_DSI2 0x4
-#define RDMA1_SOUT_DSI3 0x5
-#define RDMA2_SOUT_DPI0 0x2
-#define RDMA2_SOUT_DPI1 0x3
-#define RDMA2_SOUT_DSI1 0x1
-#define RDMA2_SOUT_DSI2 0x4
-#define RDMA2_SOUT_DSI3 0x5
-#define DPI0_SEL_IN_RDMA1 0x1
-#define DPI0_SEL_IN_RDMA2 0x3
-#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
-#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
-#define DSI0_SEL_IN_RDMA1 0x1
-#define DSI0_SEL_IN_RDMA2 0x4
-#define DSI1_SEL_IN_RDMA1 0x1
-#define DSI1_SEL_IN_RDMA2 0x4
-#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
-#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
-#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
-#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
-#define COLOR1_SEL_IN_OVL1 0x1
-
-#define OVL_MOUT_EN_RDMA 0x1
-#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
-#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
-#define DSI_SEL_IN_BLS 0x0
-#define DPI_SEL_IN_BLS 0x0
-#define DSI_SEL_IN_RDMA 0x1
-
-struct mtk_mmsys_driver_data {
- const char *clk_driver;
-};
-
-static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
- .clk_driver = "clk-mt2701-mm",
-};
-
-static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
- .clk_driver = "clk-mt2712-mm",
-};
-
-static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
- .clk_driver = "clk-mt6779-mm",
-};
-
-static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
- .clk_driver = "clk-mt6797-mm",
-};
-
-static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
- .clk_driver = "clk-mt8173-mm",
-};
-
-static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
- .clk_driver = "clk-mt8183-mm",
-};
-
-static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next,
- unsigned int *addr)
-{
- unsigned int value;
-
- if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
- *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
- value = OVL0_MOUT_EN_COLOR0;
- } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
- *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
- value = OVL_MOUT_EN_RDMA;
- } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
- *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
- value = OD_MOUT_EN_RDMA0;
- } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
- *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
- value = UFOE_MOUT_EN_DSI0;
- } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
- *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
- value = OVL1_MOUT_EN_COLOR1;
- } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
- *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
- value = GAMMA_MOUT_EN_RDMA1;
- } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
- *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
- value = OD1_MOUT_EN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DPI0;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DPI1;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DSI1;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DSI2;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DSI3;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DSI1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DSI2;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DSI3;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DPI0;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DPI1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DPI0;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DPI1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DSI1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DSI2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DSI3;
- } else {
- value = 0;
- }
-
- return value;
-}
-
-static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next,
- unsigned int *addr)
-{
- unsigned int value;
-
- if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
- *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
- value = COLOR0_SEL_IN_OVL0;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI0_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI1_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI0_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
- value = DSI1_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI2_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
- value = DSI3_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI0_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI1_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI0_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
- value = DSI1_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI2_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI3_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
- *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
- value = COLOR1_SEL_IN_OVL1;
- } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
- *addr = DISP_REG_CONFIG_DSI_SEL;
- value = DSI_SEL_IN_BLS;
- } else {
- value = 0;
- }
-
- return value;
-}
-
-static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
- enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next)
-{
- if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
- writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
- config_regs + DISP_REG_CONFIG_OUT_SEL);
- } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
- writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
- config_regs + DISP_REG_CONFIG_OUT_SEL);
- writel_relaxed(DSI_SEL_IN_RDMA,
- config_regs + DISP_REG_CONFIG_DSI_SEL);
- writel_relaxed(DPI_SEL_IN_BLS,
- config_regs + DISP_REG_CONFIG_DPI_SEL);
- }
-}
-
-void mtk_mmsys_ddp_connect(struct device *dev,
- enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next)
-{
- void __iomem *config_regs = dev_get_drvdata(dev);
- unsigned int addr, value, reg;
-
- value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
- if (value) {
- reg = readl_relaxed(config_regs + addr) | value;
- writel_relaxed(reg, config_regs + addr);
- }
-
- mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
-
- value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
- if (value) {
- reg = readl_relaxed(config_regs + addr) | value;
- writel_relaxed(reg, config_regs + addr);
- }
-}
-EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
-
-void mtk_mmsys_ddp_disconnect(struct device *dev,
- enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next)
-{
- void __iomem *config_regs = dev_get_drvdata(dev);
- unsigned int addr, value, reg;
-
- value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
- if (value) {
- reg = readl_relaxed(config_regs + addr) & ~value;
- writel_relaxed(reg, config_regs + addr);
- }
-
- value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
- if (value) {
- reg = readl_relaxed(config_regs + addr) & ~value;
- writel_relaxed(reg, config_regs + addr);
- }
-}
-EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
-
-static int mtk_mmsys_probe(struct platform_device *pdev)
-{
- const struct mtk_mmsys_driver_data *data;
- struct device *dev = &pdev->dev;
- struct platform_device *clks;
- struct platform_device *drm;
- void __iomem *config_regs;
- int ret;
-
- config_regs = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(config_regs)) {
- ret = PTR_ERR(config_regs);
- dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
- return ret;
- }
-
- platform_set_drvdata(pdev, config_regs);
-
- data = of_device_get_match_data(&pdev->dev);
-
- clks = platform_device_register_data(&pdev->dev, data->clk_driver,
- PLATFORM_DEVID_AUTO, NULL, 0);
- if (IS_ERR(clks))
- return PTR_ERR(clks);
-
- drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
- PLATFORM_DEVID_AUTO, NULL, 0);
- if (IS_ERR(drm)) {
- platform_device_unregister(clks);
- return PTR_ERR(drm);
- }
-
- return 0;
-}
-
-static const struct of_device_id of_match_mtk_mmsys[] = {
- {
- .compatible = "mediatek,mt2701-mmsys",
- .data = &mt2701_mmsys_driver_data,
- },
- {
- .compatible = "mediatek,mt2712-mmsys",
- .data = &mt2712_mmsys_driver_data,
- },
- {
- .compatible = "mediatek,mt6779-mmsys",
- .data = &mt6779_mmsys_driver_data,
- },
- {
- .compatible = "mediatek,mt6797-mmsys",
- .data = &mt6797_mmsys_driver_data,
- },
- {
- .compatible = "mediatek,mt8173-mmsys",
- .data = &mt8173_mmsys_driver_data,
- },
- {
- .compatible = "mediatek,mt8183-mmsys",
- .data = &mt8183_mmsys_driver_data,
- },
- { }
-};
-
-static struct platform_driver mtk_mmsys_drv = {
- .driver = {
- .name = "mtk-mmsys",
- .of_match_table = of_match_mtk_mmsys,
- },
- .probe = mtk_mmsys_probe,
-};
-
-builtin_platform_driver(mtk_mmsys_drv);
--
1.8.1.1.dirty
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^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 01/10] soc: mediatek: mmsys: create mmsys folder
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, linux-arm-kernel
the mmsys will more and more complicated after support
more and more SoCs, add an independent folder will be
more clear
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/soc/mediatek/Makefile | 2 +-
drivers/soc/mediatek/mmsys/Makefile | 2 +
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 373 +++++++++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 373 ---------------------------------
4 files changed, 376 insertions(+), 374 deletions(-)
create mode 100644 drivers/soc/mediatek/mmsys/Makefile
create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c
delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index b6908db..eca9774 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -5,4 +5,4 @@ obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
obj-$(CONFIG_MTK_SCPSYS_PM_DOMAINS) += mtk-pm-domains.o
-obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
+obj-$(CONFIG_MTK_MMSYS) += mmsys/
diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
new file mode 100644
index 0000000..f44eadc
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
new file mode 100644
index 0000000..18f9397
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -0,0 +1,373 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: James Liao <jamesjj.liao@mediatek.com>
+ */
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+
+#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
+#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
+#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
+#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
+#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
+#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
+#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
+#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
+#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
+#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
+#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
+#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
+#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
+#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
+
+#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
+#define DISP_REG_CONFIG_OUT_SEL 0x04c
+#define DISP_REG_CONFIG_DSI_SEL 0x050
+#define DISP_REG_CONFIG_DPI_SEL 0x064
+
+#define OVL0_MOUT_EN_COLOR0 0x1
+#define OD_MOUT_EN_RDMA0 0x1
+#define OD1_MOUT_EN_RDMA1 BIT(16)
+#define UFOE_MOUT_EN_DSI0 0x1
+#define COLOR0_SEL_IN_OVL0 0x1
+#define OVL1_MOUT_EN_COLOR1 0x1
+#define GAMMA_MOUT_EN_RDMA1 0x1
+#define RDMA0_SOUT_DPI0 0x2
+#define RDMA0_SOUT_DPI1 0x3
+#define RDMA0_SOUT_DSI1 0x1
+#define RDMA0_SOUT_DSI2 0x4
+#define RDMA0_SOUT_DSI3 0x5
+#define RDMA1_SOUT_DPI0 0x2
+#define RDMA1_SOUT_DPI1 0x3
+#define RDMA1_SOUT_DSI1 0x1
+#define RDMA1_SOUT_DSI2 0x4
+#define RDMA1_SOUT_DSI3 0x5
+#define RDMA2_SOUT_DPI0 0x2
+#define RDMA2_SOUT_DPI1 0x3
+#define RDMA2_SOUT_DSI1 0x1
+#define RDMA2_SOUT_DSI2 0x4
+#define RDMA2_SOUT_DSI3 0x5
+#define DPI0_SEL_IN_RDMA1 0x1
+#define DPI0_SEL_IN_RDMA2 0x3
+#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
+#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
+#define DSI0_SEL_IN_RDMA1 0x1
+#define DSI0_SEL_IN_RDMA2 0x4
+#define DSI1_SEL_IN_RDMA1 0x1
+#define DSI1_SEL_IN_RDMA2 0x4
+#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
+#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
+#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
+#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
+#define COLOR1_SEL_IN_OVL1 0x1
+
+#define OVL_MOUT_EN_RDMA 0x1
+#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
+#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
+#define DSI_SEL_IN_BLS 0x0
+#define DPI_SEL_IN_BLS 0x0
+#define DSI_SEL_IN_RDMA 0x1
+
+struct mtk_mmsys_driver_data {
+ const char *clk_driver;
+};
+
+static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
+ .clk_driver = "clk-mt2701-mm",
+};
+
+static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
+ .clk_driver = "clk-mt2712-mm",
+};
+
+static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
+ .clk_driver = "clk-mt6779-mm",
+};
+
+static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
+ .clk_driver = "clk-mt6797-mm",
+};
+
+static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
+ .clk_driver = "clk-mt8173-mm",
+};
+
+static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
+ .clk_driver = "clk-mt8183-mm",
+};
+
+static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ unsigned int *addr)
+{
+ unsigned int value;
+
+ if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
+ *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
+ value = OVL0_MOUT_EN_COLOR0;
+ } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
+ *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
+ value = OVL_MOUT_EN_RDMA;
+ } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
+ *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+ value = OD_MOUT_EN_RDMA0;
+ } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
+ *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
+ value = UFOE_MOUT_EN_DSI0;
+ } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
+ *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
+ value = OVL1_MOUT_EN_COLOR1;
+ } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
+ *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
+ value = GAMMA_MOUT_EN_RDMA1;
+ } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
+ *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+ value = OD1_MOUT_EN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DPI0;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DPI1;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DSI1;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DSI2;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DSI3;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DSI1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DSI2;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DSI3;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DPI0;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DPI1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DPI0;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DPI1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DSI1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DSI2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DSI3;
+ } else {
+ value = 0;
+ }
+
+ return value;
+}
+
+static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ unsigned int *addr)
+{
+ unsigned int value;
+
+ if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
+ *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
+ value = COLOR0_SEL_IN_OVL0;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
+ *addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ value = DPI0_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
+ *addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ value = DPI1_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
+ *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI0_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
+ *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ value = DSI1_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
+ *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI2_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
+ *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ value = DSI3_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
+ *addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ value = DPI0_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
+ *addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ value = DPI1_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
+ *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI0_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
+ *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ value = DSI1_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
+ *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI2_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
+ *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI3_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
+ *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
+ value = COLOR1_SEL_IN_OVL1;
+ } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
+ *addr = DISP_REG_CONFIG_DSI_SEL;
+ value = DSI_SEL_IN_BLS;
+ } else {
+ value = 0;
+ }
+
+ return value;
+}
+
+static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next)
+{
+ if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
+ writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
+ config_regs + DISP_REG_CONFIG_OUT_SEL);
+ } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
+ writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
+ config_regs + DISP_REG_CONFIG_OUT_SEL);
+ writel_relaxed(DSI_SEL_IN_RDMA,
+ config_regs + DISP_REG_CONFIG_DSI_SEL);
+ writel_relaxed(DPI_SEL_IN_BLS,
+ config_regs + DISP_REG_CONFIG_DPI_SEL);
+ }
+}
+
+void mtk_mmsys_ddp_connect(struct device *dev,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next)
+{
+ void __iomem *config_regs = dev_get_drvdata(dev);
+ unsigned int addr, value, reg;
+
+ value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
+ if (value) {
+ reg = readl_relaxed(config_regs + addr) | value;
+ writel_relaxed(reg, config_regs + addr);
+ }
+
+ mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
+
+ value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
+ if (value) {
+ reg = readl_relaxed(config_regs + addr) | value;
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
+
+void mtk_mmsys_ddp_disconnect(struct device *dev,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next)
+{
+ void __iomem *config_regs = dev_get_drvdata(dev);
+ unsigned int addr, value, reg;
+
+ value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
+ if (value) {
+ reg = readl_relaxed(config_regs + addr) & ~value;
+ writel_relaxed(reg, config_regs + addr);
+ }
+
+ value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
+ if (value) {
+ reg = readl_relaxed(config_regs + addr) & ~value;
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
+
+static int mtk_mmsys_probe(struct platform_device *pdev)
+{
+ const struct mtk_mmsys_driver_data *data;
+ struct device *dev = &pdev->dev;
+ struct platform_device *clks;
+ struct platform_device *drm;
+ void __iomem *config_regs;
+ int ret;
+
+ config_regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(config_regs)) {
+ ret = PTR_ERR(config_regs);
+ dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
+ return ret;
+ }
+
+ platform_set_drvdata(pdev, config_regs);
+
+ data = of_device_get_match_data(&pdev->dev);
+
+ clks = platform_device_register_data(&pdev->dev, data->clk_driver,
+ PLATFORM_DEVID_AUTO, NULL, 0);
+ if (IS_ERR(clks))
+ return PTR_ERR(clks);
+
+ drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
+ PLATFORM_DEVID_AUTO, NULL, 0);
+ if (IS_ERR(drm)) {
+ platform_device_unregister(clks);
+ return PTR_ERR(drm);
+ }
+
+ return 0;
+}
+
+static const struct of_device_id of_match_mtk_mmsys[] = {
+ {
+ .compatible = "mediatek,mt2701-mmsys",
+ .data = &mt2701_mmsys_driver_data,
+ },
+ {
+ .compatible = "mediatek,mt2712-mmsys",
+ .data = &mt2712_mmsys_driver_data,
+ },
+ {
+ .compatible = "mediatek,mt6779-mmsys",
+ .data = &mt6779_mmsys_driver_data,
+ },
+ {
+ .compatible = "mediatek,mt6797-mmsys",
+ .data = &mt6797_mmsys_driver_data,
+ },
+ {
+ .compatible = "mediatek,mt8173-mmsys",
+ .data = &mt8173_mmsys_driver_data,
+ },
+ {
+ .compatible = "mediatek,mt8183-mmsys",
+ .data = &mt8183_mmsys_driver_data,
+ },
+ { }
+};
+
+static struct platform_driver mtk_mmsys_drv = {
+ .driver = {
+ .name = "mtk-mmsys",
+ .of_match_table = of_match_mtk_mmsys,
+ },
+ .probe = mtk_mmsys_probe,
+};
+
+builtin_platform_driver(mtk_mmsys_drv);
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
deleted file mode 100644
index 18f9397..0000000
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ /dev/null
@@ -1,373 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2014 MediaTek Inc.
- * Author: James Liao <jamesjj.liao@mediatek.com>
- */
-
-#include <linux/device.h>
-#include <linux/io.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include <linux/soc/mediatek/mtk-mmsys.h>
-
-#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
-#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
-#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
-#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
-#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
-#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
-#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
-#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
-#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
-#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
-#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
-#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
-#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
-#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
-
-#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
-#define DISP_REG_CONFIG_OUT_SEL 0x04c
-#define DISP_REG_CONFIG_DSI_SEL 0x050
-#define DISP_REG_CONFIG_DPI_SEL 0x064
-
-#define OVL0_MOUT_EN_COLOR0 0x1
-#define OD_MOUT_EN_RDMA0 0x1
-#define OD1_MOUT_EN_RDMA1 BIT(16)
-#define UFOE_MOUT_EN_DSI0 0x1
-#define COLOR0_SEL_IN_OVL0 0x1
-#define OVL1_MOUT_EN_COLOR1 0x1
-#define GAMMA_MOUT_EN_RDMA1 0x1
-#define RDMA0_SOUT_DPI0 0x2
-#define RDMA0_SOUT_DPI1 0x3
-#define RDMA0_SOUT_DSI1 0x1
-#define RDMA0_SOUT_DSI2 0x4
-#define RDMA0_SOUT_DSI3 0x5
-#define RDMA1_SOUT_DPI0 0x2
-#define RDMA1_SOUT_DPI1 0x3
-#define RDMA1_SOUT_DSI1 0x1
-#define RDMA1_SOUT_DSI2 0x4
-#define RDMA1_SOUT_DSI3 0x5
-#define RDMA2_SOUT_DPI0 0x2
-#define RDMA2_SOUT_DPI1 0x3
-#define RDMA2_SOUT_DSI1 0x1
-#define RDMA2_SOUT_DSI2 0x4
-#define RDMA2_SOUT_DSI3 0x5
-#define DPI0_SEL_IN_RDMA1 0x1
-#define DPI0_SEL_IN_RDMA2 0x3
-#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
-#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
-#define DSI0_SEL_IN_RDMA1 0x1
-#define DSI0_SEL_IN_RDMA2 0x4
-#define DSI1_SEL_IN_RDMA1 0x1
-#define DSI1_SEL_IN_RDMA2 0x4
-#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
-#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
-#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
-#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
-#define COLOR1_SEL_IN_OVL1 0x1
-
-#define OVL_MOUT_EN_RDMA 0x1
-#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
-#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
-#define DSI_SEL_IN_BLS 0x0
-#define DPI_SEL_IN_BLS 0x0
-#define DSI_SEL_IN_RDMA 0x1
-
-struct mtk_mmsys_driver_data {
- const char *clk_driver;
-};
-
-static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
- .clk_driver = "clk-mt2701-mm",
-};
-
-static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
- .clk_driver = "clk-mt2712-mm",
-};
-
-static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
- .clk_driver = "clk-mt6779-mm",
-};
-
-static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
- .clk_driver = "clk-mt6797-mm",
-};
-
-static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
- .clk_driver = "clk-mt8173-mm",
-};
-
-static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
- .clk_driver = "clk-mt8183-mm",
-};
-
-static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next,
- unsigned int *addr)
-{
- unsigned int value;
-
- if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
- *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
- value = OVL0_MOUT_EN_COLOR0;
- } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
- *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
- value = OVL_MOUT_EN_RDMA;
- } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
- *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
- value = OD_MOUT_EN_RDMA0;
- } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
- *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
- value = UFOE_MOUT_EN_DSI0;
- } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
- *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
- value = OVL1_MOUT_EN_COLOR1;
- } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
- *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
- value = GAMMA_MOUT_EN_RDMA1;
- } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
- *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
- value = OD1_MOUT_EN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DPI0;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DPI1;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DSI1;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DSI2;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DSI3;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DSI1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DSI2;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DSI3;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DPI0;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DPI1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DPI0;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DPI1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DSI1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DSI2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DSI3;
- } else {
- value = 0;
- }
-
- return value;
-}
-
-static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next,
- unsigned int *addr)
-{
- unsigned int value;
-
- if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
- *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
- value = COLOR0_SEL_IN_OVL0;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI0_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI1_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI0_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
- value = DSI1_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI2_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
- value = DSI3_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI0_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI1_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI0_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
- value = DSI1_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI2_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI3_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
- *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
- value = COLOR1_SEL_IN_OVL1;
- } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
- *addr = DISP_REG_CONFIG_DSI_SEL;
- value = DSI_SEL_IN_BLS;
- } else {
- value = 0;
- }
-
- return value;
-}
-
-static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
- enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next)
-{
- if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
- writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
- config_regs + DISP_REG_CONFIG_OUT_SEL);
- } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
- writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
- config_regs + DISP_REG_CONFIG_OUT_SEL);
- writel_relaxed(DSI_SEL_IN_RDMA,
- config_regs + DISP_REG_CONFIG_DSI_SEL);
- writel_relaxed(DPI_SEL_IN_BLS,
- config_regs + DISP_REG_CONFIG_DPI_SEL);
- }
-}
-
-void mtk_mmsys_ddp_connect(struct device *dev,
- enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next)
-{
- void __iomem *config_regs = dev_get_drvdata(dev);
- unsigned int addr, value, reg;
-
- value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
- if (value) {
- reg = readl_relaxed(config_regs + addr) | value;
- writel_relaxed(reg, config_regs + addr);
- }
-
- mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
-
- value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
- if (value) {
- reg = readl_relaxed(config_regs + addr) | value;
- writel_relaxed(reg, config_regs + addr);
- }
-}
-EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
-
-void mtk_mmsys_ddp_disconnect(struct device *dev,
- enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next)
-{
- void __iomem *config_regs = dev_get_drvdata(dev);
- unsigned int addr, value, reg;
-
- value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
- if (value) {
- reg = readl_relaxed(config_regs + addr) & ~value;
- writel_relaxed(reg, config_regs + addr);
- }
-
- value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
- if (value) {
- reg = readl_relaxed(config_regs + addr) & ~value;
- writel_relaxed(reg, config_regs + addr);
- }
-}
-EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
-
-static int mtk_mmsys_probe(struct platform_device *pdev)
-{
- const struct mtk_mmsys_driver_data *data;
- struct device *dev = &pdev->dev;
- struct platform_device *clks;
- struct platform_device *drm;
- void __iomem *config_regs;
- int ret;
-
- config_regs = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(config_regs)) {
- ret = PTR_ERR(config_regs);
- dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
- return ret;
- }
-
- platform_set_drvdata(pdev, config_regs);
-
- data = of_device_get_match_data(&pdev->dev);
-
- clks = platform_device_register_data(&pdev->dev, data->clk_driver,
- PLATFORM_DEVID_AUTO, NULL, 0);
- if (IS_ERR(clks))
- return PTR_ERR(clks);
-
- drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
- PLATFORM_DEVID_AUTO, NULL, 0);
- if (IS_ERR(drm)) {
- platform_device_unregister(clks);
- return PTR_ERR(drm);
- }
-
- return 0;
-}
-
-static const struct of_device_id of_match_mtk_mmsys[] = {
- {
- .compatible = "mediatek,mt2701-mmsys",
- .data = &mt2701_mmsys_driver_data,
- },
- {
- .compatible = "mediatek,mt2712-mmsys",
- .data = &mt2712_mmsys_driver_data,
- },
- {
- .compatible = "mediatek,mt6779-mmsys",
- .data = &mt6779_mmsys_driver_data,
- },
- {
- .compatible = "mediatek,mt6797-mmsys",
- .data = &mt6797_mmsys_driver_data,
- },
- {
- .compatible = "mediatek,mt8173-mmsys",
- .data = &mt8173_mmsys_driver_data,
- },
- {
- .compatible = "mediatek,mt8183-mmsys",
- .data = &mt8183_mmsys_driver_data,
- },
- { }
-};
-
-static struct platform_driver mtk_mmsys_drv = {
- .driver = {
- .name = "mtk-mmsys",
- .of_match_table = of_match_mtk_mmsys,
- },
- .probe = mtk_mmsys_probe,
-};
-
-builtin_platform_driver(mtk_mmsys_drv);
--
1.8.1.1.dirty
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 02/10] soc: mediatek: mmsys: Create struct mtk_mmsys to store context data
2021-01-05 3:06 ` Yongqiang Niu
(?)
(?)
@ 2021-01-05 3:06 ` Yongqiang Niu
-1 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Yongqiang Niu,
Enric Balletbo i Serra
Apart from the driver data, in order to extend the driver to support more
and more SoCs, we will need to store other configuration data. So, create
a mtk_mmsys struct to encapsulate all that information.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 47 +++++++++++++++++++---------------
1 file changed, 27 insertions(+), 20 deletions(-)
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
index 18f9397..6c03282 100644
--- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -77,6 +77,11 @@ struct mtk_mmsys_driver_data {
const char *clk_driver;
};
+struct mtk_mmsys {
+ void __iomem *regs;
+ const struct mtk_mmsys_driver_data *data;
+};
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.clk_driver = "clk-mt2701-mm",
};
@@ -259,21 +264,21 @@ void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next)
{
- void __iomem *config_regs = dev_get_drvdata(dev);
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
unsigned int addr, value, reg;
value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
if (value) {
- reg = readl_relaxed(config_regs + addr) | value;
- writel_relaxed(reg, config_regs + addr);
+ reg = readl_relaxed(mmsys->regs + addr) | value;
+ writel_relaxed(reg, mmsys->regs + addr);
}
- mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
+ mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next);
value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
if (value) {
- reg = readl_relaxed(config_regs + addr) | value;
- writel_relaxed(reg, config_regs + addr);
+ reg = readl_relaxed(mmsys->regs + addr) | value;
+ writel_relaxed(reg, mmsys->regs + addr);
}
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
@@ -282,44 +287,46 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next)
{
- void __iomem *config_regs = dev_get_drvdata(dev);
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
unsigned int addr, value, reg;
value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
if (value) {
- reg = readl_relaxed(config_regs + addr) & ~value;
- writel_relaxed(reg, config_regs + addr);
+ reg = readl_relaxed(mmsys->regs + addr) & ~value;
+ writel_relaxed(reg, mmsys->regs + addr);
}
value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
if (value) {
- reg = readl_relaxed(config_regs + addr) & ~value;
- writel_relaxed(reg, config_regs + addr);
+ reg = readl_relaxed(mmsys->regs + addr) & ~value;
+ writel_relaxed(reg, mmsys->regs + addr);
}
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
static int mtk_mmsys_probe(struct platform_device *pdev)
{
- const struct mtk_mmsys_driver_data *data;
struct device *dev = &pdev->dev;
struct platform_device *clks;
struct platform_device *drm;
- void __iomem *config_regs;
+ struct mtk_mmsys *mmsys;
int ret;
- config_regs = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(config_regs)) {
- ret = PTR_ERR(config_regs);
+ mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
+ if (!mmsys)
+ return -ENOMEM;
+
+ mmsys->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(mmsys->regs)) {
+ ret = PTR_ERR(mmsys->regs);
dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
return ret;
}
- platform_set_drvdata(pdev, config_regs);
-
- data = of_device_get_match_data(&pdev->dev);
+ mmsys->data = of_device_get_match_data(&pdev->dev);
+ platform_set_drvdata(pdev, mmsys);
- clks = platform_device_register_data(&pdev->dev, data->clk_driver,
+ clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
PLATFORM_DEVID_AUTO, NULL, 0);
if (IS_ERR(clks))
return PTR_ERR(clks);
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 02/10] soc: mediatek: mmsys: Create struct mtk_mmsys to store context data
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, Daniel Vetter, Enric Balletbo i Serra,
linux-arm-kernel
Apart from the driver data, in order to extend the driver to support more
and more SoCs, we will need to store other configuration data. So, create
a mtk_mmsys struct to encapsulate all that information.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 47 +++++++++++++++++++---------------
1 file changed, 27 insertions(+), 20 deletions(-)
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
index 18f9397..6c03282 100644
--- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -77,6 +77,11 @@ struct mtk_mmsys_driver_data {
const char *clk_driver;
};
+struct mtk_mmsys {
+ void __iomem *regs;
+ const struct mtk_mmsys_driver_data *data;
+};
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.clk_driver = "clk-mt2701-mm",
};
@@ -259,21 +264,21 @@ void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next)
{
- void __iomem *config_regs = dev_get_drvdata(dev);
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
unsigned int addr, value, reg;
value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
if (value) {
- reg = readl_relaxed(config_regs + addr) | value;
- writel_relaxed(reg, config_regs + addr);
+ reg = readl_relaxed(mmsys->regs + addr) | value;
+ writel_relaxed(reg, mmsys->regs + addr);
}
- mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
+ mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next);
value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
if (value) {
- reg = readl_relaxed(config_regs + addr) | value;
- writel_relaxed(reg, config_regs + addr);
+ reg = readl_relaxed(mmsys->regs + addr) | value;
+ writel_relaxed(reg, mmsys->regs + addr);
}
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
@@ -282,44 +287,46 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next)
{
- void __iomem *config_regs = dev_get_drvdata(dev);
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
unsigned int addr, value, reg;
value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
if (value) {
- reg = readl_relaxed(config_regs + addr) & ~value;
- writel_relaxed(reg, config_regs + addr);
+ reg = readl_relaxed(mmsys->regs + addr) & ~value;
+ writel_relaxed(reg, mmsys->regs + addr);
}
value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
if (value) {
- reg = readl_relaxed(config_regs + addr) & ~value;
- writel_relaxed(reg, config_regs + addr);
+ reg = readl_relaxed(mmsys->regs + addr) & ~value;
+ writel_relaxed(reg, mmsys->regs + addr);
}
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
static int mtk_mmsys_probe(struct platform_device *pdev)
{
- const struct mtk_mmsys_driver_data *data;
struct device *dev = &pdev->dev;
struct platform_device *clks;
struct platform_device *drm;
- void __iomem *config_regs;
+ struct mtk_mmsys *mmsys;
int ret;
- config_regs = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(config_regs)) {
- ret = PTR_ERR(config_regs);
+ mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
+ if (!mmsys)
+ return -ENOMEM;
+
+ mmsys->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(mmsys->regs)) {
+ ret = PTR_ERR(mmsys->regs);
dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
return ret;
}
- platform_set_drvdata(pdev, config_regs);
-
- data = of_device_get_match_data(&pdev->dev);
+ mmsys->data = of_device_get_match_data(&pdev->dev);
+ platform_set_drvdata(pdev, mmsys);
- clks = platform_device_register_data(&pdev->dev, data->clk_driver,
+ clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
PLATFORM_DEVID_AUTO, NULL, 0);
if (IS_ERR(clks))
return PTR_ERR(clks);
--
1.8.1.1.dirty
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 02/10] soc: mediatek: mmsys: Create struct mtk_mmsys to store context data
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, Daniel Vetter, Enric Balletbo i Serra,
linux-arm-kernel
Apart from the driver data, in order to extend the driver to support more
and more SoCs, we will need to store other configuration data. So, create
a mtk_mmsys struct to encapsulate all that information.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 47 +++++++++++++++++++---------------
1 file changed, 27 insertions(+), 20 deletions(-)
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
index 18f9397..6c03282 100644
--- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -77,6 +77,11 @@ struct mtk_mmsys_driver_data {
const char *clk_driver;
};
+struct mtk_mmsys {
+ void __iomem *regs;
+ const struct mtk_mmsys_driver_data *data;
+};
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.clk_driver = "clk-mt2701-mm",
};
@@ -259,21 +264,21 @@ void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next)
{
- void __iomem *config_regs = dev_get_drvdata(dev);
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
unsigned int addr, value, reg;
value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
if (value) {
- reg = readl_relaxed(config_regs + addr) | value;
- writel_relaxed(reg, config_regs + addr);
+ reg = readl_relaxed(mmsys->regs + addr) | value;
+ writel_relaxed(reg, mmsys->regs + addr);
}
- mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
+ mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next);
value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
if (value) {
- reg = readl_relaxed(config_regs + addr) | value;
- writel_relaxed(reg, config_regs + addr);
+ reg = readl_relaxed(mmsys->regs + addr) | value;
+ writel_relaxed(reg, mmsys->regs + addr);
}
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
@@ -282,44 +287,46 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next)
{
- void __iomem *config_regs = dev_get_drvdata(dev);
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
unsigned int addr, value, reg;
value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
if (value) {
- reg = readl_relaxed(config_regs + addr) & ~value;
- writel_relaxed(reg, config_regs + addr);
+ reg = readl_relaxed(mmsys->regs + addr) & ~value;
+ writel_relaxed(reg, mmsys->regs + addr);
}
value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
if (value) {
- reg = readl_relaxed(config_regs + addr) & ~value;
- writel_relaxed(reg, config_regs + addr);
+ reg = readl_relaxed(mmsys->regs + addr) & ~value;
+ writel_relaxed(reg, mmsys->regs + addr);
}
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
static int mtk_mmsys_probe(struct platform_device *pdev)
{
- const struct mtk_mmsys_driver_data *data;
struct device *dev = &pdev->dev;
struct platform_device *clks;
struct platform_device *drm;
- void __iomem *config_regs;
+ struct mtk_mmsys *mmsys;
int ret;
- config_regs = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(config_regs)) {
- ret = PTR_ERR(config_regs);
+ mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
+ if (!mmsys)
+ return -ENOMEM;
+
+ mmsys->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(mmsys->regs)) {
+ ret = PTR_ERR(mmsys->regs);
dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
return ret;
}
- platform_set_drvdata(pdev, config_regs);
-
- data = of_device_get_match_data(&pdev->dev);
+ mmsys->data = of_device_get_match_data(&pdev->dev);
+ platform_set_drvdata(pdev, mmsys);
- clks = platform_device_register_data(&pdev->dev, data->clk_driver,
+ clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
PLATFORM_DEVID_AUTO, NULL, 0);
if (IS_ERR(clks))
return PTR_ERR(clks);
--
1.8.1.1.dirty
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 02/10] soc: mediatek: mmsys: Create struct mtk_mmsys to store context data
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, Enric Balletbo i Serra, linux-arm-kernel
Apart from the driver data, in order to extend the driver to support more
and more SoCs, we will need to store other configuration data. So, create
a mtk_mmsys struct to encapsulate all that information.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 47 +++++++++++++++++++---------------
1 file changed, 27 insertions(+), 20 deletions(-)
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
index 18f9397..6c03282 100644
--- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -77,6 +77,11 @@ struct mtk_mmsys_driver_data {
const char *clk_driver;
};
+struct mtk_mmsys {
+ void __iomem *regs;
+ const struct mtk_mmsys_driver_data *data;
+};
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.clk_driver = "clk-mt2701-mm",
};
@@ -259,21 +264,21 @@ void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next)
{
- void __iomem *config_regs = dev_get_drvdata(dev);
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
unsigned int addr, value, reg;
value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
if (value) {
- reg = readl_relaxed(config_regs + addr) | value;
- writel_relaxed(reg, config_regs + addr);
+ reg = readl_relaxed(mmsys->regs + addr) | value;
+ writel_relaxed(reg, mmsys->regs + addr);
}
- mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
+ mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next);
value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
if (value) {
- reg = readl_relaxed(config_regs + addr) | value;
- writel_relaxed(reg, config_regs + addr);
+ reg = readl_relaxed(mmsys->regs + addr) | value;
+ writel_relaxed(reg, mmsys->regs + addr);
}
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
@@ -282,44 +287,46 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next)
{
- void __iomem *config_regs = dev_get_drvdata(dev);
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
unsigned int addr, value, reg;
value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
if (value) {
- reg = readl_relaxed(config_regs + addr) & ~value;
- writel_relaxed(reg, config_regs + addr);
+ reg = readl_relaxed(mmsys->regs + addr) & ~value;
+ writel_relaxed(reg, mmsys->regs + addr);
}
value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
if (value) {
- reg = readl_relaxed(config_regs + addr) & ~value;
- writel_relaxed(reg, config_regs + addr);
+ reg = readl_relaxed(mmsys->regs + addr) & ~value;
+ writel_relaxed(reg, mmsys->regs + addr);
}
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
static int mtk_mmsys_probe(struct platform_device *pdev)
{
- const struct mtk_mmsys_driver_data *data;
struct device *dev = &pdev->dev;
struct platform_device *clks;
struct platform_device *drm;
- void __iomem *config_regs;
+ struct mtk_mmsys *mmsys;
int ret;
- config_regs = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(config_regs)) {
- ret = PTR_ERR(config_regs);
+ mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
+ if (!mmsys)
+ return -ENOMEM;
+
+ mmsys->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(mmsys->regs)) {
+ ret = PTR_ERR(mmsys->regs);
dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
return ret;
}
- platform_set_drvdata(pdev, config_regs);
-
- data = of_device_get_match_data(&pdev->dev);
+ mmsys->data = of_device_get_match_data(&pdev->dev);
+ platform_set_drvdata(pdev, mmsys);
- clks = platform_device_register_data(&pdev->dev, data->clk_driver,
+ clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
PLATFORM_DEVID_AUTO, NULL, 0);
if (IS_ERR(clks))
return PTR_ERR(clks);
--
1.8.1.1.dirty
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 03/10] soc: mediatek: mmsys: move register operation into mmsys path select function
2021-01-05 3:06 ` Yongqiang Niu
(?)
(?)
@ 2021-01-05 3:06 ` Yongqiang Niu
-1 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Yongqiang Niu
move register operation into mmsys path select function
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 140 +++++++++++++++++----------------
1 file changed, 71 insertions(+), 69 deletions(-)
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
index 6c03282..64c8030 100644
--- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -106,141 +106,161 @@ struct mtk_mmsys {
.clk_driver = "clk-mt8183-mm",
};
-static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next,
- unsigned int *addr)
+static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
{
- unsigned int value;
+ unsigned int addr, value, reg;
if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
- *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
value = OVL0_MOUT_EN_COLOR0;
} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
- *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
value = OVL_MOUT_EN_RDMA;
} else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
- *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
value = OD_MOUT_EN_RDMA0;
} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
- *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
value = UFOE_MOUT_EN_DSI0;
} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
- *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
value = OVL1_MOUT_EN_COLOR1;
} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
- *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
value = GAMMA_MOUT_EN_RDMA1;
} else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
- *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
value = OD1_MOUT_EN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DPI0;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DPI1;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DSI1;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DSI2;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DSI3;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DSI1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DSI2;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DSI3;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DPI0;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DPI1;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
value = RDMA2_SOUT_DPI0;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
value = RDMA2_SOUT_DPI1;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
value = RDMA2_SOUT_DSI1;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
value = RDMA2_SOUT_DSI2;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
value = RDMA2_SOUT_DSI3;
} else {
value = 0;
}
- return value;
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
}
-static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next,
- unsigned int *addr)
+static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
{
- unsigned int value;
+ unsigned int addr, value, reg;
if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
- *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
+ addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
value = COLOR0_SEL_IN_OVL0;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ addr = DISP_REG_CONFIG_DPI_SEL_IN;
value = DPI0_SEL_IN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ addr = DISP_REG_CONFIG_DPI_SEL_IN;
value = DPI1_SEL_IN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
value = DSI0_SEL_IN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ addr = DISP_REG_CONFIG_DSIO_SEL_IN;
value = DSI1_SEL_IN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
value = DSI2_SEL_IN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ addr = DISP_REG_CONFIG_DSIO_SEL_IN;
value = DSI3_SEL_IN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ addr = DISP_REG_CONFIG_DPI_SEL_IN;
value = DPI0_SEL_IN_RDMA2;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ addr = DISP_REG_CONFIG_DPI_SEL_IN;
value = DPI1_SEL_IN_RDMA2;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
value = DSI0_SEL_IN_RDMA2;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ addr = DISP_REG_CONFIG_DSIO_SEL_IN;
value = DSI1_SEL_IN_RDMA2;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
value = DSI2_SEL_IN_RDMA2;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
value = DSI3_SEL_IN_RDMA2;
} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
- *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
+ addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
value = COLOR1_SEL_IN_OVL1;
} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
- *addr = DISP_REG_CONFIG_DSI_SEL;
+ addr = DISP_REG_CONFIG_DSI_SEL;
value = DSI_SEL_IN_BLS;
} else {
value = 0;
}
- return value;
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
}
static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
@@ -265,21 +285,12 @@ void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id next)
{
struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
- unsigned int addr, value, reg;
- value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
- if (value) {
- reg = readl_relaxed(mmsys->regs + addr) | value;
- writel_relaxed(reg, mmsys->regs + addr);
- }
+ mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, true);
mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next);
- value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
- if (value) {
- reg = readl_relaxed(mmsys->regs + addr) | value;
- writel_relaxed(reg, mmsys->regs + addr);
- }
+ mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, true);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
@@ -288,19 +299,10 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id next)
{
struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
- unsigned int addr, value, reg;
- value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
- if (value) {
- reg = readl_relaxed(mmsys->regs + addr) & ~value;
- writel_relaxed(reg, mmsys->regs + addr);
- }
+ mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, false);
- value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
- if (value) {
- reg = readl_relaxed(mmsys->regs + addr) & ~value;
- writel_relaxed(reg, mmsys->regs + addr);
- }
+ mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, false);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 03/10] soc: mediatek: mmsys: move register operation into mmsys path select function
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, Daniel Vetter, linux-arm-kernel
move register operation into mmsys path select function
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 140 +++++++++++++++++----------------
1 file changed, 71 insertions(+), 69 deletions(-)
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
index 6c03282..64c8030 100644
--- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -106,141 +106,161 @@ struct mtk_mmsys {
.clk_driver = "clk-mt8183-mm",
};
-static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next,
- unsigned int *addr)
+static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
{
- unsigned int value;
+ unsigned int addr, value, reg;
if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
- *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
value = OVL0_MOUT_EN_COLOR0;
} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
- *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
value = OVL_MOUT_EN_RDMA;
} else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
- *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
value = OD_MOUT_EN_RDMA0;
} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
- *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
value = UFOE_MOUT_EN_DSI0;
} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
- *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
value = OVL1_MOUT_EN_COLOR1;
} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
- *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
value = GAMMA_MOUT_EN_RDMA1;
} else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
- *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
value = OD1_MOUT_EN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DPI0;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DPI1;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DSI1;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DSI2;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DSI3;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DSI1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DSI2;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DSI3;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DPI0;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DPI1;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
value = RDMA2_SOUT_DPI0;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
value = RDMA2_SOUT_DPI1;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
value = RDMA2_SOUT_DSI1;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
value = RDMA2_SOUT_DSI2;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
value = RDMA2_SOUT_DSI3;
} else {
value = 0;
}
- return value;
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
}
-static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next,
- unsigned int *addr)
+static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
{
- unsigned int value;
+ unsigned int addr, value, reg;
if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
- *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
+ addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
value = COLOR0_SEL_IN_OVL0;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ addr = DISP_REG_CONFIG_DPI_SEL_IN;
value = DPI0_SEL_IN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ addr = DISP_REG_CONFIG_DPI_SEL_IN;
value = DPI1_SEL_IN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
value = DSI0_SEL_IN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ addr = DISP_REG_CONFIG_DSIO_SEL_IN;
value = DSI1_SEL_IN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
value = DSI2_SEL_IN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ addr = DISP_REG_CONFIG_DSIO_SEL_IN;
value = DSI3_SEL_IN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ addr = DISP_REG_CONFIG_DPI_SEL_IN;
value = DPI0_SEL_IN_RDMA2;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ addr = DISP_REG_CONFIG_DPI_SEL_IN;
value = DPI1_SEL_IN_RDMA2;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
value = DSI0_SEL_IN_RDMA2;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ addr = DISP_REG_CONFIG_DSIO_SEL_IN;
value = DSI1_SEL_IN_RDMA2;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
value = DSI2_SEL_IN_RDMA2;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
value = DSI3_SEL_IN_RDMA2;
} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
- *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
+ addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
value = COLOR1_SEL_IN_OVL1;
} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
- *addr = DISP_REG_CONFIG_DSI_SEL;
+ addr = DISP_REG_CONFIG_DSI_SEL;
value = DSI_SEL_IN_BLS;
} else {
value = 0;
}
- return value;
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
}
static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
@@ -265,21 +285,12 @@ void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id next)
{
struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
- unsigned int addr, value, reg;
- value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
- if (value) {
- reg = readl_relaxed(mmsys->regs + addr) | value;
- writel_relaxed(reg, mmsys->regs + addr);
- }
+ mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, true);
mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next);
- value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
- if (value) {
- reg = readl_relaxed(mmsys->regs + addr) | value;
- writel_relaxed(reg, mmsys->regs + addr);
- }
+ mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, true);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
@@ -288,19 +299,10 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id next)
{
struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
- unsigned int addr, value, reg;
- value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
- if (value) {
- reg = readl_relaxed(mmsys->regs + addr) & ~value;
- writel_relaxed(reg, mmsys->regs + addr);
- }
+ mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, false);
- value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
- if (value) {
- reg = readl_relaxed(mmsys->regs + addr) & ~value;
- writel_relaxed(reg, mmsys->regs + addr);
- }
+ mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, false);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
--
1.8.1.1.dirty
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 03/10] soc: mediatek: mmsys: move register operation into mmsys path select function
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, Daniel Vetter, linux-arm-kernel
move register operation into mmsys path select function
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 140 +++++++++++++++++----------------
1 file changed, 71 insertions(+), 69 deletions(-)
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
index 6c03282..64c8030 100644
--- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -106,141 +106,161 @@ struct mtk_mmsys {
.clk_driver = "clk-mt8183-mm",
};
-static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next,
- unsigned int *addr)
+static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
{
- unsigned int value;
+ unsigned int addr, value, reg;
if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
- *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
value = OVL0_MOUT_EN_COLOR0;
} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
- *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
value = OVL_MOUT_EN_RDMA;
} else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
- *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
value = OD_MOUT_EN_RDMA0;
} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
- *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
value = UFOE_MOUT_EN_DSI0;
} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
- *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
value = OVL1_MOUT_EN_COLOR1;
} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
- *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
value = GAMMA_MOUT_EN_RDMA1;
} else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
- *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
value = OD1_MOUT_EN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DPI0;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DPI1;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DSI1;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DSI2;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DSI3;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DSI1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DSI2;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DSI3;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DPI0;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DPI1;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
value = RDMA2_SOUT_DPI0;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
value = RDMA2_SOUT_DPI1;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
value = RDMA2_SOUT_DSI1;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
value = RDMA2_SOUT_DSI2;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
value = RDMA2_SOUT_DSI3;
} else {
value = 0;
}
- return value;
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
}
-static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next,
- unsigned int *addr)
+static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
{
- unsigned int value;
+ unsigned int addr, value, reg;
if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
- *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
+ addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
value = COLOR0_SEL_IN_OVL0;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ addr = DISP_REG_CONFIG_DPI_SEL_IN;
value = DPI0_SEL_IN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ addr = DISP_REG_CONFIG_DPI_SEL_IN;
value = DPI1_SEL_IN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
value = DSI0_SEL_IN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ addr = DISP_REG_CONFIG_DSIO_SEL_IN;
value = DSI1_SEL_IN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
value = DSI2_SEL_IN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ addr = DISP_REG_CONFIG_DSIO_SEL_IN;
value = DSI3_SEL_IN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ addr = DISP_REG_CONFIG_DPI_SEL_IN;
value = DPI0_SEL_IN_RDMA2;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ addr = DISP_REG_CONFIG_DPI_SEL_IN;
value = DPI1_SEL_IN_RDMA2;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
value = DSI0_SEL_IN_RDMA2;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ addr = DISP_REG_CONFIG_DSIO_SEL_IN;
value = DSI1_SEL_IN_RDMA2;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
value = DSI2_SEL_IN_RDMA2;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
value = DSI3_SEL_IN_RDMA2;
} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
- *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
+ addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
value = COLOR1_SEL_IN_OVL1;
} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
- *addr = DISP_REG_CONFIG_DSI_SEL;
+ addr = DISP_REG_CONFIG_DSI_SEL;
value = DSI_SEL_IN_BLS;
} else {
value = 0;
}
- return value;
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
}
static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
@@ -265,21 +285,12 @@ void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id next)
{
struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
- unsigned int addr, value, reg;
- value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
- if (value) {
- reg = readl_relaxed(mmsys->regs + addr) | value;
- writel_relaxed(reg, mmsys->regs + addr);
- }
+ mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, true);
mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next);
- value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
- if (value) {
- reg = readl_relaxed(mmsys->regs + addr) | value;
- writel_relaxed(reg, mmsys->regs + addr);
- }
+ mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, true);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
@@ -288,19 +299,10 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id next)
{
struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
- unsigned int addr, value, reg;
- value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
- if (value) {
- reg = readl_relaxed(mmsys->regs + addr) & ~value;
- writel_relaxed(reg, mmsys->regs + addr);
- }
+ mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, false);
- value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
- if (value) {
- reg = readl_relaxed(mmsys->regs + addr) & ~value;
- writel_relaxed(reg, mmsys->regs + addr);
- }
+ mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, false);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
--
1.8.1.1.dirty
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 03/10] soc: mediatek: mmsys: move register operation into mmsys path select function
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, linux-arm-kernel
move register operation into mmsys path select function
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 140 +++++++++++++++++----------------
1 file changed, 71 insertions(+), 69 deletions(-)
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
index 6c03282..64c8030 100644
--- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -106,141 +106,161 @@ struct mtk_mmsys {
.clk_driver = "clk-mt8183-mm",
};
-static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next,
- unsigned int *addr)
+static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
{
- unsigned int value;
+ unsigned int addr, value, reg;
if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
- *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
value = OVL0_MOUT_EN_COLOR0;
} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
- *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
value = OVL_MOUT_EN_RDMA;
} else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
- *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
value = OD_MOUT_EN_RDMA0;
} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
- *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
value = UFOE_MOUT_EN_DSI0;
} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
- *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
value = OVL1_MOUT_EN_COLOR1;
} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
- *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
value = GAMMA_MOUT_EN_RDMA1;
} else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
- *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
value = OD1_MOUT_EN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DPI0;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DPI1;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DSI1;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DSI2;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DSI3;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DSI1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DSI2;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DSI3;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DPI0;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DPI1;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
value = RDMA2_SOUT_DPI0;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
value = RDMA2_SOUT_DPI1;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
value = RDMA2_SOUT_DSI1;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
value = RDMA2_SOUT_DSI2;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
value = RDMA2_SOUT_DSI3;
} else {
value = 0;
}
- return value;
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
}
-static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next,
- unsigned int *addr)
+static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
{
- unsigned int value;
+ unsigned int addr, value, reg;
if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
- *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
+ addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
value = COLOR0_SEL_IN_OVL0;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ addr = DISP_REG_CONFIG_DPI_SEL_IN;
value = DPI0_SEL_IN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ addr = DISP_REG_CONFIG_DPI_SEL_IN;
value = DPI1_SEL_IN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
value = DSI0_SEL_IN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ addr = DISP_REG_CONFIG_DSIO_SEL_IN;
value = DSI1_SEL_IN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
value = DSI2_SEL_IN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ addr = DISP_REG_CONFIG_DSIO_SEL_IN;
value = DSI3_SEL_IN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ addr = DISP_REG_CONFIG_DPI_SEL_IN;
value = DPI0_SEL_IN_RDMA2;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ addr = DISP_REG_CONFIG_DPI_SEL_IN;
value = DPI1_SEL_IN_RDMA2;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
value = DSI0_SEL_IN_RDMA2;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ addr = DISP_REG_CONFIG_DSIO_SEL_IN;
value = DSI1_SEL_IN_RDMA2;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
value = DSI2_SEL_IN_RDMA2;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
value = DSI3_SEL_IN_RDMA2;
} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
- *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
+ addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
value = COLOR1_SEL_IN_OVL1;
} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
- *addr = DISP_REG_CONFIG_DSI_SEL;
+ addr = DISP_REG_CONFIG_DSI_SEL;
value = DSI_SEL_IN_BLS;
} else {
value = 0;
}
- return value;
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
}
static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
@@ -265,21 +285,12 @@ void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id next)
{
struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
- unsigned int addr, value, reg;
- value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
- if (value) {
- reg = readl_relaxed(mmsys->regs + addr) | value;
- writel_relaxed(reg, mmsys->regs + addr);
- }
+ mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, true);
mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next);
- value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
- if (value) {
- reg = readl_relaxed(mmsys->regs + addr) | value;
- writel_relaxed(reg, mmsys->regs + addr);
- }
+ mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, true);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
@@ -288,19 +299,10 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id next)
{
struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
- unsigned int addr, value, reg;
- value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
- if (value) {
- reg = readl_relaxed(mmsys->regs + addr) & ~value;
- writel_relaxed(reg, mmsys->regs + addr);
- }
+ mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, false);
- value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
- if (value) {
- reg = readl_relaxed(mmsys->regs + addr) & ~value;
- writel_relaxed(reg, mmsys->regs + addr);
- }
+ mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, false);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
--
1.8.1.1.dirty
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^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 04/10] soc: mediatek: mmsys: Use function call for setting the routing registers
2021-01-05 3:06 ` Yongqiang Niu
(?)
(?)
@ 2021-01-05 3:06 ` Yongqiang Niu
-1 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Yongqiang Niu
Actually, setting the registers for routing, use multiple 'if-else' for different
routes, but this code would be more and more complicated while we
support more and more SoCs. Change that and use a function call per SoC so the
code will be more portable and clear.
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/soc/mediatek/mmsys/Makefile | 1 +
drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 254 ++++++++++++++++++++++++++++
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 266 +++---------------------------
include/linux/soc/mediatek/mtk-mmsys.h | 16 ++
4 files changed, 295 insertions(+), 242 deletions(-)
create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c
diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
index f44eadc..ac03025 100644
--- a/drivers/soc/mediatek/mmsys/Makefile
+++ b/drivers/soc/mediatek/mmsys/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o
obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c
new file mode 100644
index 0000000..6bcc5f2
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c
@@ -0,0 +1,254 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: James Liao <jamesjj.liao@mediatek.com>
+ */
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+
+#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
+#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
+#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
+#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
+#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
+#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
+#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
+#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
+#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
+#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
+#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
+#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
+#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
+#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
+
+#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
+#define DISP_REG_CONFIG_OUT_SEL 0x04c
+#define DISP_REG_CONFIG_DSI_SEL 0x050
+#define DISP_REG_CONFIG_DPI_SEL 0x064
+
+#define OVL0_MOUT_EN_COLOR0 0x1
+#define OD_MOUT_EN_RDMA0 0x1
+#define OD1_MOUT_EN_RDMA1 BIT(16)
+#define UFOE_MOUT_EN_DSI0 0x1
+#define COLOR0_SEL_IN_OVL0 0x1
+#define OVL1_MOUT_EN_COLOR1 0x1
+#define GAMMA_MOUT_EN_RDMA1 0x1
+#define RDMA0_SOUT_DPI0 0x2
+#define RDMA0_SOUT_DPI1 0x3
+#define RDMA0_SOUT_DSI1 0x1
+#define RDMA0_SOUT_DSI2 0x4
+#define RDMA0_SOUT_DSI3 0x5
+#define RDMA1_SOUT_DPI0 0x2
+#define RDMA1_SOUT_DPI1 0x3
+#define RDMA1_SOUT_DSI1 0x1
+#define RDMA1_SOUT_DSI2 0x4
+#define RDMA1_SOUT_DSI3 0x5
+#define RDMA2_SOUT_DPI0 0x2
+#define RDMA2_SOUT_DPI1 0x3
+#define RDMA2_SOUT_DSI1 0x1
+#define RDMA2_SOUT_DSI2 0x4
+#define RDMA2_SOUT_DSI3 0x5
+#define DPI0_SEL_IN_RDMA1 0x1
+#define DPI0_SEL_IN_RDMA2 0x3
+#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
+#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
+#define DSI0_SEL_IN_RDMA1 0x1
+#define DSI0_SEL_IN_RDMA2 0x4
+#define DSI1_SEL_IN_RDMA1 0x1
+#define DSI1_SEL_IN_RDMA2 0x4
+#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
+#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
+#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
+#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
+#define COLOR1_SEL_IN_OVL1 0x1
+
+#define OVL_MOUT_EN_RDMA 0x1
+#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
+#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
+#define DSI_SEL_IN_BLS 0x0
+#define DPI_SEL_IN_BLS 0x0
+#define DSI_SEL_IN_RDMA 0x1
+
+static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
+{
+ unsigned int addr, value, reg;
+
+ if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
+ addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
+ value = OVL0_MOUT_EN_COLOR0;
+ } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
+ addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
+ value = OVL_MOUT_EN_RDMA;
+ } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
+ addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+ value = OD_MOUT_EN_RDMA0;
+ } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
+ addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
+ value = UFOE_MOUT_EN_DSI0;
+ } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
+ addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
+ value = OVL1_MOUT_EN_COLOR1;
+ } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
+ addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
+ value = GAMMA_MOUT_EN_RDMA1;
+ } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
+ addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+ value = OD1_MOUT_EN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DPI0;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DPI1;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DSI1;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DSI2;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DSI3;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DSI1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DSI2;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DSI3;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DPI0;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DPI1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DPI0;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DPI1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DSI1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DSI2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DSI3;
+ } else {
+ value = 0;
+ }
+
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+
+static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
+{
+ unsigned int addr, value, reg;
+
+ if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
+ addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
+ value = COLOR0_SEL_IN_OVL0;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
+ addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ value = DPI0_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
+ addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ value = DPI1_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI0_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
+ addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ value = DSI1_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI2_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
+ addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ value = DSI3_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
+ addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ value = DPI0_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
+ addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ value = DPI1_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI0_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
+ addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ value = DSI1_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI2_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI3_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
+ addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
+ value = COLOR1_SEL_IN_OVL1;
+ } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
+ addr = DISP_REG_CONFIG_DSI_SEL;
+ value = DSI_SEL_IN_BLS;
+ } else {
+ value = 0;
+ }
+
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+
+static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next)
+{
+ if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
+ writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
+ config_regs + DISP_REG_CONFIG_OUT_SEL);
+ } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
+ writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
+ config_regs + DISP_REG_CONFIG_OUT_SEL);
+ writel_relaxed(DSI_SEL_IN_RDMA,
+ config_regs + DISP_REG_CONFIG_DSI_SEL);
+ writel_relaxed(DPI_SEL_IN_BLS,
+ config_regs + DISP_REG_CONFIG_DPI_SEL);
+ }
+}
+
+struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs = {
+ .mout_en = mtk_mmsys_ddp_mout_en,
+ .sel_in = mtk_mmsys_ddp_sel_in,
+ .sout_sel = mtk_mmsys_ddp_sout_sel,
+};
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
index 64c8030..4ca72f8 100644
--- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -10,71 +10,9 @@
#include <linux/platform_device.h>
#include <linux/soc/mediatek/mtk-mmsys.h>
-#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
-#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
-#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
-#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
-#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
-#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
-#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
-#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
-#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
-#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
-#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
-#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
-#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
-#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
-
-#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
-#define DISP_REG_CONFIG_OUT_SEL 0x04c
-#define DISP_REG_CONFIG_DSI_SEL 0x050
-#define DISP_REG_CONFIG_DPI_SEL 0x064
-
-#define OVL0_MOUT_EN_COLOR0 0x1
-#define OD_MOUT_EN_RDMA0 0x1
-#define OD1_MOUT_EN_RDMA1 BIT(16)
-#define UFOE_MOUT_EN_DSI0 0x1
-#define COLOR0_SEL_IN_OVL0 0x1
-#define OVL1_MOUT_EN_COLOR1 0x1
-#define GAMMA_MOUT_EN_RDMA1 0x1
-#define RDMA0_SOUT_DPI0 0x2
-#define RDMA0_SOUT_DPI1 0x3
-#define RDMA0_SOUT_DSI1 0x1
-#define RDMA0_SOUT_DSI2 0x4
-#define RDMA0_SOUT_DSI3 0x5
-#define RDMA1_SOUT_DPI0 0x2
-#define RDMA1_SOUT_DPI1 0x3
-#define RDMA1_SOUT_DSI1 0x1
-#define RDMA1_SOUT_DSI2 0x4
-#define RDMA1_SOUT_DSI3 0x5
-#define RDMA2_SOUT_DPI0 0x2
-#define RDMA2_SOUT_DPI1 0x3
-#define RDMA2_SOUT_DSI1 0x1
-#define RDMA2_SOUT_DSI2 0x4
-#define RDMA2_SOUT_DSI3 0x5
-#define DPI0_SEL_IN_RDMA1 0x1
-#define DPI0_SEL_IN_RDMA2 0x3
-#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
-#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
-#define DSI0_SEL_IN_RDMA1 0x1
-#define DSI0_SEL_IN_RDMA2 0x4
-#define DSI1_SEL_IN_RDMA1 0x1
-#define DSI1_SEL_IN_RDMA2 0x4
-#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
-#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
-#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
-#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
-#define COLOR1_SEL_IN_OVL1 0x1
-
-#define OVL_MOUT_EN_RDMA 0x1
-#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
-#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
-#define DSI_SEL_IN_BLS 0x0
-#define DPI_SEL_IN_BLS 0x0
-#define DSI_SEL_IN_RDMA 0x1
-
struct mtk_mmsys_driver_data {
const char *clk_driver;
+ const struct mtk_mmsys_conn_funcs *funcs;
};
struct mtk_mmsys {
@@ -84,213 +22,51 @@ struct mtk_mmsys {
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.clk_driver = "clk-mt2701-mm",
+ .funcs = &mt2701_mmsys_funcs,
};
static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
.clk_driver = "clk-mt2712-mm",
+ .funcs = &mt2701_mmsys_funcs,
};
static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
.clk_driver = "clk-mt6779-mm",
+ .funcs = &mt2701_mmsys_funcs,
};
static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
.clk_driver = "clk-mt6797-mm",
+ .funcs = &mt2701_mmsys_funcs,
};
static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.clk_driver = "clk-mt8173-mm",
+ .funcs = &mt2701_mmsys_funcs,
};
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.clk_driver = "clk-mt8183-mm",
};
-static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
- enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next,
- bool enable)
-{
- unsigned int addr, value, reg;
-
- if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
- addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
- value = OVL0_MOUT_EN_COLOR0;
- } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
- addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
- value = OVL_MOUT_EN_RDMA;
- } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
- addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
- value = OD_MOUT_EN_RDMA0;
- } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
- addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
- value = UFOE_MOUT_EN_DSI0;
- } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
- addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
- value = OVL1_MOUT_EN_COLOR1;
- } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
- addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
- value = GAMMA_MOUT_EN_RDMA1;
- } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
- addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
- value = OD1_MOUT_EN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
- addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DPI0;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
- addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DPI1;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
- addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DSI1;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
- addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DSI2;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
- addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DSI3;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
- addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DSI1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
- addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DSI2;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
- addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DSI3;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
- addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DPI0;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
- addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DPI1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
- addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DPI0;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
- addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DPI1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
- addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DSI1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
- addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DSI2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
- addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DSI3;
- } else {
- value = 0;
- }
-
- if (value) {
- reg = readl_relaxed(config_regs + addr);
-
- if (enable)
- reg |= value;
- else
- reg &= ~value;
-
- writel_relaxed(reg, config_regs + addr);
- }
-}
-
-static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
- enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next,
- bool enable)
-{
- unsigned int addr, value, reg;
-
- if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
- addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
- value = COLOR0_SEL_IN_OVL0;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
- addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI0_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
- addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI1_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
- addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI0_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
- addr = DISP_REG_CONFIG_DSIO_SEL_IN;
- value = DSI1_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
- addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI2_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
- addr = DISP_REG_CONFIG_DSIO_SEL_IN;
- value = DSI3_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
- addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI0_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
- addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI1_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
- addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI0_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
- addr = DISP_REG_CONFIG_DSIO_SEL_IN;
- value = DSI1_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
- addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI2_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
- addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI3_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
- addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
- value = COLOR1_SEL_IN_OVL1;
- } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
- addr = DISP_REG_CONFIG_DSI_SEL;
- value = DSI_SEL_IN_BLS;
- } else {
- value = 0;
- }
-
- if (value) {
- reg = readl_relaxed(config_regs + addr);
-
- if (enable)
- reg |= value;
- else
- reg &= ~value;
-
- writel_relaxed(reg, config_regs + addr);
- }
-}
-
-static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
- enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next)
-{
- if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
- writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
- config_regs + DISP_REG_CONFIG_OUT_SEL);
- } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
- writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
- config_regs + DISP_REG_CONFIG_OUT_SEL);
- writel_relaxed(DSI_SEL_IN_RDMA,
- config_regs + DISP_REG_CONFIG_DSI_SEL);
- writel_relaxed(DPI_SEL_IN_BLS,
- config_regs + DISP_REG_CONFIG_DPI_SEL);
- }
-}
-
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next)
{
struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const struct mtk_mmsys_conn_funcs *funcs = mmsys->data->funcs;
+
+ if (!funcs)
+ return;
- mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, true);
+ if (funcs->mout_en)
+ funcs->mout_en(mmsys->regs, cur, next, true);
- mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next);
+ if (funcs->sout_sel)
+ funcs->sout_sel(mmsys->regs, cur, next);
- mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, true);
+ if (funcs->sel_in)
+ funcs->sel_in(mmsys->regs, cur, next, true);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
@@ -299,10 +75,16 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id next)
{
struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const struct mtk_mmsys_conn_funcs *funcs = mmsys->data->funcs;
+
+ if (!funcs)
+ return;
- mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, false);
+ if (funcs->mout_en)
+ funcs->mout_en(mmsys->regs, cur, next, false);
- mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, false);
+ if (funcs->sel_in)
+ funcs->sel_in(mmsys->regs, cur, next, false);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 2228bf6..89000a9 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -42,6 +42,22 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_ID_MAX,
};
+struct mtk_mmsys_conn_funcs {
+ void (*mout_en)(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable);
+ void (*sel_in)(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable);
+ void (*sout_sel)(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next);
+};
+
+extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs;
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 04/10] soc: mediatek: mmsys: Use function call for setting the routing registers
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, Daniel Vetter, linux-arm-kernel
Actually, setting the registers for routing, use multiple 'if-else' for different
routes, but this code would be more and more complicated while we
support more and more SoCs. Change that and use a function call per SoC so the
code will be more portable and clear.
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/soc/mediatek/mmsys/Makefile | 1 +
drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 254 ++++++++++++++++++++++++++++
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 266 +++---------------------------
include/linux/soc/mediatek/mtk-mmsys.h | 16 ++
4 files changed, 295 insertions(+), 242 deletions(-)
create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c
diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
index f44eadc..ac03025 100644
--- a/drivers/soc/mediatek/mmsys/Makefile
+++ b/drivers/soc/mediatek/mmsys/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o
obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c
new file mode 100644
index 0000000..6bcc5f2
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c
@@ -0,0 +1,254 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: James Liao <jamesjj.liao@mediatek.com>
+ */
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+
+#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
+#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
+#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
+#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
+#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
+#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
+#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
+#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
+#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
+#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
+#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
+#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
+#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
+#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
+
+#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
+#define DISP_REG_CONFIG_OUT_SEL 0x04c
+#define DISP_REG_CONFIG_DSI_SEL 0x050
+#define DISP_REG_CONFIG_DPI_SEL 0x064
+
+#define OVL0_MOUT_EN_COLOR0 0x1
+#define OD_MOUT_EN_RDMA0 0x1
+#define OD1_MOUT_EN_RDMA1 BIT(16)
+#define UFOE_MOUT_EN_DSI0 0x1
+#define COLOR0_SEL_IN_OVL0 0x1
+#define OVL1_MOUT_EN_COLOR1 0x1
+#define GAMMA_MOUT_EN_RDMA1 0x1
+#define RDMA0_SOUT_DPI0 0x2
+#define RDMA0_SOUT_DPI1 0x3
+#define RDMA0_SOUT_DSI1 0x1
+#define RDMA0_SOUT_DSI2 0x4
+#define RDMA0_SOUT_DSI3 0x5
+#define RDMA1_SOUT_DPI0 0x2
+#define RDMA1_SOUT_DPI1 0x3
+#define RDMA1_SOUT_DSI1 0x1
+#define RDMA1_SOUT_DSI2 0x4
+#define RDMA1_SOUT_DSI3 0x5
+#define RDMA2_SOUT_DPI0 0x2
+#define RDMA2_SOUT_DPI1 0x3
+#define RDMA2_SOUT_DSI1 0x1
+#define RDMA2_SOUT_DSI2 0x4
+#define RDMA2_SOUT_DSI3 0x5
+#define DPI0_SEL_IN_RDMA1 0x1
+#define DPI0_SEL_IN_RDMA2 0x3
+#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
+#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
+#define DSI0_SEL_IN_RDMA1 0x1
+#define DSI0_SEL_IN_RDMA2 0x4
+#define DSI1_SEL_IN_RDMA1 0x1
+#define DSI1_SEL_IN_RDMA2 0x4
+#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
+#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
+#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
+#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
+#define COLOR1_SEL_IN_OVL1 0x1
+
+#define OVL_MOUT_EN_RDMA 0x1
+#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
+#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
+#define DSI_SEL_IN_BLS 0x0
+#define DPI_SEL_IN_BLS 0x0
+#define DSI_SEL_IN_RDMA 0x1
+
+static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
+{
+ unsigned int addr, value, reg;
+
+ if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
+ addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
+ value = OVL0_MOUT_EN_COLOR0;
+ } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
+ addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
+ value = OVL_MOUT_EN_RDMA;
+ } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
+ addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+ value = OD_MOUT_EN_RDMA0;
+ } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
+ addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
+ value = UFOE_MOUT_EN_DSI0;
+ } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
+ addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
+ value = OVL1_MOUT_EN_COLOR1;
+ } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
+ addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
+ value = GAMMA_MOUT_EN_RDMA1;
+ } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
+ addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+ value = OD1_MOUT_EN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DPI0;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DPI1;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DSI1;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DSI2;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DSI3;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DSI1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DSI2;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DSI3;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DPI0;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DPI1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DPI0;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DPI1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DSI1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DSI2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DSI3;
+ } else {
+ value = 0;
+ }
+
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+
+static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
+{
+ unsigned int addr, value, reg;
+
+ if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
+ addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
+ value = COLOR0_SEL_IN_OVL0;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
+ addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ value = DPI0_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
+ addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ value = DPI1_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI0_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
+ addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ value = DSI1_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI2_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
+ addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ value = DSI3_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
+ addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ value = DPI0_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
+ addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ value = DPI1_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI0_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
+ addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ value = DSI1_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI2_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI3_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
+ addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
+ value = COLOR1_SEL_IN_OVL1;
+ } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
+ addr = DISP_REG_CONFIG_DSI_SEL;
+ value = DSI_SEL_IN_BLS;
+ } else {
+ value = 0;
+ }
+
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+
+static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next)
+{
+ if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
+ writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
+ config_regs + DISP_REG_CONFIG_OUT_SEL);
+ } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
+ writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
+ config_regs + DISP_REG_CONFIG_OUT_SEL);
+ writel_relaxed(DSI_SEL_IN_RDMA,
+ config_regs + DISP_REG_CONFIG_DSI_SEL);
+ writel_relaxed(DPI_SEL_IN_BLS,
+ config_regs + DISP_REG_CONFIG_DPI_SEL);
+ }
+}
+
+struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs = {
+ .mout_en = mtk_mmsys_ddp_mout_en,
+ .sel_in = mtk_mmsys_ddp_sel_in,
+ .sout_sel = mtk_mmsys_ddp_sout_sel,
+};
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
index 64c8030..4ca72f8 100644
--- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -10,71 +10,9 @@
#include <linux/platform_device.h>
#include <linux/soc/mediatek/mtk-mmsys.h>
-#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
-#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
-#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
-#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
-#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
-#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
-#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
-#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
-#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
-#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
-#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
-#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
-#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
-#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
-
-#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
-#define DISP_REG_CONFIG_OUT_SEL 0x04c
-#define DISP_REG_CONFIG_DSI_SEL 0x050
-#define DISP_REG_CONFIG_DPI_SEL 0x064
-
-#define OVL0_MOUT_EN_COLOR0 0x1
-#define OD_MOUT_EN_RDMA0 0x1
-#define OD1_MOUT_EN_RDMA1 BIT(16)
-#define UFOE_MOUT_EN_DSI0 0x1
-#define COLOR0_SEL_IN_OVL0 0x1
-#define OVL1_MOUT_EN_COLOR1 0x1
-#define GAMMA_MOUT_EN_RDMA1 0x1
-#define RDMA0_SOUT_DPI0 0x2
-#define RDMA0_SOUT_DPI1 0x3
-#define RDMA0_SOUT_DSI1 0x1
-#define RDMA0_SOUT_DSI2 0x4
-#define RDMA0_SOUT_DSI3 0x5
-#define RDMA1_SOUT_DPI0 0x2
-#define RDMA1_SOUT_DPI1 0x3
-#define RDMA1_SOUT_DSI1 0x1
-#define RDMA1_SOUT_DSI2 0x4
-#define RDMA1_SOUT_DSI3 0x5
-#define RDMA2_SOUT_DPI0 0x2
-#define RDMA2_SOUT_DPI1 0x3
-#define RDMA2_SOUT_DSI1 0x1
-#define RDMA2_SOUT_DSI2 0x4
-#define RDMA2_SOUT_DSI3 0x5
-#define DPI0_SEL_IN_RDMA1 0x1
-#define DPI0_SEL_IN_RDMA2 0x3
-#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
-#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
-#define DSI0_SEL_IN_RDMA1 0x1
-#define DSI0_SEL_IN_RDMA2 0x4
-#define DSI1_SEL_IN_RDMA1 0x1
-#define DSI1_SEL_IN_RDMA2 0x4
-#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
-#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
-#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
-#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
-#define COLOR1_SEL_IN_OVL1 0x1
-
-#define OVL_MOUT_EN_RDMA 0x1
-#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
-#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
-#define DSI_SEL_IN_BLS 0x0
-#define DPI_SEL_IN_BLS 0x0
-#define DSI_SEL_IN_RDMA 0x1
-
struct mtk_mmsys_driver_data {
const char *clk_driver;
+ const struct mtk_mmsys_conn_funcs *funcs;
};
struct mtk_mmsys {
@@ -84,213 +22,51 @@ struct mtk_mmsys {
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.clk_driver = "clk-mt2701-mm",
+ .funcs = &mt2701_mmsys_funcs,
};
static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
.clk_driver = "clk-mt2712-mm",
+ .funcs = &mt2701_mmsys_funcs,
};
static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
.clk_driver = "clk-mt6779-mm",
+ .funcs = &mt2701_mmsys_funcs,
};
static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
.clk_driver = "clk-mt6797-mm",
+ .funcs = &mt2701_mmsys_funcs,
};
static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.clk_driver = "clk-mt8173-mm",
+ .funcs = &mt2701_mmsys_funcs,
};
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.clk_driver = "clk-mt8183-mm",
};
-static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
- enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next,
- bool enable)
-{
- unsigned int addr, value, reg;
-
- if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
- addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
- value = OVL0_MOUT_EN_COLOR0;
- } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
- addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
- value = OVL_MOUT_EN_RDMA;
- } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
- addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
- value = OD_MOUT_EN_RDMA0;
- } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
- addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
- value = UFOE_MOUT_EN_DSI0;
- } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
- addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
- value = OVL1_MOUT_EN_COLOR1;
- } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
- addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
- value = GAMMA_MOUT_EN_RDMA1;
- } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
- addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
- value = OD1_MOUT_EN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
- addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DPI0;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
- addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DPI1;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
- addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DSI1;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
- addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DSI2;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
- addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DSI3;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
- addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DSI1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
- addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DSI2;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
- addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DSI3;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
- addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DPI0;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
- addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DPI1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
- addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DPI0;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
- addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DPI1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
- addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DSI1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
- addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DSI2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
- addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DSI3;
- } else {
- value = 0;
- }
-
- if (value) {
- reg = readl_relaxed(config_regs + addr);
-
- if (enable)
- reg |= value;
- else
- reg &= ~value;
-
- writel_relaxed(reg, config_regs + addr);
- }
-}
-
-static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
- enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next,
- bool enable)
-{
- unsigned int addr, value, reg;
-
- if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
- addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
- value = COLOR0_SEL_IN_OVL0;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
- addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI0_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
- addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI1_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
- addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI0_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
- addr = DISP_REG_CONFIG_DSIO_SEL_IN;
- value = DSI1_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
- addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI2_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
- addr = DISP_REG_CONFIG_DSIO_SEL_IN;
- value = DSI3_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
- addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI0_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
- addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI1_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
- addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI0_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
- addr = DISP_REG_CONFIG_DSIO_SEL_IN;
- value = DSI1_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
- addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI2_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
- addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI3_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
- addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
- value = COLOR1_SEL_IN_OVL1;
- } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
- addr = DISP_REG_CONFIG_DSI_SEL;
- value = DSI_SEL_IN_BLS;
- } else {
- value = 0;
- }
-
- if (value) {
- reg = readl_relaxed(config_regs + addr);
-
- if (enable)
- reg |= value;
- else
- reg &= ~value;
-
- writel_relaxed(reg, config_regs + addr);
- }
-}
-
-static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
- enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next)
-{
- if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
- writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
- config_regs + DISP_REG_CONFIG_OUT_SEL);
- } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
- writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
- config_regs + DISP_REG_CONFIG_OUT_SEL);
- writel_relaxed(DSI_SEL_IN_RDMA,
- config_regs + DISP_REG_CONFIG_DSI_SEL);
- writel_relaxed(DPI_SEL_IN_BLS,
- config_regs + DISP_REG_CONFIG_DPI_SEL);
- }
-}
-
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next)
{
struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const struct mtk_mmsys_conn_funcs *funcs = mmsys->data->funcs;
+
+ if (!funcs)
+ return;
- mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, true);
+ if (funcs->mout_en)
+ funcs->mout_en(mmsys->regs, cur, next, true);
- mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next);
+ if (funcs->sout_sel)
+ funcs->sout_sel(mmsys->regs, cur, next);
- mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, true);
+ if (funcs->sel_in)
+ funcs->sel_in(mmsys->regs, cur, next, true);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
@@ -299,10 +75,16 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id next)
{
struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const struct mtk_mmsys_conn_funcs *funcs = mmsys->data->funcs;
+
+ if (!funcs)
+ return;
- mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, false);
+ if (funcs->mout_en)
+ funcs->mout_en(mmsys->regs, cur, next, false);
- mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, false);
+ if (funcs->sel_in)
+ funcs->sel_in(mmsys->regs, cur, next, false);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 2228bf6..89000a9 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -42,6 +42,22 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_ID_MAX,
};
+struct mtk_mmsys_conn_funcs {
+ void (*mout_en)(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable);
+ void (*sel_in)(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable);
+ void (*sout_sel)(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next);
+};
+
+extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs;
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
--
1.8.1.1.dirty
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 04/10] soc: mediatek: mmsys: Use function call for setting the routing registers
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, Daniel Vetter, linux-arm-kernel
Actually, setting the registers for routing, use multiple 'if-else' for different
routes, but this code would be more and more complicated while we
support more and more SoCs. Change that and use a function call per SoC so the
code will be more portable and clear.
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/soc/mediatek/mmsys/Makefile | 1 +
drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 254 ++++++++++++++++++++++++++++
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 266 +++---------------------------
include/linux/soc/mediatek/mtk-mmsys.h | 16 ++
4 files changed, 295 insertions(+), 242 deletions(-)
create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c
diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
index f44eadc..ac03025 100644
--- a/drivers/soc/mediatek/mmsys/Makefile
+++ b/drivers/soc/mediatek/mmsys/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o
obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c
new file mode 100644
index 0000000..6bcc5f2
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c
@@ -0,0 +1,254 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: James Liao <jamesjj.liao@mediatek.com>
+ */
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+
+#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
+#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
+#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
+#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
+#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
+#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
+#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
+#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
+#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
+#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
+#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
+#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
+#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
+#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
+
+#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
+#define DISP_REG_CONFIG_OUT_SEL 0x04c
+#define DISP_REG_CONFIG_DSI_SEL 0x050
+#define DISP_REG_CONFIG_DPI_SEL 0x064
+
+#define OVL0_MOUT_EN_COLOR0 0x1
+#define OD_MOUT_EN_RDMA0 0x1
+#define OD1_MOUT_EN_RDMA1 BIT(16)
+#define UFOE_MOUT_EN_DSI0 0x1
+#define COLOR0_SEL_IN_OVL0 0x1
+#define OVL1_MOUT_EN_COLOR1 0x1
+#define GAMMA_MOUT_EN_RDMA1 0x1
+#define RDMA0_SOUT_DPI0 0x2
+#define RDMA0_SOUT_DPI1 0x3
+#define RDMA0_SOUT_DSI1 0x1
+#define RDMA0_SOUT_DSI2 0x4
+#define RDMA0_SOUT_DSI3 0x5
+#define RDMA1_SOUT_DPI0 0x2
+#define RDMA1_SOUT_DPI1 0x3
+#define RDMA1_SOUT_DSI1 0x1
+#define RDMA1_SOUT_DSI2 0x4
+#define RDMA1_SOUT_DSI3 0x5
+#define RDMA2_SOUT_DPI0 0x2
+#define RDMA2_SOUT_DPI1 0x3
+#define RDMA2_SOUT_DSI1 0x1
+#define RDMA2_SOUT_DSI2 0x4
+#define RDMA2_SOUT_DSI3 0x5
+#define DPI0_SEL_IN_RDMA1 0x1
+#define DPI0_SEL_IN_RDMA2 0x3
+#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
+#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
+#define DSI0_SEL_IN_RDMA1 0x1
+#define DSI0_SEL_IN_RDMA2 0x4
+#define DSI1_SEL_IN_RDMA1 0x1
+#define DSI1_SEL_IN_RDMA2 0x4
+#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
+#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
+#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
+#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
+#define COLOR1_SEL_IN_OVL1 0x1
+
+#define OVL_MOUT_EN_RDMA 0x1
+#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
+#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
+#define DSI_SEL_IN_BLS 0x0
+#define DPI_SEL_IN_BLS 0x0
+#define DSI_SEL_IN_RDMA 0x1
+
+static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
+{
+ unsigned int addr, value, reg;
+
+ if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
+ addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
+ value = OVL0_MOUT_EN_COLOR0;
+ } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
+ addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
+ value = OVL_MOUT_EN_RDMA;
+ } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
+ addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+ value = OD_MOUT_EN_RDMA0;
+ } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
+ addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
+ value = UFOE_MOUT_EN_DSI0;
+ } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
+ addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
+ value = OVL1_MOUT_EN_COLOR1;
+ } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
+ addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
+ value = GAMMA_MOUT_EN_RDMA1;
+ } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
+ addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+ value = OD1_MOUT_EN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DPI0;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DPI1;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DSI1;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DSI2;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DSI3;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DSI1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DSI2;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DSI3;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DPI0;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DPI1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DPI0;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DPI1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DSI1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DSI2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DSI3;
+ } else {
+ value = 0;
+ }
+
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+
+static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
+{
+ unsigned int addr, value, reg;
+
+ if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
+ addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
+ value = COLOR0_SEL_IN_OVL0;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
+ addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ value = DPI0_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
+ addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ value = DPI1_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI0_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
+ addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ value = DSI1_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI2_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
+ addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ value = DSI3_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
+ addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ value = DPI0_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
+ addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ value = DPI1_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI0_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
+ addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ value = DSI1_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI2_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI3_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
+ addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
+ value = COLOR1_SEL_IN_OVL1;
+ } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
+ addr = DISP_REG_CONFIG_DSI_SEL;
+ value = DSI_SEL_IN_BLS;
+ } else {
+ value = 0;
+ }
+
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+
+static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next)
+{
+ if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
+ writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
+ config_regs + DISP_REG_CONFIG_OUT_SEL);
+ } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
+ writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
+ config_regs + DISP_REG_CONFIG_OUT_SEL);
+ writel_relaxed(DSI_SEL_IN_RDMA,
+ config_regs + DISP_REG_CONFIG_DSI_SEL);
+ writel_relaxed(DPI_SEL_IN_BLS,
+ config_regs + DISP_REG_CONFIG_DPI_SEL);
+ }
+}
+
+struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs = {
+ .mout_en = mtk_mmsys_ddp_mout_en,
+ .sel_in = mtk_mmsys_ddp_sel_in,
+ .sout_sel = mtk_mmsys_ddp_sout_sel,
+};
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
index 64c8030..4ca72f8 100644
--- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -10,71 +10,9 @@
#include <linux/platform_device.h>
#include <linux/soc/mediatek/mtk-mmsys.h>
-#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
-#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
-#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
-#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
-#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
-#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
-#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
-#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
-#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
-#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
-#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
-#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
-#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
-#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
-
-#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
-#define DISP_REG_CONFIG_OUT_SEL 0x04c
-#define DISP_REG_CONFIG_DSI_SEL 0x050
-#define DISP_REG_CONFIG_DPI_SEL 0x064
-
-#define OVL0_MOUT_EN_COLOR0 0x1
-#define OD_MOUT_EN_RDMA0 0x1
-#define OD1_MOUT_EN_RDMA1 BIT(16)
-#define UFOE_MOUT_EN_DSI0 0x1
-#define COLOR0_SEL_IN_OVL0 0x1
-#define OVL1_MOUT_EN_COLOR1 0x1
-#define GAMMA_MOUT_EN_RDMA1 0x1
-#define RDMA0_SOUT_DPI0 0x2
-#define RDMA0_SOUT_DPI1 0x3
-#define RDMA0_SOUT_DSI1 0x1
-#define RDMA0_SOUT_DSI2 0x4
-#define RDMA0_SOUT_DSI3 0x5
-#define RDMA1_SOUT_DPI0 0x2
-#define RDMA1_SOUT_DPI1 0x3
-#define RDMA1_SOUT_DSI1 0x1
-#define RDMA1_SOUT_DSI2 0x4
-#define RDMA1_SOUT_DSI3 0x5
-#define RDMA2_SOUT_DPI0 0x2
-#define RDMA2_SOUT_DPI1 0x3
-#define RDMA2_SOUT_DSI1 0x1
-#define RDMA2_SOUT_DSI2 0x4
-#define RDMA2_SOUT_DSI3 0x5
-#define DPI0_SEL_IN_RDMA1 0x1
-#define DPI0_SEL_IN_RDMA2 0x3
-#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
-#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
-#define DSI0_SEL_IN_RDMA1 0x1
-#define DSI0_SEL_IN_RDMA2 0x4
-#define DSI1_SEL_IN_RDMA1 0x1
-#define DSI1_SEL_IN_RDMA2 0x4
-#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
-#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
-#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
-#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
-#define COLOR1_SEL_IN_OVL1 0x1
-
-#define OVL_MOUT_EN_RDMA 0x1
-#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
-#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
-#define DSI_SEL_IN_BLS 0x0
-#define DPI_SEL_IN_BLS 0x0
-#define DSI_SEL_IN_RDMA 0x1
-
struct mtk_mmsys_driver_data {
const char *clk_driver;
+ const struct mtk_mmsys_conn_funcs *funcs;
};
struct mtk_mmsys {
@@ -84,213 +22,51 @@ struct mtk_mmsys {
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.clk_driver = "clk-mt2701-mm",
+ .funcs = &mt2701_mmsys_funcs,
};
static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
.clk_driver = "clk-mt2712-mm",
+ .funcs = &mt2701_mmsys_funcs,
};
static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
.clk_driver = "clk-mt6779-mm",
+ .funcs = &mt2701_mmsys_funcs,
};
static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
.clk_driver = "clk-mt6797-mm",
+ .funcs = &mt2701_mmsys_funcs,
};
static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.clk_driver = "clk-mt8173-mm",
+ .funcs = &mt2701_mmsys_funcs,
};
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.clk_driver = "clk-mt8183-mm",
};
-static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
- enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next,
- bool enable)
-{
- unsigned int addr, value, reg;
-
- if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
- addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
- value = OVL0_MOUT_EN_COLOR0;
- } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
- addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
- value = OVL_MOUT_EN_RDMA;
- } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
- addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
- value = OD_MOUT_EN_RDMA0;
- } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
- addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
- value = UFOE_MOUT_EN_DSI0;
- } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
- addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
- value = OVL1_MOUT_EN_COLOR1;
- } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
- addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
- value = GAMMA_MOUT_EN_RDMA1;
- } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
- addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
- value = OD1_MOUT_EN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
- addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DPI0;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
- addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DPI1;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
- addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DSI1;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
- addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DSI2;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
- addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DSI3;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
- addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DSI1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
- addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DSI2;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
- addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DSI3;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
- addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DPI0;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
- addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DPI1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
- addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DPI0;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
- addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DPI1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
- addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DSI1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
- addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DSI2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
- addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DSI3;
- } else {
- value = 0;
- }
-
- if (value) {
- reg = readl_relaxed(config_regs + addr);
-
- if (enable)
- reg |= value;
- else
- reg &= ~value;
-
- writel_relaxed(reg, config_regs + addr);
- }
-}
-
-static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
- enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next,
- bool enable)
-{
- unsigned int addr, value, reg;
-
- if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
- addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
- value = COLOR0_SEL_IN_OVL0;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
- addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI0_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
- addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI1_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
- addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI0_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
- addr = DISP_REG_CONFIG_DSIO_SEL_IN;
- value = DSI1_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
- addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI2_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
- addr = DISP_REG_CONFIG_DSIO_SEL_IN;
- value = DSI3_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
- addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI0_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
- addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI1_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
- addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI0_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
- addr = DISP_REG_CONFIG_DSIO_SEL_IN;
- value = DSI1_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
- addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI2_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
- addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI3_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
- addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
- value = COLOR1_SEL_IN_OVL1;
- } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
- addr = DISP_REG_CONFIG_DSI_SEL;
- value = DSI_SEL_IN_BLS;
- } else {
- value = 0;
- }
-
- if (value) {
- reg = readl_relaxed(config_regs + addr);
-
- if (enable)
- reg |= value;
- else
- reg &= ~value;
-
- writel_relaxed(reg, config_regs + addr);
- }
-}
-
-static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
- enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next)
-{
- if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
- writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
- config_regs + DISP_REG_CONFIG_OUT_SEL);
- } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
- writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
- config_regs + DISP_REG_CONFIG_OUT_SEL);
- writel_relaxed(DSI_SEL_IN_RDMA,
- config_regs + DISP_REG_CONFIG_DSI_SEL);
- writel_relaxed(DPI_SEL_IN_BLS,
- config_regs + DISP_REG_CONFIG_DPI_SEL);
- }
-}
-
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next)
{
struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const struct mtk_mmsys_conn_funcs *funcs = mmsys->data->funcs;
+
+ if (!funcs)
+ return;
- mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, true);
+ if (funcs->mout_en)
+ funcs->mout_en(mmsys->regs, cur, next, true);
- mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next);
+ if (funcs->sout_sel)
+ funcs->sout_sel(mmsys->regs, cur, next);
- mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, true);
+ if (funcs->sel_in)
+ funcs->sel_in(mmsys->regs, cur, next, true);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
@@ -299,10 +75,16 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id next)
{
struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const struct mtk_mmsys_conn_funcs *funcs = mmsys->data->funcs;
+
+ if (!funcs)
+ return;
- mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, false);
+ if (funcs->mout_en)
+ funcs->mout_en(mmsys->regs, cur, next, false);
- mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, false);
+ if (funcs->sel_in)
+ funcs->sel_in(mmsys->regs, cur, next, false);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 2228bf6..89000a9 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -42,6 +42,22 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_ID_MAX,
};
+struct mtk_mmsys_conn_funcs {
+ void (*mout_en)(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable);
+ void (*sel_in)(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable);
+ void (*sout_sel)(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next);
+};
+
+extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs;
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
--
1.8.1.1.dirty
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^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 04/10] soc: mediatek: mmsys: Use function call for setting the routing registers
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, linux-arm-kernel
Actually, setting the registers for routing, use multiple 'if-else' for different
routes, but this code would be more and more complicated while we
support more and more SoCs. Change that and use a function call per SoC so the
code will be more portable and clear.
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/soc/mediatek/mmsys/Makefile | 1 +
drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 254 ++++++++++++++++++++++++++++
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 266 +++---------------------------
include/linux/soc/mediatek/mtk-mmsys.h | 16 ++
4 files changed, 295 insertions(+), 242 deletions(-)
create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c
diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
index f44eadc..ac03025 100644
--- a/drivers/soc/mediatek/mmsys/Makefile
+++ b/drivers/soc/mediatek/mmsys/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o
obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c
new file mode 100644
index 0000000..6bcc5f2
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c
@@ -0,0 +1,254 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: James Liao <jamesjj.liao@mediatek.com>
+ */
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+
+#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
+#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
+#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
+#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
+#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
+#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
+#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
+#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
+#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
+#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
+#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
+#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
+#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
+#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
+
+#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
+#define DISP_REG_CONFIG_OUT_SEL 0x04c
+#define DISP_REG_CONFIG_DSI_SEL 0x050
+#define DISP_REG_CONFIG_DPI_SEL 0x064
+
+#define OVL0_MOUT_EN_COLOR0 0x1
+#define OD_MOUT_EN_RDMA0 0x1
+#define OD1_MOUT_EN_RDMA1 BIT(16)
+#define UFOE_MOUT_EN_DSI0 0x1
+#define COLOR0_SEL_IN_OVL0 0x1
+#define OVL1_MOUT_EN_COLOR1 0x1
+#define GAMMA_MOUT_EN_RDMA1 0x1
+#define RDMA0_SOUT_DPI0 0x2
+#define RDMA0_SOUT_DPI1 0x3
+#define RDMA0_SOUT_DSI1 0x1
+#define RDMA0_SOUT_DSI2 0x4
+#define RDMA0_SOUT_DSI3 0x5
+#define RDMA1_SOUT_DPI0 0x2
+#define RDMA1_SOUT_DPI1 0x3
+#define RDMA1_SOUT_DSI1 0x1
+#define RDMA1_SOUT_DSI2 0x4
+#define RDMA1_SOUT_DSI3 0x5
+#define RDMA2_SOUT_DPI0 0x2
+#define RDMA2_SOUT_DPI1 0x3
+#define RDMA2_SOUT_DSI1 0x1
+#define RDMA2_SOUT_DSI2 0x4
+#define RDMA2_SOUT_DSI3 0x5
+#define DPI0_SEL_IN_RDMA1 0x1
+#define DPI0_SEL_IN_RDMA2 0x3
+#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
+#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
+#define DSI0_SEL_IN_RDMA1 0x1
+#define DSI0_SEL_IN_RDMA2 0x4
+#define DSI1_SEL_IN_RDMA1 0x1
+#define DSI1_SEL_IN_RDMA2 0x4
+#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
+#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
+#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
+#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
+#define COLOR1_SEL_IN_OVL1 0x1
+
+#define OVL_MOUT_EN_RDMA 0x1
+#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
+#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
+#define DSI_SEL_IN_BLS 0x0
+#define DPI_SEL_IN_BLS 0x0
+#define DSI_SEL_IN_RDMA 0x1
+
+static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
+{
+ unsigned int addr, value, reg;
+
+ if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
+ addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
+ value = OVL0_MOUT_EN_COLOR0;
+ } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
+ addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
+ value = OVL_MOUT_EN_RDMA;
+ } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
+ addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+ value = OD_MOUT_EN_RDMA0;
+ } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
+ addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
+ value = UFOE_MOUT_EN_DSI0;
+ } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
+ addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
+ value = OVL1_MOUT_EN_COLOR1;
+ } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
+ addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
+ value = GAMMA_MOUT_EN_RDMA1;
+ } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
+ addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+ value = OD1_MOUT_EN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DPI0;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DPI1;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DSI1;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DSI2;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
+ addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DSI3;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DSI1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DSI2;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DSI3;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DPI0;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
+ addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DPI1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DPI0;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DPI1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DSI1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DSI2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
+ addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DSI3;
+ } else {
+ value = 0;
+ }
+
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+
+static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
+{
+ unsigned int addr, value, reg;
+
+ if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
+ addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
+ value = COLOR0_SEL_IN_OVL0;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
+ addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ value = DPI0_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
+ addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ value = DPI1_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI0_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
+ addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ value = DSI1_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI2_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
+ addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ value = DSI3_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
+ addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ value = DPI0_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
+ addr = DISP_REG_CONFIG_DPI_SEL_IN;
+ value = DPI1_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI0_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
+ addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+ value = DSI1_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI2_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
+ addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI3_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
+ addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
+ value = COLOR1_SEL_IN_OVL1;
+ } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
+ addr = DISP_REG_CONFIG_DSI_SEL;
+ value = DSI_SEL_IN_BLS;
+ } else {
+ value = 0;
+ }
+
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+
+static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next)
+{
+ if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
+ writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
+ config_regs + DISP_REG_CONFIG_OUT_SEL);
+ } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
+ writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
+ config_regs + DISP_REG_CONFIG_OUT_SEL);
+ writel_relaxed(DSI_SEL_IN_RDMA,
+ config_regs + DISP_REG_CONFIG_DSI_SEL);
+ writel_relaxed(DPI_SEL_IN_BLS,
+ config_regs + DISP_REG_CONFIG_DPI_SEL);
+ }
+}
+
+struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs = {
+ .mout_en = mtk_mmsys_ddp_mout_en,
+ .sel_in = mtk_mmsys_ddp_sel_in,
+ .sout_sel = mtk_mmsys_ddp_sout_sel,
+};
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
index 64c8030..4ca72f8 100644
--- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -10,71 +10,9 @@
#include <linux/platform_device.h>
#include <linux/soc/mediatek/mtk-mmsys.h>
-#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
-#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
-#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
-#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
-#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
-#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
-#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
-#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
-#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
-#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
-#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
-#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
-#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
-#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
-
-#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
-#define DISP_REG_CONFIG_OUT_SEL 0x04c
-#define DISP_REG_CONFIG_DSI_SEL 0x050
-#define DISP_REG_CONFIG_DPI_SEL 0x064
-
-#define OVL0_MOUT_EN_COLOR0 0x1
-#define OD_MOUT_EN_RDMA0 0x1
-#define OD1_MOUT_EN_RDMA1 BIT(16)
-#define UFOE_MOUT_EN_DSI0 0x1
-#define COLOR0_SEL_IN_OVL0 0x1
-#define OVL1_MOUT_EN_COLOR1 0x1
-#define GAMMA_MOUT_EN_RDMA1 0x1
-#define RDMA0_SOUT_DPI0 0x2
-#define RDMA0_SOUT_DPI1 0x3
-#define RDMA0_SOUT_DSI1 0x1
-#define RDMA0_SOUT_DSI2 0x4
-#define RDMA0_SOUT_DSI3 0x5
-#define RDMA1_SOUT_DPI0 0x2
-#define RDMA1_SOUT_DPI1 0x3
-#define RDMA1_SOUT_DSI1 0x1
-#define RDMA1_SOUT_DSI2 0x4
-#define RDMA1_SOUT_DSI3 0x5
-#define RDMA2_SOUT_DPI0 0x2
-#define RDMA2_SOUT_DPI1 0x3
-#define RDMA2_SOUT_DSI1 0x1
-#define RDMA2_SOUT_DSI2 0x4
-#define RDMA2_SOUT_DSI3 0x5
-#define DPI0_SEL_IN_RDMA1 0x1
-#define DPI0_SEL_IN_RDMA2 0x3
-#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
-#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
-#define DSI0_SEL_IN_RDMA1 0x1
-#define DSI0_SEL_IN_RDMA2 0x4
-#define DSI1_SEL_IN_RDMA1 0x1
-#define DSI1_SEL_IN_RDMA2 0x4
-#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
-#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
-#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
-#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
-#define COLOR1_SEL_IN_OVL1 0x1
-
-#define OVL_MOUT_EN_RDMA 0x1
-#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
-#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
-#define DSI_SEL_IN_BLS 0x0
-#define DPI_SEL_IN_BLS 0x0
-#define DSI_SEL_IN_RDMA 0x1
-
struct mtk_mmsys_driver_data {
const char *clk_driver;
+ const struct mtk_mmsys_conn_funcs *funcs;
};
struct mtk_mmsys {
@@ -84,213 +22,51 @@ struct mtk_mmsys {
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.clk_driver = "clk-mt2701-mm",
+ .funcs = &mt2701_mmsys_funcs,
};
static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
.clk_driver = "clk-mt2712-mm",
+ .funcs = &mt2701_mmsys_funcs,
};
static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
.clk_driver = "clk-mt6779-mm",
+ .funcs = &mt2701_mmsys_funcs,
};
static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
.clk_driver = "clk-mt6797-mm",
+ .funcs = &mt2701_mmsys_funcs,
};
static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.clk_driver = "clk-mt8173-mm",
+ .funcs = &mt2701_mmsys_funcs,
};
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.clk_driver = "clk-mt8183-mm",
};
-static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
- enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next,
- bool enable)
-{
- unsigned int addr, value, reg;
-
- if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
- addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
- value = OVL0_MOUT_EN_COLOR0;
- } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
- addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
- value = OVL_MOUT_EN_RDMA;
- } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
- addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
- value = OD_MOUT_EN_RDMA0;
- } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
- addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
- value = UFOE_MOUT_EN_DSI0;
- } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
- addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
- value = OVL1_MOUT_EN_COLOR1;
- } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
- addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
- value = GAMMA_MOUT_EN_RDMA1;
- } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
- addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
- value = OD1_MOUT_EN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
- addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DPI0;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
- addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DPI1;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
- addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DSI1;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
- addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DSI2;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
- addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DSI3;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
- addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DSI1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
- addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DSI2;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
- addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DSI3;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
- addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DPI0;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
- addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DPI1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
- addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DPI0;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
- addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DPI1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
- addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DSI1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
- addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DSI2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
- addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DSI3;
- } else {
- value = 0;
- }
-
- if (value) {
- reg = readl_relaxed(config_regs + addr);
-
- if (enable)
- reg |= value;
- else
- reg &= ~value;
-
- writel_relaxed(reg, config_regs + addr);
- }
-}
-
-static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
- enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next,
- bool enable)
-{
- unsigned int addr, value, reg;
-
- if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
- addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
- value = COLOR0_SEL_IN_OVL0;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
- addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI0_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
- addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI1_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
- addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI0_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
- addr = DISP_REG_CONFIG_DSIO_SEL_IN;
- value = DSI1_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
- addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI2_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
- addr = DISP_REG_CONFIG_DSIO_SEL_IN;
- value = DSI3_SEL_IN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
- addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI0_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
- addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI1_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
- addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI0_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
- addr = DISP_REG_CONFIG_DSIO_SEL_IN;
- value = DSI1_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
- addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI2_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
- addr = DISP_REG_CONFIG_DSIE_SEL_IN;
- value = DSI3_SEL_IN_RDMA2;
- } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
- addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
- value = COLOR1_SEL_IN_OVL1;
- } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
- addr = DISP_REG_CONFIG_DSI_SEL;
- value = DSI_SEL_IN_BLS;
- } else {
- value = 0;
- }
-
- if (value) {
- reg = readl_relaxed(config_regs + addr);
-
- if (enable)
- reg |= value;
- else
- reg &= ~value;
-
- writel_relaxed(reg, config_regs + addr);
- }
-}
-
-static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
- enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next)
-{
- if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
- writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
- config_regs + DISP_REG_CONFIG_OUT_SEL);
- } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
- writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
- config_regs + DISP_REG_CONFIG_OUT_SEL);
- writel_relaxed(DSI_SEL_IN_RDMA,
- config_regs + DISP_REG_CONFIG_DSI_SEL);
- writel_relaxed(DPI_SEL_IN_BLS,
- config_regs + DISP_REG_CONFIG_DPI_SEL);
- }
-}
-
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next)
{
struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const struct mtk_mmsys_conn_funcs *funcs = mmsys->data->funcs;
+
+ if (!funcs)
+ return;
- mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, true);
+ if (funcs->mout_en)
+ funcs->mout_en(mmsys->regs, cur, next, true);
- mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next);
+ if (funcs->sout_sel)
+ funcs->sout_sel(mmsys->regs, cur, next);
- mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, true);
+ if (funcs->sel_in)
+ funcs->sel_in(mmsys->regs, cur, next, true);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
@@ -299,10 +75,16 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id next)
{
struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const struct mtk_mmsys_conn_funcs *funcs = mmsys->data->funcs;
+
+ if (!funcs)
+ return;
- mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, false);
+ if (funcs->mout_en)
+ funcs->mout_en(mmsys->regs, cur, next, false);
- mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, false);
+ if (funcs->sel_in)
+ funcs->sel_in(mmsys->regs, cur, next, false);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 2228bf6..89000a9 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -42,6 +42,22 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_ID_MAX,
};
+struct mtk_mmsys_conn_funcs {
+ void (*mout_en)(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable);
+ void (*sel_in)(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable);
+ void (*sout_sel)(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next);
+};
+
+extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs;
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
--
1.8.1.1.dirty
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 05/10] soc: mediatek: mmsys: add mt8183 function call for setting the routing registers
2021-01-05 3:06 ` Yongqiang Niu
(?)
(?)
@ 2021-01-05 3:06 ` Yongqiang Niu
-1 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Yongqiang Niu
add mt8183 function call for setting the routing registers
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/soc/mediatek/mmsys/Makefile | 1 +
drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 110 ++++++++++++++++++++++++++++++
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 1 +
include/linux/soc/mediatek/mtk-mmsys.h | 1 +
4 files changed, 113 insertions(+)
create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c
diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
index ac03025..25eeb9e5 100644
--- a/drivers/soc/mediatek/mmsys/Makefile
+++ b/drivers/soc/mediatek/mmsys/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o
+obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o
obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
diff --git a/drivers/soc/mediatek/mmsys/mt8183-mmsys.c b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c
new file mode 100644
index 0000000..8311f89
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2020 MediaTek Inc.
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+
+#define DISP_OVL0_MOUT_EN 0xf00
+#define DISP_OVL0_2L_MOUT_EN 0xf04
+#define DISP_OVL1_2L_MOUT_EN 0xf08
+#define DISP_DITHER0_MOUT_EN 0xf0c
+#define DISP_PATH0_SEL_IN 0xf24
+#define DISP_DSI0_SEL_IN 0xf2c
+#define DISP_DPI0_SEL_IN 0xf30
+#define DISP_RDMA0_SOUT_SEL_IN 0xf50
+#define DISP_RDMA1_SOUT_SEL_IN 0xf54
+
+#define OVL0_MOUT_EN_OVL0_2L BIT(4)
+#define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
+#define OVL1_2L_MOUT_EN_RDMA1 BIT(4)
+#define DITHER0_MOUT_IN_DSI0 BIT(0)
+#define DISP_PATH0_SEL_IN_OVL0_2L 0x1
+#define DSI0_SEL_IN_RDMA0 0x1
+#define DSI0_SEL_IN_RDMA1 0x3
+#define DPI0_SEL_IN_RDMA0 0x1
+#define DPI0_SEL_IN_RDMA1 0x2
+#define RDMA0_SOUT_COLOR0 0x1
+#define RDMA1_SOUT_DSI0 0x1
+
+static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
+{
+ unsigned int addr, value, reg;
+
+ if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0) {
+ addr = DISP_OVL0_MOUT_EN;
+ value = OVL0_MOUT_EN_OVL0_2L;
+ } else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
+ addr = DISP_OVL0_2L_MOUT_EN;
+ value = OVL0_2L_MOUT_EN_DISP_PATH0;
+ } else if (cur == DDP_COMPONENT_OVL_2L1 && next == DDP_COMPONENT_RDMA1) {
+ addr = DISP_OVL1_2L_MOUT_EN;
+ value = OVL1_2L_MOUT_EN_RDMA1;
+ } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
+ addr = DISP_DITHER0_MOUT_EN;
+ value = DITHER0_MOUT_IN_DSI0;
+ } else {
+ value = 0;
+ }
+
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+
+static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
+{
+ unsigned int addr, value, reg;
+
+ if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
+ addr = DISP_PATH0_SEL_IN;
+ value = DISP_PATH0_SEL_IN_OVL0_2L;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
+ addr = DISP_DPI0_SEL_IN;
+ value = DPI0_SEL_IN_RDMA1;
+ } else {
+ value = 0;
+ }
+
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+
+static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next)
+{
+ if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) {
+ writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + DISP_RDMA0_SOUT_SEL_IN);
+ }
+}
+
+struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs = {
+ .mout_en = mtk_mmsys_ddp_mout_en,
+ .sel_in = mtk_mmsys_ddp_sel_in,
+ .sout_sel = mtk_mmsys_ddp_sout_sel,
+};
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
index 4ca72f8..075d356 100644
--- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -47,6 +47,7 @@ struct mtk_mmsys {
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.clk_driver = "clk-mt8183-mm",
+ .funcs = &mt8183_mmsys_funcs,
};
void mtk_mmsys_ddp_connect(struct device *dev,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 89000a9..7e2c0fe 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -57,6 +57,7 @@ struct mtk_mmsys_conn_funcs {
};
extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs;
+extern struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs;
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 05/10] soc: mediatek: mmsys: add mt8183 function call for setting the routing registers
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, Daniel Vetter, linux-arm-kernel
add mt8183 function call for setting the routing registers
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/soc/mediatek/mmsys/Makefile | 1 +
drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 110 ++++++++++++++++++++++++++++++
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 1 +
include/linux/soc/mediatek/mtk-mmsys.h | 1 +
4 files changed, 113 insertions(+)
create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c
diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
index ac03025..25eeb9e5 100644
--- a/drivers/soc/mediatek/mmsys/Makefile
+++ b/drivers/soc/mediatek/mmsys/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o
+obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o
obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
diff --git a/drivers/soc/mediatek/mmsys/mt8183-mmsys.c b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c
new file mode 100644
index 0000000..8311f89
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2020 MediaTek Inc.
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+
+#define DISP_OVL0_MOUT_EN 0xf00
+#define DISP_OVL0_2L_MOUT_EN 0xf04
+#define DISP_OVL1_2L_MOUT_EN 0xf08
+#define DISP_DITHER0_MOUT_EN 0xf0c
+#define DISP_PATH0_SEL_IN 0xf24
+#define DISP_DSI0_SEL_IN 0xf2c
+#define DISP_DPI0_SEL_IN 0xf30
+#define DISP_RDMA0_SOUT_SEL_IN 0xf50
+#define DISP_RDMA1_SOUT_SEL_IN 0xf54
+
+#define OVL0_MOUT_EN_OVL0_2L BIT(4)
+#define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
+#define OVL1_2L_MOUT_EN_RDMA1 BIT(4)
+#define DITHER0_MOUT_IN_DSI0 BIT(0)
+#define DISP_PATH0_SEL_IN_OVL0_2L 0x1
+#define DSI0_SEL_IN_RDMA0 0x1
+#define DSI0_SEL_IN_RDMA1 0x3
+#define DPI0_SEL_IN_RDMA0 0x1
+#define DPI0_SEL_IN_RDMA1 0x2
+#define RDMA0_SOUT_COLOR0 0x1
+#define RDMA1_SOUT_DSI0 0x1
+
+static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
+{
+ unsigned int addr, value, reg;
+
+ if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0) {
+ addr = DISP_OVL0_MOUT_EN;
+ value = OVL0_MOUT_EN_OVL0_2L;
+ } else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
+ addr = DISP_OVL0_2L_MOUT_EN;
+ value = OVL0_2L_MOUT_EN_DISP_PATH0;
+ } else if (cur == DDP_COMPONENT_OVL_2L1 && next == DDP_COMPONENT_RDMA1) {
+ addr = DISP_OVL1_2L_MOUT_EN;
+ value = OVL1_2L_MOUT_EN_RDMA1;
+ } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
+ addr = DISP_DITHER0_MOUT_EN;
+ value = DITHER0_MOUT_IN_DSI0;
+ } else {
+ value = 0;
+ }
+
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+
+static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
+{
+ unsigned int addr, value, reg;
+
+ if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
+ addr = DISP_PATH0_SEL_IN;
+ value = DISP_PATH0_SEL_IN_OVL0_2L;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
+ addr = DISP_DPI0_SEL_IN;
+ value = DPI0_SEL_IN_RDMA1;
+ } else {
+ value = 0;
+ }
+
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+
+static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next)
+{
+ if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) {
+ writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + DISP_RDMA0_SOUT_SEL_IN);
+ }
+}
+
+struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs = {
+ .mout_en = mtk_mmsys_ddp_mout_en,
+ .sel_in = mtk_mmsys_ddp_sel_in,
+ .sout_sel = mtk_mmsys_ddp_sout_sel,
+};
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
index 4ca72f8..075d356 100644
--- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -47,6 +47,7 @@ struct mtk_mmsys {
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.clk_driver = "clk-mt8183-mm",
+ .funcs = &mt8183_mmsys_funcs,
};
void mtk_mmsys_ddp_connect(struct device *dev,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 89000a9..7e2c0fe 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -57,6 +57,7 @@ struct mtk_mmsys_conn_funcs {
};
extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs;
+extern struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs;
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
--
1.8.1.1.dirty
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 05/10] soc: mediatek: mmsys: add mt8183 function call for setting the routing registers
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, Daniel Vetter, linux-arm-kernel
add mt8183 function call for setting the routing registers
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/soc/mediatek/mmsys/Makefile | 1 +
drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 110 ++++++++++++++++++++++++++++++
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 1 +
include/linux/soc/mediatek/mtk-mmsys.h | 1 +
4 files changed, 113 insertions(+)
create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c
diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
index ac03025..25eeb9e5 100644
--- a/drivers/soc/mediatek/mmsys/Makefile
+++ b/drivers/soc/mediatek/mmsys/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o
+obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o
obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
diff --git a/drivers/soc/mediatek/mmsys/mt8183-mmsys.c b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c
new file mode 100644
index 0000000..8311f89
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2020 MediaTek Inc.
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+
+#define DISP_OVL0_MOUT_EN 0xf00
+#define DISP_OVL0_2L_MOUT_EN 0xf04
+#define DISP_OVL1_2L_MOUT_EN 0xf08
+#define DISP_DITHER0_MOUT_EN 0xf0c
+#define DISP_PATH0_SEL_IN 0xf24
+#define DISP_DSI0_SEL_IN 0xf2c
+#define DISP_DPI0_SEL_IN 0xf30
+#define DISP_RDMA0_SOUT_SEL_IN 0xf50
+#define DISP_RDMA1_SOUT_SEL_IN 0xf54
+
+#define OVL0_MOUT_EN_OVL0_2L BIT(4)
+#define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
+#define OVL1_2L_MOUT_EN_RDMA1 BIT(4)
+#define DITHER0_MOUT_IN_DSI0 BIT(0)
+#define DISP_PATH0_SEL_IN_OVL0_2L 0x1
+#define DSI0_SEL_IN_RDMA0 0x1
+#define DSI0_SEL_IN_RDMA1 0x3
+#define DPI0_SEL_IN_RDMA0 0x1
+#define DPI0_SEL_IN_RDMA1 0x2
+#define RDMA0_SOUT_COLOR0 0x1
+#define RDMA1_SOUT_DSI0 0x1
+
+static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
+{
+ unsigned int addr, value, reg;
+
+ if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0) {
+ addr = DISP_OVL0_MOUT_EN;
+ value = OVL0_MOUT_EN_OVL0_2L;
+ } else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
+ addr = DISP_OVL0_2L_MOUT_EN;
+ value = OVL0_2L_MOUT_EN_DISP_PATH0;
+ } else if (cur == DDP_COMPONENT_OVL_2L1 && next == DDP_COMPONENT_RDMA1) {
+ addr = DISP_OVL1_2L_MOUT_EN;
+ value = OVL1_2L_MOUT_EN_RDMA1;
+ } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
+ addr = DISP_DITHER0_MOUT_EN;
+ value = DITHER0_MOUT_IN_DSI0;
+ } else {
+ value = 0;
+ }
+
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+
+static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
+{
+ unsigned int addr, value, reg;
+
+ if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
+ addr = DISP_PATH0_SEL_IN;
+ value = DISP_PATH0_SEL_IN_OVL0_2L;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
+ addr = DISP_DPI0_SEL_IN;
+ value = DPI0_SEL_IN_RDMA1;
+ } else {
+ value = 0;
+ }
+
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+
+static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next)
+{
+ if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) {
+ writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + DISP_RDMA0_SOUT_SEL_IN);
+ }
+}
+
+struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs = {
+ .mout_en = mtk_mmsys_ddp_mout_en,
+ .sel_in = mtk_mmsys_ddp_sel_in,
+ .sout_sel = mtk_mmsys_ddp_sout_sel,
+};
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
index 4ca72f8..075d356 100644
--- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -47,6 +47,7 @@ struct mtk_mmsys {
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.clk_driver = "clk-mt8183-mm",
+ .funcs = &mt8183_mmsys_funcs,
};
void mtk_mmsys_ddp_connect(struct device *dev,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 89000a9..7e2c0fe 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -57,6 +57,7 @@ struct mtk_mmsys_conn_funcs {
};
extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs;
+extern struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs;
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
--
1.8.1.1.dirty
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 05/10] soc: mediatek: mmsys: add mt8183 function call for setting the routing registers
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, linux-arm-kernel
add mt8183 function call for setting the routing registers
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/soc/mediatek/mmsys/Makefile | 1 +
drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 110 ++++++++++++++++++++++++++++++
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 1 +
include/linux/soc/mediatek/mtk-mmsys.h | 1 +
4 files changed, 113 insertions(+)
create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c
diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
index ac03025..25eeb9e5 100644
--- a/drivers/soc/mediatek/mmsys/Makefile
+++ b/drivers/soc/mediatek/mmsys/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o
+obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o
obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
diff --git a/drivers/soc/mediatek/mmsys/mt8183-mmsys.c b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c
new file mode 100644
index 0000000..8311f89
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2020 MediaTek Inc.
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+
+#define DISP_OVL0_MOUT_EN 0xf00
+#define DISP_OVL0_2L_MOUT_EN 0xf04
+#define DISP_OVL1_2L_MOUT_EN 0xf08
+#define DISP_DITHER0_MOUT_EN 0xf0c
+#define DISP_PATH0_SEL_IN 0xf24
+#define DISP_DSI0_SEL_IN 0xf2c
+#define DISP_DPI0_SEL_IN 0xf30
+#define DISP_RDMA0_SOUT_SEL_IN 0xf50
+#define DISP_RDMA1_SOUT_SEL_IN 0xf54
+
+#define OVL0_MOUT_EN_OVL0_2L BIT(4)
+#define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
+#define OVL1_2L_MOUT_EN_RDMA1 BIT(4)
+#define DITHER0_MOUT_IN_DSI0 BIT(0)
+#define DISP_PATH0_SEL_IN_OVL0_2L 0x1
+#define DSI0_SEL_IN_RDMA0 0x1
+#define DSI0_SEL_IN_RDMA1 0x3
+#define DPI0_SEL_IN_RDMA0 0x1
+#define DPI0_SEL_IN_RDMA1 0x2
+#define RDMA0_SOUT_COLOR0 0x1
+#define RDMA1_SOUT_DSI0 0x1
+
+static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
+{
+ unsigned int addr, value, reg;
+
+ if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0) {
+ addr = DISP_OVL0_MOUT_EN;
+ value = OVL0_MOUT_EN_OVL0_2L;
+ } else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
+ addr = DISP_OVL0_2L_MOUT_EN;
+ value = OVL0_2L_MOUT_EN_DISP_PATH0;
+ } else if (cur == DDP_COMPONENT_OVL_2L1 && next == DDP_COMPONENT_RDMA1) {
+ addr = DISP_OVL1_2L_MOUT_EN;
+ value = OVL1_2L_MOUT_EN_RDMA1;
+ } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
+ addr = DISP_DITHER0_MOUT_EN;
+ value = DITHER0_MOUT_IN_DSI0;
+ } else {
+ value = 0;
+ }
+
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+
+static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
+{
+ unsigned int addr, value, reg;
+
+ if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
+ addr = DISP_PATH0_SEL_IN;
+ value = DISP_PATH0_SEL_IN_OVL0_2L;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
+ addr = DISP_DPI0_SEL_IN;
+ value = DPI0_SEL_IN_RDMA1;
+ } else {
+ value = 0;
+ }
+
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+
+static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next)
+{
+ if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) {
+ writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + DISP_RDMA0_SOUT_SEL_IN);
+ }
+}
+
+struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs = {
+ .mout_en = mtk_mmsys_ddp_mout_en,
+ .sel_in = mtk_mmsys_ddp_sel_in,
+ .sout_sel = mtk_mmsys_ddp_sout_sel,
+};
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
index 4ca72f8..075d356 100644
--- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -47,6 +47,7 @@ struct mtk_mmsys {
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.clk_driver = "clk-mt8183-mm",
+ .funcs = &mt8183_mmsys_funcs,
};
void mtk_mmsys_ddp_connect(struct device *dev,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 89000a9..7e2c0fe 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -57,6 +57,7 @@ struct mtk_mmsys_conn_funcs {
};
extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs;
+extern struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs;
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
--
1.8.1.1.dirty
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 06/10] soc: mediatek: mmsys: add component OVL_2L2
2021-01-05 3:06 ` Yongqiang Niu
(?)
(?)
@ 2021-01-05 3:06 ` Yongqiang Niu
-1 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Yongqiang Niu
This patch add component OVL_2L2
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
include/linux/soc/mediatek/mtk-mmsys.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 7e2c0fe..ed99122 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -29,6 +29,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_OVL0,
DDP_COMPONENT_OVL_2L0,
DDP_COMPONENT_OVL_2L1,
+ DDP_COMPONENT_OVL_2L2,
DDP_COMPONENT_OVL1,
DDP_COMPONENT_PWM0,
DDP_COMPONENT_PWM1,
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 06/10] soc: mediatek: mmsys: add component OVL_2L2
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, Daniel Vetter, linux-arm-kernel
This patch add component OVL_2L2
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
include/linux/soc/mediatek/mtk-mmsys.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 7e2c0fe..ed99122 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -29,6 +29,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_OVL0,
DDP_COMPONENT_OVL_2L0,
DDP_COMPONENT_OVL_2L1,
+ DDP_COMPONENT_OVL_2L2,
DDP_COMPONENT_OVL1,
DDP_COMPONENT_PWM0,
DDP_COMPONENT_PWM1,
--
1.8.1.1.dirty
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 06/10] soc: mediatek: mmsys: add component OVL_2L2
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, Daniel Vetter, linux-arm-kernel
This patch add component OVL_2L2
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
include/linux/soc/mediatek/mtk-mmsys.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 7e2c0fe..ed99122 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -29,6 +29,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_OVL0,
DDP_COMPONENT_OVL_2L0,
DDP_COMPONENT_OVL_2L1,
+ DDP_COMPONENT_OVL_2L2,
DDP_COMPONENT_OVL1,
DDP_COMPONENT_PWM0,
DDP_COMPONENT_PWM1,
--
1.8.1.1.dirty
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 06/10] soc: mediatek: mmsys: add component OVL_2L2
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, linux-arm-kernel
This patch add component OVL_2L2
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
include/linux/soc/mediatek/mtk-mmsys.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 7e2c0fe..ed99122 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -29,6 +29,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_OVL0,
DDP_COMPONENT_OVL_2L0,
DDP_COMPONENT_OVL_2L1,
+ DDP_COMPONENT_OVL_2L2,
DDP_COMPONENT_OVL1,
DDP_COMPONENT_PWM0,
DDP_COMPONENT_PWM1,
--
1.8.1.1.dirty
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 07/10] soc: mediatek: mmsys: add component POSTMASK
2021-01-05 3:06 ` Yongqiang Niu
(?)
(?)
@ 2021-01-05 3:06 ` Yongqiang Niu
-1 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Yongqiang Niu
This patch add component POSTMASK
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
include/linux/soc/mediatek/mtk-mmsys.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index ed99122..13546e9 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -31,6 +31,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_OVL_2L1,
DDP_COMPONENT_OVL_2L2,
DDP_COMPONENT_OVL1,
+ DDP_COMPONENT_POSTMASK0,
DDP_COMPONENT_PWM0,
DDP_COMPONENT_PWM1,
DDP_COMPONENT_PWM2,
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 07/10] soc: mediatek: mmsys: add component POSTMASK
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, Daniel Vetter, linux-arm-kernel
This patch add component POSTMASK
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
include/linux/soc/mediatek/mtk-mmsys.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index ed99122..13546e9 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -31,6 +31,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_OVL_2L1,
DDP_COMPONENT_OVL_2L2,
DDP_COMPONENT_OVL1,
+ DDP_COMPONENT_POSTMASK0,
DDP_COMPONENT_PWM0,
DDP_COMPONENT_PWM1,
DDP_COMPONENT_PWM2,
--
1.8.1.1.dirty
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 07/10] soc: mediatek: mmsys: add component POSTMASK
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, Daniel Vetter, linux-arm-kernel
This patch add component POSTMASK
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
include/linux/soc/mediatek/mtk-mmsys.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index ed99122..13546e9 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -31,6 +31,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_OVL_2L1,
DDP_COMPONENT_OVL_2L2,
DDP_COMPONENT_OVL1,
+ DDP_COMPONENT_POSTMASK0,
DDP_COMPONENT_PWM0,
DDP_COMPONENT_PWM1,
DDP_COMPONENT_PWM2,
--
1.8.1.1.dirty
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 07/10] soc: mediatek: mmsys: add component POSTMASK
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, linux-arm-kernel
This patch add component POSTMASK
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
include/linux/soc/mediatek/mtk-mmsys.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index ed99122..13546e9 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -31,6 +31,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_OVL_2L1,
DDP_COMPONENT_OVL_2L2,
DDP_COMPONENT_OVL1,
+ DDP_COMPONENT_POSTMASK0,
DDP_COMPONENT_PWM0,
DDP_COMPONENT_PWM1,
DDP_COMPONENT_PWM2,
--
1.8.1.1.dirty
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 08/10] soc: mediatek: mmsys: add component RDMA4
2021-01-05 3:06 ` Yongqiang Niu
(?)
(?)
@ 2021-01-05 3:06 ` Yongqiang Niu
-1 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Yongqiang Niu
This patch add component RDMA4
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
include/linux/soc/mediatek/mtk-mmsys.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 13546e9..2c11617 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -38,6 +38,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_RDMA0,
DDP_COMPONENT_RDMA1,
DDP_COMPONENT_RDMA2,
+ DDP_COMPONENT_RDMA4,
DDP_COMPONENT_UFOE,
DDP_COMPONENT_WDMA0,
DDP_COMPONENT_WDMA1,
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 08/10] soc: mediatek: mmsys: add component RDMA4
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, Daniel Vetter, linux-arm-kernel
This patch add component RDMA4
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
include/linux/soc/mediatek/mtk-mmsys.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 13546e9..2c11617 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -38,6 +38,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_RDMA0,
DDP_COMPONENT_RDMA1,
DDP_COMPONENT_RDMA2,
+ DDP_COMPONENT_RDMA4,
DDP_COMPONENT_UFOE,
DDP_COMPONENT_WDMA0,
DDP_COMPONENT_WDMA1,
--
1.8.1.1.dirty
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 08/10] soc: mediatek: mmsys: add component RDMA4
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, Daniel Vetter, linux-arm-kernel
This patch add component RDMA4
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
include/linux/soc/mediatek/mtk-mmsys.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 13546e9..2c11617 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -38,6 +38,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_RDMA0,
DDP_COMPONENT_RDMA1,
DDP_COMPONENT_RDMA2,
+ DDP_COMPONENT_RDMA4,
DDP_COMPONENT_UFOE,
DDP_COMPONENT_WDMA0,
DDP_COMPONENT_WDMA1,
--
1.8.1.1.dirty
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 08/10] soc: mediatek: mmsys: add component RDMA4
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, linux-arm-kernel
This patch add component RDMA4
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
include/linux/soc/mediatek/mtk-mmsys.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 13546e9..2c11617 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -38,6 +38,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_RDMA0,
DDP_COMPONENT_RDMA1,
DDP_COMPONENT_RDMA2,
+ DDP_COMPONENT_RDMA4,
DDP_COMPONENT_UFOE,
DDP_COMPONENT_WDMA0,
DDP_COMPONENT_WDMA1,
--
1.8.1.1.dirty
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 09/10] soc: mediatek: mmsys: Use function call for setting mmsys ovl mout register
2021-01-05 3:06 ` Yongqiang Niu
(?)
(?)
@ 2021-01-05 3:06 ` Yongqiang Niu
-1 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Yongqiang Niu
Use function call for setting mmsys ovl mout register
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 6 ++++++
include/linux/soc/mediatek/mtk-mmsys.h | 4 ++++
2 files changed, 10 insertions(+)
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
index 075d356..34728ed 100644
--- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -68,6 +68,9 @@ void mtk_mmsys_ddp_connect(struct device *dev,
if (funcs->sel_in)
funcs->sel_in(mmsys->regs, cur, next, true);
+
+ if (funcs->ovl_mout_en)
+ funcs->ovl_mout_en(mmsys->regs, cur, next, true);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
@@ -86,6 +89,9 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
if (funcs->sel_in)
funcs->sel_in(mmsys->regs, cur, next, false);
+
+ if (funcs->ovl_mout_en)
+ funcs->ovl_mout_en(mmsys->regs, cur, next, false);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 2c11617..19318d2 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -50,6 +50,10 @@ struct mtk_mmsys_conn_funcs {
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next,
bool enable);
+ void (*ovl_mout_en)(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable);
void (*sel_in)(void __iomem *config_regs,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next,
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 09/10] soc: mediatek: mmsys: Use function call for setting mmsys ovl mout register
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, Daniel Vetter, linux-arm-kernel
Use function call for setting mmsys ovl mout register
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 6 ++++++
include/linux/soc/mediatek/mtk-mmsys.h | 4 ++++
2 files changed, 10 insertions(+)
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
index 075d356..34728ed 100644
--- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -68,6 +68,9 @@ void mtk_mmsys_ddp_connect(struct device *dev,
if (funcs->sel_in)
funcs->sel_in(mmsys->regs, cur, next, true);
+
+ if (funcs->ovl_mout_en)
+ funcs->ovl_mout_en(mmsys->regs, cur, next, true);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
@@ -86,6 +89,9 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
if (funcs->sel_in)
funcs->sel_in(mmsys->regs, cur, next, false);
+
+ if (funcs->ovl_mout_en)
+ funcs->ovl_mout_en(mmsys->regs, cur, next, false);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 2c11617..19318d2 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -50,6 +50,10 @@ struct mtk_mmsys_conn_funcs {
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next,
bool enable);
+ void (*ovl_mout_en)(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable);
void (*sel_in)(void __iomem *config_regs,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next,
--
1.8.1.1.dirty
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 09/10] soc: mediatek: mmsys: Use function call for setting mmsys ovl mout register
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, Daniel Vetter, linux-arm-kernel
Use function call for setting mmsys ovl mout register
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 6 ++++++
include/linux/soc/mediatek/mtk-mmsys.h | 4 ++++
2 files changed, 10 insertions(+)
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
index 075d356..34728ed 100644
--- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -68,6 +68,9 @@ void mtk_mmsys_ddp_connect(struct device *dev,
if (funcs->sel_in)
funcs->sel_in(mmsys->regs, cur, next, true);
+
+ if (funcs->ovl_mout_en)
+ funcs->ovl_mout_en(mmsys->regs, cur, next, true);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
@@ -86,6 +89,9 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
if (funcs->sel_in)
funcs->sel_in(mmsys->regs, cur, next, false);
+
+ if (funcs->ovl_mout_en)
+ funcs->ovl_mout_en(mmsys->regs, cur, next, false);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 2c11617..19318d2 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -50,6 +50,10 @@ struct mtk_mmsys_conn_funcs {
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next,
bool enable);
+ void (*ovl_mout_en)(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable);
void (*sel_in)(void __iomem *config_regs,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next,
--
1.8.1.1.dirty
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 09/10] soc: mediatek: mmsys: Use function call for setting mmsys ovl mout register
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, linux-arm-kernel
Use function call for setting mmsys ovl mout register
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 6 ++++++
include/linux/soc/mediatek/mtk-mmsys.h | 4 ++++
2 files changed, 10 insertions(+)
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
index 075d356..34728ed 100644
--- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -68,6 +68,9 @@ void mtk_mmsys_ddp_connect(struct device *dev,
if (funcs->sel_in)
funcs->sel_in(mmsys->regs, cur, next, true);
+
+ if (funcs->ovl_mout_en)
+ funcs->ovl_mout_en(mmsys->regs, cur, next, true);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
@@ -86,6 +89,9 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
if (funcs->sel_in)
funcs->sel_in(mmsys->regs, cur, next, false);
+
+ if (funcs->ovl_mout_en)
+ funcs->ovl_mout_en(mmsys->regs, cur, next, false);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 2c11617..19318d2 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -50,6 +50,10 @@ struct mtk_mmsys_conn_funcs {
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next,
bool enable);
+ void (*ovl_mout_en)(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable);
void (*sel_in)(void __iomem *config_regs,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next,
--
1.8.1.1.dirty
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 10/10] soc: mediatek: mmsys: add mt8192 mmsys support
2021-01-05 3:06 ` Yongqiang Niu
(?)
(?)
@ 2021-01-05 3:06 ` Yongqiang Niu
-1 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Yongqiang Niu
add mt8192 mmsys support
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/soc/mediatek/mmsys/Makefile | 1 +
drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 149 ++++++++++++++++++++++++++++++
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 9 ++
include/linux/soc/mediatek/mtk-mmsys.h | 1 +
4 files changed, 160 insertions(+)
create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c
diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
index 25eeb9e5..7508cd3 100644
--- a/drivers/soc/mediatek/mmsys/Makefile
+++ b/drivers/soc/mediatek/mmsys/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o
obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o
+obj-$(CONFIG_MTK_MMSYS) += mt8192-mmsys.o
obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
diff --git a/drivers/soc/mediatek/mmsys/mt8192-mmsys.c b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
new file mode 100644
index 0000000..2e350d1
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2020 MediaTek Inc.
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+
+#define MMSYS_OVL_MOUT_EN 0xf04
+#define DISP_OVL0_GO_BLEND BIT(0)
+#define DISP_OVL0_GO_BG BIT(1)
+#define DISP_OVL0_2L_GO_BLEND BIT(2)
+#define DISP_OVL0_2L_GO_BG BIT(3)
+#define DISP_OVL1_2L_MOUT_EN 0xf08
+#define OVL1_2L_MOUT_EN_RDMA1 BIT(4)
+#define DISP_OVL0_2L_MOUT_EN 0xf18
+#define DISP_OVL0_MOUT_EN 0xf1c
+#define OVL0_MOUT_EN_DISP_RDMA0 BIT(0)
+#define OVL0_MOUT_EN_OVL0_2L BIT(4)
+#define DISP_RDMA0_SEL_IN 0xf2c
+#define RDMA0_SEL_IN_OVL0_2L 0x3
+#define DISP_RDMA0_SOUT_SEL 0xf30
+#define RDMA0_SOUT_COLOR0 0x1
+#define DISP_CCORR0_SOUT_SEL 0xf34
+#define CCORR0_SOUT_AAL0 0x1
+#define DISP_AAL0_SEL_IN 0xf38
+#define AAL0_SEL_IN_CCORR0 0x1
+#define DISP_DITHER0_MOUT_EN 0xf3c
+#define DITHER0_MOUT_DSI0 BIT(0)
+#define DISP_DSI0_SEL_IN 0xf40
+#define DSI0_SEL_IN_DITHER0 0x1
+#define DISP_OVL2_2L_MOUT_EN 0xf4c
+#define OVL2_2L_MOUT_RDMA4 BIT(0)
+
+static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
+{
+ unsigned int addr, value, reg;
+
+ if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
+ addr = DISP_OVL0_2L_MOUT_EN;
+ value = OVL0_MOUT_EN_DISP_RDMA0;
+ } else if (cur == DDP_COMPONENT_OVL_2L2 && next == DDP_COMPONENT_RDMA4) {
+ addr = DISP_OVL2_2L_MOUT_EN;
+ value = OVL2_2L_MOUT_RDMA4;
+ } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
+ addr = DISP_DITHER0_MOUT_EN;
+ value = DITHER0_MOUT_DSI0;
+ } else {
+ value = 0;
+ }
+
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+
+static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
+{
+ unsigned int addr, value, reg;
+
+ if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
+ addr = DISP_RDMA0_SEL_IN;
+ value = RDMA0_SEL_IN_OVL0_2L;
+ } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) {
+ addr = DISP_AAL0_SEL_IN;
+ value = AAL0_SEL_IN_CCORR0;
+ } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
+ addr = DISP_DSI0_SEL_IN;
+ value = DSI0_SEL_IN_DITHER0;
+ } else {
+ value = 0;
+ }
+
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+
+static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next)
+{
+ if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) {
+ writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + DISP_RDMA0_SOUT_SEL);
+ } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) {
+ writel_relaxed(CCORR0_SOUT_AAL0, config_regs + DISP_CCORR0_SOUT_SEL);
+ }
+}
+
+static void mtk_mmsys_ovl_mout_en(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
+{
+ unsigned int addr, value, reg;
+
+ addr = MMSYS_OVL_MOUT_EN;
+
+ if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0)
+ value = DISP_OVL0_GO_BG;
+ else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_OVL0)
+ value = DISP_OVL0_2L_GO_BG;
+ else if (cur == DDP_COMPONENT_OVL0)
+ value = DISP_OVL0_GO_BLEND;
+ else if (cur == DDP_COMPONENT_OVL_2L0)
+ value = DISP_OVL0_2L_GO_BLEND;
+ else
+ value = 0;
+
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+
+struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs = {
+ .mout_en = mtk_mmsys_ddp_mout_en,
+ .ovl_mout_en = mtk_mmsys_ovl_mout_en,
+ .sel_in = mtk_mmsys_ddp_sel_in,
+ .sout_sel = mtk_mmsys_ddp_sout_sel,
+};
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
index 34728ed..2c72607 100644
--- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -50,6 +50,11 @@ struct mtk_mmsys {
.funcs = &mt8183_mmsys_funcs,
};
+static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
+ .clk_driver = "clk-mt8192-mm",
+ .funcs = &mt8192_mmsys_funcs,
+};
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next)
@@ -157,6 +162,10 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
.compatible = "mediatek,mt8183-mmsys",
.data = &mt8183_mmsys_driver_data,
},
+ {
+ .compatible = "mediatek,mt8192-mmsys",
+ .data = &mt8192_mmsys_driver_data,
+ },
{ }
};
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 19318d2..eeec96a 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -65,6 +65,7 @@ struct mtk_mmsys_conn_funcs {
extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs;
extern struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs;
+extern struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs;
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 10/10] soc: mediatek: mmsys: add mt8192 mmsys support
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, Daniel Vetter, linux-arm-kernel
add mt8192 mmsys support
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/soc/mediatek/mmsys/Makefile | 1 +
drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 149 ++++++++++++++++++++++++++++++
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 9 ++
include/linux/soc/mediatek/mtk-mmsys.h | 1 +
4 files changed, 160 insertions(+)
create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c
diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
index 25eeb9e5..7508cd3 100644
--- a/drivers/soc/mediatek/mmsys/Makefile
+++ b/drivers/soc/mediatek/mmsys/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o
obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o
+obj-$(CONFIG_MTK_MMSYS) += mt8192-mmsys.o
obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
diff --git a/drivers/soc/mediatek/mmsys/mt8192-mmsys.c b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
new file mode 100644
index 0000000..2e350d1
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2020 MediaTek Inc.
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+
+#define MMSYS_OVL_MOUT_EN 0xf04
+#define DISP_OVL0_GO_BLEND BIT(0)
+#define DISP_OVL0_GO_BG BIT(1)
+#define DISP_OVL0_2L_GO_BLEND BIT(2)
+#define DISP_OVL0_2L_GO_BG BIT(3)
+#define DISP_OVL1_2L_MOUT_EN 0xf08
+#define OVL1_2L_MOUT_EN_RDMA1 BIT(4)
+#define DISP_OVL0_2L_MOUT_EN 0xf18
+#define DISP_OVL0_MOUT_EN 0xf1c
+#define OVL0_MOUT_EN_DISP_RDMA0 BIT(0)
+#define OVL0_MOUT_EN_OVL0_2L BIT(4)
+#define DISP_RDMA0_SEL_IN 0xf2c
+#define RDMA0_SEL_IN_OVL0_2L 0x3
+#define DISP_RDMA0_SOUT_SEL 0xf30
+#define RDMA0_SOUT_COLOR0 0x1
+#define DISP_CCORR0_SOUT_SEL 0xf34
+#define CCORR0_SOUT_AAL0 0x1
+#define DISP_AAL0_SEL_IN 0xf38
+#define AAL0_SEL_IN_CCORR0 0x1
+#define DISP_DITHER0_MOUT_EN 0xf3c
+#define DITHER0_MOUT_DSI0 BIT(0)
+#define DISP_DSI0_SEL_IN 0xf40
+#define DSI0_SEL_IN_DITHER0 0x1
+#define DISP_OVL2_2L_MOUT_EN 0xf4c
+#define OVL2_2L_MOUT_RDMA4 BIT(0)
+
+static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
+{
+ unsigned int addr, value, reg;
+
+ if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
+ addr = DISP_OVL0_2L_MOUT_EN;
+ value = OVL0_MOUT_EN_DISP_RDMA0;
+ } else if (cur == DDP_COMPONENT_OVL_2L2 && next == DDP_COMPONENT_RDMA4) {
+ addr = DISP_OVL2_2L_MOUT_EN;
+ value = OVL2_2L_MOUT_RDMA4;
+ } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
+ addr = DISP_DITHER0_MOUT_EN;
+ value = DITHER0_MOUT_DSI0;
+ } else {
+ value = 0;
+ }
+
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+
+static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
+{
+ unsigned int addr, value, reg;
+
+ if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
+ addr = DISP_RDMA0_SEL_IN;
+ value = RDMA0_SEL_IN_OVL0_2L;
+ } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) {
+ addr = DISP_AAL0_SEL_IN;
+ value = AAL0_SEL_IN_CCORR0;
+ } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
+ addr = DISP_DSI0_SEL_IN;
+ value = DSI0_SEL_IN_DITHER0;
+ } else {
+ value = 0;
+ }
+
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+
+static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next)
+{
+ if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) {
+ writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + DISP_RDMA0_SOUT_SEL);
+ } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) {
+ writel_relaxed(CCORR0_SOUT_AAL0, config_regs + DISP_CCORR0_SOUT_SEL);
+ }
+}
+
+static void mtk_mmsys_ovl_mout_en(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
+{
+ unsigned int addr, value, reg;
+
+ addr = MMSYS_OVL_MOUT_EN;
+
+ if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0)
+ value = DISP_OVL0_GO_BG;
+ else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_OVL0)
+ value = DISP_OVL0_2L_GO_BG;
+ else if (cur == DDP_COMPONENT_OVL0)
+ value = DISP_OVL0_GO_BLEND;
+ else if (cur == DDP_COMPONENT_OVL_2L0)
+ value = DISP_OVL0_2L_GO_BLEND;
+ else
+ value = 0;
+
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+
+struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs = {
+ .mout_en = mtk_mmsys_ddp_mout_en,
+ .ovl_mout_en = mtk_mmsys_ovl_mout_en,
+ .sel_in = mtk_mmsys_ddp_sel_in,
+ .sout_sel = mtk_mmsys_ddp_sout_sel,
+};
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
index 34728ed..2c72607 100644
--- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -50,6 +50,11 @@ struct mtk_mmsys {
.funcs = &mt8183_mmsys_funcs,
};
+static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
+ .clk_driver = "clk-mt8192-mm",
+ .funcs = &mt8192_mmsys_funcs,
+};
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next)
@@ -157,6 +162,10 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
.compatible = "mediatek,mt8183-mmsys",
.data = &mt8183_mmsys_driver_data,
},
+ {
+ .compatible = "mediatek,mt8192-mmsys",
+ .data = &mt8192_mmsys_driver_data,
+ },
{ }
};
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 19318d2..eeec96a 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -65,6 +65,7 @@ struct mtk_mmsys_conn_funcs {
extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs;
extern struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs;
+extern struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs;
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
--
1.8.1.1.dirty
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 10/10] soc: mediatek: mmsys: add mt8192 mmsys support
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, Daniel Vetter, linux-arm-kernel
add mt8192 mmsys support
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/soc/mediatek/mmsys/Makefile | 1 +
drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 149 ++++++++++++++++++++++++++++++
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 9 ++
include/linux/soc/mediatek/mtk-mmsys.h | 1 +
4 files changed, 160 insertions(+)
create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c
diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
index 25eeb9e5..7508cd3 100644
--- a/drivers/soc/mediatek/mmsys/Makefile
+++ b/drivers/soc/mediatek/mmsys/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o
obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o
+obj-$(CONFIG_MTK_MMSYS) += mt8192-mmsys.o
obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
diff --git a/drivers/soc/mediatek/mmsys/mt8192-mmsys.c b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
new file mode 100644
index 0000000..2e350d1
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2020 MediaTek Inc.
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+
+#define MMSYS_OVL_MOUT_EN 0xf04
+#define DISP_OVL0_GO_BLEND BIT(0)
+#define DISP_OVL0_GO_BG BIT(1)
+#define DISP_OVL0_2L_GO_BLEND BIT(2)
+#define DISP_OVL0_2L_GO_BG BIT(3)
+#define DISP_OVL1_2L_MOUT_EN 0xf08
+#define OVL1_2L_MOUT_EN_RDMA1 BIT(4)
+#define DISP_OVL0_2L_MOUT_EN 0xf18
+#define DISP_OVL0_MOUT_EN 0xf1c
+#define OVL0_MOUT_EN_DISP_RDMA0 BIT(0)
+#define OVL0_MOUT_EN_OVL0_2L BIT(4)
+#define DISP_RDMA0_SEL_IN 0xf2c
+#define RDMA0_SEL_IN_OVL0_2L 0x3
+#define DISP_RDMA0_SOUT_SEL 0xf30
+#define RDMA0_SOUT_COLOR0 0x1
+#define DISP_CCORR0_SOUT_SEL 0xf34
+#define CCORR0_SOUT_AAL0 0x1
+#define DISP_AAL0_SEL_IN 0xf38
+#define AAL0_SEL_IN_CCORR0 0x1
+#define DISP_DITHER0_MOUT_EN 0xf3c
+#define DITHER0_MOUT_DSI0 BIT(0)
+#define DISP_DSI0_SEL_IN 0xf40
+#define DSI0_SEL_IN_DITHER0 0x1
+#define DISP_OVL2_2L_MOUT_EN 0xf4c
+#define OVL2_2L_MOUT_RDMA4 BIT(0)
+
+static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
+{
+ unsigned int addr, value, reg;
+
+ if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
+ addr = DISP_OVL0_2L_MOUT_EN;
+ value = OVL0_MOUT_EN_DISP_RDMA0;
+ } else if (cur == DDP_COMPONENT_OVL_2L2 && next == DDP_COMPONENT_RDMA4) {
+ addr = DISP_OVL2_2L_MOUT_EN;
+ value = OVL2_2L_MOUT_RDMA4;
+ } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
+ addr = DISP_DITHER0_MOUT_EN;
+ value = DITHER0_MOUT_DSI0;
+ } else {
+ value = 0;
+ }
+
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+
+static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
+{
+ unsigned int addr, value, reg;
+
+ if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
+ addr = DISP_RDMA0_SEL_IN;
+ value = RDMA0_SEL_IN_OVL0_2L;
+ } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) {
+ addr = DISP_AAL0_SEL_IN;
+ value = AAL0_SEL_IN_CCORR0;
+ } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
+ addr = DISP_DSI0_SEL_IN;
+ value = DSI0_SEL_IN_DITHER0;
+ } else {
+ value = 0;
+ }
+
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+
+static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next)
+{
+ if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) {
+ writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + DISP_RDMA0_SOUT_SEL);
+ } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) {
+ writel_relaxed(CCORR0_SOUT_AAL0, config_regs + DISP_CCORR0_SOUT_SEL);
+ }
+}
+
+static void mtk_mmsys_ovl_mout_en(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
+{
+ unsigned int addr, value, reg;
+
+ addr = MMSYS_OVL_MOUT_EN;
+
+ if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0)
+ value = DISP_OVL0_GO_BG;
+ else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_OVL0)
+ value = DISP_OVL0_2L_GO_BG;
+ else if (cur == DDP_COMPONENT_OVL0)
+ value = DISP_OVL0_GO_BLEND;
+ else if (cur == DDP_COMPONENT_OVL_2L0)
+ value = DISP_OVL0_2L_GO_BLEND;
+ else
+ value = 0;
+
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+
+struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs = {
+ .mout_en = mtk_mmsys_ddp_mout_en,
+ .ovl_mout_en = mtk_mmsys_ovl_mout_en,
+ .sel_in = mtk_mmsys_ddp_sel_in,
+ .sout_sel = mtk_mmsys_ddp_sout_sel,
+};
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
index 34728ed..2c72607 100644
--- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -50,6 +50,11 @@ struct mtk_mmsys {
.funcs = &mt8183_mmsys_funcs,
};
+static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
+ .clk_driver = "clk-mt8192-mm",
+ .funcs = &mt8192_mmsys_funcs,
+};
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next)
@@ -157,6 +162,10 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
.compatible = "mediatek,mt8183-mmsys",
.data = &mt8183_mmsys_driver_data,
},
+ {
+ .compatible = "mediatek,mt8192-mmsys",
+ .data = &mt8192_mmsys_driver_data,
+ },
{ }
};
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 19318d2..eeec96a 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -65,6 +65,7 @@ struct mtk_mmsys_conn_funcs {
extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs;
extern struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs;
+extern struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs;
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
--
1.8.1.1.dirty
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^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4, 10/10] soc: mediatek: mmsys: add mt8192 mmsys support
@ 2021-01-05 3:06 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-05 3:06 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, linux-arm-kernel
add mt8192 mmsys support
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/soc/mediatek/mmsys/Makefile | 1 +
drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 149 ++++++++++++++++++++++++++++++
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 9 ++
include/linux/soc/mediatek/mtk-mmsys.h | 1 +
4 files changed, 160 insertions(+)
create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c
diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
index 25eeb9e5..7508cd3 100644
--- a/drivers/soc/mediatek/mmsys/Makefile
+++ b/drivers/soc/mediatek/mmsys/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o
obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o
+obj-$(CONFIG_MTK_MMSYS) += mt8192-mmsys.o
obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
diff --git a/drivers/soc/mediatek/mmsys/mt8192-mmsys.c b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
new file mode 100644
index 0000000..2e350d1
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2020 MediaTek Inc.
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+
+#define MMSYS_OVL_MOUT_EN 0xf04
+#define DISP_OVL0_GO_BLEND BIT(0)
+#define DISP_OVL0_GO_BG BIT(1)
+#define DISP_OVL0_2L_GO_BLEND BIT(2)
+#define DISP_OVL0_2L_GO_BG BIT(3)
+#define DISP_OVL1_2L_MOUT_EN 0xf08
+#define OVL1_2L_MOUT_EN_RDMA1 BIT(4)
+#define DISP_OVL0_2L_MOUT_EN 0xf18
+#define DISP_OVL0_MOUT_EN 0xf1c
+#define OVL0_MOUT_EN_DISP_RDMA0 BIT(0)
+#define OVL0_MOUT_EN_OVL0_2L BIT(4)
+#define DISP_RDMA0_SEL_IN 0xf2c
+#define RDMA0_SEL_IN_OVL0_2L 0x3
+#define DISP_RDMA0_SOUT_SEL 0xf30
+#define RDMA0_SOUT_COLOR0 0x1
+#define DISP_CCORR0_SOUT_SEL 0xf34
+#define CCORR0_SOUT_AAL0 0x1
+#define DISP_AAL0_SEL_IN 0xf38
+#define AAL0_SEL_IN_CCORR0 0x1
+#define DISP_DITHER0_MOUT_EN 0xf3c
+#define DITHER0_MOUT_DSI0 BIT(0)
+#define DISP_DSI0_SEL_IN 0xf40
+#define DSI0_SEL_IN_DITHER0 0x1
+#define DISP_OVL2_2L_MOUT_EN 0xf4c
+#define OVL2_2L_MOUT_RDMA4 BIT(0)
+
+static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
+{
+ unsigned int addr, value, reg;
+
+ if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
+ addr = DISP_OVL0_2L_MOUT_EN;
+ value = OVL0_MOUT_EN_DISP_RDMA0;
+ } else if (cur == DDP_COMPONENT_OVL_2L2 && next == DDP_COMPONENT_RDMA4) {
+ addr = DISP_OVL2_2L_MOUT_EN;
+ value = OVL2_2L_MOUT_RDMA4;
+ } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
+ addr = DISP_DITHER0_MOUT_EN;
+ value = DITHER0_MOUT_DSI0;
+ } else {
+ value = 0;
+ }
+
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+
+static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
+{
+ unsigned int addr, value, reg;
+
+ if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
+ addr = DISP_RDMA0_SEL_IN;
+ value = RDMA0_SEL_IN_OVL0_2L;
+ } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) {
+ addr = DISP_AAL0_SEL_IN;
+ value = AAL0_SEL_IN_CCORR0;
+ } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
+ addr = DISP_DSI0_SEL_IN;
+ value = DSI0_SEL_IN_DITHER0;
+ } else {
+ value = 0;
+ }
+
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+
+static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next)
+{
+ if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) {
+ writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + DISP_RDMA0_SOUT_SEL);
+ } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) {
+ writel_relaxed(CCORR0_SOUT_AAL0, config_regs + DISP_CCORR0_SOUT_SEL);
+ }
+}
+
+static void mtk_mmsys_ovl_mout_en(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
+{
+ unsigned int addr, value, reg;
+
+ addr = MMSYS_OVL_MOUT_EN;
+
+ if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0)
+ value = DISP_OVL0_GO_BG;
+ else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_OVL0)
+ value = DISP_OVL0_2L_GO_BG;
+ else if (cur == DDP_COMPONENT_OVL0)
+ value = DISP_OVL0_GO_BLEND;
+ else if (cur == DDP_COMPONENT_OVL_2L0)
+ value = DISP_OVL0_2L_GO_BLEND;
+ else
+ value = 0;
+
+ if (value) {
+ reg = readl_relaxed(config_regs + addr);
+
+ if (enable)
+ reg |= value;
+ else
+ reg &= ~value;
+
+ writel_relaxed(reg, config_regs + addr);
+ }
+}
+
+struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs = {
+ .mout_en = mtk_mmsys_ddp_mout_en,
+ .ovl_mout_en = mtk_mmsys_ovl_mout_en,
+ .sel_in = mtk_mmsys_ddp_sel_in,
+ .sout_sel = mtk_mmsys_ddp_sout_sel,
+};
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
index 34728ed..2c72607 100644
--- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -50,6 +50,11 @@ struct mtk_mmsys {
.funcs = &mt8183_mmsys_funcs,
};
+static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
+ .clk_driver = "clk-mt8192-mm",
+ .funcs = &mt8192_mmsys_funcs,
+};
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next)
@@ -157,6 +162,10 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
.compatible = "mediatek,mt8183-mmsys",
.data = &mt8183_mmsys_driver_data,
},
+ {
+ .compatible = "mediatek,mt8192-mmsys",
+ .data = &mt8192_mmsys_driver_data,
+ },
{ }
};
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 19318d2..eeec96a 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -65,6 +65,7 @@ struct mtk_mmsys_conn_funcs {
extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs;
extern struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs;
+extern struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs;
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
--
1.8.1.1.dirty
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dri-devel@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 75+ messages in thread
* Re: [PATCH v4, 10/10] soc: mediatek: mmsys: add mt8192 mmsys support
2021-01-05 3:06 ` Yongqiang Niu
(?)
(?)
@ 2021-01-06 16:36 ` Chun-Kuang Hu
-1 siblings, 0 replies; 75+ messages in thread
From: Chun-Kuang Hu @ 2021-01-06 16:36 UTC (permalink / raw)
To: Yongqiang Niu
Cc: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger,
Mark Rutland, DTML, David Airlie, linux-kernel, DRI Development,
Project_Global_Chrome_Upstream_Group,
moderated list:ARM/Mediatek SoC support, Daniel Vetter,
Linux ARM
Hi, Yongqiang:
Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2021年1月5日 週二 上午11:17寫道：
>
> add mt8192 mmsys support
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/soc/mediatek/mmsys/Makefile | 1 +
> drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 149 ++++++++++++++++++++++++++++++
> drivers/soc/mediatek/mmsys/mtk-mmsys.c | 9 ++
> include/linux/soc/mediatek/mtk-mmsys.h | 1 +
> 4 files changed, 160 insertions(+)
> create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c
>
> diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
> index 25eeb9e5..7508cd3 100644
> --- a/drivers/soc/mediatek/mmsys/Makefile
> +++ b/drivers/soc/mediatek/mmsys/Makefile
> @@ -1,4 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0-only
> obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o
> obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o
> +obj-$(CONFIG_MTK_MMSYS) += mt8192-mmsys.o
> obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
> diff --git a/drivers/soc/mediatek/mmsys/mt8192-mmsys.c b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
> new file mode 100644
> index 0000000..2e350d1
> --- /dev/null
> +++ b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
> @@ -0,0 +1,149 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (c) 2020 MediaTek Inc.
> +
> +#include <linux/device.h>
> +#include <linux/io.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +
> +#define MMSYS_OVL_MOUT_EN 0xf04
> +#define DISP_OVL0_GO_BLEND BIT(0)
> +#define DISP_OVL0_GO_BG BIT(1)
> +#define DISP_OVL0_2L_GO_BLEND BIT(2)
> +#define DISP_OVL0_2L_GO_BG BIT(3)
> +#define DISP_OVL1_2L_MOUT_EN 0xf08
> +#define OVL1_2L_MOUT_EN_RDMA1 BIT(4)
> +#define DISP_OVL0_2L_MOUT_EN 0xf18
> +#define DISP_OVL0_MOUT_EN 0xf1c
> +#define OVL0_MOUT_EN_DISP_RDMA0 BIT(0)
> +#define OVL0_MOUT_EN_OVL0_2L BIT(4)
> +#define DISP_RDMA0_SEL_IN 0xf2c
> +#define RDMA0_SEL_IN_OVL0_2L 0x3
> +#define DISP_RDMA0_SOUT_SEL 0xf30
> +#define RDMA0_SOUT_COLOR0 0x1
> +#define DISP_CCORR0_SOUT_SEL 0xf34
> +#define CCORR0_SOUT_AAL0 0x1
> +#define DISP_AAL0_SEL_IN 0xf38
> +#define AAL0_SEL_IN_CCORR0 0x1
> +#define DISP_DITHER0_MOUT_EN 0xf3c
> +#define DITHER0_MOUT_DSI0 BIT(0)
> +#define DISP_DSI0_SEL_IN 0xf40
> +#define DSI0_SEL_IN_DITHER0 0x1
> +#define DISP_OVL2_2L_MOUT_EN 0xf4c
> +#define OVL2_2L_MOUT_RDMA4 BIT(0)
> +
> +static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + bool enable)
> +{
> + unsigned int addr, value, reg;
> +
> + if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
> + addr = DISP_OVL0_2L_MOUT_EN;
> + value = OVL0_MOUT_EN_DISP_RDMA0;
> + } else if (cur == DDP_COMPONENT_OVL_2L2 && next == DDP_COMPONENT_RDMA4) {
> + addr = DISP_OVL2_2L_MOUT_EN;
> + value = OVL2_2L_MOUT_RDMA4;
> + } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
> + addr = DISP_DITHER0_MOUT_EN;
> + value = DITHER0_MOUT_DSI0;
> + } else {
> + value = 0;
> + }
> +
> + if (value) {
> + reg = readl_relaxed(config_regs + addr);
> +
> + if (enable)
> + reg |= value;
> + else
> + reg &= ~value;
> +
> + writel_relaxed(reg, config_regs + addr);
> + }
> +}
> +
> +static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + bool enable)
> +{
> + unsigned int addr, value, reg;
> +
> + if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
> + addr = DISP_RDMA0_SEL_IN;
> + value = RDMA0_SEL_IN_OVL0_2L;
> + } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) {
> + addr = DISP_AAL0_SEL_IN;
> + value = AAL0_SEL_IN_CCORR0;
> + } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
> + addr = DISP_DSI0_SEL_IN;
> + value = DSI0_SEL_IN_DITHER0;
> + } else {
> + value = 0;
> + }
> +
> + if (value) {
> + reg = readl_relaxed(config_regs + addr);
> +
> + if (enable)
> + reg |= value;
> + else
> + reg &= ~value;
> +
> + writel_relaxed(reg, config_regs + addr);
> + }
> +}
> +
> +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next)
> +{
> + if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) {
> + writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + DISP_RDMA0_SOUT_SEL);
> + } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) {
> + writel_relaxed(CCORR0_SOUT_AAL0, config_regs + DISP_CCORR0_SOUT_SEL);
> + }
> +}
> +
> +static void mtk_mmsys_ovl_mout_en(void __iomem *config_regs,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + bool enable)
> +{
> + unsigned int addr, value, reg;
> +
> + addr = MMSYS_OVL_MOUT_EN;
> +
> + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0)
> + value = DISP_OVL0_GO_BG;
> + else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_OVL0)
> + value = DISP_OVL0_2L_GO_BG;
> + else if (cur == DDP_COMPONENT_OVL0)
> + value = DISP_OVL0_GO_BLEND;
> + else if (cur == DDP_COMPONENT_OVL_2L0)
> + value = DISP_OVL0_2L_GO_BLEND;
> + else
> + value = 0;
> +
> + if (value) {
> + reg = readl_relaxed(config_regs + addr);
> +
> + if (enable)
> + reg |= value;
> + else
> + reg &= ~value;
> +
> + writel_relaxed(reg, config_regs + addr);
> + }
I think you could squash mtk_mmsys_ovl_mout_en() into
mtk_mmsys_ddp_mout_en() and directly read/write register in if-else
statement.
Regards,
Chun-Kuang.
> +}
> +
> +struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs = {
> + .mout_en = mtk_mmsys_ddp_mout_en,
> + .ovl_mout_en = mtk_mmsys_ovl_mout_en,
> + .sel_in = mtk_mmsys_ddp_sel_in,
> + .sout_sel = mtk_mmsys_ddp_sout_sel,
> +};
> diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> index 34728ed..2c72607 100644
> --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> @@ -50,6 +50,11 @@ struct mtk_mmsys {
> .funcs = &mt8183_mmsys_funcs,
> };
>
> +static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
> + .clk_driver = "clk-mt8192-mm",
> + .funcs = &mt8192_mmsys_funcs,
> +};
> +
> void mtk_mmsys_ddp_connect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next)
> @@ -157,6 +162,10 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> .compatible = "mediatek,mt8183-mmsys",
> .data = &mt8183_mmsys_driver_data,
> },
> + {
> + .compatible = "mediatek,mt8192-mmsys",
> + .data = &mt8192_mmsys_driver_data,
> + },
> { }
> };
>
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 19318d2..eeec96a 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -65,6 +65,7 @@ struct mtk_mmsys_conn_funcs {
>
> extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs;
> extern struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs;
> +extern struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs;
>
> void mtk_mmsys_ddp_connect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4, 10/10] soc: mediatek: mmsys: add mt8192 mmsys support
@ 2021-01-06 16:36 ` Chun-Kuang Hu
0 siblings, 0 replies; 75+ messages in thread
From: Chun-Kuang Hu @ 2021-01-06 16:36 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, DTML, Daniel Vetter, David Airlie, linux-kernel,
DRI Development, Project_Global_Chrome_Upstream_Group,
Matthias Brugger, Rob Herring,
moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu,
Linux ARM
Hi, Yongqiang:
Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2021年1月5日 週二 上午11:17寫道：
>
> add mt8192 mmsys support
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/soc/mediatek/mmsys/Makefile | 1 +
> drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 149 ++++++++++++++++++++++++++++++
> drivers/soc/mediatek/mmsys/mtk-mmsys.c | 9 ++
> include/linux/soc/mediatek/mtk-mmsys.h | 1 +
> 4 files changed, 160 insertions(+)
> create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c
>
> diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
> index 25eeb9e5..7508cd3 100644
> --- a/drivers/soc/mediatek/mmsys/Makefile
> +++ b/drivers/soc/mediatek/mmsys/Makefile
> @@ -1,4 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0-only
> obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o
> obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o
> +obj-$(CONFIG_MTK_MMSYS) += mt8192-mmsys.o
> obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
> diff --git a/drivers/soc/mediatek/mmsys/mt8192-mmsys.c b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
> new file mode 100644
> index 0000000..2e350d1
> --- /dev/null
> +++ b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
> @@ -0,0 +1,149 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (c) 2020 MediaTek Inc.
> +
> +#include <linux/device.h>
> +#include <linux/io.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +
> +#define MMSYS_OVL_MOUT_EN 0xf04
> +#define DISP_OVL0_GO_BLEND BIT(0)
> +#define DISP_OVL0_GO_BG BIT(1)
> +#define DISP_OVL0_2L_GO_BLEND BIT(2)
> +#define DISP_OVL0_2L_GO_BG BIT(3)
> +#define DISP_OVL1_2L_MOUT_EN 0xf08
> +#define OVL1_2L_MOUT_EN_RDMA1 BIT(4)
> +#define DISP_OVL0_2L_MOUT_EN 0xf18
> +#define DISP_OVL0_MOUT_EN 0xf1c
> +#define OVL0_MOUT_EN_DISP_RDMA0 BIT(0)
> +#define OVL0_MOUT_EN_OVL0_2L BIT(4)
> +#define DISP_RDMA0_SEL_IN 0xf2c
> +#define RDMA0_SEL_IN_OVL0_2L 0x3
> +#define DISP_RDMA0_SOUT_SEL 0xf30
> +#define RDMA0_SOUT_COLOR0 0x1
> +#define DISP_CCORR0_SOUT_SEL 0xf34
> +#define CCORR0_SOUT_AAL0 0x1
> +#define DISP_AAL0_SEL_IN 0xf38
> +#define AAL0_SEL_IN_CCORR0 0x1
> +#define DISP_DITHER0_MOUT_EN 0xf3c
> +#define DITHER0_MOUT_DSI0 BIT(0)
> +#define DISP_DSI0_SEL_IN 0xf40
> +#define DSI0_SEL_IN_DITHER0 0x1
> +#define DISP_OVL2_2L_MOUT_EN 0xf4c
> +#define OVL2_2L_MOUT_RDMA4 BIT(0)
> +
> +static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + bool enable)
> +{
> + unsigned int addr, value, reg;
> +
> + if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
> + addr = DISP_OVL0_2L_MOUT_EN;
> + value = OVL0_MOUT_EN_DISP_RDMA0;
> + } else if (cur == DDP_COMPONENT_OVL_2L2 && next == DDP_COMPONENT_RDMA4) {
> + addr = DISP_OVL2_2L_MOUT_EN;
> + value = OVL2_2L_MOUT_RDMA4;
> + } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
> + addr = DISP_DITHER0_MOUT_EN;
> + value = DITHER0_MOUT_DSI0;
> + } else {
> + value = 0;
> + }
> +
> + if (value) {
> + reg = readl_relaxed(config_regs + addr);
> +
> + if (enable)
> + reg |= value;
> + else
> + reg &= ~value;
> +
> + writel_relaxed(reg, config_regs + addr);
> + }
> +}
> +
> +static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + bool enable)
> +{
> + unsigned int addr, value, reg;
> +
> + if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
> + addr = DISP_RDMA0_SEL_IN;
> + value = RDMA0_SEL_IN_OVL0_2L;
> + } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) {
> + addr = DISP_AAL0_SEL_IN;
> + value = AAL0_SEL_IN_CCORR0;
> + } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
> + addr = DISP_DSI0_SEL_IN;
> + value = DSI0_SEL_IN_DITHER0;
> + } else {
> + value = 0;
> + }
> +
> + if (value) {
> + reg = readl_relaxed(config_regs + addr);
> +
> + if (enable)
> + reg |= value;
> + else
> + reg &= ~value;
> +
> + writel_relaxed(reg, config_regs + addr);
> + }
> +}
> +
> +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next)
> +{
> + if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) {
> + writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + DISP_RDMA0_SOUT_SEL);
> + } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) {
> + writel_relaxed(CCORR0_SOUT_AAL0, config_regs + DISP_CCORR0_SOUT_SEL);
> + }
> +}
> +
> +static void mtk_mmsys_ovl_mout_en(void __iomem *config_regs,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + bool enable)
> +{
> + unsigned int addr, value, reg;
> +
> + addr = MMSYS_OVL_MOUT_EN;
> +
> + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0)
> + value = DISP_OVL0_GO_BG;
> + else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_OVL0)
> + value = DISP_OVL0_2L_GO_BG;
> + else if (cur == DDP_COMPONENT_OVL0)
> + value = DISP_OVL0_GO_BLEND;
> + else if (cur == DDP_COMPONENT_OVL_2L0)
> + value = DISP_OVL0_2L_GO_BLEND;
> + else
> + value = 0;
> +
> + if (value) {
> + reg = readl_relaxed(config_regs + addr);
> +
> + if (enable)
> + reg |= value;
> + else
> + reg &= ~value;
> +
> + writel_relaxed(reg, config_regs + addr);
> + }
I think you could squash mtk_mmsys_ovl_mout_en() into
mtk_mmsys_ddp_mout_en() and directly read/write register in if-else
statement.
Regards,
Chun-Kuang.
> +}
> +
> +struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs = {
> + .mout_en = mtk_mmsys_ddp_mout_en,
> + .ovl_mout_en = mtk_mmsys_ovl_mout_en,
> + .sel_in = mtk_mmsys_ddp_sel_in,
> + .sout_sel = mtk_mmsys_ddp_sout_sel,
> +};
> diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> index 34728ed..2c72607 100644
> --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> @@ -50,6 +50,11 @@ struct mtk_mmsys {
> .funcs = &mt8183_mmsys_funcs,
> };
>
> +static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
> + .clk_driver = "clk-mt8192-mm",
> + .funcs = &mt8192_mmsys_funcs,
> +};
> +
> void mtk_mmsys_ddp_connect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next)
> @@ -157,6 +162,10 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> .compatible = "mediatek,mt8183-mmsys",
> .data = &mt8183_mmsys_driver_data,
> },
> + {
> + .compatible = "mediatek,mt8192-mmsys",
> + .data = &mt8192_mmsys_driver_data,
> + },
> { }
> };
>
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 19318d2..eeec96a 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -65,6 +65,7 @@ struct mtk_mmsys_conn_funcs {
>
> extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs;
> extern struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs;
> +extern struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs;
>
> void mtk_mmsys_ddp_connect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4, 10/10] soc: mediatek: mmsys: add mt8192 mmsys support
@ 2021-01-06 16:36 ` Chun-Kuang Hu
0 siblings, 0 replies; 75+ messages in thread
From: Chun-Kuang Hu @ 2021-01-06 16:36 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, DTML, Daniel Vetter, David Airlie, linux-kernel,
DRI Development, Project_Global_Chrome_Upstream_Group,
Matthias Brugger, Rob Herring,
moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu,
Linux ARM
Hi, Yongqiang:
Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2021年1月5日 週二 上午11:17寫道：
>
> add mt8192 mmsys support
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/soc/mediatek/mmsys/Makefile | 1 +
> drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 149 ++++++++++++++++++++++++++++++
> drivers/soc/mediatek/mmsys/mtk-mmsys.c | 9 ++
> include/linux/soc/mediatek/mtk-mmsys.h | 1 +
> 4 files changed, 160 insertions(+)
> create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c
>
> diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
> index 25eeb9e5..7508cd3 100644
> --- a/drivers/soc/mediatek/mmsys/Makefile
> +++ b/drivers/soc/mediatek/mmsys/Makefile
> @@ -1,4 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0-only
> obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o
> obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o
> +obj-$(CONFIG_MTK_MMSYS) += mt8192-mmsys.o
> obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
> diff --git a/drivers/soc/mediatek/mmsys/mt8192-mmsys.c b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
> new file mode 100644
> index 0000000..2e350d1
> --- /dev/null
> +++ b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
> @@ -0,0 +1,149 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (c) 2020 MediaTek Inc.
> +
> +#include <linux/device.h>
> +#include <linux/io.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +
> +#define MMSYS_OVL_MOUT_EN 0xf04
> +#define DISP_OVL0_GO_BLEND BIT(0)
> +#define DISP_OVL0_GO_BG BIT(1)
> +#define DISP_OVL0_2L_GO_BLEND BIT(2)
> +#define DISP_OVL0_2L_GO_BG BIT(3)
> +#define DISP_OVL1_2L_MOUT_EN 0xf08
> +#define OVL1_2L_MOUT_EN_RDMA1 BIT(4)
> +#define DISP_OVL0_2L_MOUT_EN 0xf18
> +#define DISP_OVL0_MOUT_EN 0xf1c
> +#define OVL0_MOUT_EN_DISP_RDMA0 BIT(0)
> +#define OVL0_MOUT_EN_OVL0_2L BIT(4)
> +#define DISP_RDMA0_SEL_IN 0xf2c
> +#define RDMA0_SEL_IN_OVL0_2L 0x3
> +#define DISP_RDMA0_SOUT_SEL 0xf30
> +#define RDMA0_SOUT_COLOR0 0x1
> +#define DISP_CCORR0_SOUT_SEL 0xf34
> +#define CCORR0_SOUT_AAL0 0x1
> +#define DISP_AAL0_SEL_IN 0xf38
> +#define AAL0_SEL_IN_CCORR0 0x1
> +#define DISP_DITHER0_MOUT_EN 0xf3c
> +#define DITHER0_MOUT_DSI0 BIT(0)
> +#define DISP_DSI0_SEL_IN 0xf40
> +#define DSI0_SEL_IN_DITHER0 0x1
> +#define DISP_OVL2_2L_MOUT_EN 0xf4c
> +#define OVL2_2L_MOUT_RDMA4 BIT(0)
> +
> +static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + bool enable)
> +{
> + unsigned int addr, value, reg;
> +
> + if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
> + addr = DISP_OVL0_2L_MOUT_EN;
> + value = OVL0_MOUT_EN_DISP_RDMA0;
> + } else if (cur == DDP_COMPONENT_OVL_2L2 && next == DDP_COMPONENT_RDMA4) {
> + addr = DISP_OVL2_2L_MOUT_EN;
> + value = OVL2_2L_MOUT_RDMA4;
> + } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
> + addr = DISP_DITHER0_MOUT_EN;
> + value = DITHER0_MOUT_DSI0;
> + } else {
> + value = 0;
> + }
> +
> + if (value) {
> + reg = readl_relaxed(config_regs + addr);
> +
> + if (enable)
> + reg |= value;
> + else
> + reg &= ~value;
> +
> + writel_relaxed(reg, config_regs + addr);
> + }
> +}
> +
> +static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + bool enable)
> +{
> + unsigned int addr, value, reg;
> +
> + if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
> + addr = DISP_RDMA0_SEL_IN;
> + value = RDMA0_SEL_IN_OVL0_2L;
> + } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) {
> + addr = DISP_AAL0_SEL_IN;
> + value = AAL0_SEL_IN_CCORR0;
> + } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
> + addr = DISP_DSI0_SEL_IN;
> + value = DSI0_SEL_IN_DITHER0;
> + } else {
> + value = 0;
> + }
> +
> + if (value) {
> + reg = readl_relaxed(config_regs + addr);
> +
> + if (enable)
> + reg |= value;
> + else
> + reg &= ~value;
> +
> + writel_relaxed(reg, config_regs + addr);
> + }
> +}
> +
> +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next)
> +{
> + if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) {
> + writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + DISP_RDMA0_SOUT_SEL);
> + } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) {
> + writel_relaxed(CCORR0_SOUT_AAL0, config_regs + DISP_CCORR0_SOUT_SEL);
> + }
> +}
> +
> +static void mtk_mmsys_ovl_mout_en(void __iomem *config_regs,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + bool enable)
> +{
> + unsigned int addr, value, reg;
> +
> + addr = MMSYS_OVL_MOUT_EN;
> +
> + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0)
> + value = DISP_OVL0_GO_BG;
> + else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_OVL0)
> + value = DISP_OVL0_2L_GO_BG;
> + else if (cur == DDP_COMPONENT_OVL0)
> + value = DISP_OVL0_GO_BLEND;
> + else if (cur == DDP_COMPONENT_OVL_2L0)
> + value = DISP_OVL0_2L_GO_BLEND;
> + else
> + value = 0;
> +
> + if (value) {
> + reg = readl_relaxed(config_regs + addr);
> +
> + if (enable)
> + reg |= value;
> + else
> + reg &= ~value;
> +
> + writel_relaxed(reg, config_regs + addr);
> + }
I think you could squash mtk_mmsys_ovl_mout_en() into
mtk_mmsys_ddp_mout_en() and directly read/write register in if-else
statement.
Regards,
Chun-Kuang.
> +}
> +
> +struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs = {
> + .mout_en = mtk_mmsys_ddp_mout_en,
> + .ovl_mout_en = mtk_mmsys_ovl_mout_en,
> + .sel_in = mtk_mmsys_ddp_sel_in,
> + .sout_sel = mtk_mmsys_ddp_sout_sel,
> +};
> diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> index 34728ed..2c72607 100644
> --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> @@ -50,6 +50,11 @@ struct mtk_mmsys {
> .funcs = &mt8183_mmsys_funcs,
> };
>
> +static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
> + .clk_driver = "clk-mt8192-mm",
> + .funcs = &mt8192_mmsys_funcs,
> +};
> +
> void mtk_mmsys_ddp_connect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next)
> @@ -157,6 +162,10 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> .compatible = "mediatek,mt8183-mmsys",
> .data = &mt8183_mmsys_driver_data,
> },
> + {
> + .compatible = "mediatek,mt8192-mmsys",
> + .data = &mt8192_mmsys_driver_data,
> + },
> { }
> };
>
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 19318d2..eeec96a 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -65,6 +65,7 @@ struct mtk_mmsys_conn_funcs {
>
> extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs;
> extern struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs;
> +extern struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs;
>
> void mtk_mmsys_ddp_connect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4, 10/10] soc: mediatek: mmsys: add mt8192 mmsys support
@ 2021-01-06 16:36 ` Chun-Kuang Hu
0 siblings, 0 replies; 75+ messages in thread
From: Chun-Kuang Hu @ 2021-01-06 16:36 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, DTML, David Airlie, linux-kernel, DRI Development,
Project_Global_Chrome_Upstream_Group, Matthias Brugger,
Rob Herring, moderated list:ARM/Mediatek SoC support, Linux ARM
Hi, Yongqiang:
Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2021年1月5日 週二 上午11:17寫道：
>
> add mt8192 mmsys support
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/soc/mediatek/mmsys/Makefile | 1 +
> drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 149 ++++++++++++++++++++++++++++++
> drivers/soc/mediatek/mmsys/mtk-mmsys.c | 9 ++
> include/linux/soc/mediatek/mtk-mmsys.h | 1 +
> 4 files changed, 160 insertions(+)
> create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c
>
> diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
> index 25eeb9e5..7508cd3 100644
> --- a/drivers/soc/mediatek/mmsys/Makefile
> +++ b/drivers/soc/mediatek/mmsys/Makefile
> @@ -1,4 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0-only
> obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o
> obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o
> +obj-$(CONFIG_MTK_MMSYS) += mt8192-mmsys.o
> obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
> diff --git a/drivers/soc/mediatek/mmsys/mt8192-mmsys.c b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
> new file mode 100644
> index 0000000..2e350d1
> --- /dev/null
> +++ b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
> @@ -0,0 +1,149 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (c) 2020 MediaTek Inc.
> +
> +#include <linux/device.h>
> +#include <linux/io.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +
> +#define MMSYS_OVL_MOUT_EN 0xf04
> +#define DISP_OVL0_GO_BLEND BIT(0)
> +#define DISP_OVL0_GO_BG BIT(1)
> +#define DISP_OVL0_2L_GO_BLEND BIT(2)
> +#define DISP_OVL0_2L_GO_BG BIT(3)
> +#define DISP_OVL1_2L_MOUT_EN 0xf08
> +#define OVL1_2L_MOUT_EN_RDMA1 BIT(4)
> +#define DISP_OVL0_2L_MOUT_EN 0xf18
> +#define DISP_OVL0_MOUT_EN 0xf1c
> +#define OVL0_MOUT_EN_DISP_RDMA0 BIT(0)
> +#define OVL0_MOUT_EN_OVL0_2L BIT(4)
> +#define DISP_RDMA0_SEL_IN 0xf2c
> +#define RDMA0_SEL_IN_OVL0_2L 0x3
> +#define DISP_RDMA0_SOUT_SEL 0xf30
> +#define RDMA0_SOUT_COLOR0 0x1
> +#define DISP_CCORR0_SOUT_SEL 0xf34
> +#define CCORR0_SOUT_AAL0 0x1
> +#define DISP_AAL0_SEL_IN 0xf38
> +#define AAL0_SEL_IN_CCORR0 0x1
> +#define DISP_DITHER0_MOUT_EN 0xf3c
> +#define DITHER0_MOUT_DSI0 BIT(0)
> +#define DISP_DSI0_SEL_IN 0xf40
> +#define DSI0_SEL_IN_DITHER0 0x1
> +#define DISP_OVL2_2L_MOUT_EN 0xf4c
> +#define OVL2_2L_MOUT_RDMA4 BIT(0)
> +
> +static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + bool enable)
> +{
> + unsigned int addr, value, reg;
> +
> + if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
> + addr = DISP_OVL0_2L_MOUT_EN;
> + value = OVL0_MOUT_EN_DISP_RDMA0;
> + } else if (cur == DDP_COMPONENT_OVL_2L2 && next == DDP_COMPONENT_RDMA4) {
> + addr = DISP_OVL2_2L_MOUT_EN;
> + value = OVL2_2L_MOUT_RDMA4;
> + } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
> + addr = DISP_DITHER0_MOUT_EN;
> + value = DITHER0_MOUT_DSI0;
> + } else {
> + value = 0;
> + }
> +
> + if (value) {
> + reg = readl_relaxed(config_regs + addr);
> +
> + if (enable)
> + reg |= value;
> + else
> + reg &= ~value;
> +
> + writel_relaxed(reg, config_regs + addr);
> + }
> +}
> +
> +static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + bool enable)
> +{
> + unsigned int addr, value, reg;
> +
> + if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
> + addr = DISP_RDMA0_SEL_IN;
> + value = RDMA0_SEL_IN_OVL0_2L;
> + } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) {
> + addr = DISP_AAL0_SEL_IN;
> + value = AAL0_SEL_IN_CCORR0;
> + } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
> + addr = DISP_DSI0_SEL_IN;
> + value = DSI0_SEL_IN_DITHER0;
> + } else {
> + value = 0;
> + }
> +
> + if (value) {
> + reg = readl_relaxed(config_regs + addr);
> +
> + if (enable)
> + reg |= value;
> + else
> + reg &= ~value;
> +
> + writel_relaxed(reg, config_regs + addr);
> + }
> +}
> +
> +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next)
> +{
> + if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) {
> + writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + DISP_RDMA0_SOUT_SEL);
> + } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) {
> + writel_relaxed(CCORR0_SOUT_AAL0, config_regs + DISP_CCORR0_SOUT_SEL);
> + }
> +}
> +
> +static void mtk_mmsys_ovl_mout_en(void __iomem *config_regs,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + bool enable)
> +{
> + unsigned int addr, value, reg;
> +
> + addr = MMSYS_OVL_MOUT_EN;
> +
> + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0)
> + value = DISP_OVL0_GO_BG;
> + else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_OVL0)
> + value = DISP_OVL0_2L_GO_BG;
> + else if (cur == DDP_COMPONENT_OVL0)
> + value = DISP_OVL0_GO_BLEND;
> + else if (cur == DDP_COMPONENT_OVL_2L0)
> + value = DISP_OVL0_2L_GO_BLEND;
> + else
> + value = 0;
> +
> + if (value) {
> + reg = readl_relaxed(config_regs + addr);
> +
> + if (enable)
> + reg |= value;
> + else
> + reg &= ~value;
> +
> + writel_relaxed(reg, config_regs + addr);
> + }
I think you could squash mtk_mmsys_ovl_mout_en() into
mtk_mmsys_ddp_mout_en() and directly read/write register in if-else
statement.
Regards,
Chun-Kuang.
> +}
> +
> +struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs = {
> + .mout_en = mtk_mmsys_ddp_mout_en,
> + .ovl_mout_en = mtk_mmsys_ovl_mout_en,
> + .sel_in = mtk_mmsys_ddp_sel_in,
> + .sout_sel = mtk_mmsys_ddp_sout_sel,
> +};
> diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> index 34728ed..2c72607 100644
> --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> @@ -50,6 +50,11 @@ struct mtk_mmsys {
> .funcs = &mt8183_mmsys_funcs,
> };
>
> +static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
> + .clk_driver = "clk-mt8192-mm",
> + .funcs = &mt8192_mmsys_funcs,
> +};
> +
> void mtk_mmsys_ddp_connect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next)
> @@ -157,6 +162,10 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> .compatible = "mediatek,mt8183-mmsys",
> .data = &mt8183_mmsys_driver_data,
> },
> + {
> + .compatible = "mediatek,mt8192-mmsys",
> + .data = &mt8192_mmsys_driver_data,
> + },
> { }
> };
>
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 19318d2..eeec96a 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -65,6 +65,7 @@ struct mtk_mmsys_conn_funcs {
>
> extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs;
> extern struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs;
> +extern struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs;
>
> void mtk_mmsys_ddp_connect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4, 00/10] soc: mediatek: mmsys: Use function call for setting the routing registers
2021-01-05 3:06 ` Yongqiang Niu
(?)
(?)
@ 2021-01-19 4:16 ` Hsin-Yi Wang
-1 siblings, 0 replies; 75+ messages in thread
From: Hsin-Yi Wang @ 2021-01-19 4:16 UTC (permalink / raw)
To: Yongqiang Niu
Cc: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger,
Mark Rutland, Devicetree List, David Airlie, lkml, dri-devel,
Project_Global_Chrome_Upstream_Group,
moderated list:ARM/Mediatek SoC support, Daniel Vetter,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
On Tue, Jan 5, 2021 at 3:06 AM Yongqiang Niu <yongqiang.niu@mediatek.com> wrote:
>
> The following series are intended to prepare the mtk-mmsys driver to
> allow different DDP (Data Display Path) function call per SoC.
>
> base 5.11-rc1
>
> change since v3:
> - move register operation into mmsys path select function
>
> Yongqiang Niu (10):
> soc: mediatek: mmsys: create mmsys folder
> soc: mediatek: mmsys: Create struct mtk_mmsys to store context data
> soc: mediatek: mmsys: move register operation into mmsys path select
> function
> soc: mediatek: mmsys: Use function call for setting the routing
> registers
> soc: mediatek: mmsys: add mt8183 function call for setting the routing
> registers
patch 01 ~ 05: I've tested on a mt8183 device, so
Tested-by: Hsin-Yi Wang <hsinyi@chromium.org>
> soc: mediatek: mmsys: add component OVL_2L2
> soc: mediatek: mmsys: add component POSTMASK
> soc: mediatek: mmsys: add component RDMA4
> soc: mediatek: mmsys: Use function call for setting mmsys ovl mout
> register
> soc: mediatek: mmsys: add mt8192 mmsys support
>
> drivers/soc/mediatek/Makefile | 2 +-
> drivers/soc/mediatek/mmsys/Makefile | 5 +
> drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 254 ++++++++++++++++++++
> drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 110 +++++++++
> drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 149 ++++++++++++
> drivers/soc/mediatek/mmsys/mtk-mmsys.c | 180 ++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 373 ------------------------------
> include/linux/soc/mediatek/mtk-mmsys.h | 25 ++
> 8 files changed, 724 insertions(+), 374 deletions(-)
> create mode 100644 drivers/soc/mediatek/mmsys/Makefile
> create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c
> create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c
> create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c
> create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c
> delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4, 00/10] soc: mediatek: mmsys: Use function call for setting the routing registers
@ 2021-01-19 4:16 ` Hsin-Yi Wang
0 siblings, 0 replies; 75+ messages in thread
From: Hsin-Yi Wang @ 2021-01-19 4:16 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, Devicetree List, Daniel Vetter, David Airlie, lkml,
dri-devel, Project_Global_Chrome_Upstream_Group,
Matthias Brugger, Rob Herring,
moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
On Tue, Jan 5, 2021 at 3:06 AM Yongqiang Niu <yongqiang.niu@mediatek.com> wrote:
>
> The following series are intended to prepare the mtk-mmsys driver to
> allow different DDP (Data Display Path) function call per SoC.
>
> base 5.11-rc1
>
> change since v3:
> - move register operation into mmsys path select function
>
> Yongqiang Niu (10):
> soc: mediatek: mmsys: create mmsys folder
> soc: mediatek: mmsys: Create struct mtk_mmsys to store context data
> soc: mediatek: mmsys: move register operation into mmsys path select
> function
> soc: mediatek: mmsys: Use function call for setting the routing
> registers
> soc: mediatek: mmsys: add mt8183 function call for setting the routing
> registers
patch 01 ~ 05: I've tested on a mt8183 device, so
Tested-by: Hsin-Yi Wang <hsinyi@chromium.org>
> soc: mediatek: mmsys: add component OVL_2L2
> soc: mediatek: mmsys: add component POSTMASK
> soc: mediatek: mmsys: add component RDMA4
> soc: mediatek: mmsys: Use function call for setting mmsys ovl mout
> register
> soc: mediatek: mmsys: add mt8192 mmsys support
>
> drivers/soc/mediatek/Makefile | 2 +-
> drivers/soc/mediatek/mmsys/Makefile | 5 +
> drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 254 ++++++++++++++++++++
> drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 110 +++++++++
> drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 149 ++++++++++++
> drivers/soc/mediatek/mmsys/mtk-mmsys.c | 180 ++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 373 ------------------------------
> include/linux/soc/mediatek/mtk-mmsys.h | 25 ++
> 8 files changed, 724 insertions(+), 374 deletions(-)
> create mode 100644 drivers/soc/mediatek/mmsys/Makefile
> create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c
> create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c
> create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c
> create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c
> delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4, 00/10] soc: mediatek: mmsys: Use function call for setting the routing registers
@ 2021-01-19 4:16 ` Hsin-Yi Wang
0 siblings, 0 replies; 75+ messages in thread
From: Hsin-Yi Wang @ 2021-01-19 4:16 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, Devicetree List, Daniel Vetter, David Airlie, lkml,
dri-devel, Project_Global_Chrome_Upstream_Group,
Matthias Brugger, Rob Herring,
moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
On Tue, Jan 5, 2021 at 3:06 AM Yongqiang Niu <yongqiang.niu@mediatek.com> wrote:
>
> The following series are intended to prepare the mtk-mmsys driver to
> allow different DDP (Data Display Path) function call per SoC.
>
> base 5.11-rc1
>
> change since v3:
> - move register operation into mmsys path select function
>
> Yongqiang Niu (10):
> soc: mediatek: mmsys: create mmsys folder
> soc: mediatek: mmsys: Create struct mtk_mmsys to store context data
> soc: mediatek: mmsys: move register operation into mmsys path select
> function
> soc: mediatek: mmsys: Use function call for setting the routing
> registers
> soc: mediatek: mmsys: add mt8183 function call for setting the routing
> registers
patch 01 ~ 05: I've tested on a mt8183 device, so
Tested-by: Hsin-Yi Wang <hsinyi@chromium.org>
> soc: mediatek: mmsys: add component OVL_2L2
> soc: mediatek: mmsys: add component POSTMASK
> soc: mediatek: mmsys: add component RDMA4
> soc: mediatek: mmsys: Use function call for setting mmsys ovl mout
> register
> soc: mediatek: mmsys: add mt8192 mmsys support
>
> drivers/soc/mediatek/Makefile | 2 +-
> drivers/soc/mediatek/mmsys/Makefile | 5 +
> drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 254 ++++++++++++++++++++
> drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 110 +++++++++
> drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 149 ++++++++++++
> drivers/soc/mediatek/mmsys/mtk-mmsys.c | 180 ++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 373 ------------------------------
> include/linux/soc/mediatek/mtk-mmsys.h | 25 ++
> 8 files changed, 724 insertions(+), 374 deletions(-)
> create mode 100644 drivers/soc/mediatek/mmsys/Makefile
> create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c
> create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c
> create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c
> create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c
> delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4, 00/10] soc: mediatek: mmsys: Use function call for setting the routing registers
@ 2021-01-19 4:16 ` Hsin-Yi Wang
0 siblings, 0 replies; 75+ messages in thread
From: Hsin-Yi Wang @ 2021-01-19 4:16 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, Devicetree List, David Airlie, lkml, dri-devel,
Project_Global_Chrome_Upstream_Group, Matthias Brugger,
Rob Herring, moderated list:ARM/Mediatek SoC support,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
On Tue, Jan 5, 2021 at 3:06 AM Yongqiang Niu <yongqiang.niu@mediatek.com> wrote:
>
> The following series are intended to prepare the mtk-mmsys driver to
> allow different DDP (Data Display Path) function call per SoC.
>
> base 5.11-rc1
>
> change since v3:
> - move register operation into mmsys path select function
>
> Yongqiang Niu (10):
> soc: mediatek: mmsys: create mmsys folder
> soc: mediatek: mmsys: Create struct mtk_mmsys to store context data
> soc: mediatek: mmsys: move register operation into mmsys path select
> function
> soc: mediatek: mmsys: Use function call for setting the routing
> registers
> soc: mediatek: mmsys: add mt8183 function call for setting the routing
> registers
patch 01 ~ 05: I've tested on a mt8183 device, so
Tested-by: Hsin-Yi Wang <hsinyi@chromium.org>
> soc: mediatek: mmsys: add component OVL_2L2
> soc: mediatek: mmsys: add component POSTMASK
> soc: mediatek: mmsys: add component RDMA4
> soc: mediatek: mmsys: Use function call for setting mmsys ovl mout
> register
> soc: mediatek: mmsys: add mt8192 mmsys support
>
> drivers/soc/mediatek/Makefile | 2 +-
> drivers/soc/mediatek/mmsys/Makefile | 5 +
> drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 254 ++++++++++++++++++++
> drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 110 +++++++++
> drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 149 ++++++++++++
> drivers/soc/mediatek/mmsys/mtk-mmsys.c | 180 ++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 373 ------------------------------
> include/linux/soc/mediatek/mtk-mmsys.h | 25 ++
> 8 files changed, 724 insertions(+), 374 deletions(-)
> create mode 100644 drivers/soc/mediatek/mmsys/Makefile
> create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c
> create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c
> create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c
> create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c
> delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4, 03/10] soc: mediatek: mmsys: move register operation into mmsys path select function
2021-01-05 3:06 ` Yongqiang Niu
(?)
(?)
@ 2021-01-20 19:38 ` Matthias Brugger
-1 siblings, 0 replies; 75+ messages in thread
From: Matthias Brugger @ 2021-01-20 19:38 UTC (permalink / raw)
To: Yongqiang Niu
Cc: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger,
Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, linux-mediatek,
Daniel Vetter, linux-arm-kernel
On Tue, Jan 05, 2021 at 11:06:26AM +0800, Yongqiang Niu wrote:
> move register operation into mmsys path select function
Why do you want to do that. It seems the register access pattern is the
same for all SoCs so far supported, so I don't see the need to duplicate
the code in every SoC.
Regards,
Matthias
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/soc/mediatek/mmsys/mtk-mmsys.c | 140 +++++++++++++++++----------------
> 1 file changed, 71 insertions(+), 69 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> index 6c03282..64c8030 100644
> --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> @@ -106,141 +106,161 @@ struct mtk_mmsys {
> .clk_driver = "clk-mt8183-mm",
> };
>
> -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
> - enum mtk_ddp_comp_id next,
> - unsigned int *addr)
> +static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + bool enable)
> {
> - unsigned int value;
> + unsigned int addr, value, reg;
>
> if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> value = OVL0_MOUT_EN_COLOR0;
> } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
> - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> value = OVL_MOUT_EN_RDMA;
> } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> value = OD_MOUT_EN_RDMA0;
> } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> value = UFOE_MOUT_EN_DSI0;
> } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> value = OVL1_MOUT_EN_COLOR1;
> } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> value = GAMMA_MOUT_EN_RDMA1;
> } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> value = OD1_MOUT_EN_RDMA1;
> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> value = RDMA0_SOUT_DPI0;
> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> value = RDMA0_SOUT_DPI1;
> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> value = RDMA0_SOUT_DSI1;
> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> value = RDMA0_SOUT_DSI2;
> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> value = RDMA0_SOUT_DSI3;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> value = RDMA1_SOUT_DSI1;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> value = RDMA1_SOUT_DSI2;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> value = RDMA1_SOUT_DSI3;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> value = RDMA1_SOUT_DPI0;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> value = RDMA1_SOUT_DPI1;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> value = RDMA2_SOUT_DPI0;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> value = RDMA2_SOUT_DPI1;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> value = RDMA2_SOUT_DSI1;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> value = RDMA2_SOUT_DSI2;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> value = RDMA2_SOUT_DSI3;
> } else {
> value = 0;
> }
>
> - return value;
> + if (value) {
> + reg = readl_relaxed(config_regs + addr);
> +
> + if (enable)
> + reg |= value;
> + else
> + reg &= ~value;
> +
> + writel_relaxed(reg, config_regs + addr);
> + }
> }
>
> -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
> - enum mtk_ddp_comp_id next,
> - unsigned int *addr)
> +static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + bool enable)
> {
> - unsigned int value;
> + unsigned int addr, value, reg;
>
> if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> + addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> value = COLOR0_SEL_IN_OVL0;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + addr = DISP_REG_CONFIG_DPI_SEL_IN;
> value = DPI0_SEL_IN_RDMA1;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + addr = DISP_REG_CONFIG_DPI_SEL_IN;
> value = DPI1_SEL_IN_RDMA1;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> value = DSI0_SEL_IN_RDMA1;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> value = DSI1_SEL_IN_RDMA1;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> value = DSI2_SEL_IN_RDMA1;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> value = DSI3_SEL_IN_RDMA1;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + addr = DISP_REG_CONFIG_DPI_SEL_IN;
> value = DPI0_SEL_IN_RDMA2;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + addr = DISP_REG_CONFIG_DPI_SEL_IN;
> value = DPI1_SEL_IN_RDMA2;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> value = DSI0_SEL_IN_RDMA2;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> value = DSI1_SEL_IN_RDMA2;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> value = DSI2_SEL_IN_RDMA2;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> value = DSI3_SEL_IN_RDMA2;
> } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> + addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> value = COLOR1_SEL_IN_OVL1;
> } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DSI_SEL;
> + addr = DISP_REG_CONFIG_DSI_SEL;
> value = DSI_SEL_IN_BLS;
> } else {
> value = 0;
> }
>
> - return value;
> + if (value) {
> + reg = readl_relaxed(config_regs + addr);
> +
> + if (enable)
> + reg |= value;
> + else
> + reg &= ~value;
> +
> + writel_relaxed(reg, config_regs + addr);
> + }
> }
>
> static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
> @@ -265,21 +285,12 @@ void mtk_mmsys_ddp_connect(struct device *dev,
> enum mtk_ddp_comp_id next)
> {
> struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> - unsigned int addr, value, reg;
>
> - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> - if (value) {
> - reg = readl_relaxed(mmsys->regs + addr) | value;
> - writel_relaxed(reg, mmsys->regs + addr);
> - }
> + mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, true);
>
> mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next);
>
> - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> - if (value) {
> - reg = readl_relaxed(mmsys->regs + addr) | value;
> - writel_relaxed(reg, mmsys->regs + addr);
> - }
> + mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, true);
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
>
> @@ -288,19 +299,10 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> enum mtk_ddp_comp_id next)
> {
> struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> - unsigned int addr, value, reg;
>
> - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> - if (value) {
> - reg = readl_relaxed(mmsys->regs + addr) & ~value;
> - writel_relaxed(reg, mmsys->regs + addr);
> - }
> + mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, false);
>
> - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> - if (value) {
> - reg = readl_relaxed(mmsys->regs + addr) & ~value;
> - writel_relaxed(reg, mmsys->regs + addr);
> - }
> + mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, false);
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4, 03/10] soc: mediatek: mmsys: move register operation into mmsys path select function
@ 2021-01-20 19:38 ` Matthias Brugger
0 siblings, 0 replies; 75+ messages in thread
From: Matthias Brugger @ 2021-01-20 19:38 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, devicetree, Daniel Vetter, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
Matthias Brugger, Rob Herring, linux-mediatek, Philipp Zabel,
CK Hu, linux-arm-kernel
On Tue, Jan 05, 2021 at 11:06:26AM +0800, Yongqiang Niu wrote:
> move register operation into mmsys path select function
Why do you want to do that. It seems the register access pattern is the
same for all SoCs so far supported, so I don't see the need to duplicate
the code in every SoC.
Regards,
Matthias
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/soc/mediatek/mmsys/mtk-mmsys.c | 140 +++++++++++++++++----------------
> 1 file changed, 71 insertions(+), 69 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> index 6c03282..64c8030 100644
> --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> @@ -106,141 +106,161 @@ struct mtk_mmsys {
> .clk_driver = "clk-mt8183-mm",
> };
>
> -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
> - enum mtk_ddp_comp_id next,
> - unsigned int *addr)
> +static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + bool enable)
> {
> - unsigned int value;
> + unsigned int addr, value, reg;
>
> if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> value = OVL0_MOUT_EN_COLOR0;
> } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
> - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> value = OVL_MOUT_EN_RDMA;
> } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> value = OD_MOUT_EN_RDMA0;
> } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> value = UFOE_MOUT_EN_DSI0;
> } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> value = OVL1_MOUT_EN_COLOR1;
> } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> value = GAMMA_MOUT_EN_RDMA1;
> } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> value = OD1_MOUT_EN_RDMA1;
> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> value = RDMA0_SOUT_DPI0;
> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> value = RDMA0_SOUT_DPI1;
> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> value = RDMA0_SOUT_DSI1;
> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> value = RDMA0_SOUT_DSI2;
> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> value = RDMA0_SOUT_DSI3;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> value = RDMA1_SOUT_DSI1;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> value = RDMA1_SOUT_DSI2;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> value = RDMA1_SOUT_DSI3;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> value = RDMA1_SOUT_DPI0;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> value = RDMA1_SOUT_DPI1;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> value = RDMA2_SOUT_DPI0;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> value = RDMA2_SOUT_DPI1;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> value = RDMA2_SOUT_DSI1;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> value = RDMA2_SOUT_DSI2;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> value = RDMA2_SOUT_DSI3;
> } else {
> value = 0;
> }
>
> - return value;
> + if (value) {
> + reg = readl_relaxed(config_regs + addr);
> +
> + if (enable)
> + reg |= value;
> + else
> + reg &= ~value;
> +
> + writel_relaxed(reg, config_regs + addr);
> + }
> }
>
> -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
> - enum mtk_ddp_comp_id next,
> - unsigned int *addr)
> +static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + bool enable)
> {
> - unsigned int value;
> + unsigned int addr, value, reg;
>
> if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> + addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> value = COLOR0_SEL_IN_OVL0;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + addr = DISP_REG_CONFIG_DPI_SEL_IN;
> value = DPI0_SEL_IN_RDMA1;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + addr = DISP_REG_CONFIG_DPI_SEL_IN;
> value = DPI1_SEL_IN_RDMA1;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> value = DSI0_SEL_IN_RDMA1;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> value = DSI1_SEL_IN_RDMA1;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> value = DSI2_SEL_IN_RDMA1;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> value = DSI3_SEL_IN_RDMA1;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + addr = DISP_REG_CONFIG_DPI_SEL_IN;
> value = DPI0_SEL_IN_RDMA2;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + addr = DISP_REG_CONFIG_DPI_SEL_IN;
> value = DPI1_SEL_IN_RDMA2;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> value = DSI0_SEL_IN_RDMA2;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> value = DSI1_SEL_IN_RDMA2;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> value = DSI2_SEL_IN_RDMA2;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> value = DSI3_SEL_IN_RDMA2;
> } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> + addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> value = COLOR1_SEL_IN_OVL1;
> } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DSI_SEL;
> + addr = DISP_REG_CONFIG_DSI_SEL;
> value = DSI_SEL_IN_BLS;
> } else {
> value = 0;
> }
>
> - return value;
> + if (value) {
> + reg = readl_relaxed(config_regs + addr);
> +
> + if (enable)
> + reg |= value;
> + else
> + reg &= ~value;
> +
> + writel_relaxed(reg, config_regs + addr);
> + }
> }
>
> static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
> @@ -265,21 +285,12 @@ void mtk_mmsys_ddp_connect(struct device *dev,
> enum mtk_ddp_comp_id next)
> {
> struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> - unsigned int addr, value, reg;
>
> - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> - if (value) {
> - reg = readl_relaxed(mmsys->regs + addr) | value;
> - writel_relaxed(reg, mmsys->regs + addr);
> - }
> + mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, true);
>
> mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next);
>
> - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> - if (value) {
> - reg = readl_relaxed(mmsys->regs + addr) | value;
> - writel_relaxed(reg, mmsys->regs + addr);
> - }
> + mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, true);
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
>
> @@ -288,19 +299,10 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> enum mtk_ddp_comp_id next)
> {
> struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> - unsigned int addr, value, reg;
>
> - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> - if (value) {
> - reg = readl_relaxed(mmsys->regs + addr) & ~value;
> - writel_relaxed(reg, mmsys->regs + addr);
> - }
> + mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, false);
>
> - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> - if (value) {
> - reg = readl_relaxed(mmsys->regs + addr) & ~value;
> - writel_relaxed(reg, mmsys->regs + addr);
> - }
> + mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, false);
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
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Linux-mediatek@lists.infradead.org
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^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4, 03/10] soc: mediatek: mmsys: move register operation into mmsys path select function
@ 2021-01-20 19:38 ` Matthias Brugger
0 siblings, 0 replies; 75+ messages in thread
From: Matthias Brugger @ 2021-01-20 19:38 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, devicetree, Daniel Vetter, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
Matthias Brugger, Rob Herring, linux-mediatek, Philipp Zabel,
CK Hu, linux-arm-kernel
On Tue, Jan 05, 2021 at 11:06:26AM +0800, Yongqiang Niu wrote:
> move register operation into mmsys path select function
Why do you want to do that. It seems the register access pattern is the
same for all SoCs so far supported, so I don't see the need to duplicate
the code in every SoC.
Regards,
Matthias
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/soc/mediatek/mmsys/mtk-mmsys.c | 140 +++++++++++++++++----------------
> 1 file changed, 71 insertions(+), 69 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> index 6c03282..64c8030 100644
> --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> @@ -106,141 +106,161 @@ struct mtk_mmsys {
> .clk_driver = "clk-mt8183-mm",
> };
>
> -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
> - enum mtk_ddp_comp_id next,
> - unsigned int *addr)
> +static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + bool enable)
> {
> - unsigned int value;
> + unsigned int addr, value, reg;
>
> if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> value = OVL0_MOUT_EN_COLOR0;
> } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
> - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> value = OVL_MOUT_EN_RDMA;
> } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> value = OD_MOUT_EN_RDMA0;
> } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> value = UFOE_MOUT_EN_DSI0;
> } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> value = OVL1_MOUT_EN_COLOR1;
> } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> value = GAMMA_MOUT_EN_RDMA1;
> } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> value = OD1_MOUT_EN_RDMA1;
> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> value = RDMA0_SOUT_DPI0;
> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> value = RDMA0_SOUT_DPI1;
> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> value = RDMA0_SOUT_DSI1;
> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> value = RDMA0_SOUT_DSI2;
> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> value = RDMA0_SOUT_DSI3;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> value = RDMA1_SOUT_DSI1;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> value = RDMA1_SOUT_DSI2;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> value = RDMA1_SOUT_DSI3;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> value = RDMA1_SOUT_DPI0;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> value = RDMA1_SOUT_DPI1;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> value = RDMA2_SOUT_DPI0;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> value = RDMA2_SOUT_DPI1;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> value = RDMA2_SOUT_DSI1;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> value = RDMA2_SOUT_DSI2;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> value = RDMA2_SOUT_DSI3;
> } else {
> value = 0;
> }
>
> - return value;
> + if (value) {
> + reg = readl_relaxed(config_regs + addr);
> +
> + if (enable)
> + reg |= value;
> + else
> + reg &= ~value;
> +
> + writel_relaxed(reg, config_regs + addr);
> + }
> }
>
> -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
> - enum mtk_ddp_comp_id next,
> - unsigned int *addr)
> +static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + bool enable)
> {
> - unsigned int value;
> + unsigned int addr, value, reg;
>
> if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> + addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> value = COLOR0_SEL_IN_OVL0;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + addr = DISP_REG_CONFIG_DPI_SEL_IN;
> value = DPI0_SEL_IN_RDMA1;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + addr = DISP_REG_CONFIG_DPI_SEL_IN;
> value = DPI1_SEL_IN_RDMA1;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> value = DSI0_SEL_IN_RDMA1;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> value = DSI1_SEL_IN_RDMA1;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> value = DSI2_SEL_IN_RDMA1;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> value = DSI3_SEL_IN_RDMA1;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + addr = DISP_REG_CONFIG_DPI_SEL_IN;
> value = DPI0_SEL_IN_RDMA2;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + addr = DISP_REG_CONFIG_DPI_SEL_IN;
> value = DPI1_SEL_IN_RDMA2;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> value = DSI0_SEL_IN_RDMA2;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> value = DSI1_SEL_IN_RDMA2;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> value = DSI2_SEL_IN_RDMA2;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> value = DSI3_SEL_IN_RDMA2;
> } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> + addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> value = COLOR1_SEL_IN_OVL1;
> } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DSI_SEL;
> + addr = DISP_REG_CONFIG_DSI_SEL;
> value = DSI_SEL_IN_BLS;
> } else {
> value = 0;
> }
>
> - return value;
> + if (value) {
> + reg = readl_relaxed(config_regs + addr);
> +
> + if (enable)
> + reg |= value;
> + else
> + reg &= ~value;
> +
> + writel_relaxed(reg, config_regs + addr);
> + }
> }
>
> static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
> @@ -265,21 +285,12 @@ void mtk_mmsys_ddp_connect(struct device *dev,
> enum mtk_ddp_comp_id next)
> {
> struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> - unsigned int addr, value, reg;
>
> - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> - if (value) {
> - reg = readl_relaxed(mmsys->regs + addr) | value;
> - writel_relaxed(reg, mmsys->regs + addr);
> - }
> + mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, true);
>
> mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next);
>
> - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> - if (value) {
> - reg = readl_relaxed(mmsys->regs + addr) | value;
> - writel_relaxed(reg, mmsys->regs + addr);
> - }
> + mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, true);
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
>
> @@ -288,19 +299,10 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> enum mtk_ddp_comp_id next)
> {
> struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> - unsigned int addr, value, reg;
>
> - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> - if (value) {
> - reg = readl_relaxed(mmsys->regs + addr) & ~value;
> - writel_relaxed(reg, mmsys->regs + addr);
> - }
> + mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, false);
>
> - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> - if (value) {
> - reg = readl_relaxed(mmsys->regs + addr) & ~value;
> - writel_relaxed(reg, mmsys->regs + addr);
> - }
> + mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, false);
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
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^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4, 03/10] soc: mediatek: mmsys: move register operation into mmsys path select function
@ 2021-01-20 19:38 ` Matthias Brugger
0 siblings, 0 replies; 75+ messages in thread
From: Matthias Brugger @ 2021-01-20 19:38 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Matthias Brugger,
Rob Herring, linux-mediatek, linux-arm-kernel
On Tue, Jan 05, 2021 at 11:06:26AM +0800, Yongqiang Niu wrote:
> move register operation into mmsys path select function
Why do you want to do that. It seems the register access pattern is the
same for all SoCs so far supported, so I don't see the need to duplicate
the code in every SoC.
Regards,
Matthias
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/soc/mediatek/mmsys/mtk-mmsys.c | 140 +++++++++++++++++----------------
> 1 file changed, 71 insertions(+), 69 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> index 6c03282..64c8030 100644
> --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> @@ -106,141 +106,161 @@ struct mtk_mmsys {
> .clk_driver = "clk-mt8183-mm",
> };
>
> -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
> - enum mtk_ddp_comp_id next,
> - unsigned int *addr)
> +static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + bool enable)
> {
> - unsigned int value;
> + unsigned int addr, value, reg;
>
> if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> value = OVL0_MOUT_EN_COLOR0;
> } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
> - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> value = OVL_MOUT_EN_RDMA;
> } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> value = OD_MOUT_EN_RDMA0;
> } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> value = UFOE_MOUT_EN_DSI0;
> } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> value = OVL1_MOUT_EN_COLOR1;
> } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> value = GAMMA_MOUT_EN_RDMA1;
> } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> value = OD1_MOUT_EN_RDMA1;
> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> value = RDMA0_SOUT_DPI0;
> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> value = RDMA0_SOUT_DPI1;
> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> value = RDMA0_SOUT_DSI1;
> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> value = RDMA0_SOUT_DSI2;
> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> value = RDMA0_SOUT_DSI3;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> value = RDMA1_SOUT_DSI1;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> value = RDMA1_SOUT_DSI2;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> value = RDMA1_SOUT_DSI3;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> value = RDMA1_SOUT_DPI0;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> value = RDMA1_SOUT_DPI1;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> value = RDMA2_SOUT_DPI0;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> value = RDMA2_SOUT_DPI1;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> value = RDMA2_SOUT_DSI1;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> value = RDMA2_SOUT_DSI2;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> value = RDMA2_SOUT_DSI3;
> } else {
> value = 0;
> }
>
> - return value;
> + if (value) {
> + reg = readl_relaxed(config_regs + addr);
> +
> + if (enable)
> + reg |= value;
> + else
> + reg &= ~value;
> +
> + writel_relaxed(reg, config_regs + addr);
> + }
> }
>
> -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
> - enum mtk_ddp_comp_id next,
> - unsigned int *addr)
> +static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + bool enable)
> {
> - unsigned int value;
> + unsigned int addr, value, reg;
>
> if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> + addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> value = COLOR0_SEL_IN_OVL0;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + addr = DISP_REG_CONFIG_DPI_SEL_IN;
> value = DPI0_SEL_IN_RDMA1;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + addr = DISP_REG_CONFIG_DPI_SEL_IN;
> value = DPI1_SEL_IN_RDMA1;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> value = DSI0_SEL_IN_RDMA1;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> value = DSI1_SEL_IN_RDMA1;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> value = DSI2_SEL_IN_RDMA1;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> value = DSI3_SEL_IN_RDMA1;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + addr = DISP_REG_CONFIG_DPI_SEL_IN;
> value = DPI0_SEL_IN_RDMA2;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + addr = DISP_REG_CONFIG_DPI_SEL_IN;
> value = DPI1_SEL_IN_RDMA2;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> value = DSI0_SEL_IN_RDMA2;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> value = DSI1_SEL_IN_RDMA2;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> value = DSI2_SEL_IN_RDMA2;
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> value = DSI3_SEL_IN_RDMA2;
> } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> + addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> value = COLOR1_SEL_IN_OVL1;
> } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DSI_SEL;
> + addr = DISP_REG_CONFIG_DSI_SEL;
> value = DSI_SEL_IN_BLS;
> } else {
> value = 0;
> }
>
> - return value;
> + if (value) {
> + reg = readl_relaxed(config_regs + addr);
> +
> + if (enable)
> + reg |= value;
> + else
> + reg &= ~value;
> +
> + writel_relaxed(reg, config_regs + addr);
> + }
> }
>
> static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
> @@ -265,21 +285,12 @@ void mtk_mmsys_ddp_connect(struct device *dev,
> enum mtk_ddp_comp_id next)
> {
> struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> - unsigned int addr, value, reg;
>
> - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> - if (value) {
> - reg = readl_relaxed(mmsys->regs + addr) | value;
> - writel_relaxed(reg, mmsys->regs + addr);
> - }
> + mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, true);
>
> mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next);
>
> - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> - if (value) {
> - reg = readl_relaxed(mmsys->regs + addr) | value;
> - writel_relaxed(reg, mmsys->regs + addr);
> - }
> + mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, true);
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
>
> @@ -288,19 +299,10 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> enum mtk_ddp_comp_id next)
> {
> struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> - unsigned int addr, value, reg;
>
> - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> - if (value) {
> - reg = readl_relaxed(mmsys->regs + addr) & ~value;
> - writel_relaxed(reg, mmsys->regs + addr);
> - }
> + mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, false);
>
> - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> - if (value) {
> - reg = readl_relaxed(mmsys->regs + addr) & ~value;
> - writel_relaxed(reg, mmsys->regs + addr);
> - }
> + mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, false);
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
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^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4, 03/10] soc: mediatek: mmsys: move register operation into mmsys path select function
2021-01-20 19:38 ` Matthias Brugger
(?)
(?)
@ 2021-01-21 0:56 ` Yongqiang Niu
-1 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-21 0:56 UTC (permalink / raw)
To: Matthias Brugger
Cc: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger,
Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, linux-mediatek,
Daniel Vetter, linux-arm-kernel
On Wed, 2021-01-20 at 20:38 +0100, Matthias Brugger wrote:
> On Tue, Jan 05, 2021 at 11:06:26AM +0800, Yongqiang Niu wrote:
> > move register operation into mmsys path select function
>
> Why do you want to do that. It seems the register access pattern is the
> same for all SoCs so far supported, so I don't see the need to duplicate
> the code in every SoC.
>
> Regards,
> Matthias
mt2701 and mt8173 ovl mout en already different.
mt2701 ovl mout en register offset is 0x30
mt8173 olv mout en register offset is 0x40
only the use case is different;
mt2701 ovl->color0
mt8173 ovl->rmda0
there make different define for this different.
#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
for the future mt8183, ovl mout en register offset will change to
0xf00
this is only one different sample, there will be more and more
different, so we add this patch for different soc
>
> >
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > ---
> > drivers/soc/mediatek/mmsys/mtk-mmsys.c | 140 +++++++++++++++++----------------
> > 1 file changed, 71 insertions(+), 69 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> > index 6c03282..64c8030 100644
> > --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> > @@ -106,141 +106,161 @@ struct mtk_mmsys {
> > .clk_driver = "clk-mt8183-mm",
> > };
> >
> > -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
> > - enum mtk_ddp_comp_id next,
> > - unsigned int *addr)
> > +static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
> > + enum mtk_ddp_comp_id cur,
> > + enum mtk_ddp_comp_id next,
> > + bool enable)
> > {
> > - unsigned int value;
> > + unsigned int addr, value, reg;
> >
> > if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> > - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> > value = OVL0_MOUT_EN_COLOR0;
> > } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
> > - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> > value = OVL_MOUT_EN_RDMA;
> > } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
> > - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > value = OD_MOUT_EN_RDMA0;
> > } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
> > - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> > value = UFOE_MOUT_EN_DSI0;
> > } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> > - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> > value = OVL1_MOUT_EN_COLOR1;
> > } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> > - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> > value = GAMMA_MOUT_EN_RDMA1;
> > } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> > - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > value = OD1_MOUT_EN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > value = RDMA0_SOUT_DPI0;
> > } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > value = RDMA0_SOUT_DPI1;
> > } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > value = RDMA0_SOUT_DSI1;
> > } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > value = RDMA0_SOUT_DSI2;
> > } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > value = RDMA0_SOUT_DSI3;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > value = RDMA1_SOUT_DSI1;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > value = RDMA1_SOUT_DSI2;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > value = RDMA1_SOUT_DSI3;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > value = RDMA1_SOUT_DPI0;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > value = RDMA1_SOUT_DPI1;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > value = RDMA2_SOUT_DPI0;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > value = RDMA2_SOUT_DPI1;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > value = RDMA2_SOUT_DSI1;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > value = RDMA2_SOUT_DSI2;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > value = RDMA2_SOUT_DSI3;
> > } else {
> > value = 0;
> > }
> >
> > - return value;
> > + if (value) {
> > + reg = readl_relaxed(config_regs + addr);
> > +
> > + if (enable)
> > + reg |= value;
> > + else
> > + reg &= ~value;
> > +
> > + writel_relaxed(reg, config_regs + addr);
> > + }
> > }
> >
> > -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
> > - enum mtk_ddp_comp_id next,
> > - unsigned int *addr)
> > +static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
> > + enum mtk_ddp_comp_id cur,
> > + enum mtk_ddp_comp_id next,
> > + bool enable)
> > {
> > - unsigned int value;
> > + unsigned int addr, value, reg;
> >
> > if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> > - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> > + addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> > value = COLOR0_SEL_IN_OVL0;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> > - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > + addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > value = DPI0_SEL_IN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> > - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > + addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > value = DPI1_SEL_IN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
> > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > value = DSI0_SEL_IN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > value = DSI1_SEL_IN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > value = DSI2_SEL_IN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > value = DSI3_SEL_IN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> > - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > + addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > value = DPI0_SEL_IN_RDMA2;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> > - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > + addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > value = DPI1_SEL_IN_RDMA2;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
> > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > value = DSI0_SEL_IN_RDMA2;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > value = DSI1_SEL_IN_RDMA2;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > value = DSI2_SEL_IN_RDMA2;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > value = DSI3_SEL_IN_RDMA2;
> > } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> > - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> > + addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> > value = COLOR1_SEL_IN_OVL1;
> > } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> > - *addr = DISP_REG_CONFIG_DSI_SEL;
> > + addr = DISP_REG_CONFIG_DSI_SEL;
> > value = DSI_SEL_IN_BLS;
> > } else {
> > value = 0;
> > }
> >
> > - return value;
> > + if (value) {
> > + reg = readl_relaxed(config_regs + addr);
> > +
> > + if (enable)
> > + reg |= value;
> > + else
> > + reg &= ~value;
> > +
> > + writel_relaxed(reg, config_regs + addr);
> > + }
> > }
> >
> > static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
> > @@ -265,21 +285,12 @@ void mtk_mmsys_ddp_connect(struct device *dev,
> > enum mtk_ddp_comp_id next)
> > {
> > struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> > - unsigned int addr, value, reg;
> >
> > - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> > - if (value) {
> > - reg = readl_relaxed(mmsys->regs + addr) | value;
> > - writel_relaxed(reg, mmsys->regs + addr);
> > - }
> > + mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, true);
> >
> > mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next);
> >
> > - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> > - if (value) {
> > - reg = readl_relaxed(mmsys->regs + addr) | value;
> > - writel_relaxed(reg, mmsys->regs + addr);
> > - }
> > + mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, true);
> > }
> > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
> >
> > @@ -288,19 +299,10 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> > enum mtk_ddp_comp_id next)
> > {
> > struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> > - unsigned int addr, value, reg;
> >
> > - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> > - if (value) {
> > - reg = readl_relaxed(mmsys->regs + addr) & ~value;
> > - writel_relaxed(reg, mmsys->regs + addr);
> > - }
> > + mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, false);
> >
> > - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> > - if (value) {
> > - reg = readl_relaxed(mmsys->regs + addr) & ~value;
> > - writel_relaxed(reg, mmsys->regs + addr);
> > - }
> > + mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, false);
> > }
> > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
> >
> > --
> > 1.8.1.1.dirty
> > _______________________________________________
> > Linux-mediatek mailing list
> > Linux-mediatek@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4, 03/10] soc: mediatek: mmsys: move register operation into mmsys path select function
@ 2021-01-21 0:56 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-21 0:56 UTC (permalink / raw)
To: Matthias Brugger
Cc: Mark Rutland, devicetree, Daniel Vetter, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
Matthias Brugger, Rob Herring, linux-mediatek, Philipp Zabel,
CK Hu, linux-arm-kernel
On Wed, 2021-01-20 at 20:38 +0100, Matthias Brugger wrote:
> On Tue, Jan 05, 2021 at 11:06:26AM +0800, Yongqiang Niu wrote:
> > move register operation into mmsys path select function
>
> Why do you want to do that. It seems the register access pattern is the
> same for all SoCs so far supported, so I don't see the need to duplicate
> the code in every SoC.
>
> Regards,
> Matthias
mt2701 and mt8173 ovl mout en already different.
mt2701 ovl mout en register offset is 0x30
mt8173 olv mout en register offset is 0x40
only the use case is different;
mt2701 ovl->color0
mt8173 ovl->rmda0
there make different define for this different.
#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
for the future mt8183, ovl mout en register offset will change to
0xf00
this is only one different sample, there will be more and more
different, so we add this patch for different soc
>
> >
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > ---
> > drivers/soc/mediatek/mmsys/mtk-mmsys.c | 140 +++++++++++++++++----------------
> > 1 file changed, 71 insertions(+), 69 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> > index 6c03282..64c8030 100644
> > --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> > @@ -106,141 +106,161 @@ struct mtk_mmsys {
> > .clk_driver = "clk-mt8183-mm",
> > };
> >
> > -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
> > - enum mtk_ddp_comp_id next,
> > - unsigned int *addr)
> > +static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
> > + enum mtk_ddp_comp_id cur,
> > + enum mtk_ddp_comp_id next,
> > + bool enable)
> > {
> > - unsigned int value;
> > + unsigned int addr, value, reg;
> >
> > if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> > - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> > value = OVL0_MOUT_EN_COLOR0;
> > } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
> > - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> > value = OVL_MOUT_EN_RDMA;
> > } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
> > - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > value = OD_MOUT_EN_RDMA0;
> > } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
> > - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> > value = UFOE_MOUT_EN_DSI0;
> > } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> > - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> > value = OVL1_MOUT_EN_COLOR1;
> > } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> > - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> > value = GAMMA_MOUT_EN_RDMA1;
> > } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> > - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > value = OD1_MOUT_EN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > value = RDMA0_SOUT_DPI0;
> > } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > value = RDMA0_SOUT_DPI1;
> > } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > value = RDMA0_SOUT_DSI1;
> > } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > value = RDMA0_SOUT_DSI2;
> > } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > value = RDMA0_SOUT_DSI3;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > value = RDMA1_SOUT_DSI1;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > value = RDMA1_SOUT_DSI2;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > value = RDMA1_SOUT_DSI3;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > value = RDMA1_SOUT_DPI0;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > value = RDMA1_SOUT_DPI1;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > value = RDMA2_SOUT_DPI0;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > value = RDMA2_SOUT_DPI1;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > value = RDMA2_SOUT_DSI1;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > value = RDMA2_SOUT_DSI2;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > value = RDMA2_SOUT_DSI3;
> > } else {
> > value = 0;
> > }
> >
> > - return value;
> > + if (value) {
> > + reg = readl_relaxed(config_regs + addr);
> > +
> > + if (enable)
> > + reg |= value;
> > + else
> > + reg &= ~value;
> > +
> > + writel_relaxed(reg, config_regs + addr);
> > + }
> > }
> >
> > -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
> > - enum mtk_ddp_comp_id next,
> > - unsigned int *addr)
> > +static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
> > + enum mtk_ddp_comp_id cur,
> > + enum mtk_ddp_comp_id next,
> > + bool enable)
> > {
> > - unsigned int value;
> > + unsigned int addr, value, reg;
> >
> > if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> > - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> > + addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> > value = COLOR0_SEL_IN_OVL0;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> > - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > + addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > value = DPI0_SEL_IN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> > - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > + addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > value = DPI1_SEL_IN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
> > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > value = DSI0_SEL_IN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > value = DSI1_SEL_IN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > value = DSI2_SEL_IN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > value = DSI3_SEL_IN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> > - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > + addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > value = DPI0_SEL_IN_RDMA2;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> > - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > + addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > value = DPI1_SEL_IN_RDMA2;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
> > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > value = DSI0_SEL_IN_RDMA2;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > value = DSI1_SEL_IN_RDMA2;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > value = DSI2_SEL_IN_RDMA2;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > value = DSI3_SEL_IN_RDMA2;
> > } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> > - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> > + addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> > value = COLOR1_SEL_IN_OVL1;
> > } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> > - *addr = DISP_REG_CONFIG_DSI_SEL;
> > + addr = DISP_REG_CONFIG_DSI_SEL;
> > value = DSI_SEL_IN_BLS;
> > } else {
> > value = 0;
> > }
> >
> > - return value;
> > + if (value) {
> > + reg = readl_relaxed(config_regs + addr);
> > +
> > + if (enable)
> > + reg |= value;
> > + else
> > + reg &= ~value;
> > +
> > + writel_relaxed(reg, config_regs + addr);
> > + }
> > }
> >
> > static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
> > @@ -265,21 +285,12 @@ void mtk_mmsys_ddp_connect(struct device *dev,
> > enum mtk_ddp_comp_id next)
> > {
> > struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> > - unsigned int addr, value, reg;
> >
> > - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> > - if (value) {
> > - reg = readl_relaxed(mmsys->regs + addr) | value;
> > - writel_relaxed(reg, mmsys->regs + addr);
> > - }
> > + mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, true);
> >
> > mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next);
> >
> > - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> > - if (value) {
> > - reg = readl_relaxed(mmsys->regs + addr) | value;
> > - writel_relaxed(reg, mmsys->regs + addr);
> > - }
> > + mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, true);
> > }
> > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
> >
> > @@ -288,19 +299,10 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> > enum mtk_ddp_comp_id next)
> > {
> > struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> > - unsigned int addr, value, reg;
> >
> > - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> > - if (value) {
> > - reg = readl_relaxed(mmsys->regs + addr) & ~value;
> > - writel_relaxed(reg, mmsys->regs + addr);
> > - }
> > + mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, false);
> >
> > - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> > - if (value) {
> > - reg = readl_relaxed(mmsys->regs + addr) & ~value;
> > - writel_relaxed(reg, mmsys->regs + addr);
> > - }
> > + mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, false);
> > }
> > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
> >
> > --
> > 1.8.1.1.dirty
> > _______________________________________________
> > Linux-mediatek mailing list
> > Linux-mediatek@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
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^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4, 03/10] soc: mediatek: mmsys: move register operation into mmsys path select function
@ 2021-01-21 0:56 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-21 0:56 UTC (permalink / raw)
To: Matthias Brugger
Cc: Mark Rutland, devicetree, Daniel Vetter, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
Matthias Brugger, Rob Herring, linux-mediatek, Philipp Zabel,
CK Hu, linux-arm-kernel
On Wed, 2021-01-20 at 20:38 +0100, Matthias Brugger wrote:
> On Tue, Jan 05, 2021 at 11:06:26AM +0800, Yongqiang Niu wrote:
> > move register operation into mmsys path select function
>
> Why do you want to do that. It seems the register access pattern is the
> same for all SoCs so far supported, so I don't see the need to duplicate
> the code in every SoC.
>
> Regards,
> Matthias
mt2701 and mt8173 ovl mout en already different.
mt2701 ovl mout en register offset is 0x30
mt8173 olv mout en register offset is 0x40
only the use case is different;
mt2701 ovl->color0
mt8173 ovl->rmda0
there make different define for this different.
#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
for the future mt8183, ovl mout en register offset will change to
0xf00
this is only one different sample, there will be more and more
different, so we add this patch for different soc
>
> >
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > ---
> > drivers/soc/mediatek/mmsys/mtk-mmsys.c | 140 +++++++++++++++++----------------
> > 1 file changed, 71 insertions(+), 69 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> > index 6c03282..64c8030 100644
> > --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> > @@ -106,141 +106,161 @@ struct mtk_mmsys {
> > .clk_driver = "clk-mt8183-mm",
> > };
> >
> > -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
> > - enum mtk_ddp_comp_id next,
> > - unsigned int *addr)
> > +static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
> > + enum mtk_ddp_comp_id cur,
> > + enum mtk_ddp_comp_id next,
> > + bool enable)
> > {
> > - unsigned int value;
> > + unsigned int addr, value, reg;
> >
> > if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> > - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> > value = OVL0_MOUT_EN_COLOR0;
> > } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
> > - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> > value = OVL_MOUT_EN_RDMA;
> > } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
> > - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > value = OD_MOUT_EN_RDMA0;
> > } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
> > - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> > value = UFOE_MOUT_EN_DSI0;
> > } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> > - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> > value = OVL1_MOUT_EN_COLOR1;
> > } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> > - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> > value = GAMMA_MOUT_EN_RDMA1;
> > } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> > - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > value = OD1_MOUT_EN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > value = RDMA0_SOUT_DPI0;
> > } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > value = RDMA0_SOUT_DPI1;
> > } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > value = RDMA0_SOUT_DSI1;
> > } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > value = RDMA0_SOUT_DSI2;
> > } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > value = RDMA0_SOUT_DSI3;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > value = RDMA1_SOUT_DSI1;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > value = RDMA1_SOUT_DSI2;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > value = RDMA1_SOUT_DSI3;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > value = RDMA1_SOUT_DPI0;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > value = RDMA1_SOUT_DPI1;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > value = RDMA2_SOUT_DPI0;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > value = RDMA2_SOUT_DPI1;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > value = RDMA2_SOUT_DSI1;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > value = RDMA2_SOUT_DSI2;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > value = RDMA2_SOUT_DSI3;
> > } else {
> > value = 0;
> > }
> >
> > - return value;
> > + if (value) {
> > + reg = readl_relaxed(config_regs + addr);
> > +
> > + if (enable)
> > + reg |= value;
> > + else
> > + reg &= ~value;
> > +
> > + writel_relaxed(reg, config_regs + addr);
> > + }
> > }
> >
> > -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
> > - enum mtk_ddp_comp_id next,
> > - unsigned int *addr)
> > +static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
> > + enum mtk_ddp_comp_id cur,
> > + enum mtk_ddp_comp_id next,
> > + bool enable)
> > {
> > - unsigned int value;
> > + unsigned int addr, value, reg;
> >
> > if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> > - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> > + addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> > value = COLOR0_SEL_IN_OVL0;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> > - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > + addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > value = DPI0_SEL_IN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> > - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > + addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > value = DPI1_SEL_IN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
> > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > value = DSI0_SEL_IN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > value = DSI1_SEL_IN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > value = DSI2_SEL_IN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > value = DSI3_SEL_IN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> > - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > + addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > value = DPI0_SEL_IN_RDMA2;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> > - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > + addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > value = DPI1_SEL_IN_RDMA2;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
> > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > value = DSI0_SEL_IN_RDMA2;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > value = DSI1_SEL_IN_RDMA2;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > value = DSI2_SEL_IN_RDMA2;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > value = DSI3_SEL_IN_RDMA2;
> > } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> > - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> > + addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> > value = COLOR1_SEL_IN_OVL1;
> > } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> > - *addr = DISP_REG_CONFIG_DSI_SEL;
> > + addr = DISP_REG_CONFIG_DSI_SEL;
> > value = DSI_SEL_IN_BLS;
> > } else {
> > value = 0;
> > }
> >
> > - return value;
> > + if (value) {
> > + reg = readl_relaxed(config_regs + addr);
> > +
> > + if (enable)
> > + reg |= value;
> > + else
> > + reg &= ~value;
> > +
> > + writel_relaxed(reg, config_regs + addr);
> > + }
> > }
> >
> > static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
> > @@ -265,21 +285,12 @@ void mtk_mmsys_ddp_connect(struct device *dev,
> > enum mtk_ddp_comp_id next)
> > {
> > struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> > - unsigned int addr, value, reg;
> >
> > - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> > - if (value) {
> > - reg = readl_relaxed(mmsys->regs + addr) | value;
> > - writel_relaxed(reg, mmsys->regs + addr);
> > - }
> > + mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, true);
> >
> > mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next);
> >
> > - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> > - if (value) {
> > - reg = readl_relaxed(mmsys->regs + addr) | value;
> > - writel_relaxed(reg, mmsys->regs + addr);
> > - }
> > + mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, true);
> > }
> > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
> >
> > @@ -288,19 +299,10 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> > enum mtk_ddp_comp_id next)
> > {
> > struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> > - unsigned int addr, value, reg;
> >
> > - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> > - if (value) {
> > - reg = readl_relaxed(mmsys->regs + addr) & ~value;
> > - writel_relaxed(reg, mmsys->regs + addr);
> > - }
> > + mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, false);
> >
> > - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> > - if (value) {
> > - reg = readl_relaxed(mmsys->regs + addr) & ~value;
> > - writel_relaxed(reg, mmsys->regs + addr);
> > - }
> > + mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, false);
> > }
> > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
> >
> > --
> > 1.8.1.1.dirty
> > _______________________________________________
> > Linux-mediatek mailing list
> > Linux-mediatek@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
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^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4, 03/10] soc: mediatek: mmsys: move register operation into mmsys path select function
@ 2021-01-21 0:56 ` Yongqiang Niu
0 siblings, 0 replies; 75+ messages in thread
From: Yongqiang Niu @ 2021-01-21 0:56 UTC (permalink / raw)
To: Matthias Brugger
Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Matthias Brugger,
Rob Herring, linux-mediatek, linux-arm-kernel
On Wed, 2021-01-20 at 20:38 +0100, Matthias Brugger wrote:
> On Tue, Jan 05, 2021 at 11:06:26AM +0800, Yongqiang Niu wrote:
> > move register operation into mmsys path select function
>
> Why do you want to do that. It seems the register access pattern is the
> same for all SoCs so far supported, so I don't see the need to duplicate
> the code in every SoC.
>
> Regards,
> Matthias
mt2701 and mt8173 ovl mout en already different.
mt2701 ovl mout en register offset is 0x30
mt8173 olv mout en register offset is 0x40
only the use case is different;
mt2701 ovl->color0
mt8173 ovl->rmda0
there make different define for this different.
#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
for the future mt8183, ovl mout en register offset will change to
0xf00
this is only one different sample, there will be more and more
different, so we add this patch for different soc
>
> >
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > ---
> > drivers/soc/mediatek/mmsys/mtk-mmsys.c | 140 +++++++++++++++++----------------
> > 1 file changed, 71 insertions(+), 69 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> > index 6c03282..64c8030 100644
> > --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> > @@ -106,141 +106,161 @@ struct mtk_mmsys {
> > .clk_driver = "clk-mt8183-mm",
> > };
> >
> > -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
> > - enum mtk_ddp_comp_id next,
> > - unsigned int *addr)
> > +static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
> > + enum mtk_ddp_comp_id cur,
> > + enum mtk_ddp_comp_id next,
> > + bool enable)
> > {
> > - unsigned int value;
> > + unsigned int addr, value, reg;
> >
> > if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> > - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> > value = OVL0_MOUT_EN_COLOR0;
> > } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
> > - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> > value = OVL_MOUT_EN_RDMA;
> > } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
> > - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > value = OD_MOUT_EN_RDMA0;
> > } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
> > - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> > value = UFOE_MOUT_EN_DSI0;
> > } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> > - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> > value = OVL1_MOUT_EN_COLOR1;
> > } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> > - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> > value = GAMMA_MOUT_EN_RDMA1;
> > } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> > - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > value = OD1_MOUT_EN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > value = RDMA0_SOUT_DPI0;
> > } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > value = RDMA0_SOUT_DPI1;
> > } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > value = RDMA0_SOUT_DSI1;
> > } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > value = RDMA0_SOUT_DSI2;
> > } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > value = RDMA0_SOUT_DSI3;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > value = RDMA1_SOUT_DSI1;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > value = RDMA1_SOUT_DSI2;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > value = RDMA1_SOUT_DSI3;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > value = RDMA1_SOUT_DPI0;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > value = RDMA1_SOUT_DPI1;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > value = RDMA2_SOUT_DPI0;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > value = RDMA2_SOUT_DPI1;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > value = RDMA2_SOUT_DSI1;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > value = RDMA2_SOUT_DSI2;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > value = RDMA2_SOUT_DSI3;
> > } else {
> > value = 0;
> > }
> >
> > - return value;
> > + if (value) {
> > + reg = readl_relaxed(config_regs + addr);
> > +
> > + if (enable)
> > + reg |= value;
> > + else
> > + reg &= ~value;
> > +
> > + writel_relaxed(reg, config_regs + addr);
> > + }
> > }
> >
> > -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
> > - enum mtk_ddp_comp_id next,
> > - unsigned int *addr)
> > +static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
> > + enum mtk_ddp_comp_id cur,
> > + enum mtk_ddp_comp_id next,
> > + bool enable)
> > {
> > - unsigned int value;
> > + unsigned int addr, value, reg;
> >
> > if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> > - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> > + addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> > value = COLOR0_SEL_IN_OVL0;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> > - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > + addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > value = DPI0_SEL_IN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> > - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > + addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > value = DPI1_SEL_IN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
> > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > value = DSI0_SEL_IN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > value = DSI1_SEL_IN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > value = DSI2_SEL_IN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > value = DSI3_SEL_IN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> > - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > + addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > value = DPI0_SEL_IN_RDMA2;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> > - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > + addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > value = DPI1_SEL_IN_RDMA2;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
> > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > value = DSI0_SEL_IN_RDMA2;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > value = DSI1_SEL_IN_RDMA2;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > value = DSI2_SEL_IN_RDMA2;
> > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > value = DSI3_SEL_IN_RDMA2;
> > } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> > - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> > + addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> > value = COLOR1_SEL_IN_OVL1;
> > } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> > - *addr = DISP_REG_CONFIG_DSI_SEL;
> > + addr = DISP_REG_CONFIG_DSI_SEL;
> > value = DSI_SEL_IN_BLS;
> > } else {
> > value = 0;
> > }
> >
> > - return value;
> > + if (value) {
> > + reg = readl_relaxed(config_regs + addr);
> > +
> > + if (enable)
> > + reg |= value;
> > + else
> > + reg &= ~value;
> > +
> > + writel_relaxed(reg, config_regs + addr);
> > + }
> > }
> >
> > static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
> > @@ -265,21 +285,12 @@ void mtk_mmsys_ddp_connect(struct device *dev,
> > enum mtk_ddp_comp_id next)
> > {
> > struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> > - unsigned int addr, value, reg;
> >
> > - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> > - if (value) {
> > - reg = readl_relaxed(mmsys->regs + addr) | value;
> > - writel_relaxed(reg, mmsys->regs + addr);
> > - }
> > + mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, true);
> >
> > mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next);
> >
> > - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> > - if (value) {
> > - reg = readl_relaxed(mmsys->regs + addr) | value;
> > - writel_relaxed(reg, mmsys->regs + addr);
> > - }
> > + mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, true);
> > }
> > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
> >
> > @@ -288,19 +299,10 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> > enum mtk_ddp_comp_id next)
> > {
> > struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> > - unsigned int addr, value, reg;
> >
> > - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> > - if (value) {
> > - reg = readl_relaxed(mmsys->regs + addr) & ~value;
> > - writel_relaxed(reg, mmsys->regs + addr);
> > - }
> > + mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, false);
> >
> > - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> > - if (value) {
> > - reg = readl_relaxed(mmsys->regs + addr) & ~value;
> > - writel_relaxed(reg, mmsys->regs + addr);
> > - }
> > + mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, false);
> > }
> > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
> >
> > --
> > 1.8.1.1.dirty
> > _______________________________________________
> > Linux-mediatek mailing list
> > Linux-mediatek@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
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^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4, 03/10] soc: mediatek: mmsys: move register operation into mmsys path select function
2021-01-21 0:56 ` Yongqiang Niu
(?)
@ 2021-01-29 15:35 ` Matthias Brugger
-1 siblings, 0 replies; 75+ messages in thread
From: Matthias Brugger @ 2021-01-29 15:35 UTC (permalink / raw)
To: Yongqiang Niu, Matthias Brugger
Cc: Mark Rutland, devicetree, Daniel Vetter, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
Rob Herring, linux-mediatek, Philipp Zabel, CK Hu,
linux-arm-kernel
On 21/01/2021 01:56, Yongqiang Niu wrote:
> On Wed, 2021-01-20 at 20:38 +0100, Matthias Brugger wrote:
>> On Tue, Jan 05, 2021 at 11:06:26AM +0800, Yongqiang Niu wrote:
>>> move register operation into mmsys path select function
>>
>> Why do you want to do that. It seems the register access pattern is the
>> same for all SoCs so far supported, so I don't see the need to duplicate
>> the code in every SoC.
>>
>> Regards,
>> Matthias
>
> mt2701 and mt8173 ovl mout en already different.
> mt2701 ovl mout en register offset is 0x30
> mt8173 olv mout en register offset is 0x40
>
> only the use case is different;
> mt2701 ovl->color0
> mt8173 ovl->rmda0
> there make different define for this different.
>
> #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
>
> #define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
>
> for the future mt8183, ovl mout en register offset will change to
> 0xf00
>
> this is only one different sample, there will be more and more
> different, so we add this patch for different soc
>
>
That does not explain why you want to put the read and write calls in a per SoC
part, they are the same for all supported SoCs.
Anyway after having a second thought, I don't like this approach at all. I think
splitting up the code in several SoCs to not bloat the driver is a good thing,
but not as it is done in this series.
I'd prefer to use a lookup table as Enric did in his first approach [1]. We
could then add this table in a per SoC header file.
Regards,
Matthias
https://patchwork.kernel.org/project/linux-mediatek/patch/20201006193320.405529-5-enric.balletbo@collabora.com/
>>
>>>
>>> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
>>> ---
>>> drivers/soc/mediatek/mmsys/mtk-mmsys.c | 140 +++++++++++++++++----------------
>>> 1 file changed, 71 insertions(+), 69 deletions(-)
>>>
>>> diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
>>> index 6c03282..64c8030 100644
>>> --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
>>> +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
>>> @@ -106,141 +106,161 @@ struct mtk_mmsys {
>>> .clk_driver = "clk-mt8183-mm",
>>> };
>>>
>>> -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
>>> - enum mtk_ddp_comp_id next,
>>> - unsigned int *addr)
>>> +static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
>>> + enum mtk_ddp_comp_id cur,
>>> + enum mtk_ddp_comp_id next,
>>> + bool enable)
>>> {
>>> - unsigned int value;
>>> + unsigned int addr, value, reg;
>>>
>>> if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>>> - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
>>> value = OVL0_MOUT_EN_COLOR0;
>>> } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
>>> - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
>>> value = OVL_MOUT_EN_RDMA;
>>> } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
>>> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>>> value = OD_MOUT_EN_RDMA0;
>>> } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
>>> - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
>>> value = UFOE_MOUT_EN_DSI0;
>>> } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>>> - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
>>> value = OVL1_MOUT_EN_COLOR1;
>>> } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
>>> - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
>>> value = GAMMA_MOUT_EN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
>>> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>>> value = OD1_MOUT_EN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> value = RDMA0_SOUT_DPI0;
>>> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> value = RDMA0_SOUT_DPI1;
>>> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> value = RDMA0_SOUT_DSI1;
>>> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> value = RDMA0_SOUT_DSI2;
>>> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> value = RDMA0_SOUT_DSI3;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> value = RDMA1_SOUT_DSI1;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> value = RDMA1_SOUT_DSI2;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> value = RDMA1_SOUT_DSI3;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> value = RDMA1_SOUT_DPI0;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> value = RDMA1_SOUT_DPI1;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> value = RDMA2_SOUT_DPI0;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> value = RDMA2_SOUT_DPI1;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> value = RDMA2_SOUT_DSI1;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> value = RDMA2_SOUT_DSI2;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> value = RDMA2_SOUT_DSI3;
>>> } else {
>>> value = 0;
>>> }
>>>
>>> - return value;
>>> + if (value) {
>>> + reg = readl_relaxed(config_regs + addr);
>>> +
>>> + if (enable)
>>> + reg |= value;
>>> + else
>>> + reg &= ~value;
>>> +
>>> + writel_relaxed(reg, config_regs + addr);
>>> + }
>>> }
>>>
>>> -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
>>> - enum mtk_ddp_comp_id next,
>>> - unsigned int *addr)
>>> +static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
>>> + enum mtk_ddp_comp_id cur,
>>> + enum mtk_ddp_comp_id next,
>>> + bool enable)
>>> {
>>> - unsigned int value;
>>> + unsigned int addr, value, reg;
>>>
>>> if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>>> - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
>>> value = COLOR0_SEL_IN_OVL0;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>>> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> value = DPI0_SEL_IN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>>> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> value = DPI1_SEL_IN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
>>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> value = DSI0_SEL_IN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>>> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> value = DSI1_SEL_IN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> value = DSI2_SEL_IN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>>> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> value = DSI3_SEL_IN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>>> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> value = DPI0_SEL_IN_RDMA2;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>>> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> value = DPI1_SEL_IN_RDMA2;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
>>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> value = DSI0_SEL_IN_RDMA2;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>>> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> value = DSI1_SEL_IN_RDMA2;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> value = DSI2_SEL_IN_RDMA2;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> value = DSI3_SEL_IN_RDMA2;
>>> } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>>> - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
>>> value = COLOR1_SEL_IN_OVL1;
>>> } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>>> - *addr = DISP_REG_CONFIG_DSI_SEL;
>>> + addr = DISP_REG_CONFIG_DSI_SEL;
>>> value = DSI_SEL_IN_BLS;
>>> } else {
>>> value = 0;
>>> }
>>>
>>> - return value;
>>> + if (value) {
>>> + reg = readl_relaxed(config_regs + addr);
>>> +
>>> + if (enable)
>>> + reg |= value;
>>> + else
>>> + reg &= ~value;
>>> +
>>> + writel_relaxed(reg, config_regs + addr);
>>> + }
>>> }
>>>
>>> static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
>>> @@ -265,21 +285,12 @@ void mtk_mmsys_ddp_connect(struct device *dev,
>>> enum mtk_ddp_comp_id next)
>>> {
>>> struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
>>> - unsigned int addr, value, reg;
>>>
>>> - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
>>> - if (value) {
>>> - reg = readl_relaxed(mmsys->regs + addr) | value;
>>> - writel_relaxed(reg, mmsys->regs + addr);
>>> - }
>>> + mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, true);
>>>
>>> mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next);
>>>
>>> - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
>>> - if (value) {
>>> - reg = readl_relaxed(mmsys->regs + addr) | value;
>>> - writel_relaxed(reg, mmsys->regs + addr);
>>> - }
>>> + mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, true);
>>> }
>>> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
>>>
>>> @@ -288,19 +299,10 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
>>> enum mtk_ddp_comp_id next)
>>> {
>>> struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
>>> - unsigned int addr, value, reg;
>>>
>>> - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
>>> - if (value) {
>>> - reg = readl_relaxed(mmsys->regs + addr) & ~value;
>>> - writel_relaxed(reg, mmsys->regs + addr);
>>> - }
>>> + mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, false);
>>>
>>> - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
>>> - if (value) {
>>> - reg = readl_relaxed(mmsys->regs + addr) & ~value;
>>> - writel_relaxed(reg, mmsys->regs + addr);
>>> - }
>>> + mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, false);
>>> }
>>> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>>>
>>> --
>>> 1.8.1.1.dirty
>>> _______________________________________________
>>> Linux-mediatek mailing list
>>> Linux-mediatek@lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/linux-mediatek
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4, 03/10] soc: mediatek: mmsys: move register operation into mmsys path select function
@ 2021-01-29 15:35 ` Matthias Brugger
0 siblings, 0 replies; 75+ messages in thread
From: Matthias Brugger @ 2021-01-29 15:35 UTC (permalink / raw)
To: Yongqiang Niu, Matthias Brugger
Cc: Mark Rutland, devicetree, Daniel Vetter, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
Rob Herring, linux-mediatek, Philipp Zabel, CK Hu,
linux-arm-kernel
On 21/01/2021 01:56, Yongqiang Niu wrote:
> On Wed, 2021-01-20 at 20:38 +0100, Matthias Brugger wrote:
>> On Tue, Jan 05, 2021 at 11:06:26AM +0800, Yongqiang Niu wrote:
>>> move register operation into mmsys path select function
>>
>> Why do you want to do that. It seems the register access pattern is the
>> same for all SoCs so far supported, so I don't see the need to duplicate
>> the code in every SoC.
>>
>> Regards,
>> Matthias
>
> mt2701 and mt8173 ovl mout en already different.
> mt2701 ovl mout en register offset is 0x30
> mt8173 olv mout en register offset is 0x40
>
> only the use case is different;
> mt2701 ovl->color0
> mt8173 ovl->rmda0
> there make different define for this different.
>
> #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
>
> #define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
>
> for the future mt8183, ovl mout en register offset will change to
> 0xf00
>
> this is only one different sample, there will be more and more
> different, so we add this patch for different soc
>
>
That does not explain why you want to put the read and write calls in a per SoC
part, they are the same for all supported SoCs.
Anyway after having a second thought, I don't like this approach at all. I think
splitting up the code in several SoCs to not bloat the driver is a good thing,
but not as it is done in this series.
I'd prefer to use a lookup table as Enric did in his first approach [1]. We
could then add this table in a per SoC header file.
Regards,
Matthias
https://patchwork.kernel.org/project/linux-mediatek/patch/20201006193320.405529-5-enric.balletbo@collabora.com/
>>
>>>
>>> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
>>> ---
>>> drivers/soc/mediatek/mmsys/mtk-mmsys.c | 140 +++++++++++++++++----------------
>>> 1 file changed, 71 insertions(+), 69 deletions(-)
>>>
>>> diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
>>> index 6c03282..64c8030 100644
>>> --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
>>> +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
>>> @@ -106,141 +106,161 @@ struct mtk_mmsys {
>>> .clk_driver = "clk-mt8183-mm",
>>> };
>>>
>>> -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
>>> - enum mtk_ddp_comp_id next,
>>> - unsigned int *addr)
>>> +static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
>>> + enum mtk_ddp_comp_id cur,
>>> + enum mtk_ddp_comp_id next,
>>> + bool enable)
>>> {
>>> - unsigned int value;
>>> + unsigned int addr, value, reg;
>>>
>>> if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>>> - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
>>> value = OVL0_MOUT_EN_COLOR0;
>>> } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
>>> - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
>>> value = OVL_MOUT_EN_RDMA;
>>> } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
>>> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>>> value = OD_MOUT_EN_RDMA0;
>>> } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
>>> - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
>>> value = UFOE_MOUT_EN_DSI0;
>>> } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>>> - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
>>> value = OVL1_MOUT_EN_COLOR1;
>>> } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
>>> - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
>>> value = GAMMA_MOUT_EN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
>>> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>>> value = OD1_MOUT_EN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> value = RDMA0_SOUT_DPI0;
>>> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> value = RDMA0_SOUT_DPI1;
>>> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> value = RDMA0_SOUT_DSI1;
>>> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> value = RDMA0_SOUT_DSI2;
>>> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> value = RDMA0_SOUT_DSI3;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> value = RDMA1_SOUT_DSI1;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> value = RDMA1_SOUT_DSI2;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> value = RDMA1_SOUT_DSI3;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> value = RDMA1_SOUT_DPI0;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> value = RDMA1_SOUT_DPI1;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> value = RDMA2_SOUT_DPI0;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> value = RDMA2_SOUT_DPI1;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> value = RDMA2_SOUT_DSI1;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> value = RDMA2_SOUT_DSI2;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> value = RDMA2_SOUT_DSI3;
>>> } else {
>>> value = 0;
>>> }
>>>
>>> - return value;
>>> + if (value) {
>>> + reg = readl_relaxed(config_regs + addr);
>>> +
>>> + if (enable)
>>> + reg |= value;
>>> + else
>>> + reg &= ~value;
>>> +
>>> + writel_relaxed(reg, config_regs + addr);
>>> + }
>>> }
>>>
>>> -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
>>> - enum mtk_ddp_comp_id next,
>>> - unsigned int *addr)
>>> +static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
>>> + enum mtk_ddp_comp_id cur,
>>> + enum mtk_ddp_comp_id next,
>>> + bool enable)
>>> {
>>> - unsigned int value;
>>> + unsigned int addr, value, reg;
>>>
>>> if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>>> - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
>>> value = COLOR0_SEL_IN_OVL0;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>>> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> value = DPI0_SEL_IN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>>> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> value = DPI1_SEL_IN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
>>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> value = DSI0_SEL_IN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>>> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> value = DSI1_SEL_IN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> value = DSI2_SEL_IN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>>> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> value = DSI3_SEL_IN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>>> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> value = DPI0_SEL_IN_RDMA2;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>>> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> value = DPI1_SEL_IN_RDMA2;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
>>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> value = DSI0_SEL_IN_RDMA2;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>>> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> value = DSI1_SEL_IN_RDMA2;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> value = DSI2_SEL_IN_RDMA2;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> value = DSI3_SEL_IN_RDMA2;
>>> } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>>> - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
>>> value = COLOR1_SEL_IN_OVL1;
>>> } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>>> - *addr = DISP_REG_CONFIG_DSI_SEL;
>>> + addr = DISP_REG_CONFIG_DSI_SEL;
>>> value = DSI_SEL_IN_BLS;
>>> } else {
>>> value = 0;
>>> }
>>>
>>> - return value;
>>> + if (value) {
>>> + reg = readl_relaxed(config_regs + addr);
>>> +
>>> + if (enable)
>>> + reg |= value;
>>> + else
>>> + reg &= ~value;
>>> +
>>> + writel_relaxed(reg, config_regs + addr);
>>> + }
>>> }
>>>
>>> static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
>>> @@ -265,21 +285,12 @@ void mtk_mmsys_ddp_connect(struct device *dev,
>>> enum mtk_ddp_comp_id next)
>>> {
>>> struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
>>> - unsigned int addr, value, reg;
>>>
>>> - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
>>> - if (value) {
>>> - reg = readl_relaxed(mmsys->regs + addr) | value;
>>> - writel_relaxed(reg, mmsys->regs + addr);
>>> - }
>>> + mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, true);
>>>
>>> mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next);
>>>
>>> - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
>>> - if (value) {
>>> - reg = readl_relaxed(mmsys->regs + addr) | value;
>>> - writel_relaxed(reg, mmsys->regs + addr);
>>> - }
>>> + mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, true);
>>> }
>>> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
>>>
>>> @@ -288,19 +299,10 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
>>> enum mtk_ddp_comp_id next)
>>> {
>>> struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
>>> - unsigned int addr, value, reg;
>>>
>>> - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
>>> - if (value) {
>>> - reg = readl_relaxed(mmsys->regs + addr) & ~value;
>>> - writel_relaxed(reg, mmsys->regs + addr);
>>> - }
>>> + mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, false);
>>>
>>> - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
>>> - if (value) {
>>> - reg = readl_relaxed(mmsys->regs + addr) & ~value;
>>> - writel_relaxed(reg, mmsys->regs + addr);
>>> - }
>>> + mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, false);
>>> }
>>> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>>>
>>> --
>>> 1.8.1.1.dirty
>>> _______________________________________________
>>> Linux-mediatek mailing list
>>> Linux-mediatek@lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/linux-mediatek
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4, 03/10] soc: mediatek: mmsys: move register operation into mmsys path select function
@ 2021-01-29 15:35 ` Matthias Brugger
0 siblings, 0 replies; 75+ messages in thread
From: Matthias Brugger @ 2021-01-29 15:35 UTC (permalink / raw)
To: Yongqiang Niu, Matthias Brugger
Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Rob Herring,
linux-mediatek, linux-arm-kernel
On 21/01/2021 01:56, Yongqiang Niu wrote:
> On Wed, 2021-01-20 at 20:38 +0100, Matthias Brugger wrote:
>> On Tue, Jan 05, 2021 at 11:06:26AM +0800, Yongqiang Niu wrote:
>>> move register operation into mmsys path select function
>>
>> Why do you want to do that. It seems the register access pattern is the
>> same for all SoCs so far supported, so I don't see the need to duplicate
>> the code in every SoC.
>>
>> Regards,
>> Matthias
>
> mt2701 and mt8173 ovl mout en already different.
> mt2701 ovl mout en register offset is 0x30
> mt8173 olv mout en register offset is 0x40
>
> only the use case is different;
> mt2701 ovl->color0
> mt8173 ovl->rmda0
> there make different define for this different.
>
> #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
>
> #define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
>
> for the future mt8183, ovl mout en register offset will change to
> 0xf00
>
> this is only one different sample, there will be more and more
> different, so we add this patch for different soc
>
>
That does not explain why you want to put the read and write calls in a per SoC
part, they are the same for all supported SoCs.
Anyway after having a second thought, I don't like this approach at all. I think
splitting up the code in several SoCs to not bloat the driver is a good thing,
but not as it is done in this series.
I'd prefer to use a lookup table as Enric did in his first approach [1]. We
could then add this table in a per SoC header file.
Regards,
Matthias
https://patchwork.kernel.org/project/linux-mediatek/patch/20201006193320.405529-5-enric.balletbo@collabora.com/
>>
>>>
>>> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
>>> ---
>>> drivers/soc/mediatek/mmsys/mtk-mmsys.c | 140 +++++++++++++++++----------------
>>> 1 file changed, 71 insertions(+), 69 deletions(-)
>>>
>>> diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
>>> index 6c03282..64c8030 100644
>>> --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
>>> +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
>>> @@ -106,141 +106,161 @@ struct mtk_mmsys {
>>> .clk_driver = "clk-mt8183-mm",
>>> };
>>>
>>> -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
>>> - enum mtk_ddp_comp_id next,
>>> - unsigned int *addr)
>>> +static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
>>> + enum mtk_ddp_comp_id cur,
>>> + enum mtk_ddp_comp_id next,
>>> + bool enable)
>>> {
>>> - unsigned int value;
>>> + unsigned int addr, value, reg;
>>>
>>> if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>>> - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
>>> value = OVL0_MOUT_EN_COLOR0;
>>> } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
>>> - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
>>> value = OVL_MOUT_EN_RDMA;
>>> } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
>>> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>>> value = OD_MOUT_EN_RDMA0;
>>> } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
>>> - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
>>> value = UFOE_MOUT_EN_DSI0;
>>> } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>>> - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
>>> value = OVL1_MOUT_EN_COLOR1;
>>> } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
>>> - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
>>> value = GAMMA_MOUT_EN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
>>> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>>> value = OD1_MOUT_EN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> value = RDMA0_SOUT_DPI0;
>>> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> value = RDMA0_SOUT_DPI1;
>>> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> value = RDMA0_SOUT_DSI1;
>>> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> value = RDMA0_SOUT_DSI2;
>>> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> value = RDMA0_SOUT_DSI3;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> value = RDMA1_SOUT_DSI1;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> value = RDMA1_SOUT_DSI2;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> value = RDMA1_SOUT_DSI3;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> value = RDMA1_SOUT_DPI0;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> value = RDMA1_SOUT_DPI1;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> value = RDMA2_SOUT_DPI0;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> value = RDMA2_SOUT_DPI1;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> value = RDMA2_SOUT_DSI1;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> value = RDMA2_SOUT_DSI2;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> value = RDMA2_SOUT_DSI3;
>>> } else {
>>> value = 0;
>>> }
>>>
>>> - return value;
>>> + if (value) {
>>> + reg = readl_relaxed(config_regs + addr);
>>> +
>>> + if (enable)
>>> + reg |= value;
>>> + else
>>> + reg &= ~value;
>>> +
>>> + writel_relaxed(reg, config_regs + addr);
>>> + }
>>> }
>>>
>>> -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
>>> - enum mtk_ddp_comp_id next,
>>> - unsigned int *addr)
>>> +static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
>>> + enum mtk_ddp_comp_id cur,
>>> + enum mtk_ddp_comp_id next,
>>> + bool enable)
>>> {
>>> - unsigned int value;
>>> + unsigned int addr, value, reg;
>>>
>>> if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>>> - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
>>> value = COLOR0_SEL_IN_OVL0;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>>> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> value = DPI0_SEL_IN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>>> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> value = DPI1_SEL_IN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
>>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> value = DSI0_SEL_IN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>>> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> value = DSI1_SEL_IN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> value = DSI2_SEL_IN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>>> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> value = DSI3_SEL_IN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>>> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> value = DPI0_SEL_IN_RDMA2;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>>> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> value = DPI1_SEL_IN_RDMA2;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
>>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> value = DSI0_SEL_IN_RDMA2;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>>> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> value = DSI1_SEL_IN_RDMA2;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> value = DSI2_SEL_IN_RDMA2;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> value = DSI3_SEL_IN_RDMA2;
>>> } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>>> - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
>>> value = COLOR1_SEL_IN_OVL1;
>>> } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>>> - *addr = DISP_REG_CONFIG_DSI_SEL;
>>> + addr = DISP_REG_CONFIG_DSI_SEL;
>>> value = DSI_SEL_IN_BLS;
>>> } else {
>>> value = 0;
>>> }
>>>
>>> - return value;
>>> + if (value) {
>>> + reg = readl_relaxed(config_regs + addr);
>>> +
>>> + if (enable)
>>> + reg |= value;
>>> + else
>>> + reg &= ~value;
>>> +
>>> + writel_relaxed(reg, config_regs + addr);
>>> + }
>>> }
>>>
>>> static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
>>> @@ -265,21 +285,12 @@ void mtk_mmsys_ddp_connect(struct device *dev,
>>> enum mtk_ddp_comp_id next)
>>> {
>>> struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
>>> - unsigned int addr, value, reg;
>>>
>>> - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
>>> - if (value) {
>>> - reg = readl_relaxed(mmsys->regs + addr) | value;
>>> - writel_relaxed(reg, mmsys->regs + addr);
>>> - }
>>> + mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, true);
>>>
>>> mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next);
>>>
>>> - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
>>> - if (value) {
>>> - reg = readl_relaxed(mmsys->regs + addr) | value;
>>> - writel_relaxed(reg, mmsys->regs + addr);
>>> - }
>>> + mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, true);
>>> }
>>> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
>>>
>>> @@ -288,19 +299,10 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
>>> enum mtk_ddp_comp_id next)
>>> {
>>> struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
>>> - unsigned int addr, value, reg;
>>>
>>> - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
>>> - if (value) {
>>> - reg = readl_relaxed(mmsys->regs + addr) & ~value;
>>> - writel_relaxed(reg, mmsys->regs + addr);
>>> - }
>>> + mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, false);
>>>
>>> - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
>>> - if (value) {
>>> - reg = readl_relaxed(mmsys->regs + addr) & ~value;
>>> - writel_relaxed(reg, mmsys->regs + addr);
>>> - }
>>> + mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, false);
>>> }
>>> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>>>
>>> --
>>> 1.8.1.1.dirty
>>> _______________________________________________
>>> Linux-mediatek mailing list
>>> Linux-mediatek@lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/linux-mediatek
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4, 01/10] soc: mediatek: mmsys: create mmsys folder
2021-01-05 3:06 ` Yongqiang Niu
(?)
(?)
@ 2021-02-09 15:38 ` Enric Balletbo Serra
-1 siblings, 0 replies; 75+ messages in thread
From: Enric Balletbo Serra @ 2021-02-09 15:38 UTC (permalink / raw)
To: Yongqiang Niu
Cc: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger,
Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group,
moderated list:ARM/Mediatek SoC support, Daniel Vetter,
Linux ARM
Hi Yongqiang Niu,
Thank you for your patch.
Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dt., 5
de gen. 2021 a les 4:07:
>
> the mmsys will more and more complicated after support
> more and more SoCs, add an independent folder will be
> more clear
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/soc/mediatek/Makefile | 2 +-
It will not apply cleanly anymore after the below commit that is
already queued. Maybe you could rebase the patches and resend them
again?
commit e1e4f7fea37572f0ccf3887430e52c491e9accb6
Author: CK Hu <ck.hu@mediatek.com>
Date: Tue Jul 21 15:46:06 2020 +0800
soc / drm: mediatek: Move mtk mutex driver to soc folder
mtk mutex is used by DRM and MDP driver, and its function is SoC-specific,
so move it to soc folder.
With that fixed,
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Thanks,
Enric
> drivers/soc/mediatek/mmsys/Makefile | 2 +
> drivers/soc/mediatek/mmsys/mtk-mmsys.c | 373 +++++++++++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 373 ---------------------------------
> 4 files changed, 376 insertions(+), 374 deletions(-)
> create mode 100644 drivers/soc/mediatek/mmsys/Makefile
> create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c
> delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c
>
> diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> index b6908db..eca9774 100644
> --- a/drivers/soc/mediatek/Makefile
> +++ b/drivers/soc/mediatek/Makefile
> @@ -5,4 +5,4 @@ obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
> obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
> obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
> obj-$(CONFIG_MTK_SCPSYS_PM_DOMAINS) += mtk-pm-domains.o
> -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
> +obj-$(CONFIG_MTK_MMSYS) += mmsys/
> diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
> new file mode 100644
> index 0000000..f44eadc
> --- /dev/null
> +++ b/drivers/soc/mediatek/mmsys/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
> diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> new file mode 100644
> index 0000000..18f9397
> --- /dev/null
> +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> @@ -0,0 +1,373 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2014 MediaTek Inc.
> + * Author: James Liao <jamesjj.liao@mediatek.com>
> + */
> +
> +#include <linux/device.h>
> +#include <linux/io.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +
> +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
> +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
> +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
> +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
> +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
> +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
> +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
> +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
> +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
> +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
> +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
> +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
> +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
> +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
> +
> +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
> +#define DISP_REG_CONFIG_OUT_SEL 0x04c
> +#define DISP_REG_CONFIG_DSI_SEL 0x050
> +#define DISP_REG_CONFIG_DPI_SEL 0x064
> +
> +#define OVL0_MOUT_EN_COLOR0 0x1
> +#define OD_MOUT_EN_RDMA0 0x1
> +#define OD1_MOUT_EN_RDMA1 BIT(16)
> +#define UFOE_MOUT_EN_DSI0 0x1
> +#define COLOR0_SEL_IN_OVL0 0x1
> +#define OVL1_MOUT_EN_COLOR1 0x1
> +#define GAMMA_MOUT_EN_RDMA1 0x1
> +#define RDMA0_SOUT_DPI0 0x2
> +#define RDMA0_SOUT_DPI1 0x3
> +#define RDMA0_SOUT_DSI1 0x1
> +#define RDMA0_SOUT_DSI2 0x4
> +#define RDMA0_SOUT_DSI3 0x5
> +#define RDMA1_SOUT_DPI0 0x2
> +#define RDMA1_SOUT_DPI1 0x3
> +#define RDMA1_SOUT_DSI1 0x1
> +#define RDMA1_SOUT_DSI2 0x4
> +#define RDMA1_SOUT_DSI3 0x5
> +#define RDMA2_SOUT_DPI0 0x2
> +#define RDMA2_SOUT_DPI1 0x3
> +#define RDMA2_SOUT_DSI1 0x1
> +#define RDMA2_SOUT_DSI2 0x4
> +#define RDMA2_SOUT_DSI3 0x5
> +#define DPI0_SEL_IN_RDMA1 0x1
> +#define DPI0_SEL_IN_RDMA2 0x3
> +#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
> +#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
> +#define DSI0_SEL_IN_RDMA1 0x1
> +#define DSI0_SEL_IN_RDMA2 0x4
> +#define DSI1_SEL_IN_RDMA1 0x1
> +#define DSI1_SEL_IN_RDMA2 0x4
> +#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
> +#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
> +#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
> +#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
> +#define COLOR1_SEL_IN_OVL1 0x1
> +
> +#define OVL_MOUT_EN_RDMA 0x1
> +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
> +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
> +#define DSI_SEL_IN_BLS 0x0
> +#define DPI_SEL_IN_BLS 0x0
> +#define DSI_SEL_IN_RDMA 0x1
> +
> +struct mtk_mmsys_driver_data {
> + const char *clk_driver;
> +};
> +
> +static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> + .clk_driver = "clk-mt2701-mm",
> +};
> +
> +static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
> + .clk_driver = "clk-mt2712-mm",
> +};
> +
> +static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
> + .clk_driver = "clk-mt6779-mm",
> +};
> +
> +static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
> + .clk_driver = "clk-mt6797-mm",
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> + .clk_driver = "clk-mt8173-mm",
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> + .clk_driver = "clk-mt8183-mm",
> +};
> +
> +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + unsigned int *addr)
> +{
> + unsigned int value;
> +
> + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> + value = OVL0_MOUT_EN_COLOR0;
> + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
> + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> + value = OVL_MOUT_EN_RDMA;
> + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
> + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> + value = OD_MOUT_EN_RDMA0;
> + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
> + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> + value = UFOE_MOUT_EN_DSI0;
> + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> + value = OVL1_MOUT_EN_COLOR1;
> + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> + value = GAMMA_MOUT_EN_RDMA1;
> + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> + value = OD1_MOUT_EN_RDMA1;
> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + value = RDMA0_SOUT_DPI0;
> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + value = RDMA0_SOUT_DPI1;
> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + value = RDMA0_SOUT_DSI1;
> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + value = RDMA0_SOUT_DSI2;
> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + value = RDMA0_SOUT_DSI3;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + value = RDMA1_SOUT_DSI1;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + value = RDMA1_SOUT_DSI2;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + value = RDMA1_SOUT_DSI3;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + value = RDMA1_SOUT_DPI0;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + value = RDMA1_SOUT_DPI1;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + value = RDMA2_SOUT_DPI0;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + value = RDMA2_SOUT_DPI1;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + value = RDMA2_SOUT_DSI1;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + value = RDMA2_SOUT_DSI2;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + value = RDMA2_SOUT_DSI3;
> + } else {
> + value = 0;
> + }
> +
> + return value;
> +}
> +
> +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + unsigned int *addr)
> +{
> + unsigned int value;
> +
> + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> + value = COLOR0_SEL_IN_OVL0;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + value = DPI0_SEL_IN_RDMA1;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + value = DPI1_SEL_IN_RDMA1;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + value = DSI0_SEL_IN_RDMA1;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> + *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> + value = DSI1_SEL_IN_RDMA1;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + value = DSI2_SEL_IN_RDMA1;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> + *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> + value = DSI3_SEL_IN_RDMA1;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + value = DPI0_SEL_IN_RDMA2;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + value = DPI1_SEL_IN_RDMA2;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + value = DSI0_SEL_IN_RDMA2;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> + *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> + value = DSI1_SEL_IN_RDMA2;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + value = DSI2_SEL_IN_RDMA2;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + value = DSI3_SEL_IN_RDMA2;
> + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> + value = COLOR1_SEL_IN_OVL1;
> + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> + *addr = DISP_REG_CONFIG_DSI_SEL;
> + value = DSI_SEL_IN_BLS;
> + } else {
> + value = 0;
> + }
> +
> + return value;
> +}
> +
> +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next)
> +{
> + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
> + config_regs + DISP_REG_CONFIG_OUT_SEL);
> + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
> + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
> + config_regs + DISP_REG_CONFIG_OUT_SEL);
> + writel_relaxed(DSI_SEL_IN_RDMA,
> + config_regs + DISP_REG_CONFIG_DSI_SEL);
> + writel_relaxed(DPI_SEL_IN_BLS,
> + config_regs + DISP_REG_CONFIG_DPI_SEL);
> + }
> +}
> +
> +void mtk_mmsys_ddp_connect(struct device *dev,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next)
> +{
> + void __iomem *config_regs = dev_get_drvdata(dev);
> + unsigned int addr, value, reg;
> +
> + value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> + if (value) {
> + reg = readl_relaxed(config_regs + addr) | value;
> + writel_relaxed(reg, config_regs + addr);
> + }
> +
> + mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
> +
> + value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> + if (value) {
> + reg = readl_relaxed(config_regs + addr) | value;
> + writel_relaxed(reg, config_regs + addr);
> + }
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
> +
> +void mtk_mmsys_ddp_disconnect(struct device *dev,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next)
> +{
> + void __iomem *config_regs = dev_get_drvdata(dev);
> + unsigned int addr, value, reg;
> +
> + value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> + if (value) {
> + reg = readl_relaxed(config_regs + addr) & ~value;
> + writel_relaxed(reg, config_regs + addr);
> + }
> +
> + value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> + if (value) {
> + reg = readl_relaxed(config_regs + addr) & ~value;
> + writel_relaxed(reg, config_regs + addr);
> + }
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
> +
> +static int mtk_mmsys_probe(struct platform_device *pdev)
> +{
> + const struct mtk_mmsys_driver_data *data;
> + struct device *dev = &pdev->dev;
> + struct platform_device *clks;
> + struct platform_device *drm;
> + void __iomem *config_regs;
> + int ret;
> +
> + config_regs = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(config_regs)) {
> + ret = PTR_ERR(config_regs);
> + dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
> + return ret;
> + }
> +
> + platform_set_drvdata(pdev, config_regs);
> +
> + data = of_device_get_match_data(&pdev->dev);
> +
> + clks = platform_device_register_data(&pdev->dev, data->clk_driver,
> + PLATFORM_DEVID_AUTO, NULL, 0);
> + if (IS_ERR(clks))
> + return PTR_ERR(clks);
> +
> + drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
> + PLATFORM_DEVID_AUTO, NULL, 0);
> + if (IS_ERR(drm)) {
> + platform_device_unregister(clks);
> + return PTR_ERR(drm);
> + }
> +
> + return 0;
> +}
> +
> +static const struct of_device_id of_match_mtk_mmsys[] = {
> + {
> + .compatible = "mediatek,mt2701-mmsys",
> + .data = &mt2701_mmsys_driver_data,
> + },
> + {
> + .compatible = "mediatek,mt2712-mmsys",
> + .data = &mt2712_mmsys_driver_data,
> + },
> + {
> + .compatible = "mediatek,mt6779-mmsys",
> + .data = &mt6779_mmsys_driver_data,
> + },
> + {
> + .compatible = "mediatek,mt6797-mmsys",
> + .data = &mt6797_mmsys_driver_data,
> + },
> + {
> + .compatible = "mediatek,mt8173-mmsys",
> + .data = &mt8173_mmsys_driver_data,
> + },
> + {
> + .compatible = "mediatek,mt8183-mmsys",
> + .data = &mt8183_mmsys_driver_data,
> + },
> + { }
> +};
> +
> +static struct platform_driver mtk_mmsys_drv = {
> + .driver = {
> + .name = "mtk-mmsys",
> + .of_match_table = of_match_mtk_mmsys,
> + },
> + .probe = mtk_mmsys_probe,
> +};
> +
> +builtin_platform_driver(mtk_mmsys_drv);
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> deleted file mode 100644
> index 18f9397..0000000
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ /dev/null
> @@ -1,373 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * Copyright (c) 2014 MediaTek Inc.
> - * Author: James Liao <jamesjj.liao@mediatek.com>
> - */
> -
> -#include <linux/device.h>
> -#include <linux/io.h>
> -#include <linux/of_device.h>
> -#include <linux/platform_device.h>
> -#include <linux/soc/mediatek/mtk-mmsys.h>
> -
> -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
> -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
> -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
> -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
> -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
> -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
> -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
> -#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
> -#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
> -#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
> -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
> -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
> -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
> -#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
> -
> -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
> -#define DISP_REG_CONFIG_OUT_SEL 0x04c
> -#define DISP_REG_CONFIG_DSI_SEL 0x050
> -#define DISP_REG_CONFIG_DPI_SEL 0x064
> -
> -#define OVL0_MOUT_EN_COLOR0 0x1
> -#define OD_MOUT_EN_RDMA0 0x1
> -#define OD1_MOUT_EN_RDMA1 BIT(16)
> -#define UFOE_MOUT_EN_DSI0 0x1
> -#define COLOR0_SEL_IN_OVL0 0x1
> -#define OVL1_MOUT_EN_COLOR1 0x1
> -#define GAMMA_MOUT_EN_RDMA1 0x1
> -#define RDMA0_SOUT_DPI0 0x2
> -#define RDMA0_SOUT_DPI1 0x3
> -#define RDMA0_SOUT_DSI1 0x1
> -#define RDMA0_SOUT_DSI2 0x4
> -#define RDMA0_SOUT_DSI3 0x5
> -#define RDMA1_SOUT_DPI0 0x2
> -#define RDMA1_SOUT_DPI1 0x3
> -#define RDMA1_SOUT_DSI1 0x1
> -#define RDMA1_SOUT_DSI2 0x4
> -#define RDMA1_SOUT_DSI3 0x5
> -#define RDMA2_SOUT_DPI0 0x2
> -#define RDMA2_SOUT_DPI1 0x3
> -#define RDMA2_SOUT_DSI1 0x1
> -#define RDMA2_SOUT_DSI2 0x4
> -#define RDMA2_SOUT_DSI3 0x5
> -#define DPI0_SEL_IN_RDMA1 0x1
> -#define DPI0_SEL_IN_RDMA2 0x3
> -#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
> -#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
> -#define DSI0_SEL_IN_RDMA1 0x1
> -#define DSI0_SEL_IN_RDMA2 0x4
> -#define DSI1_SEL_IN_RDMA1 0x1
> -#define DSI1_SEL_IN_RDMA2 0x4
> -#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
> -#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
> -#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
> -#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
> -#define COLOR1_SEL_IN_OVL1 0x1
> -
> -#define OVL_MOUT_EN_RDMA 0x1
> -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
> -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
> -#define DSI_SEL_IN_BLS 0x0
> -#define DPI_SEL_IN_BLS 0x0
> -#define DSI_SEL_IN_RDMA 0x1
> -
> -struct mtk_mmsys_driver_data {
> - const char *clk_driver;
> -};
> -
> -static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> - .clk_driver = "clk-mt2701-mm",
> -};
> -
> -static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
> - .clk_driver = "clk-mt2712-mm",
> -};
> -
> -static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
> - .clk_driver = "clk-mt6779-mm",
> -};
> -
> -static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
> - .clk_driver = "clk-mt6797-mm",
> -};
> -
> -static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> - .clk_driver = "clk-mt8173-mm",
> -};
> -
> -static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> - .clk_driver = "clk-mt8183-mm",
> -};
> -
> -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
> - enum mtk_ddp_comp_id next,
> - unsigned int *addr)
> -{
> - unsigned int value;
> -
> - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> - value = OVL0_MOUT_EN_COLOR0;
> - } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
> - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> - value = OVL_MOUT_EN_RDMA;
> - } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> - value = OD_MOUT_EN_RDMA0;
> - } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> - value = UFOE_MOUT_EN_DSI0;
> - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> - value = OVL1_MOUT_EN_COLOR1;
> - } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> - value = GAMMA_MOUT_EN_RDMA1;
> - } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> - value = OD1_MOUT_EN_RDMA1;
> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> - value = RDMA0_SOUT_DPI0;
> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> - value = RDMA0_SOUT_DPI1;
> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> - value = RDMA0_SOUT_DSI1;
> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> - value = RDMA0_SOUT_DSI2;
> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> - value = RDMA0_SOUT_DSI3;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> - value = RDMA1_SOUT_DSI1;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> - value = RDMA1_SOUT_DSI2;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> - value = RDMA1_SOUT_DSI3;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> - value = RDMA1_SOUT_DPI0;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> - value = RDMA1_SOUT_DPI1;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> - value = RDMA2_SOUT_DPI0;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> - value = RDMA2_SOUT_DPI1;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> - value = RDMA2_SOUT_DSI1;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> - value = RDMA2_SOUT_DSI2;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> - value = RDMA2_SOUT_DSI3;
> - } else {
> - value = 0;
> - }
> -
> - return value;
> -}
> -
> -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
> - enum mtk_ddp_comp_id next,
> - unsigned int *addr)
> -{
> - unsigned int value;
> -
> - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> - value = COLOR0_SEL_IN_OVL0;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> - value = DPI0_SEL_IN_RDMA1;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> - value = DPI1_SEL_IN_RDMA1;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> - value = DSI0_SEL_IN_RDMA1;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> - value = DSI1_SEL_IN_RDMA1;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> - value = DSI2_SEL_IN_RDMA1;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> - value = DSI3_SEL_IN_RDMA1;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> - value = DPI0_SEL_IN_RDMA2;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> - value = DPI1_SEL_IN_RDMA2;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> - value = DSI0_SEL_IN_RDMA2;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> - value = DSI1_SEL_IN_RDMA2;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> - value = DSI2_SEL_IN_RDMA2;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> - value = DSI3_SEL_IN_RDMA2;
> - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> - value = COLOR1_SEL_IN_OVL1;
> - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DSI_SEL;
> - value = DSI_SEL_IN_BLS;
> - } else {
> - value = 0;
> - }
> -
> - return value;
> -}
> -
> -static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
> - enum mtk_ddp_comp_id cur,
> - enum mtk_ddp_comp_id next)
> -{
> - if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
> - config_regs + DISP_REG_CONFIG_OUT_SEL);
> - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
> - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
> - config_regs + DISP_REG_CONFIG_OUT_SEL);
> - writel_relaxed(DSI_SEL_IN_RDMA,
> - config_regs + DISP_REG_CONFIG_DSI_SEL);
> - writel_relaxed(DPI_SEL_IN_BLS,
> - config_regs + DISP_REG_CONFIG_DPI_SEL);
> - }
> -}
> -
> -void mtk_mmsys_ddp_connect(struct device *dev,
> - enum mtk_ddp_comp_id cur,
> - enum mtk_ddp_comp_id next)
> -{
> - void __iomem *config_regs = dev_get_drvdata(dev);
> - unsigned int addr, value, reg;
> -
> - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> - if (value) {
> - reg = readl_relaxed(config_regs + addr) | value;
> - writel_relaxed(reg, config_regs + addr);
> - }
> -
> - mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
> -
> - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> - if (value) {
> - reg = readl_relaxed(config_regs + addr) | value;
> - writel_relaxed(reg, config_regs + addr);
> - }
> -}
> -EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
> -
> -void mtk_mmsys_ddp_disconnect(struct device *dev,
> - enum mtk_ddp_comp_id cur,
> - enum mtk_ddp_comp_id next)
> -{
> - void __iomem *config_regs = dev_get_drvdata(dev);
> - unsigned int addr, value, reg;
> -
> - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> - if (value) {
> - reg = readl_relaxed(config_regs + addr) & ~value;
> - writel_relaxed(reg, config_regs + addr);
> - }
> -
> - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> - if (value) {
> - reg = readl_relaxed(config_regs + addr) & ~value;
> - writel_relaxed(reg, config_regs + addr);
> - }
> -}
> -EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
> -
> -static int mtk_mmsys_probe(struct platform_device *pdev)
> -{
> - const struct mtk_mmsys_driver_data *data;
> - struct device *dev = &pdev->dev;
> - struct platform_device *clks;
> - struct platform_device *drm;
> - void __iomem *config_regs;
> - int ret;
> -
> - config_regs = devm_platform_ioremap_resource(pdev, 0);
> - if (IS_ERR(config_regs)) {
> - ret = PTR_ERR(config_regs);
> - dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
> - return ret;
> - }
> -
> - platform_set_drvdata(pdev, config_regs);
> -
> - data = of_device_get_match_data(&pdev->dev);
> -
> - clks = platform_device_register_data(&pdev->dev, data->clk_driver,
> - PLATFORM_DEVID_AUTO, NULL, 0);
> - if (IS_ERR(clks))
> - return PTR_ERR(clks);
> -
> - drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
> - PLATFORM_DEVID_AUTO, NULL, 0);
> - if (IS_ERR(drm)) {
> - platform_device_unregister(clks);
> - return PTR_ERR(drm);
> - }
> -
> - return 0;
> -}
> -
> -static const struct of_device_id of_match_mtk_mmsys[] = {
> - {
> - .compatible = "mediatek,mt2701-mmsys",
> - .data = &mt2701_mmsys_driver_data,
> - },
> - {
> - .compatible = "mediatek,mt2712-mmsys",
> - .data = &mt2712_mmsys_driver_data,
> - },
> - {
> - .compatible = "mediatek,mt6779-mmsys",
> - .data = &mt6779_mmsys_driver_data,
> - },
> - {
> - .compatible = "mediatek,mt6797-mmsys",
> - .data = &mt6797_mmsys_driver_data,
> - },
> - {
> - .compatible = "mediatek,mt8173-mmsys",
> - .data = &mt8173_mmsys_driver_data,
> - },
> - {
> - .compatible = "mediatek,mt8183-mmsys",
> - .data = &mt8183_mmsys_driver_data,
> - },
> - { }
> -};
> -
> -static struct platform_driver mtk_mmsys_drv = {
> - .driver = {
> - .name = "mtk-mmsys",
> - .of_match_table = of_match_mtk_mmsys,
> - },
> - .probe = mtk_mmsys_probe,
> -};
> -
> -builtin_platform_driver(mtk_mmsys_drv);
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4, 01/10] soc: mediatek: mmsys: create mmsys folder
@ 2021-02-09 15:38 ` Enric Balletbo Serra
0 siblings, 0 replies; 75+ messages in thread
From: Enric Balletbo Serra @ 2021-02-09 15:38 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, devicetree, Daniel Vetter, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
Matthias Brugger, Rob Herring,
moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu,
Linux ARM
Hi Yongqiang Niu,
Thank you for your patch.
Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dt., 5
de gen. 2021 a les 4:07:
>
> the mmsys will more and more complicated after support
> more and more SoCs, add an independent folder will be
> more clear
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/soc/mediatek/Makefile | 2 +-
It will not apply cleanly anymore after the below commit that is
already queued. Maybe you could rebase the patches and resend them
again?
commit e1e4f7fea37572f0ccf3887430e52c491e9accb6
Author: CK Hu <ck.hu@mediatek.com>
Date: Tue Jul 21 15:46:06 2020 +0800
soc / drm: mediatek: Move mtk mutex driver to soc folder
mtk mutex is used by DRM and MDP driver, and its function is SoC-specific,
so move it to soc folder.
With that fixed,
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Thanks,
Enric
> drivers/soc/mediatek/mmsys/Makefile | 2 +
> drivers/soc/mediatek/mmsys/mtk-mmsys.c | 373 +++++++++++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 373 ---------------------------------
> 4 files changed, 376 insertions(+), 374 deletions(-)
> create mode 100644 drivers/soc/mediatek/mmsys/Makefile
> create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c
> delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c
>
> diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> index b6908db..eca9774 100644
> --- a/drivers/soc/mediatek/Makefile
> +++ b/drivers/soc/mediatek/Makefile
> @@ -5,4 +5,4 @@ obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
> obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
> obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
> obj-$(CONFIG_MTK_SCPSYS_PM_DOMAINS) += mtk-pm-domains.o
> -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
> +obj-$(CONFIG_MTK_MMSYS) += mmsys/
> diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
> new file mode 100644
> index 0000000..f44eadc
> --- /dev/null
> +++ b/drivers/soc/mediatek/mmsys/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
> diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> new file mode 100644
> index 0000000..18f9397
> --- /dev/null
> +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> @@ -0,0 +1,373 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2014 MediaTek Inc.
> + * Author: James Liao <jamesjj.liao@mediatek.com>
> + */
> +
> +#include <linux/device.h>
> +#include <linux/io.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +
> +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
> +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
> +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
> +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
> +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
> +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
> +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
> +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
> +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
> +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
> +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
> +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
> +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
> +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
> +
> +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
> +#define DISP_REG_CONFIG_OUT_SEL 0x04c
> +#define DISP_REG_CONFIG_DSI_SEL 0x050
> +#define DISP_REG_CONFIG_DPI_SEL 0x064
> +
> +#define OVL0_MOUT_EN_COLOR0 0x1
> +#define OD_MOUT_EN_RDMA0 0x1
> +#define OD1_MOUT_EN_RDMA1 BIT(16)
> +#define UFOE_MOUT_EN_DSI0 0x1
> +#define COLOR0_SEL_IN_OVL0 0x1
> +#define OVL1_MOUT_EN_COLOR1 0x1
> +#define GAMMA_MOUT_EN_RDMA1 0x1
> +#define RDMA0_SOUT_DPI0 0x2
> +#define RDMA0_SOUT_DPI1 0x3
> +#define RDMA0_SOUT_DSI1 0x1
> +#define RDMA0_SOUT_DSI2 0x4
> +#define RDMA0_SOUT_DSI3 0x5
> +#define RDMA1_SOUT_DPI0 0x2
> +#define RDMA1_SOUT_DPI1 0x3
> +#define RDMA1_SOUT_DSI1 0x1
> +#define RDMA1_SOUT_DSI2 0x4
> +#define RDMA1_SOUT_DSI3 0x5
> +#define RDMA2_SOUT_DPI0 0x2
> +#define RDMA2_SOUT_DPI1 0x3
> +#define RDMA2_SOUT_DSI1 0x1
> +#define RDMA2_SOUT_DSI2 0x4
> +#define RDMA2_SOUT_DSI3 0x5
> +#define DPI0_SEL_IN_RDMA1 0x1
> +#define DPI0_SEL_IN_RDMA2 0x3
> +#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
> +#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
> +#define DSI0_SEL_IN_RDMA1 0x1
> +#define DSI0_SEL_IN_RDMA2 0x4
> +#define DSI1_SEL_IN_RDMA1 0x1
> +#define DSI1_SEL_IN_RDMA2 0x4
> +#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
> +#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
> +#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
> +#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
> +#define COLOR1_SEL_IN_OVL1 0x1
> +
> +#define OVL_MOUT_EN_RDMA 0x1
> +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
> +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
> +#define DSI_SEL_IN_BLS 0x0
> +#define DPI_SEL_IN_BLS 0x0
> +#define DSI_SEL_IN_RDMA 0x1
> +
> +struct mtk_mmsys_driver_data {
> + const char *clk_driver;
> +};
> +
> +static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> + .clk_driver = "clk-mt2701-mm",
> +};
> +
> +static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
> + .clk_driver = "clk-mt2712-mm",
> +};
> +
> +static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
> + .clk_driver = "clk-mt6779-mm",
> +};
> +
> +static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
> + .clk_driver = "clk-mt6797-mm",
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> + .clk_driver = "clk-mt8173-mm",
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> + .clk_driver = "clk-mt8183-mm",
> +};
> +
> +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + unsigned int *addr)
> +{
> + unsigned int value;
> +
> + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> + value = OVL0_MOUT_EN_COLOR0;
> + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
> + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> + value = OVL_MOUT_EN_RDMA;
> + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
> + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> + value = OD_MOUT_EN_RDMA0;
> + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
> + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> + value = UFOE_MOUT_EN_DSI0;
> + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> + value = OVL1_MOUT_EN_COLOR1;
> + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> + value = GAMMA_MOUT_EN_RDMA1;
> + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> + value = OD1_MOUT_EN_RDMA1;
> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + value = RDMA0_SOUT_DPI0;
> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + value = RDMA0_SOUT_DPI1;
> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + value = RDMA0_SOUT_DSI1;
> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + value = RDMA0_SOUT_DSI2;
> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + value = RDMA0_SOUT_DSI3;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + value = RDMA1_SOUT_DSI1;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + value = RDMA1_SOUT_DSI2;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + value = RDMA1_SOUT_DSI3;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + value = RDMA1_SOUT_DPI0;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + value = RDMA1_SOUT_DPI1;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + value = RDMA2_SOUT_DPI0;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + value = RDMA2_SOUT_DPI1;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + value = RDMA2_SOUT_DSI1;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + value = RDMA2_SOUT_DSI2;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + value = RDMA2_SOUT_DSI3;
> + } else {
> + value = 0;
> + }
> +
> + return value;
> +}
> +
> +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + unsigned int *addr)
> +{
> + unsigned int value;
> +
> + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> + value = COLOR0_SEL_IN_OVL0;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + value = DPI0_SEL_IN_RDMA1;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + value = DPI1_SEL_IN_RDMA1;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + value = DSI0_SEL_IN_RDMA1;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> + *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> + value = DSI1_SEL_IN_RDMA1;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + value = DSI2_SEL_IN_RDMA1;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> + *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> + value = DSI3_SEL_IN_RDMA1;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + value = DPI0_SEL_IN_RDMA2;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + value = DPI1_SEL_IN_RDMA2;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + value = DSI0_SEL_IN_RDMA2;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> + *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> + value = DSI1_SEL_IN_RDMA2;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + value = DSI2_SEL_IN_RDMA2;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + value = DSI3_SEL_IN_RDMA2;
> + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> + value = COLOR1_SEL_IN_OVL1;
> + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> + *addr = DISP_REG_CONFIG_DSI_SEL;
> + value = DSI_SEL_IN_BLS;
> + } else {
> + value = 0;
> + }
> +
> + return value;
> +}
> +
> +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next)
> +{
> + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
> + config_regs + DISP_REG_CONFIG_OUT_SEL);
> + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
> + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
> + config_regs + DISP_REG_CONFIG_OUT_SEL);
> + writel_relaxed(DSI_SEL_IN_RDMA,
> + config_regs + DISP_REG_CONFIG_DSI_SEL);
> + writel_relaxed(DPI_SEL_IN_BLS,
> + config_regs + DISP_REG_CONFIG_DPI_SEL);
> + }
> +}
> +
> +void mtk_mmsys_ddp_connect(struct device *dev,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next)
> +{
> + void __iomem *config_regs = dev_get_drvdata(dev);
> + unsigned int addr, value, reg;
> +
> + value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> + if (value) {
> + reg = readl_relaxed(config_regs + addr) | value;
> + writel_relaxed(reg, config_regs + addr);
> + }
> +
> + mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
> +
> + value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> + if (value) {
> + reg = readl_relaxed(config_regs + addr) | value;
> + writel_relaxed(reg, config_regs + addr);
> + }
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
> +
> +void mtk_mmsys_ddp_disconnect(struct device *dev,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next)
> +{
> + void __iomem *config_regs = dev_get_drvdata(dev);
> + unsigned int addr, value, reg;
> +
> + value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> + if (value) {
> + reg = readl_relaxed(config_regs + addr) & ~value;
> + writel_relaxed(reg, config_regs + addr);
> + }
> +
> + value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> + if (value) {
> + reg = readl_relaxed(config_regs + addr) & ~value;
> + writel_relaxed(reg, config_regs + addr);
> + }
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
> +
> +static int mtk_mmsys_probe(struct platform_device *pdev)
> +{
> + const struct mtk_mmsys_driver_data *data;
> + struct device *dev = &pdev->dev;
> + struct platform_device *clks;
> + struct platform_device *drm;
> + void __iomem *config_regs;
> + int ret;
> +
> + config_regs = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(config_regs)) {
> + ret = PTR_ERR(config_regs);
> + dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
> + return ret;
> + }
> +
> + platform_set_drvdata(pdev, config_regs);
> +
> + data = of_device_get_match_data(&pdev->dev);
> +
> + clks = platform_device_register_data(&pdev->dev, data->clk_driver,
> + PLATFORM_DEVID_AUTO, NULL, 0);
> + if (IS_ERR(clks))
> + return PTR_ERR(clks);
> +
> + drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
> + PLATFORM_DEVID_AUTO, NULL, 0);
> + if (IS_ERR(drm)) {
> + platform_device_unregister(clks);
> + return PTR_ERR(drm);
> + }
> +
> + return 0;
> +}
> +
> +static const struct of_device_id of_match_mtk_mmsys[] = {
> + {
> + .compatible = "mediatek,mt2701-mmsys",
> + .data = &mt2701_mmsys_driver_data,
> + },
> + {
> + .compatible = "mediatek,mt2712-mmsys",
> + .data = &mt2712_mmsys_driver_data,
> + },
> + {
> + .compatible = "mediatek,mt6779-mmsys",
> + .data = &mt6779_mmsys_driver_data,
> + },
> + {
> + .compatible = "mediatek,mt6797-mmsys",
> + .data = &mt6797_mmsys_driver_data,
> + },
> + {
> + .compatible = "mediatek,mt8173-mmsys",
> + .data = &mt8173_mmsys_driver_data,
> + },
> + {
> + .compatible = "mediatek,mt8183-mmsys",
> + .data = &mt8183_mmsys_driver_data,
> + },
> + { }
> +};
> +
> +static struct platform_driver mtk_mmsys_drv = {
> + .driver = {
> + .name = "mtk-mmsys",
> + .of_match_table = of_match_mtk_mmsys,
> + },
> + .probe = mtk_mmsys_probe,
> +};
> +
> +builtin_platform_driver(mtk_mmsys_drv);
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> deleted file mode 100644
> index 18f9397..0000000
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ /dev/null
> @@ -1,373 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * Copyright (c) 2014 MediaTek Inc.
> - * Author: James Liao <jamesjj.liao@mediatek.com>
> - */
> -
> -#include <linux/device.h>
> -#include <linux/io.h>
> -#include <linux/of_device.h>
> -#include <linux/platform_device.h>
> -#include <linux/soc/mediatek/mtk-mmsys.h>
> -
> -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
> -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
> -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
> -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
> -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
> -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
> -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
> -#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
> -#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
> -#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
> -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
> -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
> -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
> -#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
> -
> -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
> -#define DISP_REG_CONFIG_OUT_SEL 0x04c
> -#define DISP_REG_CONFIG_DSI_SEL 0x050
> -#define DISP_REG_CONFIG_DPI_SEL 0x064
> -
> -#define OVL0_MOUT_EN_COLOR0 0x1
> -#define OD_MOUT_EN_RDMA0 0x1
> -#define OD1_MOUT_EN_RDMA1 BIT(16)
> -#define UFOE_MOUT_EN_DSI0 0x1
> -#define COLOR0_SEL_IN_OVL0 0x1
> -#define OVL1_MOUT_EN_COLOR1 0x1
> -#define GAMMA_MOUT_EN_RDMA1 0x1
> -#define RDMA0_SOUT_DPI0 0x2
> -#define RDMA0_SOUT_DPI1 0x3
> -#define RDMA0_SOUT_DSI1 0x1
> -#define RDMA0_SOUT_DSI2 0x4
> -#define RDMA0_SOUT_DSI3 0x5
> -#define RDMA1_SOUT_DPI0 0x2
> -#define RDMA1_SOUT_DPI1 0x3
> -#define RDMA1_SOUT_DSI1 0x1
> -#define RDMA1_SOUT_DSI2 0x4
> -#define RDMA1_SOUT_DSI3 0x5
> -#define RDMA2_SOUT_DPI0 0x2
> -#define RDMA2_SOUT_DPI1 0x3
> -#define RDMA2_SOUT_DSI1 0x1
> -#define RDMA2_SOUT_DSI2 0x4
> -#define RDMA2_SOUT_DSI3 0x5
> -#define DPI0_SEL_IN_RDMA1 0x1
> -#define DPI0_SEL_IN_RDMA2 0x3
> -#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
> -#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
> -#define DSI0_SEL_IN_RDMA1 0x1
> -#define DSI0_SEL_IN_RDMA2 0x4
> -#define DSI1_SEL_IN_RDMA1 0x1
> -#define DSI1_SEL_IN_RDMA2 0x4
> -#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
> -#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
> -#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
> -#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
> -#define COLOR1_SEL_IN_OVL1 0x1
> -
> -#define OVL_MOUT_EN_RDMA 0x1
> -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
> -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
> -#define DSI_SEL_IN_BLS 0x0
> -#define DPI_SEL_IN_BLS 0x0
> -#define DSI_SEL_IN_RDMA 0x1
> -
> -struct mtk_mmsys_driver_data {
> - const char *clk_driver;
> -};
> -
> -static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> - .clk_driver = "clk-mt2701-mm",
> -};
> -
> -static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
> - .clk_driver = "clk-mt2712-mm",
> -};
> -
> -static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
> - .clk_driver = "clk-mt6779-mm",
> -};
> -
> -static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
> - .clk_driver = "clk-mt6797-mm",
> -};
> -
> -static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> - .clk_driver = "clk-mt8173-mm",
> -};
> -
> -static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> - .clk_driver = "clk-mt8183-mm",
> -};
> -
> -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
> - enum mtk_ddp_comp_id next,
> - unsigned int *addr)
> -{
> - unsigned int value;
> -
> - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> - value = OVL0_MOUT_EN_COLOR0;
> - } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
> - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> - value = OVL_MOUT_EN_RDMA;
> - } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> - value = OD_MOUT_EN_RDMA0;
> - } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> - value = UFOE_MOUT_EN_DSI0;
> - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> - value = OVL1_MOUT_EN_COLOR1;
> - } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> - value = GAMMA_MOUT_EN_RDMA1;
> - } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> - value = OD1_MOUT_EN_RDMA1;
> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> - value = RDMA0_SOUT_DPI0;
> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> - value = RDMA0_SOUT_DPI1;
> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> - value = RDMA0_SOUT_DSI1;
> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> - value = RDMA0_SOUT_DSI2;
> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> - value = RDMA0_SOUT_DSI3;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> - value = RDMA1_SOUT_DSI1;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> - value = RDMA1_SOUT_DSI2;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> - value = RDMA1_SOUT_DSI3;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> - value = RDMA1_SOUT_DPI0;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> - value = RDMA1_SOUT_DPI1;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> - value = RDMA2_SOUT_DPI0;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> - value = RDMA2_SOUT_DPI1;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> - value = RDMA2_SOUT_DSI1;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> - value = RDMA2_SOUT_DSI2;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> - value = RDMA2_SOUT_DSI3;
> - } else {
> - value = 0;
> - }
> -
> - return value;
> -}
> -
> -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
> - enum mtk_ddp_comp_id next,
> - unsigned int *addr)
> -{
> - unsigned int value;
> -
> - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> - value = COLOR0_SEL_IN_OVL0;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> - value = DPI0_SEL_IN_RDMA1;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> - value = DPI1_SEL_IN_RDMA1;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> - value = DSI0_SEL_IN_RDMA1;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> - value = DSI1_SEL_IN_RDMA1;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> - value = DSI2_SEL_IN_RDMA1;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> - value = DSI3_SEL_IN_RDMA1;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> - value = DPI0_SEL_IN_RDMA2;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> - value = DPI1_SEL_IN_RDMA2;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> - value = DSI0_SEL_IN_RDMA2;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> - value = DSI1_SEL_IN_RDMA2;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> - value = DSI2_SEL_IN_RDMA2;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> - value = DSI3_SEL_IN_RDMA2;
> - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> - value = COLOR1_SEL_IN_OVL1;
> - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DSI_SEL;
> - value = DSI_SEL_IN_BLS;
> - } else {
> - value = 0;
> - }
> -
> - return value;
> -}
> -
> -static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
> - enum mtk_ddp_comp_id cur,
> - enum mtk_ddp_comp_id next)
> -{
> - if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
> - config_regs + DISP_REG_CONFIG_OUT_SEL);
> - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
> - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
> - config_regs + DISP_REG_CONFIG_OUT_SEL);
> - writel_relaxed(DSI_SEL_IN_RDMA,
> - config_regs + DISP_REG_CONFIG_DSI_SEL);
> - writel_relaxed(DPI_SEL_IN_BLS,
> - config_regs + DISP_REG_CONFIG_DPI_SEL);
> - }
> -}
> -
> -void mtk_mmsys_ddp_connect(struct device *dev,
> - enum mtk_ddp_comp_id cur,
> - enum mtk_ddp_comp_id next)
> -{
> - void __iomem *config_regs = dev_get_drvdata(dev);
> - unsigned int addr, value, reg;
> -
> - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> - if (value) {
> - reg = readl_relaxed(config_regs + addr) | value;
> - writel_relaxed(reg, config_regs + addr);
> - }
> -
> - mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
> -
> - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> - if (value) {
> - reg = readl_relaxed(config_regs + addr) | value;
> - writel_relaxed(reg, config_regs + addr);
> - }
> -}
> -EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
> -
> -void mtk_mmsys_ddp_disconnect(struct device *dev,
> - enum mtk_ddp_comp_id cur,
> - enum mtk_ddp_comp_id next)
> -{
> - void __iomem *config_regs = dev_get_drvdata(dev);
> - unsigned int addr, value, reg;
> -
> - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> - if (value) {
> - reg = readl_relaxed(config_regs + addr) & ~value;
> - writel_relaxed(reg, config_regs + addr);
> - }
> -
> - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> - if (value) {
> - reg = readl_relaxed(config_regs + addr) & ~value;
> - writel_relaxed(reg, config_regs + addr);
> - }
> -}
> -EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
> -
> -static int mtk_mmsys_probe(struct platform_device *pdev)
> -{
> - const struct mtk_mmsys_driver_data *data;
> - struct device *dev = &pdev->dev;
> - struct platform_device *clks;
> - struct platform_device *drm;
> - void __iomem *config_regs;
> - int ret;
> -
> - config_regs = devm_platform_ioremap_resource(pdev, 0);
> - if (IS_ERR(config_regs)) {
> - ret = PTR_ERR(config_regs);
> - dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
> - return ret;
> - }
> -
> - platform_set_drvdata(pdev, config_regs);
> -
> - data = of_device_get_match_data(&pdev->dev);
> -
> - clks = platform_device_register_data(&pdev->dev, data->clk_driver,
> - PLATFORM_DEVID_AUTO, NULL, 0);
> - if (IS_ERR(clks))
> - return PTR_ERR(clks);
> -
> - drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
> - PLATFORM_DEVID_AUTO, NULL, 0);
> - if (IS_ERR(drm)) {
> - platform_device_unregister(clks);
> - return PTR_ERR(drm);
> - }
> -
> - return 0;
> -}
> -
> -static const struct of_device_id of_match_mtk_mmsys[] = {
> - {
> - .compatible = "mediatek,mt2701-mmsys",
> - .data = &mt2701_mmsys_driver_data,
> - },
> - {
> - .compatible = "mediatek,mt2712-mmsys",
> - .data = &mt2712_mmsys_driver_data,
> - },
> - {
> - .compatible = "mediatek,mt6779-mmsys",
> - .data = &mt6779_mmsys_driver_data,
> - },
> - {
> - .compatible = "mediatek,mt6797-mmsys",
> - .data = &mt6797_mmsys_driver_data,
> - },
> - {
> - .compatible = "mediatek,mt8173-mmsys",
> - .data = &mt8173_mmsys_driver_data,
> - },
> - {
> - .compatible = "mediatek,mt8183-mmsys",
> - .data = &mt8183_mmsys_driver_data,
> - },
> - { }
> -};
> -
> -static struct platform_driver mtk_mmsys_drv = {
> - .driver = {
> - .name = "mtk-mmsys",
> - .of_match_table = of_match_mtk_mmsys,
> - },
> - .probe = mtk_mmsys_probe,
> -};
> -
> -builtin_platform_driver(mtk_mmsys_drv);
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
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^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4, 01/10] soc: mediatek: mmsys: create mmsys folder
@ 2021-02-09 15:38 ` Enric Balletbo Serra
0 siblings, 0 replies; 75+ messages in thread
From: Enric Balletbo Serra @ 2021-02-09 15:38 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, devicetree, Daniel Vetter, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
Matthias Brugger, Rob Herring,
moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu,
Linux ARM
Hi Yongqiang Niu,
Thank you for your patch.
Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dt., 5
de gen. 2021 a les 4:07:
>
> the mmsys will more and more complicated after support
> more and more SoCs, add an independent folder will be
> more clear
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/soc/mediatek/Makefile | 2 +-
It will not apply cleanly anymore after the below commit that is
already queued. Maybe you could rebase the patches and resend them
again?
commit e1e4f7fea37572f0ccf3887430e52c491e9accb6
Author: CK Hu <ck.hu@mediatek.com>
Date: Tue Jul 21 15:46:06 2020 +0800
soc / drm: mediatek: Move mtk mutex driver to soc folder
mtk mutex is used by DRM and MDP driver, and its function is SoC-specific,
so move it to soc folder.
With that fixed,
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Thanks,
Enric
> drivers/soc/mediatek/mmsys/Makefile | 2 +
> drivers/soc/mediatek/mmsys/mtk-mmsys.c | 373 +++++++++++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 373 ---------------------------------
> 4 files changed, 376 insertions(+), 374 deletions(-)
> create mode 100644 drivers/soc/mediatek/mmsys/Makefile
> create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c
> delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c
>
> diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> index b6908db..eca9774 100644
> --- a/drivers/soc/mediatek/Makefile
> +++ b/drivers/soc/mediatek/Makefile
> @@ -5,4 +5,4 @@ obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
> obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
> obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
> obj-$(CONFIG_MTK_SCPSYS_PM_DOMAINS) += mtk-pm-domains.o
> -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
> +obj-$(CONFIG_MTK_MMSYS) += mmsys/
> diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
> new file mode 100644
> index 0000000..f44eadc
> --- /dev/null
> +++ b/drivers/soc/mediatek/mmsys/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
> diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> new file mode 100644
> index 0000000..18f9397
> --- /dev/null
> +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> @@ -0,0 +1,373 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2014 MediaTek Inc.
> + * Author: James Liao <jamesjj.liao@mediatek.com>
> + */
> +
> +#include <linux/device.h>
> +#include <linux/io.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +
> +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
> +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
> +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
> +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
> +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
> +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
> +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
> +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
> +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
> +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
> +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
> +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
> +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
> +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
> +
> +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
> +#define DISP_REG_CONFIG_OUT_SEL 0x04c
> +#define DISP_REG_CONFIG_DSI_SEL 0x050
> +#define DISP_REG_CONFIG_DPI_SEL 0x064
> +
> +#define OVL0_MOUT_EN_COLOR0 0x1
> +#define OD_MOUT_EN_RDMA0 0x1
> +#define OD1_MOUT_EN_RDMA1 BIT(16)
> +#define UFOE_MOUT_EN_DSI0 0x1
> +#define COLOR0_SEL_IN_OVL0 0x1
> +#define OVL1_MOUT_EN_COLOR1 0x1
> +#define GAMMA_MOUT_EN_RDMA1 0x1
> +#define RDMA0_SOUT_DPI0 0x2
> +#define RDMA0_SOUT_DPI1 0x3
> +#define RDMA0_SOUT_DSI1 0x1
> +#define RDMA0_SOUT_DSI2 0x4
> +#define RDMA0_SOUT_DSI3 0x5
> +#define RDMA1_SOUT_DPI0 0x2
> +#define RDMA1_SOUT_DPI1 0x3
> +#define RDMA1_SOUT_DSI1 0x1
> +#define RDMA1_SOUT_DSI2 0x4
> +#define RDMA1_SOUT_DSI3 0x5
> +#define RDMA2_SOUT_DPI0 0x2
> +#define RDMA2_SOUT_DPI1 0x3
> +#define RDMA2_SOUT_DSI1 0x1
> +#define RDMA2_SOUT_DSI2 0x4
> +#define RDMA2_SOUT_DSI3 0x5
> +#define DPI0_SEL_IN_RDMA1 0x1
> +#define DPI0_SEL_IN_RDMA2 0x3
> +#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
> +#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
> +#define DSI0_SEL_IN_RDMA1 0x1
> +#define DSI0_SEL_IN_RDMA2 0x4
> +#define DSI1_SEL_IN_RDMA1 0x1
> +#define DSI1_SEL_IN_RDMA2 0x4
> +#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
> +#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
> +#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
> +#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
> +#define COLOR1_SEL_IN_OVL1 0x1
> +
> +#define OVL_MOUT_EN_RDMA 0x1
> +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
> +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
> +#define DSI_SEL_IN_BLS 0x0
> +#define DPI_SEL_IN_BLS 0x0
> +#define DSI_SEL_IN_RDMA 0x1
> +
> +struct mtk_mmsys_driver_data {
> + const char *clk_driver;
> +};
> +
> +static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> + .clk_driver = "clk-mt2701-mm",
> +};
> +
> +static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
> + .clk_driver = "clk-mt2712-mm",
> +};
> +
> +static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
> + .clk_driver = "clk-mt6779-mm",
> +};
> +
> +static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
> + .clk_driver = "clk-mt6797-mm",
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> + .clk_driver = "clk-mt8173-mm",
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> + .clk_driver = "clk-mt8183-mm",
> +};
> +
> +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + unsigned int *addr)
> +{
> + unsigned int value;
> +
> + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> + value = OVL0_MOUT_EN_COLOR0;
> + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
> + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> + value = OVL_MOUT_EN_RDMA;
> + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
> + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> + value = OD_MOUT_EN_RDMA0;
> + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
> + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> + value = UFOE_MOUT_EN_DSI0;
> + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> + value = OVL1_MOUT_EN_COLOR1;
> + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> + value = GAMMA_MOUT_EN_RDMA1;
> + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> + value = OD1_MOUT_EN_RDMA1;
> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + value = RDMA0_SOUT_DPI0;
> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + value = RDMA0_SOUT_DPI1;
> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + value = RDMA0_SOUT_DSI1;
> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + value = RDMA0_SOUT_DSI2;
> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + value = RDMA0_SOUT_DSI3;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + value = RDMA1_SOUT_DSI1;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + value = RDMA1_SOUT_DSI2;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + value = RDMA1_SOUT_DSI3;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + value = RDMA1_SOUT_DPI0;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + value = RDMA1_SOUT_DPI1;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + value = RDMA2_SOUT_DPI0;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + value = RDMA2_SOUT_DPI1;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + value = RDMA2_SOUT_DSI1;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + value = RDMA2_SOUT_DSI2;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + value = RDMA2_SOUT_DSI3;
> + } else {
> + value = 0;
> + }
> +
> + return value;
> +}
> +
> +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + unsigned int *addr)
> +{
> + unsigned int value;
> +
> + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> + value = COLOR0_SEL_IN_OVL0;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + value = DPI0_SEL_IN_RDMA1;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + value = DPI1_SEL_IN_RDMA1;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + value = DSI0_SEL_IN_RDMA1;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> + *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> + value = DSI1_SEL_IN_RDMA1;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + value = DSI2_SEL_IN_RDMA1;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> + *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> + value = DSI3_SEL_IN_RDMA1;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + value = DPI0_SEL_IN_RDMA2;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + value = DPI1_SEL_IN_RDMA2;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + value = DSI0_SEL_IN_RDMA2;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> + *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> + value = DSI1_SEL_IN_RDMA2;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + value = DSI2_SEL_IN_RDMA2;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + value = DSI3_SEL_IN_RDMA2;
> + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> + value = COLOR1_SEL_IN_OVL1;
> + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> + *addr = DISP_REG_CONFIG_DSI_SEL;
> + value = DSI_SEL_IN_BLS;
> + } else {
> + value = 0;
> + }
> +
> + return value;
> +}
> +
> +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next)
> +{
> + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
> + config_regs + DISP_REG_CONFIG_OUT_SEL);
> + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
> + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
> + config_regs + DISP_REG_CONFIG_OUT_SEL);
> + writel_relaxed(DSI_SEL_IN_RDMA,
> + config_regs + DISP_REG_CONFIG_DSI_SEL);
> + writel_relaxed(DPI_SEL_IN_BLS,
> + config_regs + DISP_REG_CONFIG_DPI_SEL);
> + }
> +}
> +
> +void mtk_mmsys_ddp_connect(struct device *dev,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next)
> +{
> + void __iomem *config_regs = dev_get_drvdata(dev);
> + unsigned int addr, value, reg;
> +
> + value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> + if (value) {
> + reg = readl_relaxed(config_regs + addr) | value;
> + writel_relaxed(reg, config_regs + addr);
> + }
> +
> + mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
> +
> + value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> + if (value) {
> + reg = readl_relaxed(config_regs + addr) | value;
> + writel_relaxed(reg, config_regs + addr);
> + }
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
> +
> +void mtk_mmsys_ddp_disconnect(struct device *dev,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next)
> +{
> + void __iomem *config_regs = dev_get_drvdata(dev);
> + unsigned int addr, value, reg;
> +
> + value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> + if (value) {
> + reg = readl_relaxed(config_regs + addr) & ~value;
> + writel_relaxed(reg, config_regs + addr);
> + }
> +
> + value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> + if (value) {
> + reg = readl_relaxed(config_regs + addr) & ~value;
> + writel_relaxed(reg, config_regs + addr);
> + }
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
> +
> +static int mtk_mmsys_probe(struct platform_device *pdev)
> +{
> + const struct mtk_mmsys_driver_data *data;
> + struct device *dev = &pdev->dev;
> + struct platform_device *clks;
> + struct platform_device *drm;
> + void __iomem *config_regs;
> + int ret;
> +
> + config_regs = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(config_regs)) {
> + ret = PTR_ERR(config_regs);
> + dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
> + return ret;
> + }
> +
> + platform_set_drvdata(pdev, config_regs);
> +
> + data = of_device_get_match_data(&pdev->dev);
> +
> + clks = platform_device_register_data(&pdev->dev, data->clk_driver,
> + PLATFORM_DEVID_AUTO, NULL, 0);
> + if (IS_ERR(clks))
> + return PTR_ERR(clks);
> +
> + drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
> + PLATFORM_DEVID_AUTO, NULL, 0);
> + if (IS_ERR(drm)) {
> + platform_device_unregister(clks);
> + return PTR_ERR(drm);
> + }
> +
> + return 0;
> +}
> +
> +static const struct of_device_id of_match_mtk_mmsys[] = {
> + {
> + .compatible = "mediatek,mt2701-mmsys",
> + .data = &mt2701_mmsys_driver_data,
> + },
> + {
> + .compatible = "mediatek,mt2712-mmsys",
> + .data = &mt2712_mmsys_driver_data,
> + },
> + {
> + .compatible = "mediatek,mt6779-mmsys",
> + .data = &mt6779_mmsys_driver_data,
> + },
> + {
> + .compatible = "mediatek,mt6797-mmsys",
> + .data = &mt6797_mmsys_driver_data,
> + },
> + {
> + .compatible = "mediatek,mt8173-mmsys",
> + .data = &mt8173_mmsys_driver_data,
> + },
> + {
> + .compatible = "mediatek,mt8183-mmsys",
> + .data = &mt8183_mmsys_driver_data,
> + },
> + { }
> +};
> +
> +static struct platform_driver mtk_mmsys_drv = {
> + .driver = {
> + .name = "mtk-mmsys",
> + .of_match_table = of_match_mtk_mmsys,
> + },
> + .probe = mtk_mmsys_probe,
> +};
> +
> +builtin_platform_driver(mtk_mmsys_drv);
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> deleted file mode 100644
> index 18f9397..0000000
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ /dev/null
> @@ -1,373 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * Copyright (c) 2014 MediaTek Inc.
> - * Author: James Liao <jamesjj.liao@mediatek.com>
> - */
> -
> -#include <linux/device.h>
> -#include <linux/io.h>
> -#include <linux/of_device.h>
> -#include <linux/platform_device.h>
> -#include <linux/soc/mediatek/mtk-mmsys.h>
> -
> -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
> -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
> -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
> -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
> -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
> -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
> -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
> -#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
> -#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
> -#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
> -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
> -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
> -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
> -#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
> -
> -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
> -#define DISP_REG_CONFIG_OUT_SEL 0x04c
> -#define DISP_REG_CONFIG_DSI_SEL 0x050
> -#define DISP_REG_CONFIG_DPI_SEL 0x064
> -
> -#define OVL0_MOUT_EN_COLOR0 0x1
> -#define OD_MOUT_EN_RDMA0 0x1
> -#define OD1_MOUT_EN_RDMA1 BIT(16)
> -#define UFOE_MOUT_EN_DSI0 0x1
> -#define COLOR0_SEL_IN_OVL0 0x1
> -#define OVL1_MOUT_EN_COLOR1 0x1
> -#define GAMMA_MOUT_EN_RDMA1 0x1
> -#define RDMA0_SOUT_DPI0 0x2
> -#define RDMA0_SOUT_DPI1 0x3
> -#define RDMA0_SOUT_DSI1 0x1
> -#define RDMA0_SOUT_DSI2 0x4
> -#define RDMA0_SOUT_DSI3 0x5
> -#define RDMA1_SOUT_DPI0 0x2
> -#define RDMA1_SOUT_DPI1 0x3
> -#define RDMA1_SOUT_DSI1 0x1
> -#define RDMA1_SOUT_DSI2 0x4
> -#define RDMA1_SOUT_DSI3 0x5
> -#define RDMA2_SOUT_DPI0 0x2
> -#define RDMA2_SOUT_DPI1 0x3
> -#define RDMA2_SOUT_DSI1 0x1
> -#define RDMA2_SOUT_DSI2 0x4
> -#define RDMA2_SOUT_DSI3 0x5
> -#define DPI0_SEL_IN_RDMA1 0x1
> -#define DPI0_SEL_IN_RDMA2 0x3
> -#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
> -#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
> -#define DSI0_SEL_IN_RDMA1 0x1
> -#define DSI0_SEL_IN_RDMA2 0x4
> -#define DSI1_SEL_IN_RDMA1 0x1
> -#define DSI1_SEL_IN_RDMA2 0x4
> -#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
> -#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
> -#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
> -#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
> -#define COLOR1_SEL_IN_OVL1 0x1
> -
> -#define OVL_MOUT_EN_RDMA 0x1
> -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
> -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
> -#define DSI_SEL_IN_BLS 0x0
> -#define DPI_SEL_IN_BLS 0x0
> -#define DSI_SEL_IN_RDMA 0x1
> -
> -struct mtk_mmsys_driver_data {
> - const char *clk_driver;
> -};
> -
> -static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> - .clk_driver = "clk-mt2701-mm",
> -};
> -
> -static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
> - .clk_driver = "clk-mt2712-mm",
> -};
> -
> -static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
> - .clk_driver = "clk-mt6779-mm",
> -};
> -
> -static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
> - .clk_driver = "clk-mt6797-mm",
> -};
> -
> -static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> - .clk_driver = "clk-mt8173-mm",
> -};
> -
> -static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> - .clk_driver = "clk-mt8183-mm",
> -};
> -
> -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
> - enum mtk_ddp_comp_id next,
> - unsigned int *addr)
> -{
> - unsigned int value;
> -
> - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> - value = OVL0_MOUT_EN_COLOR0;
> - } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
> - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> - value = OVL_MOUT_EN_RDMA;
> - } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> - value = OD_MOUT_EN_RDMA0;
> - } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> - value = UFOE_MOUT_EN_DSI0;
> - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> - value = OVL1_MOUT_EN_COLOR1;
> - } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> - value = GAMMA_MOUT_EN_RDMA1;
> - } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> - value = OD1_MOUT_EN_RDMA1;
> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> - value = RDMA0_SOUT_DPI0;
> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> - value = RDMA0_SOUT_DPI1;
> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> - value = RDMA0_SOUT_DSI1;
> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> - value = RDMA0_SOUT_DSI2;
> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> - value = RDMA0_SOUT_DSI3;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> - value = RDMA1_SOUT_DSI1;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> - value = RDMA1_SOUT_DSI2;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> - value = RDMA1_SOUT_DSI3;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> - value = RDMA1_SOUT_DPI0;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> - value = RDMA1_SOUT_DPI1;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> - value = RDMA2_SOUT_DPI0;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> - value = RDMA2_SOUT_DPI1;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> - value = RDMA2_SOUT_DSI1;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> - value = RDMA2_SOUT_DSI2;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> - value = RDMA2_SOUT_DSI3;
> - } else {
> - value = 0;
> - }
> -
> - return value;
> -}
> -
> -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
> - enum mtk_ddp_comp_id next,
> - unsigned int *addr)
> -{
> - unsigned int value;
> -
> - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> - value = COLOR0_SEL_IN_OVL0;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> - value = DPI0_SEL_IN_RDMA1;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> - value = DPI1_SEL_IN_RDMA1;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> - value = DSI0_SEL_IN_RDMA1;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> - value = DSI1_SEL_IN_RDMA1;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> - value = DSI2_SEL_IN_RDMA1;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> - value = DSI3_SEL_IN_RDMA1;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> - value = DPI0_SEL_IN_RDMA2;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> - value = DPI1_SEL_IN_RDMA2;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> - value = DSI0_SEL_IN_RDMA2;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> - value = DSI1_SEL_IN_RDMA2;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> - value = DSI2_SEL_IN_RDMA2;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> - value = DSI3_SEL_IN_RDMA2;
> - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> - value = COLOR1_SEL_IN_OVL1;
> - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DSI_SEL;
> - value = DSI_SEL_IN_BLS;
> - } else {
> - value = 0;
> - }
> -
> - return value;
> -}
> -
> -static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
> - enum mtk_ddp_comp_id cur,
> - enum mtk_ddp_comp_id next)
> -{
> - if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
> - config_regs + DISP_REG_CONFIG_OUT_SEL);
> - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
> - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
> - config_regs + DISP_REG_CONFIG_OUT_SEL);
> - writel_relaxed(DSI_SEL_IN_RDMA,
> - config_regs + DISP_REG_CONFIG_DSI_SEL);
> - writel_relaxed(DPI_SEL_IN_BLS,
> - config_regs + DISP_REG_CONFIG_DPI_SEL);
> - }
> -}
> -
> -void mtk_mmsys_ddp_connect(struct device *dev,
> - enum mtk_ddp_comp_id cur,
> - enum mtk_ddp_comp_id next)
> -{
> - void __iomem *config_regs = dev_get_drvdata(dev);
> - unsigned int addr, value, reg;
> -
> - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> - if (value) {
> - reg = readl_relaxed(config_regs + addr) | value;
> - writel_relaxed(reg, config_regs + addr);
> - }
> -
> - mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
> -
> - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> - if (value) {
> - reg = readl_relaxed(config_regs + addr) | value;
> - writel_relaxed(reg, config_regs + addr);
> - }
> -}
> -EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
> -
> -void mtk_mmsys_ddp_disconnect(struct device *dev,
> - enum mtk_ddp_comp_id cur,
> - enum mtk_ddp_comp_id next)
> -{
> - void __iomem *config_regs = dev_get_drvdata(dev);
> - unsigned int addr, value, reg;
> -
> - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> - if (value) {
> - reg = readl_relaxed(config_regs + addr) & ~value;
> - writel_relaxed(reg, config_regs + addr);
> - }
> -
> - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> - if (value) {
> - reg = readl_relaxed(config_regs + addr) & ~value;
> - writel_relaxed(reg, config_regs + addr);
> - }
> -}
> -EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
> -
> -static int mtk_mmsys_probe(struct platform_device *pdev)
> -{
> - const struct mtk_mmsys_driver_data *data;
> - struct device *dev = &pdev->dev;
> - struct platform_device *clks;
> - struct platform_device *drm;
> - void __iomem *config_regs;
> - int ret;
> -
> - config_regs = devm_platform_ioremap_resource(pdev, 0);
> - if (IS_ERR(config_regs)) {
> - ret = PTR_ERR(config_regs);
> - dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
> - return ret;
> - }
> -
> - platform_set_drvdata(pdev, config_regs);
> -
> - data = of_device_get_match_data(&pdev->dev);
> -
> - clks = platform_device_register_data(&pdev->dev, data->clk_driver,
> - PLATFORM_DEVID_AUTO, NULL, 0);
> - if (IS_ERR(clks))
> - return PTR_ERR(clks);
> -
> - drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
> - PLATFORM_DEVID_AUTO, NULL, 0);
> - if (IS_ERR(drm)) {
> - platform_device_unregister(clks);
> - return PTR_ERR(drm);
> - }
> -
> - return 0;
> -}
> -
> -static const struct of_device_id of_match_mtk_mmsys[] = {
> - {
> - .compatible = "mediatek,mt2701-mmsys",
> - .data = &mt2701_mmsys_driver_data,
> - },
> - {
> - .compatible = "mediatek,mt2712-mmsys",
> - .data = &mt2712_mmsys_driver_data,
> - },
> - {
> - .compatible = "mediatek,mt6779-mmsys",
> - .data = &mt6779_mmsys_driver_data,
> - },
> - {
> - .compatible = "mediatek,mt6797-mmsys",
> - .data = &mt6797_mmsys_driver_data,
> - },
> - {
> - .compatible = "mediatek,mt8173-mmsys",
> - .data = &mt8173_mmsys_driver_data,
> - },
> - {
> - .compatible = "mediatek,mt8183-mmsys",
> - .data = &mt8183_mmsys_driver_data,
> - },
> - { }
> -};
> -
> -static struct platform_driver mtk_mmsys_drv = {
> - .driver = {
> - .name = "mtk-mmsys",
> - .of_match_table = of_match_mtk_mmsys,
> - },
> - .probe = mtk_mmsys_probe,
> -};
> -
> -builtin_platform_driver(mtk_mmsys_drv);
> --
> 1.8.1.1.dirty
> _______________________________________________
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> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
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^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4, 01/10] soc: mediatek: mmsys: create mmsys folder
@ 2021-02-09 15:38 ` Enric Balletbo Serra
0 siblings, 0 replies; 75+ messages in thread
From: Enric Balletbo Serra @ 2021-02-09 15:38 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Matthias Brugger,
Rob Herring, moderated list:ARM/Mediatek SoC support, Linux ARM
Hi Yongqiang Niu,
Thank you for your patch.
Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dt., 5
de gen. 2021 a les 4:07:
>
> the mmsys will more and more complicated after support
> more and more SoCs, add an independent folder will be
> more clear
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/soc/mediatek/Makefile | 2 +-
It will not apply cleanly anymore after the below commit that is
already queued. Maybe you could rebase the patches and resend them
again?
commit e1e4f7fea37572f0ccf3887430e52c491e9accb6
Author: CK Hu <ck.hu@mediatek.com>
Date: Tue Jul 21 15:46:06 2020 +0800
soc / drm: mediatek: Move mtk mutex driver to soc folder
mtk mutex is used by DRM and MDP driver, and its function is SoC-specific,
so move it to soc folder.
With that fixed,
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Thanks,
Enric
> drivers/soc/mediatek/mmsys/Makefile | 2 +
> drivers/soc/mediatek/mmsys/mtk-mmsys.c | 373 +++++++++++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 373 ---------------------------------
> 4 files changed, 376 insertions(+), 374 deletions(-)
> create mode 100644 drivers/soc/mediatek/mmsys/Makefile
> create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c
> delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c
>
> diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> index b6908db..eca9774 100644
> --- a/drivers/soc/mediatek/Makefile
> +++ b/drivers/soc/mediatek/Makefile
> @@ -5,4 +5,4 @@ obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
> obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
> obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
> obj-$(CONFIG_MTK_SCPSYS_PM_DOMAINS) += mtk-pm-domains.o
> -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
> +obj-$(CONFIG_MTK_MMSYS) += mmsys/
> diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
> new file mode 100644
> index 0000000..f44eadc
> --- /dev/null
> +++ b/drivers/soc/mediatek/mmsys/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
> diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> new file mode 100644
> index 0000000..18f9397
> --- /dev/null
> +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> @@ -0,0 +1,373 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2014 MediaTek Inc.
> + * Author: James Liao <jamesjj.liao@mediatek.com>
> + */
> +
> +#include <linux/device.h>
> +#include <linux/io.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +
> +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
> +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
> +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
> +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
> +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
> +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
> +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
> +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
> +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
> +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
> +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
> +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
> +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
> +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
> +
> +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
> +#define DISP_REG_CONFIG_OUT_SEL 0x04c
> +#define DISP_REG_CONFIG_DSI_SEL 0x050
> +#define DISP_REG_CONFIG_DPI_SEL 0x064
> +
> +#define OVL0_MOUT_EN_COLOR0 0x1
> +#define OD_MOUT_EN_RDMA0 0x1
> +#define OD1_MOUT_EN_RDMA1 BIT(16)
> +#define UFOE_MOUT_EN_DSI0 0x1
> +#define COLOR0_SEL_IN_OVL0 0x1
> +#define OVL1_MOUT_EN_COLOR1 0x1
> +#define GAMMA_MOUT_EN_RDMA1 0x1
> +#define RDMA0_SOUT_DPI0 0x2
> +#define RDMA0_SOUT_DPI1 0x3
> +#define RDMA0_SOUT_DSI1 0x1
> +#define RDMA0_SOUT_DSI2 0x4
> +#define RDMA0_SOUT_DSI3 0x5
> +#define RDMA1_SOUT_DPI0 0x2
> +#define RDMA1_SOUT_DPI1 0x3
> +#define RDMA1_SOUT_DSI1 0x1
> +#define RDMA1_SOUT_DSI2 0x4
> +#define RDMA1_SOUT_DSI3 0x5
> +#define RDMA2_SOUT_DPI0 0x2
> +#define RDMA2_SOUT_DPI1 0x3
> +#define RDMA2_SOUT_DSI1 0x1
> +#define RDMA2_SOUT_DSI2 0x4
> +#define RDMA2_SOUT_DSI3 0x5
> +#define DPI0_SEL_IN_RDMA1 0x1
> +#define DPI0_SEL_IN_RDMA2 0x3
> +#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
> +#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
> +#define DSI0_SEL_IN_RDMA1 0x1
> +#define DSI0_SEL_IN_RDMA2 0x4
> +#define DSI1_SEL_IN_RDMA1 0x1
> +#define DSI1_SEL_IN_RDMA2 0x4
> +#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
> +#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
> +#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
> +#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
> +#define COLOR1_SEL_IN_OVL1 0x1
> +
> +#define OVL_MOUT_EN_RDMA 0x1
> +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
> +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
> +#define DSI_SEL_IN_BLS 0x0
> +#define DPI_SEL_IN_BLS 0x0
> +#define DSI_SEL_IN_RDMA 0x1
> +
> +struct mtk_mmsys_driver_data {
> + const char *clk_driver;
> +};
> +
> +static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> + .clk_driver = "clk-mt2701-mm",
> +};
> +
> +static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
> + .clk_driver = "clk-mt2712-mm",
> +};
> +
> +static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
> + .clk_driver = "clk-mt6779-mm",
> +};
> +
> +static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
> + .clk_driver = "clk-mt6797-mm",
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> + .clk_driver = "clk-mt8173-mm",
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> + .clk_driver = "clk-mt8183-mm",
> +};
> +
> +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + unsigned int *addr)
> +{
> + unsigned int value;
> +
> + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> + value = OVL0_MOUT_EN_COLOR0;
> + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
> + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> + value = OVL_MOUT_EN_RDMA;
> + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
> + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> + value = OD_MOUT_EN_RDMA0;
> + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
> + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> + value = UFOE_MOUT_EN_DSI0;
> + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> + value = OVL1_MOUT_EN_COLOR1;
> + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> + value = GAMMA_MOUT_EN_RDMA1;
> + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> + value = OD1_MOUT_EN_RDMA1;
> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + value = RDMA0_SOUT_DPI0;
> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + value = RDMA0_SOUT_DPI1;
> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + value = RDMA0_SOUT_DSI1;
> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + value = RDMA0_SOUT_DSI2;
> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + value = RDMA0_SOUT_DSI3;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + value = RDMA1_SOUT_DSI1;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + value = RDMA1_SOUT_DSI2;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + value = RDMA1_SOUT_DSI3;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + value = RDMA1_SOUT_DPI0;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + value = RDMA1_SOUT_DPI1;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + value = RDMA2_SOUT_DPI0;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + value = RDMA2_SOUT_DPI1;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + value = RDMA2_SOUT_DSI1;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + value = RDMA2_SOUT_DSI2;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + value = RDMA2_SOUT_DSI3;
> + } else {
> + value = 0;
> + }
> +
> + return value;
> +}
> +
> +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + unsigned int *addr)
> +{
> + unsigned int value;
> +
> + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> + value = COLOR0_SEL_IN_OVL0;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + value = DPI0_SEL_IN_RDMA1;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + value = DPI1_SEL_IN_RDMA1;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + value = DSI0_SEL_IN_RDMA1;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> + *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> + value = DSI1_SEL_IN_RDMA1;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + value = DSI2_SEL_IN_RDMA1;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> + *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> + value = DSI3_SEL_IN_RDMA1;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + value = DPI0_SEL_IN_RDMA2;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + value = DPI1_SEL_IN_RDMA2;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + value = DSI0_SEL_IN_RDMA2;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> + *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> + value = DSI1_SEL_IN_RDMA2;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + value = DSI2_SEL_IN_RDMA2;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + value = DSI3_SEL_IN_RDMA2;
> + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> + value = COLOR1_SEL_IN_OVL1;
> + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> + *addr = DISP_REG_CONFIG_DSI_SEL;
> + value = DSI_SEL_IN_BLS;
> + } else {
> + value = 0;
> + }
> +
> + return value;
> +}
> +
> +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next)
> +{
> + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
> + config_regs + DISP_REG_CONFIG_OUT_SEL);
> + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
> + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
> + config_regs + DISP_REG_CONFIG_OUT_SEL);
> + writel_relaxed(DSI_SEL_IN_RDMA,
> + config_regs + DISP_REG_CONFIG_DSI_SEL);
> + writel_relaxed(DPI_SEL_IN_BLS,
> + config_regs + DISP_REG_CONFIG_DPI_SEL);
> + }
> +}
> +
> +void mtk_mmsys_ddp_connect(struct device *dev,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next)
> +{
> + void __iomem *config_regs = dev_get_drvdata(dev);
> + unsigned int addr, value, reg;
> +
> + value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> + if (value) {
> + reg = readl_relaxed(config_regs + addr) | value;
> + writel_relaxed(reg, config_regs + addr);
> + }
> +
> + mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
> +
> + value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> + if (value) {
> + reg = readl_relaxed(config_regs + addr) | value;
> + writel_relaxed(reg, config_regs + addr);
> + }
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
> +
> +void mtk_mmsys_ddp_disconnect(struct device *dev,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next)
> +{
> + void __iomem *config_regs = dev_get_drvdata(dev);
> + unsigned int addr, value, reg;
> +
> + value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> + if (value) {
> + reg = readl_relaxed(config_regs + addr) & ~value;
> + writel_relaxed(reg, config_regs + addr);
> + }
> +
> + value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> + if (value) {
> + reg = readl_relaxed(config_regs + addr) & ~value;
> + writel_relaxed(reg, config_regs + addr);
> + }
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
> +
> +static int mtk_mmsys_probe(struct platform_device *pdev)
> +{
> + const struct mtk_mmsys_driver_data *data;
> + struct device *dev = &pdev->dev;
> + struct platform_device *clks;
> + struct platform_device *drm;
> + void __iomem *config_regs;
> + int ret;
> +
> + config_regs = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(config_regs)) {
> + ret = PTR_ERR(config_regs);
> + dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
> + return ret;
> + }
> +
> + platform_set_drvdata(pdev, config_regs);
> +
> + data = of_device_get_match_data(&pdev->dev);
> +
> + clks = platform_device_register_data(&pdev->dev, data->clk_driver,
> + PLATFORM_DEVID_AUTO, NULL, 0);
> + if (IS_ERR(clks))
> + return PTR_ERR(clks);
> +
> + drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
> + PLATFORM_DEVID_AUTO, NULL, 0);
> + if (IS_ERR(drm)) {
> + platform_device_unregister(clks);
> + return PTR_ERR(drm);
> + }
> +
> + return 0;
> +}
> +
> +static const struct of_device_id of_match_mtk_mmsys[] = {
> + {
> + .compatible = "mediatek,mt2701-mmsys",
> + .data = &mt2701_mmsys_driver_data,
> + },
> + {
> + .compatible = "mediatek,mt2712-mmsys",
> + .data = &mt2712_mmsys_driver_data,
> + },
> + {
> + .compatible = "mediatek,mt6779-mmsys",
> + .data = &mt6779_mmsys_driver_data,
> + },
> + {
> + .compatible = "mediatek,mt6797-mmsys",
> + .data = &mt6797_mmsys_driver_data,
> + },
> + {
> + .compatible = "mediatek,mt8173-mmsys",
> + .data = &mt8173_mmsys_driver_data,
> + },
> + {
> + .compatible = "mediatek,mt8183-mmsys",
> + .data = &mt8183_mmsys_driver_data,
> + },
> + { }
> +};
> +
> +static struct platform_driver mtk_mmsys_drv = {
> + .driver = {
> + .name = "mtk-mmsys",
> + .of_match_table = of_match_mtk_mmsys,
> + },
> + .probe = mtk_mmsys_probe,
> +};
> +
> +builtin_platform_driver(mtk_mmsys_drv);
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> deleted file mode 100644
> index 18f9397..0000000
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ /dev/null
> @@ -1,373 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * Copyright (c) 2014 MediaTek Inc.
> - * Author: James Liao <jamesjj.liao@mediatek.com>
> - */
> -
> -#include <linux/device.h>
> -#include <linux/io.h>
> -#include <linux/of_device.h>
> -#include <linux/platform_device.h>
> -#include <linux/soc/mediatek/mtk-mmsys.h>
> -
> -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
> -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
> -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
> -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
> -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
> -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
> -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
> -#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
> -#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
> -#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
> -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
> -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
> -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
> -#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
> -
> -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
> -#define DISP_REG_CONFIG_OUT_SEL 0x04c
> -#define DISP_REG_CONFIG_DSI_SEL 0x050
> -#define DISP_REG_CONFIG_DPI_SEL 0x064
> -
> -#define OVL0_MOUT_EN_COLOR0 0x1
> -#define OD_MOUT_EN_RDMA0 0x1
> -#define OD1_MOUT_EN_RDMA1 BIT(16)
> -#define UFOE_MOUT_EN_DSI0 0x1
> -#define COLOR0_SEL_IN_OVL0 0x1
> -#define OVL1_MOUT_EN_COLOR1 0x1
> -#define GAMMA_MOUT_EN_RDMA1 0x1
> -#define RDMA0_SOUT_DPI0 0x2
> -#define RDMA0_SOUT_DPI1 0x3
> -#define RDMA0_SOUT_DSI1 0x1
> -#define RDMA0_SOUT_DSI2 0x4
> -#define RDMA0_SOUT_DSI3 0x5
> -#define RDMA1_SOUT_DPI0 0x2
> -#define RDMA1_SOUT_DPI1 0x3
> -#define RDMA1_SOUT_DSI1 0x1
> -#define RDMA1_SOUT_DSI2 0x4
> -#define RDMA1_SOUT_DSI3 0x5
> -#define RDMA2_SOUT_DPI0 0x2
> -#define RDMA2_SOUT_DPI1 0x3
> -#define RDMA2_SOUT_DSI1 0x1
> -#define RDMA2_SOUT_DSI2 0x4
> -#define RDMA2_SOUT_DSI3 0x5
> -#define DPI0_SEL_IN_RDMA1 0x1
> -#define DPI0_SEL_IN_RDMA2 0x3
> -#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
> -#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
> -#define DSI0_SEL_IN_RDMA1 0x1
> -#define DSI0_SEL_IN_RDMA2 0x4
> -#define DSI1_SEL_IN_RDMA1 0x1
> -#define DSI1_SEL_IN_RDMA2 0x4
> -#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
> -#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
> -#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
> -#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
> -#define COLOR1_SEL_IN_OVL1 0x1
> -
> -#define OVL_MOUT_EN_RDMA 0x1
> -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
> -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
> -#define DSI_SEL_IN_BLS 0x0
> -#define DPI_SEL_IN_BLS 0x0
> -#define DSI_SEL_IN_RDMA 0x1
> -
> -struct mtk_mmsys_driver_data {
> - const char *clk_driver;
> -};
> -
> -static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> - .clk_driver = "clk-mt2701-mm",
> -};
> -
> -static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
> - .clk_driver = "clk-mt2712-mm",
> -};
> -
> -static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
> - .clk_driver = "clk-mt6779-mm",
> -};
> -
> -static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
> - .clk_driver = "clk-mt6797-mm",
> -};
> -
> -static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> - .clk_driver = "clk-mt8173-mm",
> -};
> -
> -static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> - .clk_driver = "clk-mt8183-mm",
> -};
> -
> -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
> - enum mtk_ddp_comp_id next,
> - unsigned int *addr)
> -{
> - unsigned int value;
> -
> - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> - value = OVL0_MOUT_EN_COLOR0;
> - } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
> - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> - value = OVL_MOUT_EN_RDMA;
> - } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> - value = OD_MOUT_EN_RDMA0;
> - } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> - value = UFOE_MOUT_EN_DSI0;
> - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> - value = OVL1_MOUT_EN_COLOR1;
> - } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> - value = GAMMA_MOUT_EN_RDMA1;
> - } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> - value = OD1_MOUT_EN_RDMA1;
> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> - value = RDMA0_SOUT_DPI0;
> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> - value = RDMA0_SOUT_DPI1;
> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> - value = RDMA0_SOUT_DSI1;
> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> - value = RDMA0_SOUT_DSI2;
> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> - value = RDMA0_SOUT_DSI3;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> - value = RDMA1_SOUT_DSI1;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> - value = RDMA1_SOUT_DSI2;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> - value = RDMA1_SOUT_DSI3;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> - value = RDMA1_SOUT_DPI0;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> - value = RDMA1_SOUT_DPI1;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> - value = RDMA2_SOUT_DPI0;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> - value = RDMA2_SOUT_DPI1;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> - value = RDMA2_SOUT_DSI1;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> - value = RDMA2_SOUT_DSI2;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> - value = RDMA2_SOUT_DSI3;
> - } else {
> - value = 0;
> - }
> -
> - return value;
> -}
> -
> -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
> - enum mtk_ddp_comp_id next,
> - unsigned int *addr)
> -{
> - unsigned int value;
> -
> - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> - value = COLOR0_SEL_IN_OVL0;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> - value = DPI0_SEL_IN_RDMA1;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> - value = DPI1_SEL_IN_RDMA1;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> - value = DSI0_SEL_IN_RDMA1;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> - value = DSI1_SEL_IN_RDMA1;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> - value = DSI2_SEL_IN_RDMA1;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> - value = DSI3_SEL_IN_RDMA1;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> - value = DPI0_SEL_IN_RDMA2;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> - value = DPI1_SEL_IN_RDMA2;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> - value = DSI0_SEL_IN_RDMA2;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> - value = DSI1_SEL_IN_RDMA2;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> - value = DSI2_SEL_IN_RDMA2;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> - value = DSI3_SEL_IN_RDMA2;
> - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> - value = COLOR1_SEL_IN_OVL1;
> - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DSI_SEL;
> - value = DSI_SEL_IN_BLS;
> - } else {
> - value = 0;
> - }
> -
> - return value;
> -}
> -
> -static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
> - enum mtk_ddp_comp_id cur,
> - enum mtk_ddp_comp_id next)
> -{
> - if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
> - config_regs + DISP_REG_CONFIG_OUT_SEL);
> - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
> - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
> - config_regs + DISP_REG_CONFIG_OUT_SEL);
> - writel_relaxed(DSI_SEL_IN_RDMA,
> - config_regs + DISP_REG_CONFIG_DSI_SEL);
> - writel_relaxed(DPI_SEL_IN_BLS,
> - config_regs + DISP_REG_CONFIG_DPI_SEL);
> - }
> -}
> -
> -void mtk_mmsys_ddp_connect(struct device *dev,
> - enum mtk_ddp_comp_id cur,
> - enum mtk_ddp_comp_id next)
> -{
> - void __iomem *config_regs = dev_get_drvdata(dev);
> - unsigned int addr, value, reg;
> -
> - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> - if (value) {
> - reg = readl_relaxed(config_regs + addr) | value;
> - writel_relaxed(reg, config_regs + addr);
> - }
> -
> - mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
> -
> - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> - if (value) {
> - reg = readl_relaxed(config_regs + addr) | value;
> - writel_relaxed(reg, config_regs + addr);
> - }
> -}
> -EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
> -
> -void mtk_mmsys_ddp_disconnect(struct device *dev,
> - enum mtk_ddp_comp_id cur,
> - enum mtk_ddp_comp_id next)
> -{
> - void __iomem *config_regs = dev_get_drvdata(dev);
> - unsigned int addr, value, reg;
> -
> - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> - if (value) {
> - reg = readl_relaxed(config_regs + addr) & ~value;
> - writel_relaxed(reg, config_regs + addr);
> - }
> -
> - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> - if (value) {
> - reg = readl_relaxed(config_regs + addr) & ~value;
> - writel_relaxed(reg, config_regs + addr);
> - }
> -}
> -EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
> -
> -static int mtk_mmsys_probe(struct platform_device *pdev)
> -{
> - const struct mtk_mmsys_driver_data *data;
> - struct device *dev = &pdev->dev;
> - struct platform_device *clks;
> - struct platform_device *drm;
> - void __iomem *config_regs;
> - int ret;
> -
> - config_regs = devm_platform_ioremap_resource(pdev, 0);
> - if (IS_ERR(config_regs)) {
> - ret = PTR_ERR(config_regs);
> - dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
> - return ret;
> - }
> -
> - platform_set_drvdata(pdev, config_regs);
> -
> - data = of_device_get_match_data(&pdev->dev);
> -
> - clks = platform_device_register_data(&pdev->dev, data->clk_driver,
> - PLATFORM_DEVID_AUTO, NULL, 0);
> - if (IS_ERR(clks))
> - return PTR_ERR(clks);
> -
> - drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
> - PLATFORM_DEVID_AUTO, NULL, 0);
> - if (IS_ERR(drm)) {
> - platform_device_unregister(clks);
> - return PTR_ERR(drm);
> - }
> -
> - return 0;
> -}
> -
> -static const struct of_device_id of_match_mtk_mmsys[] = {
> - {
> - .compatible = "mediatek,mt2701-mmsys",
> - .data = &mt2701_mmsys_driver_data,
> - },
> - {
> - .compatible = "mediatek,mt2712-mmsys",
> - .data = &mt2712_mmsys_driver_data,
> - },
> - {
> - .compatible = "mediatek,mt6779-mmsys",
> - .data = &mt6779_mmsys_driver_data,
> - },
> - {
> - .compatible = "mediatek,mt6797-mmsys",
> - .data = &mt6797_mmsys_driver_data,
> - },
> - {
> - .compatible = "mediatek,mt8173-mmsys",
> - .data = &mt8173_mmsys_driver_data,
> - },
> - {
> - .compatible = "mediatek,mt8183-mmsys",
> - .data = &mt8183_mmsys_driver_data,
> - },
> - { }
> -};
> -
> -static struct platform_driver mtk_mmsys_drv = {
> - .driver = {
> - .name = "mtk-mmsys",
> - .of_match_table = of_match_mtk_mmsys,
> - },
> - .probe = mtk_mmsys_probe,
> -};
> -
> -builtin_platform_driver(mtk_mmsys_drv);
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
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^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4, 01/10] soc: mediatek: mmsys: create mmsys folder
2021-02-09 15:38 ` Enric Balletbo Serra
(?)
(?)
@ 2021-02-10 11:59 ` Matthias Brugger
-1 siblings, 0 replies; 75+ messages in thread
From: Matthias Brugger @ 2021-02-10 11:59 UTC (permalink / raw)
To: Enric Balletbo Serra, Yongqiang Niu
Cc: CK Hu, Philipp Zabel, Rob Herring, Mark Rutland, devicetree,
David Airlie, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group,
moderated list:ARM/Mediatek SoC support, Daniel Vetter,
Linux ARM
On 09/02/2021 16:38, Enric Balletbo Serra wrote:
> Hi Yongqiang Niu,
>
> Thank you for your patch.
>
> Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dt., 5
> de gen. 2021 a les 4:07:
>>
>> the mmsys will more and more complicated after support
>> more and more SoCs, add an independent folder will be
>> more clear
>>
>> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
>> ---
>> drivers/soc/mediatek/Makefile | 2 +-
>
> It will not apply cleanly anymore after the below commit that is
> already queued. Maybe you could rebase the patches and resend them
> again?
>
Please don't do that, as I pointed out in [1] I don't like the approach of a new
folder. If you disagree please let me know why. Otherwise please send a new
version with the changes suggested by me :)
Regards,
Matthias
[1]
https://lore.kernel.org/linux-mediatek/4cadc9f0-0761-7609-abac-d2211b097bda@gmail.com/
> commit e1e4f7fea37572f0ccf3887430e52c491e9accb6
> Author: CK Hu <ck.hu@mediatek.com>
> Date: Tue Jul 21 15:46:06 2020 +0800
>
> soc / drm: mediatek: Move mtk mutex driver to soc folder
>
> mtk mutex is used by DRM and MDP driver, and its function is SoC-specific,
> so move it to soc folder.
>
> With that fixed,
>
> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
>
> Thanks,
> Enric
>
>> drivers/soc/mediatek/mmsys/Makefile | 2 +
>> drivers/soc/mediatek/mmsys/mtk-mmsys.c | 373 +++++++++++++++++++++++++++++++++
>> drivers/soc/mediatek/mtk-mmsys.c | 373 ---------------------------------
>> 4 files changed, 376 insertions(+), 374 deletions(-)
>> create mode 100644 drivers/soc/mediatek/mmsys/Makefile
>> create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c
>> delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c
>>
>> diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
>> index b6908db..eca9774 100644
>> --- a/drivers/soc/mediatek/Makefile
>> +++ b/drivers/soc/mediatek/Makefile
>> @@ -5,4 +5,4 @@ obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
>> obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
>> obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
>> obj-$(CONFIG_MTK_SCPSYS_PM_DOMAINS) += mtk-pm-domains.o
>> -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
>> +obj-$(CONFIG_MTK_MMSYS) += mmsys/
>> diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
>> new file mode 100644
>> index 0000000..f44eadc
>> --- /dev/null
>> +++ b/drivers/soc/mediatek/mmsys/Makefile
>> @@ -0,0 +1,2 @@
>> +# SPDX-License-Identifier: GPL-2.0-only
>> +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
>> diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
>> new file mode 100644
>> index 0000000..18f9397
>> --- /dev/null
>> +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
>> @@ -0,0 +1,373 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) 2014 MediaTek Inc.
>> + * Author: James Liao <jamesjj.liao@mediatek.com>
>> + */
>> +
>> +#include <linux/device.h>
>> +#include <linux/io.h>
>> +#include <linux/of_device.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/soc/mediatek/mtk-mmsys.h>
>> +
>> +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
>> +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
>> +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
>> +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
>> +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
>> +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
>> +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
>> +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
>> +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
>> +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
>> +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
>> +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
>> +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
>> +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
>> +
>> +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
>> +#define DISP_REG_CONFIG_OUT_SEL 0x04c
>> +#define DISP_REG_CONFIG_DSI_SEL 0x050
>> +#define DISP_REG_CONFIG_DPI_SEL 0x064
>> +
>> +#define OVL0_MOUT_EN_COLOR0 0x1
>> +#define OD_MOUT_EN_RDMA0 0x1
>> +#define OD1_MOUT_EN_RDMA1 BIT(16)
>> +#define UFOE_MOUT_EN_DSI0 0x1
>> +#define COLOR0_SEL_IN_OVL0 0x1
>> +#define OVL1_MOUT_EN_COLOR1 0x1
>> +#define GAMMA_MOUT_EN_RDMA1 0x1
>> +#define RDMA0_SOUT_DPI0 0x2
>> +#define RDMA0_SOUT_DPI1 0x3
>> +#define RDMA0_SOUT_DSI1 0x1
>> +#define RDMA0_SOUT_DSI2 0x4
>> +#define RDMA0_SOUT_DSI3 0x5
>> +#define RDMA1_SOUT_DPI0 0x2
>> +#define RDMA1_SOUT_DPI1 0x3
>> +#define RDMA1_SOUT_DSI1 0x1
>> +#define RDMA1_SOUT_DSI2 0x4
>> +#define RDMA1_SOUT_DSI3 0x5
>> +#define RDMA2_SOUT_DPI0 0x2
>> +#define RDMA2_SOUT_DPI1 0x3
>> +#define RDMA2_SOUT_DSI1 0x1
>> +#define RDMA2_SOUT_DSI2 0x4
>> +#define RDMA2_SOUT_DSI3 0x5
>> +#define DPI0_SEL_IN_RDMA1 0x1
>> +#define DPI0_SEL_IN_RDMA2 0x3
>> +#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
>> +#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
>> +#define DSI0_SEL_IN_RDMA1 0x1
>> +#define DSI0_SEL_IN_RDMA2 0x4
>> +#define DSI1_SEL_IN_RDMA1 0x1
>> +#define DSI1_SEL_IN_RDMA2 0x4
>> +#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
>> +#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
>> +#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
>> +#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
>> +#define COLOR1_SEL_IN_OVL1 0x1
>> +
>> +#define OVL_MOUT_EN_RDMA 0x1
>> +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
>> +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
>> +#define DSI_SEL_IN_BLS 0x0
>> +#define DPI_SEL_IN_BLS 0x0
>> +#define DSI_SEL_IN_RDMA 0x1
>> +
>> +struct mtk_mmsys_driver_data {
>> + const char *clk_driver;
>> +};
>> +
>> +static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
>> + .clk_driver = "clk-mt2701-mm",
>> +};
>> +
>> +static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
>> + .clk_driver = "clk-mt2712-mm",
>> +};
>> +
>> +static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
>> + .clk_driver = "clk-mt6779-mm",
>> +};
>> +
>> +static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
>> + .clk_driver = "clk-mt6797-mm",
>> +};
>> +
>> +static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
>> + .clk_driver = "clk-mt8173-mm",
>> +};
>> +
>> +static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
>> + .clk_driver = "clk-mt8183-mm",
>> +};
>> +
>> +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
>> + enum mtk_ddp_comp_id next,
>> + unsigned int *addr)
>> +{
>> + unsigned int value;
>> +
>> + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>> + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
>> + value = OVL0_MOUT_EN_COLOR0;
>> + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
>> + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
>> + value = OVL_MOUT_EN_RDMA;
>> + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
>> + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>> + value = OD_MOUT_EN_RDMA0;
>> + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
>> + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
>> + value = UFOE_MOUT_EN_DSI0;
>> + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>> + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
>> + value = OVL1_MOUT_EN_COLOR1;
>> + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
>> + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
>> + value = GAMMA_MOUT_EN_RDMA1;
>> + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
>> + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>> + value = OD1_MOUT_EN_RDMA1;
>> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> + value = RDMA0_SOUT_DPI0;
>> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> + value = RDMA0_SOUT_DPI1;
>> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> + value = RDMA0_SOUT_DSI1;
>> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> + value = RDMA0_SOUT_DSI2;
>> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> + value = RDMA0_SOUT_DSI3;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> + value = RDMA1_SOUT_DSI1;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> + value = RDMA1_SOUT_DSI2;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> + value = RDMA1_SOUT_DSI3;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> + value = RDMA1_SOUT_DPI0;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> + value = RDMA1_SOUT_DPI1;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> + value = RDMA2_SOUT_DPI0;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> + value = RDMA2_SOUT_DPI1;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> + value = RDMA2_SOUT_DSI1;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> + value = RDMA2_SOUT_DSI2;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> + value = RDMA2_SOUT_DSI3;
>> + } else {
>> + value = 0;
>> + }
>> +
>> + return value;
>> +}
>> +
>> +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
>> + enum mtk_ddp_comp_id next,
>> + unsigned int *addr)
>> +{
>> + unsigned int value;
>> +
>> + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>> + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
>> + value = COLOR0_SEL_IN_OVL0;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>> + value = DPI0_SEL_IN_RDMA1;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>> + value = DPI1_SEL_IN_RDMA1;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
>> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> + value = DSI0_SEL_IN_RDMA1;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>> + *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>> + value = DSI1_SEL_IN_RDMA1;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> + value = DSI2_SEL_IN_RDMA1;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>> + *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>> + value = DSI3_SEL_IN_RDMA1;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>> + value = DPI0_SEL_IN_RDMA2;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>> + value = DPI1_SEL_IN_RDMA2;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
>> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> + value = DSI0_SEL_IN_RDMA2;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>> + *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>> + value = DSI1_SEL_IN_RDMA2;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> + value = DSI2_SEL_IN_RDMA2;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> + value = DSI3_SEL_IN_RDMA2;
>> + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>> + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
>> + value = COLOR1_SEL_IN_OVL1;
>> + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>> + *addr = DISP_REG_CONFIG_DSI_SEL;
>> + value = DSI_SEL_IN_BLS;
>> + } else {
>> + value = 0;
>> + }
>> +
>> + return value;
>> +}
>> +
>> +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
>> + enum mtk_ddp_comp_id cur,
>> + enum mtk_ddp_comp_id next)
>> +{
>> + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>> + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
>> + config_regs + DISP_REG_CONFIG_OUT_SEL);
>> + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
>> + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
>> + config_regs + DISP_REG_CONFIG_OUT_SEL);
>> + writel_relaxed(DSI_SEL_IN_RDMA,
>> + config_regs + DISP_REG_CONFIG_DSI_SEL);
>> + writel_relaxed(DPI_SEL_IN_BLS,
>> + config_regs + DISP_REG_CONFIG_DPI_SEL);
>> + }
>> +}
>> +
>> +void mtk_mmsys_ddp_connect(struct device *dev,
>> + enum mtk_ddp_comp_id cur,
>> + enum mtk_ddp_comp_id next)
>> +{
>> + void __iomem *config_regs = dev_get_drvdata(dev);
>> + unsigned int addr, value, reg;
>> +
>> + value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
>> + if (value) {
>> + reg = readl_relaxed(config_regs + addr) | value;
>> + writel_relaxed(reg, config_regs + addr);
>> + }
>> +
>> + mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
>> +
>> + value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
>> + if (value) {
>> + reg = readl_relaxed(config_regs + addr) | value;
>> + writel_relaxed(reg, config_regs + addr);
>> + }
>> +}
>> +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
>> +
>> +void mtk_mmsys_ddp_disconnect(struct device *dev,
>> + enum mtk_ddp_comp_id cur,
>> + enum mtk_ddp_comp_id next)
>> +{
>> + void __iomem *config_regs = dev_get_drvdata(dev);
>> + unsigned int addr, value, reg;
>> +
>> + value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
>> + if (value) {
>> + reg = readl_relaxed(config_regs + addr) & ~value;
>> + writel_relaxed(reg, config_regs + addr);
>> + }
>> +
>> + value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
>> + if (value) {
>> + reg = readl_relaxed(config_regs + addr) & ~value;
>> + writel_relaxed(reg, config_regs + addr);
>> + }
>> +}
>> +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>> +
>> +static int mtk_mmsys_probe(struct platform_device *pdev)
>> +{
>> + const struct mtk_mmsys_driver_data *data;
>> + struct device *dev = &pdev->dev;
>> + struct platform_device *clks;
>> + struct platform_device *drm;
>> + void __iomem *config_regs;
>> + int ret;
>> +
>> + config_regs = devm_platform_ioremap_resource(pdev, 0);
>> + if (IS_ERR(config_regs)) {
>> + ret = PTR_ERR(config_regs);
>> + dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
>> + return ret;
>> + }
>> +
>> + platform_set_drvdata(pdev, config_regs);
>> +
>> + data = of_device_get_match_data(&pdev->dev);
>> +
>> + clks = platform_device_register_data(&pdev->dev, data->clk_driver,
>> + PLATFORM_DEVID_AUTO, NULL, 0);
>> + if (IS_ERR(clks))
>> + return PTR_ERR(clks);
>> +
>> + drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
>> + PLATFORM_DEVID_AUTO, NULL, 0);
>> + if (IS_ERR(drm)) {
>> + platform_device_unregister(clks);
>> + return PTR_ERR(drm);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static const struct of_device_id of_match_mtk_mmsys[] = {
>> + {
>> + .compatible = "mediatek,mt2701-mmsys",
>> + .data = &mt2701_mmsys_driver_data,
>> + },
>> + {
>> + .compatible = "mediatek,mt2712-mmsys",
>> + .data = &mt2712_mmsys_driver_data,
>> + },
>> + {
>> + .compatible = "mediatek,mt6779-mmsys",
>> + .data = &mt6779_mmsys_driver_data,
>> + },
>> + {
>> + .compatible = "mediatek,mt6797-mmsys",
>> + .data = &mt6797_mmsys_driver_data,
>> + },
>> + {
>> + .compatible = "mediatek,mt8173-mmsys",
>> + .data = &mt8173_mmsys_driver_data,
>> + },
>> + {
>> + .compatible = "mediatek,mt8183-mmsys",
>> + .data = &mt8183_mmsys_driver_data,
>> + },
>> + { }
>> +};
>> +
>> +static struct platform_driver mtk_mmsys_drv = {
>> + .driver = {
>> + .name = "mtk-mmsys",
>> + .of_match_table = of_match_mtk_mmsys,
>> + },
>> + .probe = mtk_mmsys_probe,
>> +};
>> +
>> +builtin_platform_driver(mtk_mmsys_drv);
>> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
>> deleted file mode 100644
>> index 18f9397..0000000
>> --- a/drivers/soc/mediatek/mtk-mmsys.c
>> +++ /dev/null
>> @@ -1,373 +0,0 @@
>> -// SPDX-License-Identifier: GPL-2.0-only
>> -/*
>> - * Copyright (c) 2014 MediaTek Inc.
>> - * Author: James Liao <jamesjj.liao@mediatek.com>
>> - */
>> -
>> -#include <linux/device.h>
>> -#include <linux/io.h>
>> -#include <linux/of_device.h>
>> -#include <linux/platform_device.h>
>> -#include <linux/soc/mediatek/mtk-mmsys.h>
>> -
>> -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
>> -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
>> -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
>> -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
>> -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
>> -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
>> -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
>> -#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
>> -#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
>> -#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
>> -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
>> -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
>> -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
>> -#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
>> -
>> -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
>> -#define DISP_REG_CONFIG_OUT_SEL 0x04c
>> -#define DISP_REG_CONFIG_DSI_SEL 0x050
>> -#define DISP_REG_CONFIG_DPI_SEL 0x064
>> -
>> -#define OVL0_MOUT_EN_COLOR0 0x1
>> -#define OD_MOUT_EN_RDMA0 0x1
>> -#define OD1_MOUT_EN_RDMA1 BIT(16)
>> -#define UFOE_MOUT_EN_DSI0 0x1
>> -#define COLOR0_SEL_IN_OVL0 0x1
>> -#define OVL1_MOUT_EN_COLOR1 0x1
>> -#define GAMMA_MOUT_EN_RDMA1 0x1
>> -#define RDMA0_SOUT_DPI0 0x2
>> -#define RDMA0_SOUT_DPI1 0x3
>> -#define RDMA0_SOUT_DSI1 0x1
>> -#define RDMA0_SOUT_DSI2 0x4
>> -#define RDMA0_SOUT_DSI3 0x5
>> -#define RDMA1_SOUT_DPI0 0x2
>> -#define RDMA1_SOUT_DPI1 0x3
>> -#define RDMA1_SOUT_DSI1 0x1
>> -#define RDMA1_SOUT_DSI2 0x4
>> -#define RDMA1_SOUT_DSI3 0x5
>> -#define RDMA2_SOUT_DPI0 0x2
>> -#define RDMA2_SOUT_DPI1 0x3
>> -#define RDMA2_SOUT_DSI1 0x1
>> -#define RDMA2_SOUT_DSI2 0x4
>> -#define RDMA2_SOUT_DSI3 0x5
>> -#define DPI0_SEL_IN_RDMA1 0x1
>> -#define DPI0_SEL_IN_RDMA2 0x3
>> -#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
>> -#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
>> -#define DSI0_SEL_IN_RDMA1 0x1
>> -#define DSI0_SEL_IN_RDMA2 0x4
>> -#define DSI1_SEL_IN_RDMA1 0x1
>> -#define DSI1_SEL_IN_RDMA2 0x4
>> -#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
>> -#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
>> -#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
>> -#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
>> -#define COLOR1_SEL_IN_OVL1 0x1
>> -
>> -#define OVL_MOUT_EN_RDMA 0x1
>> -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
>> -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
>> -#define DSI_SEL_IN_BLS 0x0
>> -#define DPI_SEL_IN_BLS 0x0
>> -#define DSI_SEL_IN_RDMA 0x1
>> -
>> -struct mtk_mmsys_driver_data {
>> - const char *clk_driver;
>> -};
>> -
>> -static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
>> - .clk_driver = "clk-mt2701-mm",
>> -};
>> -
>> -static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
>> - .clk_driver = "clk-mt2712-mm",
>> -};
>> -
>> -static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
>> - .clk_driver = "clk-mt6779-mm",
>> -};
>> -
>> -static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
>> - .clk_driver = "clk-mt6797-mm",
>> -};
>> -
>> -static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
>> - .clk_driver = "clk-mt8173-mm",
>> -};
>> -
>> -static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
>> - .clk_driver = "clk-mt8183-mm",
>> -};
>> -
>> -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
>> - enum mtk_ddp_comp_id next,
>> - unsigned int *addr)
>> -{
>> - unsigned int value;
>> -
>> - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>> - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
>> - value = OVL0_MOUT_EN_COLOR0;
>> - } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
>> - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
>> - value = OVL_MOUT_EN_RDMA;
>> - } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
>> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>> - value = OD_MOUT_EN_RDMA0;
>> - } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
>> - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
>> - value = UFOE_MOUT_EN_DSI0;
>> - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>> - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
>> - value = OVL1_MOUT_EN_COLOR1;
>> - } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
>> - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
>> - value = GAMMA_MOUT_EN_RDMA1;
>> - } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
>> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>> - value = OD1_MOUT_EN_RDMA1;
>> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> - value = RDMA0_SOUT_DPI0;
>> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> - value = RDMA0_SOUT_DPI1;
>> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> - value = RDMA0_SOUT_DSI1;
>> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> - value = RDMA0_SOUT_DSI2;
>> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> - value = RDMA0_SOUT_DSI3;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> - value = RDMA1_SOUT_DSI1;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> - value = RDMA1_SOUT_DSI2;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> - value = RDMA1_SOUT_DSI3;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> - value = RDMA1_SOUT_DPI0;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> - value = RDMA1_SOUT_DPI1;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> - value = RDMA2_SOUT_DPI0;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> - value = RDMA2_SOUT_DPI1;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> - value = RDMA2_SOUT_DSI1;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> - value = RDMA2_SOUT_DSI2;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> - value = RDMA2_SOUT_DSI3;
>> - } else {
>> - value = 0;
>> - }
>> -
>> - return value;
>> -}
>> -
>> -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
>> - enum mtk_ddp_comp_id next,
>> - unsigned int *addr)
>> -{
>> - unsigned int value;
>> -
>> - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>> - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
>> - value = COLOR0_SEL_IN_OVL0;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>> - value = DPI0_SEL_IN_RDMA1;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>> - value = DPI1_SEL_IN_RDMA1;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> - value = DSI0_SEL_IN_RDMA1;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>> - value = DSI1_SEL_IN_RDMA1;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> - value = DSI2_SEL_IN_RDMA1;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>> - value = DSI3_SEL_IN_RDMA1;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>> - value = DPI0_SEL_IN_RDMA2;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>> - value = DPI1_SEL_IN_RDMA2;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> - value = DSI0_SEL_IN_RDMA2;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>> - value = DSI1_SEL_IN_RDMA2;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> - value = DSI2_SEL_IN_RDMA2;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> - value = DSI3_SEL_IN_RDMA2;
>> - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>> - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
>> - value = COLOR1_SEL_IN_OVL1;
>> - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>> - *addr = DISP_REG_CONFIG_DSI_SEL;
>> - value = DSI_SEL_IN_BLS;
>> - } else {
>> - value = 0;
>> - }
>> -
>> - return value;
>> -}
>> -
>> -static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
>> - enum mtk_ddp_comp_id cur,
>> - enum mtk_ddp_comp_id next)
>> -{
>> - if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>> - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
>> - config_regs + DISP_REG_CONFIG_OUT_SEL);
>> - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
>> - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
>> - config_regs + DISP_REG_CONFIG_OUT_SEL);
>> - writel_relaxed(DSI_SEL_IN_RDMA,
>> - config_regs + DISP_REG_CONFIG_DSI_SEL);
>> - writel_relaxed(DPI_SEL_IN_BLS,
>> - config_regs + DISP_REG_CONFIG_DPI_SEL);
>> - }
>> -}
>> -
>> -void mtk_mmsys_ddp_connect(struct device *dev,
>> - enum mtk_ddp_comp_id cur,
>> - enum mtk_ddp_comp_id next)
>> -{
>> - void __iomem *config_regs = dev_get_drvdata(dev);
>> - unsigned int addr, value, reg;
>> -
>> - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
>> - if (value) {
>> - reg = readl_relaxed(config_regs + addr) | value;
>> - writel_relaxed(reg, config_regs + addr);
>> - }
>> -
>> - mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
>> -
>> - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
>> - if (value) {
>> - reg = readl_relaxed(config_regs + addr) | value;
>> - writel_relaxed(reg, config_regs + addr);
>> - }
>> -}
>> -EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
>> -
>> -void mtk_mmsys_ddp_disconnect(struct device *dev,
>> - enum mtk_ddp_comp_id cur,
>> - enum mtk_ddp_comp_id next)
>> -{
>> - void __iomem *config_regs = dev_get_drvdata(dev);
>> - unsigned int addr, value, reg;
>> -
>> - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
>> - if (value) {
>> - reg = readl_relaxed(config_regs + addr) & ~value;
>> - writel_relaxed(reg, config_regs + addr);
>> - }
>> -
>> - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
>> - if (value) {
>> - reg = readl_relaxed(config_regs + addr) & ~value;
>> - writel_relaxed(reg, config_regs + addr);
>> - }
>> -}
>> -EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>> -
>> -static int mtk_mmsys_probe(struct platform_device *pdev)
>> -{
>> - const struct mtk_mmsys_driver_data *data;
>> - struct device *dev = &pdev->dev;
>> - struct platform_device *clks;
>> - struct platform_device *drm;
>> - void __iomem *config_regs;
>> - int ret;
>> -
>> - config_regs = devm_platform_ioremap_resource(pdev, 0);
>> - if (IS_ERR(config_regs)) {
>> - ret = PTR_ERR(config_regs);
>> - dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
>> - return ret;
>> - }
>> -
>> - platform_set_drvdata(pdev, config_regs);
>> -
>> - data = of_device_get_match_data(&pdev->dev);
>> -
>> - clks = platform_device_register_data(&pdev->dev, data->clk_driver,
>> - PLATFORM_DEVID_AUTO, NULL, 0);
>> - if (IS_ERR(clks))
>> - return PTR_ERR(clks);
>> -
>> - drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
>> - PLATFORM_DEVID_AUTO, NULL, 0);
>> - if (IS_ERR(drm)) {
>> - platform_device_unregister(clks);
>> - return PTR_ERR(drm);
>> - }
>> -
>> - return 0;
>> -}
>> -
>> -static const struct of_device_id of_match_mtk_mmsys[] = {
>> - {
>> - .compatible = "mediatek,mt2701-mmsys",
>> - .data = &mt2701_mmsys_driver_data,
>> - },
>> - {
>> - .compatible = "mediatek,mt2712-mmsys",
>> - .data = &mt2712_mmsys_driver_data,
>> - },
>> - {
>> - .compatible = "mediatek,mt6779-mmsys",
>> - .data = &mt6779_mmsys_driver_data,
>> - },
>> - {
>> - .compatible = "mediatek,mt6797-mmsys",
>> - .data = &mt6797_mmsys_driver_data,
>> - },
>> - {
>> - .compatible = "mediatek,mt8173-mmsys",
>> - .data = &mt8173_mmsys_driver_data,
>> - },
>> - {
>> - .compatible = "mediatek,mt8183-mmsys",
>> - .data = &mt8183_mmsys_driver_data,
>> - },
>> - { }
>> -};
>> -
>> -static struct platform_driver mtk_mmsys_drv = {
>> - .driver = {
>> - .name = "mtk-mmsys",
>> - .of_match_table = of_match_mtk_mmsys,
>> - },
>> - .probe = mtk_mmsys_probe,
>> -};
>> -
>> -builtin_platform_driver(mtk_mmsys_drv);
>> --
>> 1.8.1.1.dirty
>> _______________________________________________
>> Linux-mediatek mailing list
>> Linux-mediatek@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4, 01/10] soc: mediatek: mmsys: create mmsys folder
@ 2021-02-10 11:59 ` Matthias Brugger
0 siblings, 0 replies; 75+ messages in thread
From: Matthias Brugger @ 2021-02-10 11:59 UTC (permalink / raw)
To: Enric Balletbo Serra, Yongqiang Niu
Cc: Mark Rutland, devicetree, Daniel Vetter, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
Rob Herring, moderated list:ARM/Mediatek SoC support,
Philipp Zabel, CK Hu, Linux ARM
On 09/02/2021 16:38, Enric Balletbo Serra wrote:
> Hi Yongqiang Niu,
>
> Thank you for your patch.
>
> Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dt., 5
> de gen. 2021 a les 4:07:
>>
>> the mmsys will more and more complicated after support
>> more and more SoCs, add an independent folder will be
>> more clear
>>
>> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
>> ---
>> drivers/soc/mediatek/Makefile | 2 +-
>
> It will not apply cleanly anymore after the below commit that is
> already queued. Maybe you could rebase the patches and resend them
> again?
>
Please don't do that, as I pointed out in [1] I don't like the approach of a new
folder. If you disagree please let me know why. Otherwise please send a new
version with the changes suggested by me :)
Regards,
Matthias
[1]
https://lore.kernel.org/linux-mediatek/4cadc9f0-0761-7609-abac-d2211b097bda@gmail.com/
> commit e1e4f7fea37572f0ccf3887430e52c491e9accb6
> Author: CK Hu <ck.hu@mediatek.com>
> Date: Tue Jul 21 15:46:06 2020 +0800
>
> soc / drm: mediatek: Move mtk mutex driver to soc folder
>
> mtk mutex is used by DRM and MDP driver, and its function is SoC-specific,
> so move it to soc folder.
>
> With that fixed,
>
> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
>
> Thanks,
> Enric
>
>> drivers/soc/mediatek/mmsys/Makefile | 2 +
>> drivers/soc/mediatek/mmsys/mtk-mmsys.c | 373 +++++++++++++++++++++++++++++++++
>> drivers/soc/mediatek/mtk-mmsys.c | 373 ---------------------------------
>> 4 files changed, 376 insertions(+), 374 deletions(-)
>> create mode 100644 drivers/soc/mediatek/mmsys/Makefile
>> create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c
>> delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c
>>
>> diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
>> index b6908db..eca9774 100644
>> --- a/drivers/soc/mediatek/Makefile
>> +++ b/drivers/soc/mediatek/Makefile
>> @@ -5,4 +5,4 @@ obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
>> obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
>> obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
>> obj-$(CONFIG_MTK_SCPSYS_PM_DOMAINS) += mtk-pm-domains.o
>> -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
>> +obj-$(CONFIG_MTK_MMSYS) += mmsys/
>> diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
>> new file mode 100644
>> index 0000000..f44eadc
>> --- /dev/null
>> +++ b/drivers/soc/mediatek/mmsys/Makefile
>> @@ -0,0 +1,2 @@
>> +# SPDX-License-Identifier: GPL-2.0-only
>> +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
>> diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
>> new file mode 100644
>> index 0000000..18f9397
>> --- /dev/null
>> +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
>> @@ -0,0 +1,373 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) 2014 MediaTek Inc.
>> + * Author: James Liao <jamesjj.liao@mediatek.com>
>> + */
>> +
>> +#include <linux/device.h>
>> +#include <linux/io.h>
>> +#include <linux/of_device.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/soc/mediatek/mtk-mmsys.h>
>> +
>> +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
>> +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
>> +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
>> +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
>> +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
>> +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
>> +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
>> +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
>> +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
>> +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
>> +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
>> +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
>> +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
>> +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
>> +
>> +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
>> +#define DISP_REG_CONFIG_OUT_SEL 0x04c
>> +#define DISP_REG_CONFIG_DSI_SEL 0x050
>> +#define DISP_REG_CONFIG_DPI_SEL 0x064
>> +
>> +#define OVL0_MOUT_EN_COLOR0 0x1
>> +#define OD_MOUT_EN_RDMA0 0x1
>> +#define OD1_MOUT_EN_RDMA1 BIT(16)
>> +#define UFOE_MOUT_EN_DSI0 0x1
>> +#define COLOR0_SEL_IN_OVL0 0x1
>> +#define OVL1_MOUT_EN_COLOR1 0x1
>> +#define GAMMA_MOUT_EN_RDMA1 0x1
>> +#define RDMA0_SOUT_DPI0 0x2
>> +#define RDMA0_SOUT_DPI1 0x3
>> +#define RDMA0_SOUT_DSI1 0x1
>> +#define RDMA0_SOUT_DSI2 0x4
>> +#define RDMA0_SOUT_DSI3 0x5
>> +#define RDMA1_SOUT_DPI0 0x2
>> +#define RDMA1_SOUT_DPI1 0x3
>> +#define RDMA1_SOUT_DSI1 0x1
>> +#define RDMA1_SOUT_DSI2 0x4
>> +#define RDMA1_SOUT_DSI3 0x5
>> +#define RDMA2_SOUT_DPI0 0x2
>> +#define RDMA2_SOUT_DPI1 0x3
>> +#define RDMA2_SOUT_DSI1 0x1
>> +#define RDMA2_SOUT_DSI2 0x4
>> +#define RDMA2_SOUT_DSI3 0x5
>> +#define DPI0_SEL_IN_RDMA1 0x1
>> +#define DPI0_SEL_IN_RDMA2 0x3
>> +#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
>> +#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
>> +#define DSI0_SEL_IN_RDMA1 0x1
>> +#define DSI0_SEL_IN_RDMA2 0x4
>> +#define DSI1_SEL_IN_RDMA1 0x1
>> +#define DSI1_SEL_IN_RDMA2 0x4
>> +#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
>> +#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
>> +#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
>> +#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
>> +#define COLOR1_SEL_IN_OVL1 0x1
>> +
>> +#define OVL_MOUT_EN_RDMA 0x1
>> +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
>> +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
>> +#define DSI_SEL_IN_BLS 0x0
>> +#define DPI_SEL_IN_BLS 0x0
>> +#define DSI_SEL_IN_RDMA 0x1
>> +
>> +struct mtk_mmsys_driver_data {
>> + const char *clk_driver;
>> +};
>> +
>> +static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
>> + .clk_driver = "clk-mt2701-mm",
>> +};
>> +
>> +static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
>> + .clk_driver = "clk-mt2712-mm",
>> +};
>> +
>> +static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
>> + .clk_driver = "clk-mt6779-mm",
>> +};
>> +
>> +static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
>> + .clk_driver = "clk-mt6797-mm",
>> +};
>> +
>> +static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
>> + .clk_driver = "clk-mt8173-mm",
>> +};
>> +
>> +static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
>> + .clk_driver = "clk-mt8183-mm",
>> +};
>> +
>> +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
>> + enum mtk_ddp_comp_id next,
>> + unsigned int *addr)
>> +{
>> + unsigned int value;
>> +
>> + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>> + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
>> + value = OVL0_MOUT_EN_COLOR0;
>> + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
>> + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
>> + value = OVL_MOUT_EN_RDMA;
>> + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
>> + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>> + value = OD_MOUT_EN_RDMA0;
>> + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
>> + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
>> + value = UFOE_MOUT_EN_DSI0;
>> + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>> + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
>> + value = OVL1_MOUT_EN_COLOR1;
>> + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
>> + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
>> + value = GAMMA_MOUT_EN_RDMA1;
>> + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
>> + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>> + value = OD1_MOUT_EN_RDMA1;
>> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> + value = RDMA0_SOUT_DPI0;
>> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> + value = RDMA0_SOUT_DPI1;
>> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> + value = RDMA0_SOUT_DSI1;
>> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> + value = RDMA0_SOUT_DSI2;
>> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> + value = RDMA0_SOUT_DSI3;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> + value = RDMA1_SOUT_DSI1;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> + value = RDMA1_SOUT_DSI2;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> + value = RDMA1_SOUT_DSI3;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> + value = RDMA1_SOUT_DPI0;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> + value = RDMA1_SOUT_DPI1;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> + value = RDMA2_SOUT_DPI0;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> + value = RDMA2_SOUT_DPI1;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> + value = RDMA2_SOUT_DSI1;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> + value = RDMA2_SOUT_DSI2;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> + value = RDMA2_SOUT_DSI3;
>> + } else {
>> + value = 0;
>> + }
>> +
>> + return value;
>> +}
>> +
>> +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
>> + enum mtk_ddp_comp_id next,
>> + unsigned int *addr)
>> +{
>> + unsigned int value;
>> +
>> + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>> + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
>> + value = COLOR0_SEL_IN_OVL0;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>> + value = DPI0_SEL_IN_RDMA1;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>> + value = DPI1_SEL_IN_RDMA1;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
>> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> + value = DSI0_SEL_IN_RDMA1;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>> + *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>> + value = DSI1_SEL_IN_RDMA1;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> + value = DSI2_SEL_IN_RDMA1;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>> + *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>> + value = DSI3_SEL_IN_RDMA1;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>> + value = DPI0_SEL_IN_RDMA2;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>> + value = DPI1_SEL_IN_RDMA2;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
>> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> + value = DSI0_SEL_IN_RDMA2;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>> + *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>> + value = DSI1_SEL_IN_RDMA2;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> + value = DSI2_SEL_IN_RDMA2;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> + value = DSI3_SEL_IN_RDMA2;
>> + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>> + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
>> + value = COLOR1_SEL_IN_OVL1;
>> + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>> + *addr = DISP_REG_CONFIG_DSI_SEL;
>> + value = DSI_SEL_IN_BLS;
>> + } else {
>> + value = 0;
>> + }
>> +
>> + return value;
>> +}
>> +
>> +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
>> + enum mtk_ddp_comp_id cur,
>> + enum mtk_ddp_comp_id next)
>> +{
>> + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>> + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
>> + config_regs + DISP_REG_CONFIG_OUT_SEL);
>> + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
>> + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
>> + config_regs + DISP_REG_CONFIG_OUT_SEL);
>> + writel_relaxed(DSI_SEL_IN_RDMA,
>> + config_regs + DISP_REG_CONFIG_DSI_SEL);
>> + writel_relaxed(DPI_SEL_IN_BLS,
>> + config_regs + DISP_REG_CONFIG_DPI_SEL);
>> + }
>> +}
>> +
>> +void mtk_mmsys_ddp_connect(struct device *dev,
>> + enum mtk_ddp_comp_id cur,
>> + enum mtk_ddp_comp_id next)
>> +{
>> + void __iomem *config_regs = dev_get_drvdata(dev);
>> + unsigned int addr, value, reg;
>> +
>> + value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
>> + if (value) {
>> + reg = readl_relaxed(config_regs + addr) | value;
>> + writel_relaxed(reg, config_regs + addr);
>> + }
>> +
>> + mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
>> +
>> + value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
>> + if (value) {
>> + reg = readl_relaxed(config_regs + addr) | value;
>> + writel_relaxed(reg, config_regs + addr);
>> + }
>> +}
>> +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
>> +
>> +void mtk_mmsys_ddp_disconnect(struct device *dev,
>> + enum mtk_ddp_comp_id cur,
>> + enum mtk_ddp_comp_id next)
>> +{
>> + void __iomem *config_regs = dev_get_drvdata(dev);
>> + unsigned int addr, value, reg;
>> +
>> + value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
>> + if (value) {
>> + reg = readl_relaxed(config_regs + addr) & ~value;
>> + writel_relaxed(reg, config_regs + addr);
>> + }
>> +
>> + value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
>> + if (value) {
>> + reg = readl_relaxed(config_regs + addr) & ~value;
>> + writel_relaxed(reg, config_regs + addr);
>> + }
>> +}
>> +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>> +
>> +static int mtk_mmsys_probe(struct platform_device *pdev)
>> +{
>> + const struct mtk_mmsys_driver_data *data;
>> + struct device *dev = &pdev->dev;
>> + struct platform_device *clks;
>> + struct platform_device *drm;
>> + void __iomem *config_regs;
>> + int ret;
>> +
>> + config_regs = devm_platform_ioremap_resource(pdev, 0);
>> + if (IS_ERR(config_regs)) {
>> + ret = PTR_ERR(config_regs);
>> + dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
>> + return ret;
>> + }
>> +
>> + platform_set_drvdata(pdev, config_regs);
>> +
>> + data = of_device_get_match_data(&pdev->dev);
>> +
>> + clks = platform_device_register_data(&pdev->dev, data->clk_driver,
>> + PLATFORM_DEVID_AUTO, NULL, 0);
>> + if (IS_ERR(clks))
>> + return PTR_ERR(clks);
>> +
>> + drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
>> + PLATFORM_DEVID_AUTO, NULL, 0);
>> + if (IS_ERR(drm)) {
>> + platform_device_unregister(clks);
>> + return PTR_ERR(drm);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static const struct of_device_id of_match_mtk_mmsys[] = {
>> + {
>> + .compatible = "mediatek,mt2701-mmsys",
>> + .data = &mt2701_mmsys_driver_data,
>> + },
>> + {
>> + .compatible = "mediatek,mt2712-mmsys",
>> + .data = &mt2712_mmsys_driver_data,
>> + },
>> + {
>> + .compatible = "mediatek,mt6779-mmsys",
>> + .data = &mt6779_mmsys_driver_data,
>> + },
>> + {
>> + .compatible = "mediatek,mt6797-mmsys",
>> + .data = &mt6797_mmsys_driver_data,
>> + },
>> + {
>> + .compatible = "mediatek,mt8173-mmsys",
>> + .data = &mt8173_mmsys_driver_data,
>> + },
>> + {
>> + .compatible = "mediatek,mt8183-mmsys",
>> + .data = &mt8183_mmsys_driver_data,
>> + },
>> + { }
>> +};
>> +
>> +static struct platform_driver mtk_mmsys_drv = {
>> + .driver = {
>> + .name = "mtk-mmsys",
>> + .of_match_table = of_match_mtk_mmsys,
>> + },
>> + .probe = mtk_mmsys_probe,
>> +};
>> +
>> +builtin_platform_driver(mtk_mmsys_drv);
>> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
>> deleted file mode 100644
>> index 18f9397..0000000
>> --- a/drivers/soc/mediatek/mtk-mmsys.c
>> +++ /dev/null
>> @@ -1,373 +0,0 @@
>> -// SPDX-License-Identifier: GPL-2.0-only
>> -/*
>> - * Copyright (c) 2014 MediaTek Inc.
>> - * Author: James Liao <jamesjj.liao@mediatek.com>
>> - */
>> -
>> -#include <linux/device.h>
>> -#include <linux/io.h>
>> -#include <linux/of_device.h>
>> -#include <linux/platform_device.h>
>> -#include <linux/soc/mediatek/mtk-mmsys.h>
>> -
>> -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
>> -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
>> -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
>> -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
>> -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
>> -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
>> -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
>> -#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
>> -#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
>> -#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
>> -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
>> -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
>> -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
>> -#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
>> -
>> -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
>> -#define DISP_REG_CONFIG_OUT_SEL 0x04c
>> -#define DISP_REG_CONFIG_DSI_SEL 0x050
>> -#define DISP_REG_CONFIG_DPI_SEL 0x064
>> -
>> -#define OVL0_MOUT_EN_COLOR0 0x1
>> -#define OD_MOUT_EN_RDMA0 0x1
>> -#define OD1_MOUT_EN_RDMA1 BIT(16)
>> -#define UFOE_MOUT_EN_DSI0 0x1
>> -#define COLOR0_SEL_IN_OVL0 0x1
>> -#define OVL1_MOUT_EN_COLOR1 0x1
>> -#define GAMMA_MOUT_EN_RDMA1 0x1
>> -#define RDMA0_SOUT_DPI0 0x2
>> -#define RDMA0_SOUT_DPI1 0x3
>> -#define RDMA0_SOUT_DSI1 0x1
>> -#define RDMA0_SOUT_DSI2 0x4
>> -#define RDMA0_SOUT_DSI3 0x5
>> -#define RDMA1_SOUT_DPI0 0x2
>> -#define RDMA1_SOUT_DPI1 0x3
>> -#define RDMA1_SOUT_DSI1 0x1
>> -#define RDMA1_SOUT_DSI2 0x4
>> -#define RDMA1_SOUT_DSI3 0x5
>> -#define RDMA2_SOUT_DPI0 0x2
>> -#define RDMA2_SOUT_DPI1 0x3
>> -#define RDMA2_SOUT_DSI1 0x1
>> -#define RDMA2_SOUT_DSI2 0x4
>> -#define RDMA2_SOUT_DSI3 0x5
>> -#define DPI0_SEL_IN_RDMA1 0x1
>> -#define DPI0_SEL_IN_RDMA2 0x3
>> -#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
>> -#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
>> -#define DSI0_SEL_IN_RDMA1 0x1
>> -#define DSI0_SEL_IN_RDMA2 0x4
>> -#define DSI1_SEL_IN_RDMA1 0x1
>> -#define DSI1_SEL_IN_RDMA2 0x4
>> -#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
>> -#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
>> -#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
>> -#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
>> -#define COLOR1_SEL_IN_OVL1 0x1
>> -
>> -#define OVL_MOUT_EN_RDMA 0x1
>> -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
>> -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
>> -#define DSI_SEL_IN_BLS 0x0
>> -#define DPI_SEL_IN_BLS 0x0
>> -#define DSI_SEL_IN_RDMA 0x1
>> -
>> -struct mtk_mmsys_driver_data {
>> - const char *clk_driver;
>> -};
>> -
>> -static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
>> - .clk_driver = "clk-mt2701-mm",
>> -};
>> -
>> -static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
>> - .clk_driver = "clk-mt2712-mm",
>> -};
>> -
>> -static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
>> - .clk_driver = "clk-mt6779-mm",
>> -};
>> -
>> -static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
>> - .clk_driver = "clk-mt6797-mm",
>> -};
>> -
>> -static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
>> - .clk_driver = "clk-mt8173-mm",
>> -};
>> -
>> -static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
>> - .clk_driver = "clk-mt8183-mm",
>> -};
>> -
>> -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
>> - enum mtk_ddp_comp_id next,
>> - unsigned int *addr)
>> -{
>> - unsigned int value;
>> -
>> - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>> - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
>> - value = OVL0_MOUT_EN_COLOR0;
>> - } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
>> - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
>> - value = OVL_MOUT_EN_RDMA;
>> - } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
>> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>> - value = OD_MOUT_EN_RDMA0;
>> - } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
>> - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
>> - value = UFOE_MOUT_EN_DSI0;
>> - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>> - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
>> - value = OVL1_MOUT_EN_COLOR1;
>> - } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
>> - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
>> - value = GAMMA_MOUT_EN_RDMA1;
>> - } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
>> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>> - value = OD1_MOUT_EN_RDMA1;
>> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> - value = RDMA0_SOUT_DPI0;
>> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> - value = RDMA0_SOUT_DPI1;
>> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> - value = RDMA0_SOUT_DSI1;
>> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> - value = RDMA0_SOUT_DSI2;
>> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> - value = RDMA0_SOUT_DSI3;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> - value = RDMA1_SOUT_DSI1;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> - value = RDMA1_SOUT_DSI2;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> - value = RDMA1_SOUT_DSI3;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> - value = RDMA1_SOUT_DPI0;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> - value = RDMA1_SOUT_DPI1;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> - value = RDMA2_SOUT_DPI0;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> - value = RDMA2_SOUT_DPI1;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> - value = RDMA2_SOUT_DSI1;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> - value = RDMA2_SOUT_DSI2;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> - value = RDMA2_SOUT_DSI3;
>> - } else {
>> - value = 0;
>> - }
>> -
>> - return value;
>> -}
>> -
>> -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
>> - enum mtk_ddp_comp_id next,
>> - unsigned int *addr)
>> -{
>> - unsigned int value;
>> -
>> - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>> - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
>> - value = COLOR0_SEL_IN_OVL0;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>> - value = DPI0_SEL_IN_RDMA1;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>> - value = DPI1_SEL_IN_RDMA1;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> - value = DSI0_SEL_IN_RDMA1;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>> - value = DSI1_SEL_IN_RDMA1;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> - value = DSI2_SEL_IN_RDMA1;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>> - value = DSI3_SEL_IN_RDMA1;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>> - value = DPI0_SEL_IN_RDMA2;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>> - value = DPI1_SEL_IN_RDMA2;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> - value = DSI0_SEL_IN_RDMA2;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>> - value = DSI1_SEL_IN_RDMA2;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> - value = DSI2_SEL_IN_RDMA2;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> - value = DSI3_SEL_IN_RDMA2;
>> - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>> - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
>> - value = COLOR1_SEL_IN_OVL1;
>> - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>> - *addr = DISP_REG_CONFIG_DSI_SEL;
>> - value = DSI_SEL_IN_BLS;
>> - } else {
>> - value = 0;
>> - }
>> -
>> - return value;
>> -}
>> -
>> -static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
>> - enum mtk_ddp_comp_id cur,
>> - enum mtk_ddp_comp_id next)
>> -{
>> - if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>> - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
>> - config_regs + DISP_REG_CONFIG_OUT_SEL);
>> - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
>> - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
>> - config_regs + DISP_REG_CONFIG_OUT_SEL);
>> - writel_relaxed(DSI_SEL_IN_RDMA,
>> - config_regs + DISP_REG_CONFIG_DSI_SEL);
>> - writel_relaxed(DPI_SEL_IN_BLS,
>> - config_regs + DISP_REG_CONFIG_DPI_SEL);
>> - }
>> -}
>> -
>> -void mtk_mmsys_ddp_connect(struct device *dev,
>> - enum mtk_ddp_comp_id cur,
>> - enum mtk_ddp_comp_id next)
>> -{
>> - void __iomem *config_regs = dev_get_drvdata(dev);
>> - unsigned int addr, value, reg;
>> -
>> - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
>> - if (value) {
>> - reg = readl_relaxed(config_regs + addr) | value;
>> - writel_relaxed(reg, config_regs + addr);
>> - }
>> -
>> - mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
>> -
>> - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
>> - if (value) {
>> - reg = readl_relaxed(config_regs + addr) | value;
>> - writel_relaxed(reg, config_regs + addr);
>> - }
>> -}
>> -EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
>> -
>> -void mtk_mmsys_ddp_disconnect(struct device *dev,
>> - enum mtk_ddp_comp_id cur,
>> - enum mtk_ddp_comp_id next)
>> -{
>> - void __iomem *config_regs = dev_get_drvdata(dev);
>> - unsigned int addr, value, reg;
>> -
>> - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
>> - if (value) {
>> - reg = readl_relaxed(config_regs + addr) & ~value;
>> - writel_relaxed(reg, config_regs + addr);
>> - }
>> -
>> - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
>> - if (value) {
>> - reg = readl_relaxed(config_regs + addr) & ~value;
>> - writel_relaxed(reg, config_regs + addr);
>> - }
>> -}
>> -EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>> -
>> -static int mtk_mmsys_probe(struct platform_device *pdev)
>> -{
>> - const struct mtk_mmsys_driver_data *data;
>> - struct device *dev = &pdev->dev;
>> - struct platform_device *clks;
>> - struct platform_device *drm;
>> - void __iomem *config_regs;
>> - int ret;
>> -
>> - config_regs = devm_platform_ioremap_resource(pdev, 0);
>> - if (IS_ERR(config_regs)) {
>> - ret = PTR_ERR(config_regs);
>> - dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
>> - return ret;
>> - }
>> -
>> - platform_set_drvdata(pdev, config_regs);
>> -
>> - data = of_device_get_match_data(&pdev->dev);
>> -
>> - clks = platform_device_register_data(&pdev->dev, data->clk_driver,
>> - PLATFORM_DEVID_AUTO, NULL, 0);
>> - if (IS_ERR(clks))
>> - return PTR_ERR(clks);
>> -
>> - drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
>> - PLATFORM_DEVID_AUTO, NULL, 0);
>> - if (IS_ERR(drm)) {
>> - platform_device_unregister(clks);
>> - return PTR_ERR(drm);
>> - }
>> -
>> - return 0;
>> -}
>> -
>> -static const struct of_device_id of_match_mtk_mmsys[] = {
>> - {
>> - .compatible = "mediatek,mt2701-mmsys",
>> - .data = &mt2701_mmsys_driver_data,
>> - },
>> - {
>> - .compatible = "mediatek,mt2712-mmsys",
>> - .data = &mt2712_mmsys_driver_data,
>> - },
>> - {
>> - .compatible = "mediatek,mt6779-mmsys",
>> - .data = &mt6779_mmsys_driver_data,
>> - },
>> - {
>> - .compatible = "mediatek,mt6797-mmsys",
>> - .data = &mt6797_mmsys_driver_data,
>> - },
>> - {
>> - .compatible = "mediatek,mt8173-mmsys",
>> - .data = &mt8173_mmsys_driver_data,
>> - },
>> - {
>> - .compatible = "mediatek,mt8183-mmsys",
>> - .data = &mt8183_mmsys_driver_data,
>> - },
>> - { }
>> -};
>> -
>> -static struct platform_driver mtk_mmsys_drv = {
>> - .driver = {
>> - .name = "mtk-mmsys",
>> - .of_match_table = of_match_mtk_mmsys,
>> - },
>> - .probe = mtk_mmsys_probe,
>> -};
>> -
>> -builtin_platform_driver(mtk_mmsys_drv);
>> --
>> 1.8.1.1.dirty
>> _______________________________________________
>> Linux-mediatek mailing list
>> Linux-mediatek@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4, 01/10] soc: mediatek: mmsys: create mmsys folder
@ 2021-02-10 11:59 ` Matthias Brugger
0 siblings, 0 replies; 75+ messages in thread
From: Matthias Brugger @ 2021-02-10 11:59 UTC (permalink / raw)
To: Enric Balletbo Serra, Yongqiang Niu
Cc: Mark Rutland, devicetree, Daniel Vetter, David Airlie,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
Rob Herring, moderated list:ARM/Mediatek SoC support,
Philipp Zabel, CK Hu, Linux ARM
On 09/02/2021 16:38, Enric Balletbo Serra wrote:
> Hi Yongqiang Niu,
>
> Thank you for your patch.
>
> Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dt., 5
> de gen. 2021 a les 4:07:
>>
>> the mmsys will more and more complicated after support
>> more and more SoCs, add an independent folder will be
>> more clear
>>
>> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
>> ---
>> drivers/soc/mediatek/Makefile | 2 +-
>
> It will not apply cleanly anymore after the below commit that is
> already queued. Maybe you could rebase the patches and resend them
> again?
>
Please don't do that, as I pointed out in [1] I don't like the approach of a new
folder. If you disagree please let me know why. Otherwise please send a new
version with the changes suggested by me :)
Regards,
Matthias
[1]
https://lore.kernel.org/linux-mediatek/4cadc9f0-0761-7609-abac-d2211b097bda@gmail.com/
> commit e1e4f7fea37572f0ccf3887430e52c491e9accb6
> Author: CK Hu <ck.hu@mediatek.com>
> Date: Tue Jul 21 15:46:06 2020 +0800
>
> soc / drm: mediatek: Move mtk mutex driver to soc folder
>
> mtk mutex is used by DRM and MDP driver, and its function is SoC-specific,
> so move it to soc folder.
>
> With that fixed,
>
> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
>
> Thanks,
> Enric
>
>> drivers/soc/mediatek/mmsys/Makefile | 2 +
>> drivers/soc/mediatek/mmsys/mtk-mmsys.c | 373 +++++++++++++++++++++++++++++++++
>> drivers/soc/mediatek/mtk-mmsys.c | 373 ---------------------------------
>> 4 files changed, 376 insertions(+), 374 deletions(-)
>> create mode 100644 drivers/soc/mediatek/mmsys/Makefile
>> create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c
>> delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c
>>
>> diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
>> index b6908db..eca9774 100644
>> --- a/drivers/soc/mediatek/Makefile
>> +++ b/drivers/soc/mediatek/Makefile
>> @@ -5,4 +5,4 @@ obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
>> obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
>> obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
>> obj-$(CONFIG_MTK_SCPSYS_PM_DOMAINS) += mtk-pm-domains.o
>> -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
>> +obj-$(CONFIG_MTK_MMSYS) += mmsys/
>> diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
>> new file mode 100644
>> index 0000000..f44eadc
>> --- /dev/null
>> +++ b/drivers/soc/mediatek/mmsys/Makefile
>> @@ -0,0 +1,2 @@
>> +# SPDX-License-Identifier: GPL-2.0-only
>> +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
>> diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
>> new file mode 100644
>> index 0000000..18f9397
>> --- /dev/null
>> +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
>> @@ -0,0 +1,373 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) 2014 MediaTek Inc.
>> + * Author: James Liao <jamesjj.liao@mediatek.com>
>> + */
>> +
>> +#include <linux/device.h>
>> +#include <linux/io.h>
>> +#include <linux/of_device.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/soc/mediatek/mtk-mmsys.h>
>> +
>> +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
>> +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
>> +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
>> +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
>> +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
>> +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
>> +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
>> +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
>> +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
>> +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
>> +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
>> +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
>> +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
>> +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
>> +
>> +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
>> +#define DISP_REG_CONFIG_OUT_SEL 0x04c
>> +#define DISP_REG_CONFIG_DSI_SEL 0x050
>> +#define DISP_REG_CONFIG_DPI_SEL 0x064
>> +
>> +#define OVL0_MOUT_EN_COLOR0 0x1
>> +#define OD_MOUT_EN_RDMA0 0x1
>> +#define OD1_MOUT_EN_RDMA1 BIT(16)
>> +#define UFOE_MOUT_EN_DSI0 0x1
>> +#define COLOR0_SEL_IN_OVL0 0x1
>> +#define OVL1_MOUT_EN_COLOR1 0x1
>> +#define GAMMA_MOUT_EN_RDMA1 0x1
>> +#define RDMA0_SOUT_DPI0 0x2
>> +#define RDMA0_SOUT_DPI1 0x3
>> +#define RDMA0_SOUT_DSI1 0x1
>> +#define RDMA0_SOUT_DSI2 0x4
>> +#define RDMA0_SOUT_DSI3 0x5
>> +#define RDMA1_SOUT_DPI0 0x2
>> +#define RDMA1_SOUT_DPI1 0x3
>> +#define RDMA1_SOUT_DSI1 0x1
>> +#define RDMA1_SOUT_DSI2 0x4
>> +#define RDMA1_SOUT_DSI3 0x5
>> +#define RDMA2_SOUT_DPI0 0x2
>> +#define RDMA2_SOUT_DPI1 0x3
>> +#define RDMA2_SOUT_DSI1 0x1
>> +#define RDMA2_SOUT_DSI2 0x4
>> +#define RDMA2_SOUT_DSI3 0x5
>> +#define DPI0_SEL_IN_RDMA1 0x1
>> +#define DPI0_SEL_IN_RDMA2 0x3
>> +#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
>> +#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
>> +#define DSI0_SEL_IN_RDMA1 0x1
>> +#define DSI0_SEL_IN_RDMA2 0x4
>> +#define DSI1_SEL_IN_RDMA1 0x1
>> +#define DSI1_SEL_IN_RDMA2 0x4
>> +#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
>> +#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
>> +#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
>> +#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
>> +#define COLOR1_SEL_IN_OVL1 0x1
>> +
>> +#define OVL_MOUT_EN_RDMA 0x1
>> +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
>> +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
>> +#define DSI_SEL_IN_BLS 0x0
>> +#define DPI_SEL_IN_BLS 0x0
>> +#define DSI_SEL_IN_RDMA 0x1
>> +
>> +struct mtk_mmsys_driver_data {
>> + const char *clk_driver;
>> +};
>> +
>> +static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
>> + .clk_driver = "clk-mt2701-mm",
>> +};
>> +
>> +static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
>> + .clk_driver = "clk-mt2712-mm",
>> +};
>> +
>> +static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
>> + .clk_driver = "clk-mt6779-mm",
>> +};
>> +
>> +static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
>> + .clk_driver = "clk-mt6797-mm",
>> +};
>> +
>> +static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
>> + .clk_driver = "clk-mt8173-mm",
>> +};
>> +
>> +static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
>> + .clk_driver = "clk-mt8183-mm",
>> +};
>> +
>> +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
>> + enum mtk_ddp_comp_id next,
>> + unsigned int *addr)
>> +{
>> + unsigned int value;
>> +
>> + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>> + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
>> + value = OVL0_MOUT_EN_COLOR0;
>> + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
>> + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
>> + value = OVL_MOUT_EN_RDMA;
>> + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
>> + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>> + value = OD_MOUT_EN_RDMA0;
>> + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
>> + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
>> + value = UFOE_MOUT_EN_DSI0;
>> + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>> + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
>> + value = OVL1_MOUT_EN_COLOR1;
>> + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
>> + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
>> + value = GAMMA_MOUT_EN_RDMA1;
>> + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
>> + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>> + value = OD1_MOUT_EN_RDMA1;
>> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> + value = RDMA0_SOUT_DPI0;
>> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> + value = RDMA0_SOUT_DPI1;
>> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> + value = RDMA0_SOUT_DSI1;
>> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> + value = RDMA0_SOUT_DSI2;
>> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> + value = RDMA0_SOUT_DSI3;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> + value = RDMA1_SOUT_DSI1;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> + value = RDMA1_SOUT_DSI2;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> + value = RDMA1_SOUT_DSI3;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> + value = RDMA1_SOUT_DPI0;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> + value = RDMA1_SOUT_DPI1;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> + value = RDMA2_SOUT_DPI0;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> + value = RDMA2_SOUT_DPI1;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> + value = RDMA2_SOUT_DSI1;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> + value = RDMA2_SOUT_DSI2;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> + value = RDMA2_SOUT_DSI3;
>> + } else {
>> + value = 0;
>> + }
>> +
>> + return value;
>> +}
>> +
>> +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
>> + enum mtk_ddp_comp_id next,
>> + unsigned int *addr)
>> +{
>> + unsigned int value;
>> +
>> + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>> + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
>> + value = COLOR0_SEL_IN_OVL0;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>> + value = DPI0_SEL_IN_RDMA1;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>> + value = DPI1_SEL_IN_RDMA1;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
>> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> + value = DSI0_SEL_IN_RDMA1;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>> + *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>> + value = DSI1_SEL_IN_RDMA1;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> + value = DSI2_SEL_IN_RDMA1;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>> + *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>> + value = DSI3_SEL_IN_RDMA1;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>> + value = DPI0_SEL_IN_RDMA2;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>> + value = DPI1_SEL_IN_RDMA2;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
>> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> + value = DSI0_SEL_IN_RDMA2;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>> + *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>> + value = DSI1_SEL_IN_RDMA2;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> + value = DSI2_SEL_IN_RDMA2;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> + value = DSI3_SEL_IN_RDMA2;
>> + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>> + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
>> + value = COLOR1_SEL_IN_OVL1;
>> + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>> + *addr = DISP_REG_CONFIG_DSI_SEL;
>> + value = DSI_SEL_IN_BLS;
>> + } else {
>> + value = 0;
>> + }
>> +
>> + return value;
>> +}
>> +
>> +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
>> + enum mtk_ddp_comp_id cur,
>> + enum mtk_ddp_comp_id next)
>> +{
>> + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>> + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
>> + config_regs + DISP_REG_CONFIG_OUT_SEL);
>> + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
>> + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
>> + config_regs + DISP_REG_CONFIG_OUT_SEL);
>> + writel_relaxed(DSI_SEL_IN_RDMA,
>> + config_regs + DISP_REG_CONFIG_DSI_SEL);
>> + writel_relaxed(DPI_SEL_IN_BLS,
>> + config_regs + DISP_REG_CONFIG_DPI_SEL);
>> + }
>> +}
>> +
>> +void mtk_mmsys_ddp_connect(struct device *dev,
>> + enum mtk_ddp_comp_id cur,
>> + enum mtk_ddp_comp_id next)
>> +{
>> + void __iomem *config_regs = dev_get_drvdata(dev);
>> + unsigned int addr, value, reg;
>> +
>> + value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
>> + if (value) {
>> + reg = readl_relaxed(config_regs + addr) | value;
>> + writel_relaxed(reg, config_regs + addr);
>> + }
>> +
>> + mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
>> +
>> + value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
>> + if (value) {
>> + reg = readl_relaxed(config_regs + addr) | value;
>> + writel_relaxed(reg, config_regs + addr);
>> + }
>> +}
>> +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
>> +
>> +void mtk_mmsys_ddp_disconnect(struct device *dev,
>> + enum mtk_ddp_comp_id cur,
>> + enum mtk_ddp_comp_id next)
>> +{
>> + void __iomem *config_regs = dev_get_drvdata(dev);
>> + unsigned int addr, value, reg;
>> +
>> + value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
>> + if (value) {
>> + reg = readl_relaxed(config_regs + addr) & ~value;
>> + writel_relaxed(reg, config_regs + addr);
>> + }
>> +
>> + value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
>> + if (value) {
>> + reg = readl_relaxed(config_regs + addr) & ~value;
>> + writel_relaxed(reg, config_regs + addr);
>> + }
>> +}
>> +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>> +
>> +static int mtk_mmsys_probe(struct platform_device *pdev)
>> +{
>> + const struct mtk_mmsys_driver_data *data;
>> + struct device *dev = &pdev->dev;
>> + struct platform_device *clks;
>> + struct platform_device *drm;
>> + void __iomem *config_regs;
>> + int ret;
>> +
>> + config_regs = devm_platform_ioremap_resource(pdev, 0);
>> + if (IS_ERR(config_regs)) {
>> + ret = PTR_ERR(config_regs);
>> + dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
>> + return ret;
>> + }
>> +
>> + platform_set_drvdata(pdev, config_regs);
>> +
>> + data = of_device_get_match_data(&pdev->dev);
>> +
>> + clks = platform_device_register_data(&pdev->dev, data->clk_driver,
>> + PLATFORM_DEVID_AUTO, NULL, 0);
>> + if (IS_ERR(clks))
>> + return PTR_ERR(clks);
>> +
>> + drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
>> + PLATFORM_DEVID_AUTO, NULL, 0);
>> + if (IS_ERR(drm)) {
>> + platform_device_unregister(clks);
>> + return PTR_ERR(drm);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static const struct of_device_id of_match_mtk_mmsys[] = {
>> + {
>> + .compatible = "mediatek,mt2701-mmsys",
>> + .data = &mt2701_mmsys_driver_data,
>> + },
>> + {
>> + .compatible = "mediatek,mt2712-mmsys",
>> + .data = &mt2712_mmsys_driver_data,
>> + },
>> + {
>> + .compatible = "mediatek,mt6779-mmsys",
>> + .data = &mt6779_mmsys_driver_data,
>> + },
>> + {
>> + .compatible = "mediatek,mt6797-mmsys",
>> + .data = &mt6797_mmsys_driver_data,
>> + },
>> + {
>> + .compatible = "mediatek,mt8173-mmsys",
>> + .data = &mt8173_mmsys_driver_data,
>> + },
>> + {
>> + .compatible = "mediatek,mt8183-mmsys",
>> + .data = &mt8183_mmsys_driver_data,
>> + },
>> + { }
>> +};
>> +
>> +static struct platform_driver mtk_mmsys_drv = {
>> + .driver = {
>> + .name = "mtk-mmsys",
>> + .of_match_table = of_match_mtk_mmsys,
>> + },
>> + .probe = mtk_mmsys_probe,
>> +};
>> +
>> +builtin_platform_driver(mtk_mmsys_drv);
>> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
>> deleted file mode 100644
>> index 18f9397..0000000
>> --- a/drivers/soc/mediatek/mtk-mmsys.c
>> +++ /dev/null
>> @@ -1,373 +0,0 @@
>> -// SPDX-License-Identifier: GPL-2.0-only
>> -/*
>> - * Copyright (c) 2014 MediaTek Inc.
>> - * Author: James Liao <jamesjj.liao@mediatek.com>
>> - */
>> -
>> -#include <linux/device.h>
>> -#include <linux/io.h>
>> -#include <linux/of_device.h>
>> -#include <linux/platform_device.h>
>> -#include <linux/soc/mediatek/mtk-mmsys.h>
>> -
>> -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
>> -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
>> -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
>> -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
>> -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
>> -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
>> -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
>> -#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
>> -#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
>> -#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
>> -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
>> -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
>> -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
>> -#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
>> -
>> -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
>> -#define DISP_REG_CONFIG_OUT_SEL 0x04c
>> -#define DISP_REG_CONFIG_DSI_SEL 0x050
>> -#define DISP_REG_CONFIG_DPI_SEL 0x064
>> -
>> -#define OVL0_MOUT_EN_COLOR0 0x1
>> -#define OD_MOUT_EN_RDMA0 0x1
>> -#define OD1_MOUT_EN_RDMA1 BIT(16)
>> -#define UFOE_MOUT_EN_DSI0 0x1
>> -#define COLOR0_SEL_IN_OVL0 0x1
>> -#define OVL1_MOUT_EN_COLOR1 0x1
>> -#define GAMMA_MOUT_EN_RDMA1 0x1
>> -#define RDMA0_SOUT_DPI0 0x2
>> -#define RDMA0_SOUT_DPI1 0x3
>> -#define RDMA0_SOUT_DSI1 0x1
>> -#define RDMA0_SOUT_DSI2 0x4
>> -#define RDMA0_SOUT_DSI3 0x5
>> -#define RDMA1_SOUT_DPI0 0x2
>> -#define RDMA1_SOUT_DPI1 0x3
>> -#define RDMA1_SOUT_DSI1 0x1
>> -#define RDMA1_SOUT_DSI2 0x4
>> -#define RDMA1_SOUT_DSI3 0x5
>> -#define RDMA2_SOUT_DPI0 0x2
>> -#define RDMA2_SOUT_DPI1 0x3
>> -#define RDMA2_SOUT_DSI1 0x1
>> -#define RDMA2_SOUT_DSI2 0x4
>> -#define RDMA2_SOUT_DSI3 0x5
>> -#define DPI0_SEL_IN_RDMA1 0x1
>> -#define DPI0_SEL_IN_RDMA2 0x3
>> -#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
>> -#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
>> -#define DSI0_SEL_IN_RDMA1 0x1
>> -#define DSI0_SEL_IN_RDMA2 0x4
>> -#define DSI1_SEL_IN_RDMA1 0x1
>> -#define DSI1_SEL_IN_RDMA2 0x4
>> -#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
>> -#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
>> -#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
>> -#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
>> -#define COLOR1_SEL_IN_OVL1 0x1
>> -
>> -#define OVL_MOUT_EN_RDMA 0x1
>> -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
>> -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
>> -#define DSI_SEL_IN_BLS 0x0
>> -#define DPI_SEL_IN_BLS 0x0
>> -#define DSI_SEL_IN_RDMA 0x1
>> -
>> -struct mtk_mmsys_driver_data {
>> - const char *clk_driver;
>> -};
>> -
>> -static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
>> - .clk_driver = "clk-mt2701-mm",
>> -};
>> -
>> -static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
>> - .clk_driver = "clk-mt2712-mm",
>> -};
>> -
>> -static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
>> - .clk_driver = "clk-mt6779-mm",
>> -};
>> -
>> -static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
>> - .clk_driver = "clk-mt6797-mm",
>> -};
>> -
>> -static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
>> - .clk_driver = "clk-mt8173-mm",
>> -};
>> -
>> -static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
>> - .clk_driver = "clk-mt8183-mm",
>> -};
>> -
>> -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
>> - enum mtk_ddp_comp_id next,
>> - unsigned int *addr)
>> -{
>> - unsigned int value;
>> -
>> - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>> - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
>> - value = OVL0_MOUT_EN_COLOR0;
>> - } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
>> - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
>> - value = OVL_MOUT_EN_RDMA;
>> - } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
>> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>> - value = OD_MOUT_EN_RDMA0;
>> - } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
>> - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
>> - value = UFOE_MOUT_EN_DSI0;
>> - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>> - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
>> - value = OVL1_MOUT_EN_COLOR1;
>> - } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
>> - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
>> - value = GAMMA_MOUT_EN_RDMA1;
>> - } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
>> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>> - value = OD1_MOUT_EN_RDMA1;
>> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> - value = RDMA0_SOUT_DPI0;
>> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> - value = RDMA0_SOUT_DPI1;
>> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> - value = RDMA0_SOUT_DSI1;
>> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> - value = RDMA0_SOUT_DSI2;
>> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> - value = RDMA0_SOUT_DSI3;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> - value = RDMA1_SOUT_DSI1;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> - value = RDMA1_SOUT_DSI2;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> - value = RDMA1_SOUT_DSI3;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> - value = RDMA1_SOUT_DPI0;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> - value = RDMA1_SOUT_DPI1;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> - value = RDMA2_SOUT_DPI0;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> - value = RDMA2_SOUT_DPI1;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> - value = RDMA2_SOUT_DSI1;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> - value = RDMA2_SOUT_DSI2;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> - value = RDMA2_SOUT_DSI3;
>> - } else {
>> - value = 0;
>> - }
>> -
>> - return value;
>> -}
>> -
>> -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
>> - enum mtk_ddp_comp_id next,
>> - unsigned int *addr)
>> -{
>> - unsigned int value;
>> -
>> - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>> - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
>> - value = COLOR0_SEL_IN_OVL0;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>> - value = DPI0_SEL_IN_RDMA1;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>> - value = DPI1_SEL_IN_RDMA1;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> - value = DSI0_SEL_IN_RDMA1;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>> - value = DSI1_SEL_IN_RDMA1;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> - value = DSI2_SEL_IN_RDMA1;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>> - value = DSI3_SEL_IN_RDMA1;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>> - value = DPI0_SEL_IN_RDMA2;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>> - value = DPI1_SEL_IN_RDMA2;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> - value = DSI0_SEL_IN_RDMA2;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>> - value = DSI1_SEL_IN_RDMA2;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> - value = DSI2_SEL_IN_RDMA2;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> - value = DSI3_SEL_IN_RDMA2;
>> - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>> - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
>> - value = COLOR1_SEL_IN_OVL1;
>> - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>> - *addr = DISP_REG_CONFIG_DSI_SEL;
>> - value = DSI_SEL_IN_BLS;
>> - } else {
>> - value = 0;
>> - }
>> -
>> - return value;
>> -}
>> -
>> -static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
>> - enum mtk_ddp_comp_id cur,
>> - enum mtk_ddp_comp_id next)
>> -{
>> - if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>> - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
>> - config_regs + DISP_REG_CONFIG_OUT_SEL);
>> - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
>> - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
>> - config_regs + DISP_REG_CONFIG_OUT_SEL);
>> - writel_relaxed(DSI_SEL_IN_RDMA,
>> - config_regs + DISP_REG_CONFIG_DSI_SEL);
>> - writel_relaxed(DPI_SEL_IN_BLS,
>> - config_regs + DISP_REG_CONFIG_DPI_SEL);
>> - }
>> -}
>> -
>> -void mtk_mmsys_ddp_connect(struct device *dev,
>> - enum mtk_ddp_comp_id cur,
>> - enum mtk_ddp_comp_id next)
>> -{
>> - void __iomem *config_regs = dev_get_drvdata(dev);
>> - unsigned int addr, value, reg;
>> -
>> - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
>> - if (value) {
>> - reg = readl_relaxed(config_regs + addr) | value;
>> - writel_relaxed(reg, config_regs + addr);
>> - }
>> -
>> - mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
>> -
>> - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
>> - if (value) {
>> - reg = readl_relaxed(config_regs + addr) | value;
>> - writel_relaxed(reg, config_regs + addr);
>> - }
>> -}
>> -EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
>> -
>> -void mtk_mmsys_ddp_disconnect(struct device *dev,
>> - enum mtk_ddp_comp_id cur,
>> - enum mtk_ddp_comp_id next)
>> -{
>> - void __iomem *config_regs = dev_get_drvdata(dev);
>> - unsigned int addr, value, reg;
>> -
>> - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
>> - if (value) {
>> - reg = readl_relaxed(config_regs + addr) & ~value;
>> - writel_relaxed(reg, config_regs + addr);
>> - }
>> -
>> - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
>> - if (value) {
>> - reg = readl_relaxed(config_regs + addr) & ~value;
>> - writel_relaxed(reg, config_regs + addr);
>> - }
>> -}
>> -EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>> -
>> -static int mtk_mmsys_probe(struct platform_device *pdev)
>> -{
>> - const struct mtk_mmsys_driver_data *data;
>> - struct device *dev = &pdev->dev;
>> - struct platform_device *clks;
>> - struct platform_device *drm;
>> - void __iomem *config_regs;
>> - int ret;
>> -
>> - config_regs = devm_platform_ioremap_resource(pdev, 0);
>> - if (IS_ERR(config_regs)) {
>> - ret = PTR_ERR(config_regs);
>> - dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
>> - return ret;
>> - }
>> -
>> - platform_set_drvdata(pdev, config_regs);
>> -
>> - data = of_device_get_match_data(&pdev->dev);
>> -
>> - clks = platform_device_register_data(&pdev->dev, data->clk_driver,
>> - PLATFORM_DEVID_AUTO, NULL, 0);
>> - if (IS_ERR(clks))
>> - return PTR_ERR(clks);
>> -
>> - drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
>> - PLATFORM_DEVID_AUTO, NULL, 0);
>> - if (IS_ERR(drm)) {
>> - platform_device_unregister(clks);
>> - return PTR_ERR(drm);
>> - }
>> -
>> - return 0;
>> -}
>> -
>> -static const struct of_device_id of_match_mtk_mmsys[] = {
>> - {
>> - .compatible = "mediatek,mt2701-mmsys",
>> - .data = &mt2701_mmsys_driver_data,
>> - },
>> - {
>> - .compatible = "mediatek,mt2712-mmsys",
>> - .data = &mt2712_mmsys_driver_data,
>> - },
>> - {
>> - .compatible = "mediatek,mt6779-mmsys",
>> - .data = &mt6779_mmsys_driver_data,
>> - },
>> - {
>> - .compatible = "mediatek,mt6797-mmsys",
>> - .data = &mt6797_mmsys_driver_data,
>> - },
>> - {
>> - .compatible = "mediatek,mt8173-mmsys",
>> - .data = &mt8173_mmsys_driver_data,
>> - },
>> - {
>> - .compatible = "mediatek,mt8183-mmsys",
>> - .data = &mt8183_mmsys_driver_data,
>> - },
>> - { }
>> -};
>> -
>> -static struct platform_driver mtk_mmsys_drv = {
>> - .driver = {
>> - .name = "mtk-mmsys",
>> - .of_match_table = of_match_mtk_mmsys,
>> - },
>> - .probe = mtk_mmsys_probe,
>> -};
>> -
>> -builtin_platform_driver(mtk_mmsys_drv);
>> --
>> 1.8.1.1.dirty
>> _______________________________________________
>> Linux-mediatek mailing list
>> Linux-mediatek@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-mediatek
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^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4, 01/10] soc: mediatek: mmsys: create mmsys folder
@ 2021-02-10 11:59 ` Matthias Brugger
0 siblings, 0 replies; 75+ messages in thread
From: Matthias Brugger @ 2021-02-10 11:59 UTC (permalink / raw)
To: Enric Balletbo Serra, Yongqiang Niu
Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Rob Herring,
moderated list:ARM/Mediatek SoC support, Linux ARM
On 09/02/2021 16:38, Enric Balletbo Serra wrote:
> Hi Yongqiang Niu,
>
> Thank you for your patch.
>
> Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dt., 5
> de gen. 2021 a les 4:07:
>>
>> the mmsys will more and more complicated after support
>> more and more SoCs, add an independent folder will be
>> more clear
>>
>> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
>> ---
>> drivers/soc/mediatek/Makefile | 2 +-
>
> It will not apply cleanly anymore after the below commit that is
> already queued. Maybe you could rebase the patches and resend them
> again?
>
Please don't do that, as I pointed out in [1] I don't like the approach of a new
folder. If you disagree please let me know why. Otherwise please send a new
version with the changes suggested by me :)
Regards,
Matthias
[1]
https://lore.kernel.org/linux-mediatek/4cadc9f0-0761-7609-abac-d2211b097bda@gmail.com/
> commit e1e4f7fea37572f0ccf3887430e52c491e9accb6
> Author: CK Hu <ck.hu@mediatek.com>
> Date: Tue Jul 21 15:46:06 2020 +0800
>
> soc / drm: mediatek: Move mtk mutex driver to soc folder
>
> mtk mutex is used by DRM and MDP driver, and its function is SoC-specific,
> so move it to soc folder.
>
> With that fixed,
>
> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
>
> Thanks,
> Enric
>
>> drivers/soc/mediatek/mmsys/Makefile | 2 +
>> drivers/soc/mediatek/mmsys/mtk-mmsys.c | 373 +++++++++++++++++++++++++++++++++
>> drivers/soc/mediatek/mtk-mmsys.c | 373 ---------------------------------
>> 4 files changed, 376 insertions(+), 374 deletions(-)
>> create mode 100644 drivers/soc/mediatek/mmsys/Makefile
>> create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c
>> delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c
>>
>> diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
>> index b6908db..eca9774 100644
>> --- a/drivers/soc/mediatek/Makefile
>> +++ b/drivers/soc/mediatek/Makefile
>> @@ -5,4 +5,4 @@ obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
>> obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
>> obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
>> obj-$(CONFIG_MTK_SCPSYS_PM_DOMAINS) += mtk-pm-domains.o
>> -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
>> +obj-$(CONFIG_MTK_MMSYS) += mmsys/
>> diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
>> new file mode 100644
>> index 0000000..f44eadc
>> --- /dev/null
>> +++ b/drivers/soc/mediatek/mmsys/Makefile
>> @@ -0,0 +1,2 @@
>> +# SPDX-License-Identifier: GPL-2.0-only
>> +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
>> diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
>> new file mode 100644
>> index 0000000..18f9397
>> --- /dev/null
>> +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
>> @@ -0,0 +1,373 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) 2014 MediaTek Inc.
>> + * Author: James Liao <jamesjj.liao@mediatek.com>
>> + */
>> +
>> +#include <linux/device.h>
>> +#include <linux/io.h>
>> +#include <linux/of_device.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/soc/mediatek/mtk-mmsys.h>
>> +
>> +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
>> +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
>> +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
>> +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
>> +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
>> +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
>> +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
>> +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
>> +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
>> +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
>> +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
>> +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
>> +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
>> +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
>> +
>> +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
>> +#define DISP_REG_CONFIG_OUT_SEL 0x04c
>> +#define DISP_REG_CONFIG_DSI_SEL 0x050
>> +#define DISP_REG_CONFIG_DPI_SEL 0x064
>> +
>> +#define OVL0_MOUT_EN_COLOR0 0x1
>> +#define OD_MOUT_EN_RDMA0 0x1
>> +#define OD1_MOUT_EN_RDMA1 BIT(16)
>> +#define UFOE_MOUT_EN_DSI0 0x1
>> +#define COLOR0_SEL_IN_OVL0 0x1
>> +#define OVL1_MOUT_EN_COLOR1 0x1
>> +#define GAMMA_MOUT_EN_RDMA1 0x1
>> +#define RDMA0_SOUT_DPI0 0x2
>> +#define RDMA0_SOUT_DPI1 0x3
>> +#define RDMA0_SOUT_DSI1 0x1
>> +#define RDMA0_SOUT_DSI2 0x4
>> +#define RDMA0_SOUT_DSI3 0x5
>> +#define RDMA1_SOUT_DPI0 0x2
>> +#define RDMA1_SOUT_DPI1 0x3
>> +#define RDMA1_SOUT_DSI1 0x1
>> +#define RDMA1_SOUT_DSI2 0x4
>> +#define RDMA1_SOUT_DSI3 0x5
>> +#define RDMA2_SOUT_DPI0 0x2
>> +#define RDMA2_SOUT_DPI1 0x3
>> +#define RDMA2_SOUT_DSI1 0x1
>> +#define RDMA2_SOUT_DSI2 0x4
>> +#define RDMA2_SOUT_DSI3 0x5
>> +#define DPI0_SEL_IN_RDMA1 0x1
>> +#define DPI0_SEL_IN_RDMA2 0x3
>> +#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
>> +#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
>> +#define DSI0_SEL_IN_RDMA1 0x1
>> +#define DSI0_SEL_IN_RDMA2 0x4
>> +#define DSI1_SEL_IN_RDMA1 0x1
>> +#define DSI1_SEL_IN_RDMA2 0x4
>> +#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
>> +#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
>> +#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
>> +#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
>> +#define COLOR1_SEL_IN_OVL1 0x1
>> +
>> +#define OVL_MOUT_EN_RDMA 0x1
>> +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
>> +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
>> +#define DSI_SEL_IN_BLS 0x0
>> +#define DPI_SEL_IN_BLS 0x0
>> +#define DSI_SEL_IN_RDMA 0x1
>> +
>> +struct mtk_mmsys_driver_data {
>> + const char *clk_driver;
>> +};
>> +
>> +static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
>> + .clk_driver = "clk-mt2701-mm",
>> +};
>> +
>> +static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
>> + .clk_driver = "clk-mt2712-mm",
>> +};
>> +
>> +static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
>> + .clk_driver = "clk-mt6779-mm",
>> +};
>> +
>> +static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
>> + .clk_driver = "clk-mt6797-mm",
>> +};
>> +
>> +static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
>> + .clk_driver = "clk-mt8173-mm",
>> +};
>> +
>> +static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
>> + .clk_driver = "clk-mt8183-mm",
>> +};
>> +
>> +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
>> + enum mtk_ddp_comp_id next,
>> + unsigned int *addr)
>> +{
>> + unsigned int value;
>> +
>> + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>> + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
>> + value = OVL0_MOUT_EN_COLOR0;
>> + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
>> + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
>> + value = OVL_MOUT_EN_RDMA;
>> + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
>> + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>> + value = OD_MOUT_EN_RDMA0;
>> + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
>> + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
>> + value = UFOE_MOUT_EN_DSI0;
>> + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>> + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
>> + value = OVL1_MOUT_EN_COLOR1;
>> + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
>> + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
>> + value = GAMMA_MOUT_EN_RDMA1;
>> + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
>> + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>> + value = OD1_MOUT_EN_RDMA1;
>> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> + value = RDMA0_SOUT_DPI0;
>> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> + value = RDMA0_SOUT_DPI1;
>> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> + value = RDMA0_SOUT_DSI1;
>> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> + value = RDMA0_SOUT_DSI2;
>> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> + value = RDMA0_SOUT_DSI3;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> + value = RDMA1_SOUT_DSI1;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> + value = RDMA1_SOUT_DSI2;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> + value = RDMA1_SOUT_DSI3;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> + value = RDMA1_SOUT_DPI0;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> + value = RDMA1_SOUT_DPI1;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> + value = RDMA2_SOUT_DPI0;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> + value = RDMA2_SOUT_DPI1;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> + value = RDMA2_SOUT_DSI1;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> + value = RDMA2_SOUT_DSI2;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> + value = RDMA2_SOUT_DSI3;
>> + } else {
>> + value = 0;
>> + }
>> +
>> + return value;
>> +}
>> +
>> +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
>> + enum mtk_ddp_comp_id next,
>> + unsigned int *addr)
>> +{
>> + unsigned int value;
>> +
>> + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>> + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
>> + value = COLOR0_SEL_IN_OVL0;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>> + value = DPI0_SEL_IN_RDMA1;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>> + value = DPI1_SEL_IN_RDMA1;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
>> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> + value = DSI0_SEL_IN_RDMA1;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>> + *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>> + value = DSI1_SEL_IN_RDMA1;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> + value = DSI2_SEL_IN_RDMA1;
>> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>> + *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>> + value = DSI3_SEL_IN_RDMA1;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>> + value = DPI0_SEL_IN_RDMA2;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>> + value = DPI1_SEL_IN_RDMA2;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
>> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> + value = DSI0_SEL_IN_RDMA2;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>> + *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>> + value = DSI1_SEL_IN_RDMA2;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> + value = DSI2_SEL_IN_RDMA2;
>> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> + value = DSI3_SEL_IN_RDMA2;
>> + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>> + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
>> + value = COLOR1_SEL_IN_OVL1;
>> + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>> + *addr = DISP_REG_CONFIG_DSI_SEL;
>> + value = DSI_SEL_IN_BLS;
>> + } else {
>> + value = 0;
>> + }
>> +
>> + return value;
>> +}
>> +
>> +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
>> + enum mtk_ddp_comp_id cur,
>> + enum mtk_ddp_comp_id next)
>> +{
>> + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>> + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
>> + config_regs + DISP_REG_CONFIG_OUT_SEL);
>> + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
>> + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
>> + config_regs + DISP_REG_CONFIG_OUT_SEL);
>> + writel_relaxed(DSI_SEL_IN_RDMA,
>> + config_regs + DISP_REG_CONFIG_DSI_SEL);
>> + writel_relaxed(DPI_SEL_IN_BLS,
>> + config_regs + DISP_REG_CONFIG_DPI_SEL);
>> + }
>> +}
>> +
>> +void mtk_mmsys_ddp_connect(struct device *dev,
>> + enum mtk_ddp_comp_id cur,
>> + enum mtk_ddp_comp_id next)
>> +{
>> + void __iomem *config_regs = dev_get_drvdata(dev);
>> + unsigned int addr, value, reg;
>> +
>> + value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
>> + if (value) {
>> + reg = readl_relaxed(config_regs + addr) | value;
>> + writel_relaxed(reg, config_regs + addr);
>> + }
>> +
>> + mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
>> +
>> + value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
>> + if (value) {
>> + reg = readl_relaxed(config_regs + addr) | value;
>> + writel_relaxed(reg, config_regs + addr);
>> + }
>> +}
>> +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
>> +
>> +void mtk_mmsys_ddp_disconnect(struct device *dev,
>> + enum mtk_ddp_comp_id cur,
>> + enum mtk_ddp_comp_id next)
>> +{
>> + void __iomem *config_regs = dev_get_drvdata(dev);
>> + unsigned int addr, value, reg;
>> +
>> + value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
>> + if (value) {
>> + reg = readl_relaxed(config_regs + addr) & ~value;
>> + writel_relaxed(reg, config_regs + addr);
>> + }
>> +
>> + value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
>> + if (value) {
>> + reg = readl_relaxed(config_regs + addr) & ~value;
>> + writel_relaxed(reg, config_regs + addr);
>> + }
>> +}
>> +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>> +
>> +static int mtk_mmsys_probe(struct platform_device *pdev)
>> +{
>> + const struct mtk_mmsys_driver_data *data;
>> + struct device *dev = &pdev->dev;
>> + struct platform_device *clks;
>> + struct platform_device *drm;
>> + void __iomem *config_regs;
>> + int ret;
>> +
>> + config_regs = devm_platform_ioremap_resource(pdev, 0);
>> + if (IS_ERR(config_regs)) {
>> + ret = PTR_ERR(config_regs);
>> + dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
>> + return ret;
>> + }
>> +
>> + platform_set_drvdata(pdev, config_regs);
>> +
>> + data = of_device_get_match_data(&pdev->dev);
>> +
>> + clks = platform_device_register_data(&pdev->dev, data->clk_driver,
>> + PLATFORM_DEVID_AUTO, NULL, 0);
>> + if (IS_ERR(clks))
>> + return PTR_ERR(clks);
>> +
>> + drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
>> + PLATFORM_DEVID_AUTO, NULL, 0);
>> + if (IS_ERR(drm)) {
>> + platform_device_unregister(clks);
>> + return PTR_ERR(drm);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static const struct of_device_id of_match_mtk_mmsys[] = {
>> + {
>> + .compatible = "mediatek,mt2701-mmsys",
>> + .data = &mt2701_mmsys_driver_data,
>> + },
>> + {
>> + .compatible = "mediatek,mt2712-mmsys",
>> + .data = &mt2712_mmsys_driver_data,
>> + },
>> + {
>> + .compatible = "mediatek,mt6779-mmsys",
>> + .data = &mt6779_mmsys_driver_data,
>> + },
>> + {
>> + .compatible = "mediatek,mt6797-mmsys",
>> + .data = &mt6797_mmsys_driver_data,
>> + },
>> + {
>> + .compatible = "mediatek,mt8173-mmsys",
>> + .data = &mt8173_mmsys_driver_data,
>> + },
>> + {
>> + .compatible = "mediatek,mt8183-mmsys",
>> + .data = &mt8183_mmsys_driver_data,
>> + },
>> + { }
>> +};
>> +
>> +static struct platform_driver mtk_mmsys_drv = {
>> + .driver = {
>> + .name = "mtk-mmsys",
>> + .of_match_table = of_match_mtk_mmsys,
>> + },
>> + .probe = mtk_mmsys_probe,
>> +};
>> +
>> +builtin_platform_driver(mtk_mmsys_drv);
>> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
>> deleted file mode 100644
>> index 18f9397..0000000
>> --- a/drivers/soc/mediatek/mtk-mmsys.c
>> +++ /dev/null
>> @@ -1,373 +0,0 @@
>> -// SPDX-License-Identifier: GPL-2.0-only
>> -/*
>> - * Copyright (c) 2014 MediaTek Inc.
>> - * Author: James Liao <jamesjj.liao@mediatek.com>
>> - */
>> -
>> -#include <linux/device.h>
>> -#include <linux/io.h>
>> -#include <linux/of_device.h>
>> -#include <linux/platform_device.h>
>> -#include <linux/soc/mediatek/mtk-mmsys.h>
>> -
>> -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
>> -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
>> -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
>> -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
>> -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
>> -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
>> -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
>> -#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
>> -#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
>> -#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
>> -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
>> -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
>> -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
>> -#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
>> -
>> -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
>> -#define DISP_REG_CONFIG_OUT_SEL 0x04c
>> -#define DISP_REG_CONFIG_DSI_SEL 0x050
>> -#define DISP_REG_CONFIG_DPI_SEL 0x064
>> -
>> -#define OVL0_MOUT_EN_COLOR0 0x1
>> -#define OD_MOUT_EN_RDMA0 0x1
>> -#define OD1_MOUT_EN_RDMA1 BIT(16)
>> -#define UFOE_MOUT_EN_DSI0 0x1
>> -#define COLOR0_SEL_IN_OVL0 0x1
>> -#define OVL1_MOUT_EN_COLOR1 0x1
>> -#define GAMMA_MOUT_EN_RDMA1 0x1
>> -#define RDMA0_SOUT_DPI0 0x2
>> -#define RDMA0_SOUT_DPI1 0x3
>> -#define RDMA0_SOUT_DSI1 0x1
>> -#define RDMA0_SOUT_DSI2 0x4
>> -#define RDMA0_SOUT_DSI3 0x5
>> -#define RDMA1_SOUT_DPI0 0x2
>> -#define RDMA1_SOUT_DPI1 0x3
>> -#define RDMA1_SOUT_DSI1 0x1
>> -#define RDMA1_SOUT_DSI2 0x4
>> -#define RDMA1_SOUT_DSI3 0x5
>> -#define RDMA2_SOUT_DPI0 0x2
>> -#define RDMA2_SOUT_DPI1 0x3
>> -#define RDMA2_SOUT_DSI1 0x1
>> -#define RDMA2_SOUT_DSI2 0x4
>> -#define RDMA2_SOUT_DSI3 0x5
>> -#define DPI0_SEL_IN_RDMA1 0x1
>> -#define DPI0_SEL_IN_RDMA2 0x3
>> -#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
>> -#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
>> -#define DSI0_SEL_IN_RDMA1 0x1
>> -#define DSI0_SEL_IN_RDMA2 0x4
>> -#define DSI1_SEL_IN_RDMA1 0x1
>> -#define DSI1_SEL_IN_RDMA2 0x4
>> -#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
>> -#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
>> -#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
>> -#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
>> -#define COLOR1_SEL_IN_OVL1 0x1
>> -
>> -#define OVL_MOUT_EN_RDMA 0x1
>> -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
>> -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
>> -#define DSI_SEL_IN_BLS 0x0
>> -#define DPI_SEL_IN_BLS 0x0
>> -#define DSI_SEL_IN_RDMA 0x1
>> -
>> -struct mtk_mmsys_driver_data {
>> - const char *clk_driver;
>> -};
>> -
>> -static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
>> - .clk_driver = "clk-mt2701-mm",
>> -};
>> -
>> -static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
>> - .clk_driver = "clk-mt2712-mm",
>> -};
>> -
>> -static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
>> - .clk_driver = "clk-mt6779-mm",
>> -};
>> -
>> -static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
>> - .clk_driver = "clk-mt6797-mm",
>> -};
>> -
>> -static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
>> - .clk_driver = "clk-mt8173-mm",
>> -};
>> -
>> -static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
>> - .clk_driver = "clk-mt8183-mm",
>> -};
>> -
>> -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
>> - enum mtk_ddp_comp_id next,
>> - unsigned int *addr)
>> -{
>> - unsigned int value;
>> -
>> - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>> - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
>> - value = OVL0_MOUT_EN_COLOR0;
>> - } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
>> - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
>> - value = OVL_MOUT_EN_RDMA;
>> - } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
>> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>> - value = OD_MOUT_EN_RDMA0;
>> - } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
>> - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
>> - value = UFOE_MOUT_EN_DSI0;
>> - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>> - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
>> - value = OVL1_MOUT_EN_COLOR1;
>> - } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
>> - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
>> - value = GAMMA_MOUT_EN_RDMA1;
>> - } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
>> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>> - value = OD1_MOUT_EN_RDMA1;
>> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> - value = RDMA0_SOUT_DPI0;
>> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> - value = RDMA0_SOUT_DPI1;
>> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> - value = RDMA0_SOUT_DSI1;
>> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> - value = RDMA0_SOUT_DSI2;
>> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>> - value = RDMA0_SOUT_DSI3;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> - value = RDMA1_SOUT_DSI1;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> - value = RDMA1_SOUT_DSI2;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> - value = RDMA1_SOUT_DSI3;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> - value = RDMA1_SOUT_DPI0;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>> - value = RDMA1_SOUT_DPI1;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> - value = RDMA2_SOUT_DPI0;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> - value = RDMA2_SOUT_DPI1;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> - value = RDMA2_SOUT_DSI1;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> - value = RDMA2_SOUT_DSI2;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>> - value = RDMA2_SOUT_DSI3;
>> - } else {
>> - value = 0;
>> - }
>> -
>> - return value;
>> -}
>> -
>> -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
>> - enum mtk_ddp_comp_id next,
>> - unsigned int *addr)
>> -{
>> - unsigned int value;
>> -
>> - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>> - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
>> - value = COLOR0_SEL_IN_OVL0;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>> - value = DPI0_SEL_IN_RDMA1;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>> - value = DPI1_SEL_IN_RDMA1;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> - value = DSI0_SEL_IN_RDMA1;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>> - value = DSI1_SEL_IN_RDMA1;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> - value = DSI2_SEL_IN_RDMA1;
>> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>> - value = DSI3_SEL_IN_RDMA1;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>> - value = DPI0_SEL_IN_RDMA2;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>> - value = DPI1_SEL_IN_RDMA2;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> - value = DSI0_SEL_IN_RDMA2;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>> - value = DSI1_SEL_IN_RDMA2;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> - value = DSI2_SEL_IN_RDMA2;
>> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>> - value = DSI3_SEL_IN_RDMA2;
>> - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>> - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
>> - value = COLOR1_SEL_IN_OVL1;
>> - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>> - *addr = DISP_REG_CONFIG_DSI_SEL;
>> - value = DSI_SEL_IN_BLS;
>> - } else {
>> - value = 0;
>> - }
>> -
>> - return value;
>> -}
>> -
>> -static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
>> - enum mtk_ddp_comp_id cur,
>> - enum mtk_ddp_comp_id next)
>> -{
>> - if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>> - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
>> - config_regs + DISP_REG_CONFIG_OUT_SEL);
>> - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
>> - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
>> - config_regs + DISP_REG_CONFIG_OUT_SEL);
>> - writel_relaxed(DSI_SEL_IN_RDMA,
>> - config_regs + DISP_REG_CONFIG_DSI_SEL);
>> - writel_relaxed(DPI_SEL_IN_BLS,
>> - config_regs + DISP_REG_CONFIG_DPI_SEL);
>> - }
>> -}
>> -
>> -void mtk_mmsys_ddp_connect(struct device *dev,
>> - enum mtk_ddp_comp_id cur,
>> - enum mtk_ddp_comp_id next)
>> -{
>> - void __iomem *config_regs = dev_get_drvdata(dev);
>> - unsigned int addr, value, reg;
>> -
>> - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
>> - if (value) {
>> - reg = readl_relaxed(config_regs + addr) | value;
>> - writel_relaxed(reg, config_regs + addr);
>> - }
>> -
>> - mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
>> -
>> - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
>> - if (value) {
>> - reg = readl_relaxed(config_regs + addr) | value;
>> - writel_relaxed(reg, config_regs + addr);
>> - }
>> -}
>> -EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
>> -
>> -void mtk_mmsys_ddp_disconnect(struct device *dev,
>> - enum mtk_ddp_comp_id cur,
>> - enum mtk_ddp_comp_id next)
>> -{
>> - void __iomem *config_regs = dev_get_drvdata(dev);
>> - unsigned int addr, value, reg;
>> -
>> - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
>> - if (value) {
>> - reg = readl_relaxed(config_regs + addr) & ~value;
>> - writel_relaxed(reg, config_regs + addr);
>> - }
>> -
>> - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
>> - if (value) {
>> - reg = readl_relaxed(config_regs + addr) & ~value;
>> - writel_relaxed(reg, config_regs + addr);
>> - }
>> -}
>> -EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>> -
>> -static int mtk_mmsys_probe(struct platform_device *pdev)
>> -{
>> - const struct mtk_mmsys_driver_data *data;
>> - struct device *dev = &pdev->dev;
>> - struct platform_device *clks;
>> - struct platform_device *drm;
>> - void __iomem *config_regs;
>> - int ret;
>> -
>> - config_regs = devm_platform_ioremap_resource(pdev, 0);
>> - if (IS_ERR(config_regs)) {
>> - ret = PTR_ERR(config_regs);
>> - dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
>> - return ret;
>> - }
>> -
>> - platform_set_drvdata(pdev, config_regs);
>> -
>> - data = of_device_get_match_data(&pdev->dev);
>> -
>> - clks = platform_device_register_data(&pdev->dev, data->clk_driver,
>> - PLATFORM_DEVID_AUTO, NULL, 0);
>> - if (IS_ERR(clks))
>> - return PTR_ERR(clks);
>> -
>> - drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
>> - PLATFORM_DEVID_AUTO, NULL, 0);
>> - if (IS_ERR(drm)) {
>> - platform_device_unregister(clks);
>> - return PTR_ERR(drm);
>> - }
>> -
>> - return 0;
>> -}
>> -
>> -static const struct of_device_id of_match_mtk_mmsys[] = {
>> - {
>> - .compatible = "mediatek,mt2701-mmsys",
>> - .data = &mt2701_mmsys_driver_data,
>> - },
>> - {
>> - .compatible = "mediatek,mt2712-mmsys",
>> - .data = &mt2712_mmsys_driver_data,
>> - },
>> - {
>> - .compatible = "mediatek,mt6779-mmsys",
>> - .data = &mt6779_mmsys_driver_data,
>> - },
>> - {
>> - .compatible = "mediatek,mt6797-mmsys",
>> - .data = &mt6797_mmsys_driver_data,
>> - },
>> - {
>> - .compatible = "mediatek,mt8173-mmsys",
>> - .data = &mt8173_mmsys_driver_data,
>> - },
>> - {
>> - .compatible = "mediatek,mt8183-mmsys",
>> - .data = &mt8183_mmsys_driver_data,
>> - },
>> - { }
>> -};
>> -
>> -static struct platform_driver mtk_mmsys_drv = {
>> - .driver = {
>> - .name = "mtk-mmsys",
>> - .of_match_table = of_match_mtk_mmsys,
>> - },
>> - .probe = mtk_mmsys_probe,
>> -};
>> -
>> -builtin_platform_driver(mtk_mmsys_drv);
>> --
>> 1.8.1.1.dirty
>> _______________________________________________
>> Linux-mediatek mailing list
>> Linux-mediatek@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4, 08/10] soc: mediatek: mmsys: add component RDMA4
2021-01-05 3:06 ` Yongqiang Niu
(?)
(?)
@ 2021-03-22 15:08 ` Chun-Kuang Hu
-1 siblings, 0 replies; 75+ messages in thread
From: Chun-Kuang Hu @ 2021-03-22 15:08 UTC (permalink / raw)
To: Yongqiang Niu
Cc: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger,
Mark Rutland, DTML, David Airlie, linux-kernel, DRI Development,
Project_Global_Chrome_Upstream_Group,
moderated list:ARM/Mediatek SoC support, Daniel Vetter,
Linux ARM
Hi, Matthias:
Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2021年1月5日 週二 上午11:07寫道：
>
> This patch add component RDMA4
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
How do you think about this patch? One drm patch [1] depends on this patch.
[1] https://patchwork.kernel.org/project/linux-mediatek/patch/20210202081237.774442-4-hsinyi@chromium.org/
Regards,
Chun-Kuang.
> ---
> include/linux/soc/mediatek/mtk-mmsys.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 13546e9..2c11617 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -38,6 +38,7 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_RDMA0,
> DDP_COMPONENT_RDMA1,
> DDP_COMPONENT_RDMA2,
> + DDP_COMPONENT_RDMA4,
> DDP_COMPONENT_UFOE,
> DDP_COMPONENT_WDMA0,
> DDP_COMPONENT_WDMA1,
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4, 08/10] soc: mediatek: mmsys: add component RDMA4
@ 2021-03-22 15:08 ` Chun-Kuang Hu
0 siblings, 0 replies; 75+ messages in thread
From: Chun-Kuang Hu @ 2021-03-22 15:08 UTC (permalink / raw)
To: Yongqiang Niu
Cc: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger,
Mark Rutland, DTML, David Airlie, linux-kernel, DRI Development,
Project_Global_Chrome_Upstream_Group,
moderated list:ARM/Mediatek SoC support, Daniel Vetter,
Linux ARM
Hi, Matthias:
Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2021年1月5日 週二 上午11:07寫道：
>
> This patch add component RDMA4
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
How do you think about this patch? One drm patch [1] depends on this patch.
[1] https://patchwork.kernel.org/project/linux-mediatek/patch/20210202081237.774442-4-hsinyi@chromium.org/
Regards,
Chun-Kuang.
> ---
> include/linux/soc/mediatek/mtk-mmsys.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 13546e9..2c11617 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -38,6 +38,7 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_RDMA0,
> DDP_COMPONENT_RDMA1,
> DDP_COMPONENT_RDMA2,
> + DDP_COMPONENT_RDMA4,
> DDP_COMPONENT_UFOE,
> DDP_COMPONENT_WDMA0,
> DDP_COMPONENT_WDMA1,
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4, 08/10] soc: mediatek: mmsys: add component RDMA4
@ 2021-03-22 15:08 ` Chun-Kuang Hu
0 siblings, 0 replies; 75+ messages in thread
From: Chun-Kuang Hu @ 2021-03-22 15:08 UTC (permalink / raw)
To: Yongqiang Niu
Cc: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger,
Mark Rutland, DTML, David Airlie, linux-kernel, DRI Development,
Project_Global_Chrome_Upstream_Group,
moderated list:ARM/Mediatek SoC support, Daniel Vetter,
Linux ARM
Hi, Matthias:
Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2021年1月5日 週二 上午11:07寫道：
>
> This patch add component RDMA4
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
How do you think about this patch? One drm patch [1] depends on this patch.
[1] https://patchwork.kernel.org/project/linux-mediatek/patch/20210202081237.774442-4-hsinyi@chromium.org/
Regards,
Chun-Kuang.
> ---
> include/linux/soc/mediatek/mtk-mmsys.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 13546e9..2c11617 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -38,6 +38,7 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_RDMA0,
> DDP_COMPONENT_RDMA1,
> DDP_COMPONENT_RDMA2,
> + DDP_COMPONENT_RDMA4,
> DDP_COMPONENT_UFOE,
> DDP_COMPONENT_WDMA0,
> DDP_COMPONENT_WDMA1,
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4, 08/10] soc: mediatek: mmsys: add component RDMA4
@ 2021-03-22 15:08 ` Chun-Kuang Hu
0 siblings, 0 replies; 75+ messages in thread
From: Chun-Kuang Hu @ 2021-03-22 15:08 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, DTML, David Airlie, linux-kernel, DRI Development,
Project_Global_Chrome_Upstream_Group, Matthias Brugger,
Rob Herring, moderated list:ARM/Mediatek SoC support, Linux ARM
Hi, Matthias:
Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2021年1月5日 週二 上午11:07寫道：
>
> This patch add component RDMA4
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
How do you think about this patch? One drm patch [1] depends on this patch.
[1] https://patchwork.kernel.org/project/linux-mediatek/patch/20210202081237.774442-4-hsinyi@chromium.org/
Regards,
Chun-Kuang.
> ---
> include/linux/soc/mediatek/mtk-mmsys.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 13546e9..2c11617 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -38,6 +38,7 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_RDMA0,
> DDP_COMPONENT_RDMA1,
> DDP_COMPONENT_RDMA2,
> + DDP_COMPONENT_RDMA4,
> DDP_COMPONENT_UFOE,
> DDP_COMPONENT_WDMA0,
> DDP_COMPONENT_WDMA1,
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 75+ messages in thread
end of thread, other threads:[~2021-03-22 15:11 UTC | newest]
Thread overview: 75+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-01-05 3:06 [PATCH v4, 00/10] soc: mediatek: mmsys: Use function call for setting the routing registers Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-01-05 3:06 ` [PATCH v4, 01/10] soc: mediatek: mmsys: create mmsys folder Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-02-09 15:38 ` Enric Balletbo Serra
2021-02-09 15:38 ` Enric Balletbo Serra
2021-02-09 15:38 ` Enric Balletbo Serra
2021-02-09 15:38 ` Enric Balletbo Serra
2021-02-10 11:59 ` Matthias Brugger
2021-02-10 11:59 ` Matthias Brugger
2021-02-10 11:59 ` Matthias Brugger
2021-02-10 11:59 ` Matthias Brugger
2021-01-05 3:06 ` [PATCH v4, 02/10] soc: mediatek: mmsys: Create struct mtk_mmsys to store context data Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-01-05 3:06 ` [PATCH v4, 03/10] soc: mediatek: mmsys: move register operation into mmsys path select function Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-01-20 19:38 ` Matthias Brugger
2021-01-20 19:38 ` Matthias Brugger
2021-01-20 19:38 ` Matthias Brugger
2021-01-20 19:38 ` Matthias Brugger
2021-01-21 0:56 ` Yongqiang Niu
2021-01-21 0:56 ` Yongqiang Niu
2021-01-21 0:56 ` Yongqiang Niu
2021-01-21 0:56 ` Yongqiang Niu
2021-01-29 15:35 ` Matthias Brugger
2021-01-29 15:35 ` Matthias Brugger
2021-01-29 15:35 ` Matthias Brugger
2021-01-05 3:06 ` [PATCH v4, 04/10] soc: mediatek: mmsys: Use function call for setting the routing registers Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-01-05 3:06 ` [PATCH v4, 05/10] soc: mediatek: mmsys: add mt8183 " Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-01-05 3:06 ` [PATCH v4, 06/10] soc: mediatek: mmsys: add component OVL_2L2 Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-01-05 3:06 ` [PATCH v4, 07/10] soc: mediatek: mmsys: add component POSTMASK Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-01-05 3:06 ` [PATCH v4, 08/10] soc: mediatek: mmsys: add component RDMA4 Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-03-22 15:08 ` Chun-Kuang Hu
2021-03-22 15:08 ` Chun-Kuang Hu
2021-03-22 15:08 ` Chun-Kuang Hu
2021-03-22 15:08 ` Chun-Kuang Hu
2021-01-05 3:06 ` [PATCH v4, 09/10] soc: mediatek: mmsys: Use function call for setting mmsys ovl mout register Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-01-05 3:06 ` [PATCH v4, 10/10] soc: mediatek: mmsys: add mt8192 mmsys support Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-01-05 3:06 ` Yongqiang Niu
2021-01-06 16:36 ` Chun-Kuang Hu
2021-01-06 16:36 ` Chun-Kuang Hu
2021-01-06 16:36 ` Chun-Kuang Hu
2021-01-06 16:36 ` Chun-Kuang Hu
2021-01-19 4:16 ` [PATCH v4, 00/10] soc: mediatek: mmsys: Use function call for setting the routing registers Hsin-Yi Wang
2021-01-19 4:16 ` Hsin-Yi Wang
2021-01-19 4:16 ` Hsin-Yi Wang
2021-01-19 4:16 ` Hsin-Yi Wang
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