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From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Andi Shyti <andi.shyti@linux.intel.com>,
	Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: "Chris Wilson" <chris.p.wilson@intel.com>,
	"Fei Yang" <fei.yang@intel.com>,
	"Thomas Hellstrom" <thomas.hellstrom@intel.com>,
	"Bruce Chang" <yu.bruce.chang@intel.com>,
	"Daniel Vetter" <daniel@ffwll.ch>,
	"Dave Airlie" <airlied@redhat.com>,
	"David Airlie" <airlied@linux.ie>,
	"Jani Nikula" <jani.nikula@linux.intel.com>,
	"John Harrison" <John.C.Harrison@intel.com>,
	"Joonas Lahtinen" <joonas.lahtinen@linux.intel.com>,
	"Matt Roper" <matthew.d.roper@intel.com>,
	"Matthew Brost" <matthew.brost@intel.com>,
	"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
	"Tejas Upadhyay" <tejaskumarx.surendrakumar.upadhyay@intel.com>,
	"Umesh Nerlige Ramappa" <umesh.nerlige.ramappa@intel.com>,
	dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
	linux-kernel@vger.kernel.org, mauro.chehab@linux.intel.com,
	"Mika Kuoppala" <mika.kuoppala@linux.intel.com>,
	"Chris Wilson" <chris@chris-wilson.co.uk>,
	stable@vger.kernel.org,
	"Thomas Hellström" <thomas.hellstrom@linux.intel.com>
Subject: Re: [PATCH 5/6] drm/i915/gt: Serialize GRDOM access between multiple engine resets
Date: Fri, 24 Jun 2022 09:34:21 +0100	[thread overview]
Message-ID: <160e613f-a0a8-18ff-5d4b-249d4280caa8@linux.intel.com> (raw)
In-Reply-To: <YrRLyg1IJoZpVGfg@intel.intel>


On 23/06/2022 12:17, Andi Shyti wrote:
> Hi Mauro,
> 
> On Wed, Jun 15, 2022 at 04:27:39PM +0100, Mauro Carvalho Chehab wrote:
>> From: Chris Wilson <chris.p.wilson@intel.com>
>>
>> Don't allow two engines to be reset in parallel, as they would both
>> try to select a reset bit (and send requests to common registers)
>> and wait on that register, at the same time. Serialize control of
>> the reset requests/acks using the uncore->lock, which will also ensure
>> that no other GT state changes at the same time as the actual reset.
>>
>> Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
>>
>> Reported-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> Cc: Andi Shyti <andi.shyti@intel.com>
>> Cc: stable@vger.kernel.org
>> Acked-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
>> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
> 
> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>

Notice I had a bunch of questions and asks in this series so please do 
not merge until those are addressed.

In this particular patch (and some others) for instance Fixes: tag, at 
least against that sha, shouldn't be there.

Regards,

Tvrtko

WARNING: multiple messages have this Message-ID (diff)
From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Andi Shyti <andi.shyti@linux.intel.com>,
	Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: "David Airlie" <airlied@linux.ie>,
	dri-devel@lists.freedesktop.org,
	"Chris Wilson" <chris@chris-wilson.co.uk>,
	"Fei Yang" <fei.yang@intel.com>,
	"Matthew Brost" <matthew.brost@intel.com>,
	"Mika Kuoppala" <mika.kuoppala@linux.intel.com>,
	"Chris Wilson" <chris.p.wilson@intel.com>,
	"Dave Airlie" <airlied@redhat.com>,
	"Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
	intel-gfx@lists.freedesktop.org,
	"Thomas Hellstrom" <thomas.hellstrom@intel.com>,
	"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
	mauro.chehab@linux.intel.com, linux-kernel@vger.kernel.org,
	stable@vger.kernel.org, "Bruce Chang" <yu.bruce.chang@intel.com>,
	"Tejas Upadhyay" <tejaskumarx.surendrakumar.upadhyay@intel.com>,
	"Umesh Nerlige Ramappa" <umesh.nerlige.ramappa@intel.com>,
	"John Harrison" <John.C.Harrison@intel.com>
Subject: Re: [PATCH 5/6] drm/i915/gt: Serialize GRDOM access between multiple engine resets
Date: Fri, 24 Jun 2022 09:34:21 +0100	[thread overview]
Message-ID: <160e613f-a0a8-18ff-5d4b-249d4280caa8@linux.intel.com> (raw)
In-Reply-To: <YrRLyg1IJoZpVGfg@intel.intel>


On 23/06/2022 12:17, Andi Shyti wrote:
> Hi Mauro,
> 
> On Wed, Jun 15, 2022 at 04:27:39PM +0100, Mauro Carvalho Chehab wrote:
>> From: Chris Wilson <chris.p.wilson@intel.com>
>>
>> Don't allow two engines to be reset in parallel, as they would both
>> try to select a reset bit (and send requests to common registers)
>> and wait on that register, at the same time. Serialize control of
>> the reset requests/acks using the uncore->lock, which will also ensure
>> that no other GT state changes at the same time as the actual reset.
>>
>> Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
>>
>> Reported-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> Cc: Andi Shyti <andi.shyti@intel.com>
>> Cc: stable@vger.kernel.org
>> Acked-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
>> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
> 
> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>

Notice I had a bunch of questions and asks in this series so please do 
not merge until those are addressed.

In this particular patch (and some others) for instance Fixes: tag, at 
least against that sha, shouldn't be there.

Regards,

Tvrtko

WARNING: multiple messages have this Message-ID (diff)
From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Andi Shyti <andi.shyti@linux.intel.com>,
	Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: "David Airlie" <airlied@linux.ie>,
	dri-devel@lists.freedesktop.org,
	"Chris Wilson" <chris@chris-wilson.co.uk>,
	"Chris Wilson" <chris.p.wilson@intel.com>,
	"Dave Airlie" <airlied@redhat.com>,
	"Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
	intel-gfx@lists.freedesktop.org,
	"Thomas Hellstrom" <thomas.hellstrom@intel.com>,
	"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
	mauro.chehab@linux.intel.com, linux-kernel@vger.kernel.org,
	stable@vger.kernel.org,
	"Tejas Upadhyay" <tejaskumarx.surendrakumar.upadhyay@intel.com>
Subject: Re: [Intel-gfx] [PATCH 5/6] drm/i915/gt: Serialize GRDOM access between multiple engine resets
Date: Fri, 24 Jun 2022 09:34:21 +0100	[thread overview]
Message-ID: <160e613f-a0a8-18ff-5d4b-249d4280caa8@linux.intel.com> (raw)
In-Reply-To: <YrRLyg1IJoZpVGfg@intel.intel>


On 23/06/2022 12:17, Andi Shyti wrote:
> Hi Mauro,
> 
> On Wed, Jun 15, 2022 at 04:27:39PM +0100, Mauro Carvalho Chehab wrote:
>> From: Chris Wilson <chris.p.wilson@intel.com>
>>
>> Don't allow two engines to be reset in parallel, as they would both
>> try to select a reset bit (and send requests to common registers)
>> and wait on that register, at the same time. Serialize control of
>> the reset requests/acks using the uncore->lock, which will also ensure
>> that no other GT state changes at the same time as the actual reset.
>>
>> Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
>>
>> Reported-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> Cc: Andi Shyti <andi.shyti@intel.com>
>> Cc: stable@vger.kernel.org
>> Acked-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
>> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
> 
> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>

Notice I had a bunch of questions and asks in this series so please do 
not merge until those are addressed.

In this particular patch (and some others) for instance Fixes: tag, at 
least against that sha, shouldn't be there.

Regards,

Tvrtko

  reply	other threads:[~2022-06-24  8:34 UTC|newest]

Thread overview: 87+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-15 15:27 [PATCH 0/6] Fix TLB invalidate issues with Broadwell Mauro Carvalho Chehab
2022-06-15 15:27 ` Mauro Carvalho Chehab
2022-06-15 15:27 ` [Intel-gfx] " Mauro Carvalho Chehab
2022-06-15 15:27 ` [PATCH 1/6] drm/i915/gt: Ignore TLB invalidations on idle engines Mauro Carvalho Chehab
2022-06-15 15:27   ` Mauro Carvalho Chehab
2022-06-15 15:27   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-06-16  7:21   ` Tvrtko Ursulin
2022-06-16  7:21     ` [Intel-gfx] " Tvrtko Ursulin
2022-06-16  7:21     ` Tvrtko Ursulin
2022-06-23 11:04   ` Andi Shyti
2022-06-23 11:04     ` [Intel-gfx] " Andi Shyti
2022-06-23 11:04     ` Andi Shyti
2022-06-15 15:27 ` [PATCH 2/6] drm/i915/gt: Invalidate TLB of the OA unit at TLB invalidations Mauro Carvalho Chehab
2022-06-15 15:27   ` Mauro Carvalho Chehab
2022-06-15 15:27   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-06-15 17:03   ` Umesh Nerlige Ramappa
2022-06-15 17:03     ` Umesh Nerlige Ramappa
2022-06-23 11:07   ` Andi Shyti
2022-06-23 11:07     ` [Intel-gfx] " Andi Shyti
2022-06-23 11:07     ` Andi Shyti
2022-06-15 15:27 ` [PATCH 3/6] drm/i915/gt: Skip TLB invalidations once wedged Mauro Carvalho Chehab
2022-06-15 15:27   ` Mauro Carvalho Chehab
2022-06-15 15:27   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-06-16  7:25   ` Tvrtko Ursulin
2022-06-16  7:25     ` [Intel-gfx] " Tvrtko Ursulin
2022-06-16  7:25     ` Tvrtko Ursulin
2022-06-23 11:08   ` Andi Shyti
2022-06-23 11:08     ` [Intel-gfx] " Andi Shyti
2022-06-23 11:08     ` Andi Shyti
2022-06-15 15:27 ` [PATCH 4/6] drm/i915/gt: Only invalidate TLBs exposed to user manipulation Mauro Carvalho Chehab
2022-06-15 15:27   ` Mauro Carvalho Chehab
2022-06-15 15:27   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-06-16  7:33   ` Tvrtko Ursulin
2022-06-16  7:33     ` [Intel-gfx] " Tvrtko Ursulin
2022-06-16  7:33     ` Tvrtko Ursulin
2022-06-23 11:13   ` Andi Shyti
2022-06-23 11:13     ` [Intel-gfx] " Andi Shyti
2022-06-23 11:13     ` Andi Shyti
2022-06-15 15:27 ` [PATCH 5/6] drm/i915/gt: Serialize GRDOM access between multiple engine resets Mauro Carvalho Chehab
2022-06-15 15:27   ` Mauro Carvalho Chehab
2022-06-15 15:27   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-06-16  7:35   ` Tvrtko Ursulin
2022-06-16  7:35     ` [Intel-gfx] " Tvrtko Ursulin
2022-06-16  7:35     ` Tvrtko Ursulin
2022-06-23 11:17   ` Andi Shyti
2022-06-23 11:17     ` [Intel-gfx] " Andi Shyti
2022-06-23 11:17     ` Andi Shyti
2022-06-24  8:34     ` Tvrtko Ursulin [this message]
2022-06-24  8:34       ` [Intel-gfx] " Tvrtko Ursulin
2022-06-24  8:34       ` Tvrtko Ursulin
2022-06-27  9:00       ` Mauro Carvalho Chehab
2022-06-27  9:00         ` Mauro Carvalho Chehab
2022-06-27  9:00         ` [Intel-gfx] " Mauro Carvalho Chehab
2022-06-28 15:49         ` Tvrtko Ursulin
2022-06-28 15:49           ` [Intel-gfx] " Tvrtko Ursulin
2022-06-28 15:49           ` Tvrtko Ursulin
2022-06-29 15:30           ` Mauro Carvalho Chehab
2022-06-29 15:30             ` [Intel-gfx] " Mauro Carvalho Chehab
2022-06-29 15:30             ` Mauro Carvalho Chehab
2022-06-29 16:02             ` Tvrtko Ursulin
2022-06-29 16:02               ` Tvrtko Ursulin
2022-06-29 16:02               ` [Intel-gfx] " Tvrtko Ursulin
2022-06-30  7:32               ` Mauro Carvalho Chehab
2022-06-30  7:32                 ` [Intel-gfx] " Mauro Carvalho Chehab
2022-06-30  7:32                 ` Mauro Carvalho Chehab
2022-06-30  8:12                 ` Tvrtko Ursulin
2022-06-30  8:12                   ` Tvrtko Ursulin
2022-06-30  8:12                   ` [Intel-gfx] " Tvrtko Ursulin
2022-06-30 16:01                   ` Mauro Carvalho Chehab
2022-06-30 16:01                     ` [Intel-gfx] " Mauro Carvalho Chehab
2022-06-30 16:01                     ` Mauro Carvalho Chehab
2022-07-01  7:56                     ` Tvrtko Ursulin
2022-07-01  7:56                       ` [Intel-gfx] " Tvrtko Ursulin
2022-07-01  7:56                       ` Tvrtko Ursulin
2022-07-04  8:42                       ` Mauro Carvalho Chehab
2022-07-04  8:42                         ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-04  8:42                         ` Mauro Carvalho Chehab
2022-06-15 15:27 ` [PATCH 6/6] drm/i915/gt: Serialize TLB invalidates with GT resets Mauro Carvalho Chehab
2022-06-15 15:27   ` Mauro Carvalho Chehab
2022-06-15 15:27   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-06-23 11:18   ` Andi Shyti
2022-06-23 11:18     ` [Intel-gfx] " Andi Shyti
2022-06-23 11:18     ` Andi Shyti
2022-06-15 17:26 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Fix TLB invalidate issues with Broadwell Patchwork
2022-06-15 17:26 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-06-15 17:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-06-15 23:45 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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