From: Shradha Todi <shradha.t@samsung.com>
To: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-pci@vger.kernel.org
Cc: pankaj.dubey@samsung.com, sriram.dash@samsung.com,
niyas.ahmed@samsung.com, p.rajanbabu@samsung.com,
l.mehra@samsung.com, hari.tv@samsung.com,
Anvesh Salveru <anvesh.salveru@gmail.com>,
Shradha Todi <shradha.t@samsung.com>,
Jingoo Han <jingoohan1@gmail.com>,
Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Rob Herring <robh@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>
Subject: [PATCH v7 2/5] PCI: dwc: add support to handle ZRX-DC Compliant PHYs
Date: Thu, 7 Jan 2021 20:58:40 +0530 [thread overview]
Message-ID: <1610033323-10560-3-git-send-email-shradha.t@samsung.com> (raw)
In-Reply-To: <1610033323-10560-1-git-send-email-shradha.t@samsung.com>
From: Pankaj Dubey <pankaj.dubey@samsung.com>
Many platforms use DesignWare controller but the PHY can be different in
different platforms. If the PHY is compliant is to ZRX-DC specification it
helps in low power consumption during power states.
If current data rate is 8.0 GT/s or higher and PHY is not compliant to
ZRX-DC specification, then after every 100ms link should transition to
recovery state during the low power states.
DesignWare controller provides GEN3_ZRXDC_NONCOMPL field in
GEN3_RELATED_OFF to specify about ZRX-DC compliant PHY.
Platforms with ZRX-DC compliant PHY can set phy_zrxdc_compliant variable to
specify this property to the controller.
Signed-off-by: Anvesh Salveru <anvesh.salveru@gmail.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Shradha Todi <shradha.t@samsung.com>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/controller/dwc/pcie-designware.c | 6 ++++++
drivers/pci/controller/dwc/pcie-designware.h | 4 ++++
2 files changed, 10 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 645fa18..74590c7 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -722,4 +722,10 @@ void dw_pcie_setup(struct dw_pcie *pci)
PCIE_PL_CHK_REG_CHK_REG_START;
dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
}
+
+ if (pci->phy_zrxdc_compliant) {
+ val = dw_pcie_readl_dbi(pci, PCIE_PORT_GEN3_RELATED);
+ val &= ~PORT_LOGIC_GEN3_ZRXDC_NONCOMPL;
+ dw_pcie_writel_dbi(pci, PCIE_PORT_GEN3_RELATED, val);
+ }
}
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 0207840..8b905a2 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -74,6 +74,9 @@
#define PCIE_MSI_INTR0_MASK 0x82C
#define PCIE_MSI_INTR0_STATUS 0x830
+#define PCIE_PORT_GEN3_RELATED 0x890
+#define PORT_LOGIC_GEN3_ZRXDC_NONCOMPL BIT(0)
+
#define PCIE_PORT_MULTI_LANE_CTRL 0x8C0
#define PORT_MLTI_UPCFG_SUPPORT BIT(7)
@@ -273,6 +276,7 @@ struct dw_pcie {
u8 n_fts[2];
bool iatu_unroll_enabled: 1;
bool io_cfg_atu_shared: 1;
+ bool phy_zrxdc_compliant;
};
#define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
--
2.7.4
next prev parent reply other threads:[~2021-01-07 16:11 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20210107152945epcas5p158e88c757a44e98f4e9a898d3ff5f87c@epcas5p1.samsung.com>
2021-01-07 15:28 ` [PATCH v7 0/5] Add support to handle ZRX-DC Compliant PHYs Shradha Todi
[not found] ` <CGME20210107153013epcas5p27700f30e341d7f1fb457035a690490c6@epcas5p2.samsung.com>
2021-01-07 15:28 ` [PATCH v7 1/5] phy: core: add phy_property_present method Shradha Todi
[not found] ` <CGME20210107153030epcas5p14b0967c4d8d9804a2d084981af445c58@epcas5p1.samsung.com>
2021-01-07 15:28 ` Shradha Todi [this message]
2021-01-07 18:44 ` [PATCH v7 2/5] PCI: dwc: add support to handle ZRX-DC Compliant PHYs Bjorn Helgaas
2021-01-12 1:52 ` Pankaj Dubey
[not found] ` <CGME20210107153051epcas5p4f54210f89f8b8d2e18be016521657be0@epcas5p4.samsung.com>
2021-01-07 15:28 ` [PATCH v7 3/5] dt-bindings: PHY: P2U: Add binding for ZRX-DC PHY property Shradha Todi
[not found] ` <CGME20210107153105epcas5p49ca103794f62faa48c5bedcfc8b4a287@epcas5p4.samsung.com>
2021-01-07 15:28 ` [PATCH v7 4/5] PCI: tegra: Remove platform driver support for ZRX-DC compliant PHY Shradha Todi
2021-01-07 18:46 ` kernel test robot
2021-01-07 18:46 ` kernel test robot
[not found] ` <CGME20210107153116epcas5p3510286e503e690537d5b2eb7486fa7ab@epcas5p3.samsung.com>
2021-01-07 15:28 ` [PATCH v7 5/5] arm64: tegra: Add support for ZRX DC PHY property Shradha Todi
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