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From: Liu Ying <victor.liu@nxp.com>
To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-media@vger.kernel.org
Cc: airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org,
	shawnguo@kernel.org, s.hauer@pengutronix.de,
	kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com,
	mchehab@kernel.org, a.hajda@samsung.com, narmstrong@baylibre.com,
	Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se,
	jernej.skrabec@siol.net, kishon@ti.com, vkoul@kernel.org
Subject: [PATCH v2 01/14] phy: Add LVDS configuration options
Date: Thu, 14 Jan 2021 17:21:59 +0800	[thread overview]
Message-ID: <1610616132-8220-2-git-send-email-victor.liu@nxp.com> (raw)
In-Reply-To: <1610616132-8220-1-git-send-email-victor.liu@nxp.com>

This patch allows LVDS PHYs to be configured through
the generic functions and through a custom structure
added to the generic union.

The parameters added here are based on common LVDS PHY
implementation practices.  The set of parameters
should cover all potential users.

Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: NXP Linux Team <linux-imx@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v1->v2:
* No change.

 include/linux/phy/phy-lvds.h | 48 ++++++++++++++++++++++++++++++++++++++++++++
 include/linux/phy/phy.h      |  4 ++++
 2 files changed, 52 insertions(+)
 create mode 100644 include/linux/phy/phy-lvds.h

diff --git a/include/linux/phy/phy-lvds.h b/include/linux/phy/phy-lvds.h
new file mode 100644
index 00000000..1b5b9d6
--- /dev/null
+++ b/include/linux/phy/phy-lvds.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2020 NXP
+ */
+
+#ifndef __PHY_LVDS_H_
+#define __PHY_LVDS_H_
+
+/**
+ * struct phy_configure_opts_lvds - LVDS configuration set
+ *
+ * This structure is used to represent the configuration state of a
+ * LVDS phy.
+ */
+struct phy_configure_opts_lvds {
+	/**
+	 * @bits_per_lane_and_dclk_cycle:
+	 *
+	 * Number of bits per data lane and differential clock cycle.
+	 */
+	unsigned int bits_per_lane_and_dclk_cycle;
+
+	/**
+	 * @differential_clk_rate:
+	 *
+	 * Clock rate, in Hertz, of the LVDS differential clock.
+	 */
+	unsigned long differential_clk_rate;
+
+	/**
+	 * @lanes:
+	 *
+	 * Number of active, consecutive, data lanes, starting from
+	 * lane 0, used for the transmissions.
+	 */
+	unsigned int lanes;
+
+	/**
+	 * @is_slave:
+	 *
+	 * Boolean, true if the phy is a slave which works together
+	 * with a master phy to support dual link transmission,
+	 * otherwise a regular phy or a master phy.
+	 */
+	bool is_slave;
+};
+
+#endif /* __PHY_LVDS_H_ */
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index e435bdb..d450b44 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -17,6 +17,7 @@
 #include <linux/regulator/consumer.h>
 
 #include <linux/phy/phy-dp.h>
+#include <linux/phy/phy-lvds.h>
 #include <linux/phy/phy-mipi-dphy.h>
 
 struct phy;
@@ -51,10 +52,13 @@ enum phy_mode {
  *		the MIPI_DPHY phy mode.
  * @dp:		Configuration set applicable for phys supporting
  *		the DisplayPort protocol.
+ * @lvds:	Configuration set applicable for phys supporting
+ *		the LVDS phy mode.
  */
 union phy_configure_opts {
 	struct phy_configure_opts_mipi_dphy	mipi_dphy;
 	struct phy_configure_opts_dp		dp;
+	struct phy_configure_opts_lvds		lvds;
 };
 
 /**
-- 
2.7.4


WARNING: multiple messages have this Message-ID (diff)
From: Liu Ying <victor.liu@nxp.com>
To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-media@vger.kernel.org
Cc: jernej.skrabec@siol.net, daniel@ffwll.ch,
	narmstrong@baylibre.com, airlied@linux.ie, festevam@gmail.com,
	s.hauer@pengutronix.de, jonas@kwiboo.se, kishon@ti.com,
	a.hajda@samsung.com, vkoul@kernel.org, robh+dt@kernel.org,
	linux-imx@nxp.com, kernel@pengutronix.de, mchehab@kernel.org,
	shawnguo@kernel.org, Laurent.pinchart@ideasonboard.com
Subject: [PATCH v2 01/14] phy: Add LVDS configuration options
Date: Thu, 14 Jan 2021 17:21:59 +0800	[thread overview]
Message-ID: <1610616132-8220-2-git-send-email-victor.liu@nxp.com> (raw)
In-Reply-To: <1610616132-8220-1-git-send-email-victor.liu@nxp.com>

This patch allows LVDS PHYs to be configured through
the generic functions and through a custom structure
added to the generic union.

The parameters added here are based on common LVDS PHY
implementation practices.  The set of parameters
should cover all potential users.

Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: NXP Linux Team <linux-imx@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v1->v2:
* No change.

 include/linux/phy/phy-lvds.h | 48 ++++++++++++++++++++++++++++++++++++++++++++
 include/linux/phy/phy.h      |  4 ++++
 2 files changed, 52 insertions(+)
 create mode 100644 include/linux/phy/phy-lvds.h

diff --git a/include/linux/phy/phy-lvds.h b/include/linux/phy/phy-lvds.h
new file mode 100644
index 00000000..1b5b9d6
--- /dev/null
+++ b/include/linux/phy/phy-lvds.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2020 NXP
+ */
+
+#ifndef __PHY_LVDS_H_
+#define __PHY_LVDS_H_
+
+/**
+ * struct phy_configure_opts_lvds - LVDS configuration set
+ *
+ * This structure is used to represent the configuration state of a
+ * LVDS phy.
+ */
+struct phy_configure_opts_lvds {
+	/**
+	 * @bits_per_lane_and_dclk_cycle:
+	 *
+	 * Number of bits per data lane and differential clock cycle.
+	 */
+	unsigned int bits_per_lane_and_dclk_cycle;
+
+	/**
+	 * @differential_clk_rate:
+	 *
+	 * Clock rate, in Hertz, of the LVDS differential clock.
+	 */
+	unsigned long differential_clk_rate;
+
+	/**
+	 * @lanes:
+	 *
+	 * Number of active, consecutive, data lanes, starting from
+	 * lane 0, used for the transmissions.
+	 */
+	unsigned int lanes;
+
+	/**
+	 * @is_slave:
+	 *
+	 * Boolean, true if the phy is a slave which works together
+	 * with a master phy to support dual link transmission,
+	 * otherwise a regular phy or a master phy.
+	 */
+	bool is_slave;
+};
+
+#endif /* __PHY_LVDS_H_ */
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index e435bdb..d450b44 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -17,6 +17,7 @@
 #include <linux/regulator/consumer.h>
 
 #include <linux/phy/phy-dp.h>
+#include <linux/phy/phy-lvds.h>
 #include <linux/phy/phy-mipi-dphy.h>
 
 struct phy;
@@ -51,10 +52,13 @@ enum phy_mode {
  *		the MIPI_DPHY phy mode.
  * @dp:		Configuration set applicable for phys supporting
  *		the DisplayPort protocol.
+ * @lvds:	Configuration set applicable for phys supporting
+ *		the LVDS phy mode.
  */
 union phy_configure_opts {
 	struct phy_configure_opts_mipi_dphy	mipi_dphy;
 	struct phy_configure_opts_dp		dp;
+	struct phy_configure_opts_lvds		lvds;
 };
 
 /**
-- 
2.7.4


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Liu Ying <victor.liu@nxp.com>
To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-media@vger.kernel.org
Cc: jernej.skrabec@siol.net, narmstrong@baylibre.com,
	airlied@linux.ie, s.hauer@pengutronix.de, jonas@kwiboo.se,
	kishon@ti.com, a.hajda@samsung.com, vkoul@kernel.org,
	robh+dt@kernel.org, linux-imx@nxp.com, kernel@pengutronix.de,
	mchehab@kernel.org, shawnguo@kernel.org,
	Laurent.pinchart@ideasonboard.com
Subject: [PATCH v2 01/14] phy: Add LVDS configuration options
Date: Thu, 14 Jan 2021 17:21:59 +0800	[thread overview]
Message-ID: <1610616132-8220-2-git-send-email-victor.liu@nxp.com> (raw)
In-Reply-To: <1610616132-8220-1-git-send-email-victor.liu@nxp.com>

This patch allows LVDS PHYs to be configured through
the generic functions and through a custom structure
added to the generic union.

The parameters added here are based on common LVDS PHY
implementation practices.  The set of parameters
should cover all potential users.

Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: NXP Linux Team <linux-imx@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v1->v2:
* No change.

 include/linux/phy/phy-lvds.h | 48 ++++++++++++++++++++++++++++++++++++++++++++
 include/linux/phy/phy.h      |  4 ++++
 2 files changed, 52 insertions(+)
 create mode 100644 include/linux/phy/phy-lvds.h

diff --git a/include/linux/phy/phy-lvds.h b/include/linux/phy/phy-lvds.h
new file mode 100644
index 00000000..1b5b9d6
--- /dev/null
+++ b/include/linux/phy/phy-lvds.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2020 NXP
+ */
+
+#ifndef __PHY_LVDS_H_
+#define __PHY_LVDS_H_
+
+/**
+ * struct phy_configure_opts_lvds - LVDS configuration set
+ *
+ * This structure is used to represent the configuration state of a
+ * LVDS phy.
+ */
+struct phy_configure_opts_lvds {
+	/**
+	 * @bits_per_lane_and_dclk_cycle:
+	 *
+	 * Number of bits per data lane and differential clock cycle.
+	 */
+	unsigned int bits_per_lane_and_dclk_cycle;
+
+	/**
+	 * @differential_clk_rate:
+	 *
+	 * Clock rate, in Hertz, of the LVDS differential clock.
+	 */
+	unsigned long differential_clk_rate;
+
+	/**
+	 * @lanes:
+	 *
+	 * Number of active, consecutive, data lanes, starting from
+	 * lane 0, used for the transmissions.
+	 */
+	unsigned int lanes;
+
+	/**
+	 * @is_slave:
+	 *
+	 * Boolean, true if the phy is a slave which works together
+	 * with a master phy to support dual link transmission,
+	 * otherwise a regular phy or a master phy.
+	 */
+	bool is_slave;
+};
+
+#endif /* __PHY_LVDS_H_ */
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index e435bdb..d450b44 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -17,6 +17,7 @@
 #include <linux/regulator/consumer.h>
 
 #include <linux/phy/phy-dp.h>
+#include <linux/phy/phy-lvds.h>
 #include <linux/phy/phy-mipi-dphy.h>
 
 struct phy;
@@ -51,10 +52,13 @@ enum phy_mode {
  *		the MIPI_DPHY phy mode.
  * @dp:		Configuration set applicable for phys supporting
  *		the DisplayPort protocol.
+ * @lvds:	Configuration set applicable for phys supporting
+ *		the LVDS phy mode.
  */
 union phy_configure_opts {
 	struct phy_configure_opts_mipi_dphy	mipi_dphy;
 	struct phy_configure_opts_dp		dp;
+	struct phy_configure_opts_lvds		lvds;
 };
 
 /**
-- 
2.7.4

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

  reply	other threads:[~2021-01-14  9:34 UTC|newest]

Thread overview: 63+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-14  9:21 [PATCH v2 00/14] Add some DRM bridge drivers support for i.MX8qm/qxp SoCs Liu Ying
2021-01-14  9:21 ` Liu Ying
2021-01-14  9:21 ` Liu Ying
2021-01-14  9:21 ` Liu Ying [this message]
2021-01-14  9:21   ` [PATCH v2 01/14] phy: Add LVDS configuration options Liu Ying
2021-01-14  9:21   ` Liu Ying
2021-01-14  9:22 ` [PATCH v2 02/14] media: uapi: Add some RGB bus formats for i.MX8qm/qxp pixel combiner Liu Ying
2021-01-14  9:22   ` Liu Ying
2021-01-14  9:22   ` Liu Ying
2021-01-14  9:22 ` [PATCH v2 03/14] media: docs: " Liu Ying
2021-01-14  9:22   ` Liu Ying
2021-01-14  9:22   ` Liu Ying
2021-01-14  9:22 ` [PATCH v2 04/14] dt-bindings: display: bridge: Add i.MX8qm/qxp pixel combiner binding Liu Ying
2021-01-14  9:22   ` Liu Ying
2021-01-14  9:22   ` Liu Ying
2021-01-25 21:09   ` Rob Herring
2021-01-25 21:09     ` Rob Herring
2021-01-25 21:09     ` Rob Herring
2021-01-14  9:22 ` [PATCH v2 05/14] drm/bridge: imx: Add i.MX8qm/qxp pixel combiner support Liu Ying
2021-01-14  9:22   ` Liu Ying
2021-01-14  9:22   ` Liu Ying
2021-01-14  9:22 ` [PATCH v2 06/14] dt-bindings: display: bridge: Add i.MX8qm/qxp display pixel link binding Liu Ying
2021-01-14  9:22   ` Liu Ying
2021-01-14  9:22   ` Liu Ying
2021-01-25 21:10   ` Rob Herring
2021-01-25 21:10     ` Rob Herring
2021-01-25 21:10     ` Rob Herring
2021-01-14  9:22 ` [PATCH v2 07/14] drm/bridge: imx: Add i.MX8qm/qxp display pixel link support Liu Ying
2021-01-14  9:22   ` Liu Ying
2021-01-14  9:22   ` Liu Ying
2021-01-14  9:22 ` [PATCH v2 08/14] dt-bindings: display: bridge: Add i.MX8qxp pixel link to DPI binding Liu Ying
2021-01-14  9:22   ` Liu Ying
2021-01-14  9:22   ` Liu Ying
2021-01-25 21:13   ` Rob Herring
2021-01-25 21:13     ` Rob Herring
2021-01-25 21:13     ` Rob Herring
2021-01-26  9:00     ` Liu Ying
2021-01-26  9:00       ` Liu Ying
2021-01-26  9:00       ` Liu Ying
2021-01-14  9:22 ` [PATCH v2 09/14] drm/bridge: imx: Add i.MX8qxp pixel link to DPI support Liu Ying
2021-01-14  9:22   ` Liu Ying
2021-01-14  9:22   ` Liu Ying
2021-01-14  9:22 ` [PATCH v2 10/14] drm/bridge: imx: Add LDB driver helper support Liu Ying
2021-01-14  9:22   ` Liu Ying
2021-01-14  9:22   ` Liu Ying
2021-01-14  9:22 ` [PATCH v2 11/14] dt-bindings: display: bridge: Add i.MX8qm/qxp LVDS display bridge binding Liu Ying
2021-01-14  9:22   ` Liu Ying
2021-01-14  9:22   ` Liu Ying
2021-01-25 21:19   ` Rob Herring
2021-01-25 21:19     ` Rob Herring
2021-01-25 21:19     ` Rob Herring
2021-01-26  9:02     ` Liu Ying
2021-01-26  9:02       ` Liu Ying
2021-01-26  9:02       ` Liu Ying
2021-01-14  9:22 ` [PATCH v2 12/14] drm/bridge: imx: Add LDB support for i.MX8qxp Liu Ying
2021-01-14  9:22   ` Liu Ying
2021-01-14  9:22   ` Liu Ying
2021-01-14  9:22 ` [PATCH v2 13/14] drm/bridge: imx: Add LDB support for i.MX8qm Liu Ying
2021-01-14  9:22   ` Liu Ying
2021-01-14  9:22   ` Liu Ying
2021-01-14  9:22 ` [PATCH v2 14/14] MAINTAINERS: add maintainer for DRM bridge drivers for i.MX SoCs Liu Ying
2021-01-14  9:22   ` Liu Ying
2021-01-14  9:22   ` Liu Ying

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