From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D59CC433DB for ; Wed, 27 Jan 2021 12:00:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C567820771 for ; Wed, 27 Jan 2021 12:00:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237270AbhA0L76 (ORCPT ); Wed, 27 Jan 2021 06:59:58 -0500 Received: from mx0a-0016f401.pphosted.com ([67.231.148.174]:34478 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S237207AbhA0Lrh (ORCPT ); Wed, 27 Jan 2021 06:47:37 -0500 Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 10RBeLHB000957; Wed, 27 Jan 2021 03:44:49 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=km1SSvkjcFlecBnfqs0aQMqb68jUv/dgma5LuQzQjKM=; b=Pj3Gj2DhiZpCh6b1yLCUIWsnDoCYd8i7n32FrtQ6k+E0ejr6eUv5rHJVf2Siew0WX/1i mLa2xyl/KAjvVg9rWq09TIt19kc1Ceez5dEpoFN0mwXjSN+zZHWKQdp4DQ+nesvM3BUj 8T7yUwH4ADrAQAzbI+ZcGatXDUH8WnVDxv7RlBUdaMV2UoGXzJNCks4LEs65vATS1W1j DWktyNKIBKHS92dZDbQrGZuEBNjzR0l2BjRQshxtwFtoembHUzQSkTHwpr4VrWeA3ljG Onkg6znsyoPoqSS5NRwfacbNafUrTjKNCU9gzCgiepJy3wAKcTy+8eRMK4Am/cp1gVqF EA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 368j1ube91-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 27 Jan 2021 03:44:49 -0800 Received: from SC-EXCH01.marvell.com (10.93.176.81) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 27 Jan 2021 03:44:48 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 27 Jan 2021 03:44:47 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 27 Jan 2021 03:44:47 -0800 Received: from stefan-pc.marvell.com (stefan-pc.marvell.com [10.5.25.21]) by maili.marvell.com (Postfix) with ESMTP id C2A243F703F; Wed, 27 Jan 2021 03:44:44 -0800 (PST) From: To: CC: , , , , , , , , , , , Subject: [PATCH v4 net-next 18/19] net: mvpp2: limit minimum ring size to 1024 descriptors Date: Wed, 27 Jan 2021 13:43:34 +0200 Message-ID: <1611747815-1934-19-git-send-email-stefanc@marvell.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1611747815-1934-1-git-send-email-stefanc@marvell.com> References: <1611747815-1934-1-git-send-email-stefanc@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.343,18.0.737 definitions=2021-01-27_05:2021-01-27,2021-01-27 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Stefan Chulski To support Flow Control ring size should be at least 1024 descriptors. Signed-off-by: Stefan Chulski --- drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c index 55138c7..bb7dfed 100644 --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c @@ -4545,6 +4545,8 @@ static int mvpp2_check_ringparam_valid(struct net_device *dev, if (ring->rx_pending > MVPP2_MAX_RXD_MAX) new_rx_pending = MVPP2_MAX_RXD_MAX; + else if (ring->rx_pending < MSS_THRESHOLD_START) + new_rx_pending = MSS_THRESHOLD_START; else if (!IS_ALIGNED(ring->rx_pending, 16)) new_rx_pending = ALIGN(ring->rx_pending, 16); -- 1.9.1