From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.2 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EC45C433E6 for ; Thu, 28 Jan 2021 08:30:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D465664DD9 for ; Thu, 28 Jan 2021 08:30:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231387AbhA1I3z (ORCPT ); Thu, 28 Jan 2021 03:29:55 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:59724 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S229709AbhA1I3c (ORCPT ); Thu, 28 Jan 2021 03:29:32 -0500 X-UUID: a9e73fc880d84326a83f29bee8eadb6d-20210128 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:Reply-To:From:Subject:Message-ID; bh=xuMAXwo6AmkpKMd7GIWUbcpQOz0B7oib5M57arUVcdY=; b=ODT4aWplJCcUN+8IAk/DRmMTo3FCEb8CmoBGmeHhorpfjRPMe5K8ClwTdqKTvtxDbtHhoVl023FebbqAb6lyTKKMFl6oTiXFQx9BbtE4oonwhwOvGgCKNJW8wfI7Fbof2DMmxncui0Gkcofa8gw4TSrroQBO6bPxdyt9+qOTAJ8=; X-UUID: a9e73fc880d84326a83f29bee8eadb6d-20210128 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1238747793; Thu, 28 Jan 2021 16:28:44 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 16:28:43 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 Jan 2021 16:28:42 +0800 Message-ID: <1611822522.1947.12.camel@mhfsdcap03> Subject: Re: [PATCH v11 7/9] drm/mediatek: enable dither function From: Yongqiang Niu Reply-To: Yongqiang Niu To: Hsin-Yi Wang CC: CK Hu , Philipp Zabel , Matthias Brugger , David Airlie , Daniel Vetter , Mark Rutland , dri-devel , Devicetree List , lkml , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , "moderated list:ARM/Mediatek SoC support" Date: Thu, 28 Jan 2021 16:28:42 +0800 In-Reply-To: References: <20210128072802.830971-1-hsinyi@chromium.org> <20210128072802.830971-8-hsinyi@chromium.org> <1611819766.16091.4.camel@mtksdaap41> <1611820770.1947.8.camel@mhfsdcap03> <1611821233.18369.4.camel@mtksdaap41> <1611821396.1947.10.camel@mhfsdcap03> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: base64 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org T24gVGh1LCAyMDIxLTAxLTI4IGF0IDE2OjE4ICswODAwLCBIc2luLVlpIFdhbmcgd3JvdGU6DQo+ IE9uIFRodSwgSmFuIDI4LCAyMDIxIGF0IDQ6MTAgUE0gWW9uZ3FpYW5nIE5pdQ0KPiA8eW9uZ3Fp YW5nLm5pdUBtZWRpYXRlay5jb20+IHdyb3RlOg0KPiA+DQo+ID4gT24gVGh1LCAyMDIxLTAxLTI4 IGF0IDE2OjA3ICswODAwLCBDSyBIdSB3cm90ZToNCj4gPiA+IE9uIFRodSwgMjAyMS0wMS0yOCBh dCAxNTo1OSArMDgwMCwgWW9uZ3FpYW5nIE5pdSB3cm90ZToNCj4gPiA+ID4gT24gVGh1LCAyMDIx LTAxLTI4IGF0IDE1OjQyICswODAwLCBDSyBIdSB3cm90ZToNCj4gPiA+ID4gPiBIaSwgSHNpbi1Z aToNCj4gPiA+ID4gPg0KPiA+ID4gPiA+IE9uIFRodSwgMjAyMS0wMS0yOCBhdCAxNToyOCArMDgw MCwgSHNpbi1ZaSBXYW5nIHdyb3RlOg0KPiA+ID4gPiA+ID4gRnJvbTogWW9uZ3FpYW5nIE5pdSA8 eW9uZ3FpYW5nLm5pdUBtZWRpYXRlay5jb20+DQo+ID4gPiA+ID4gPg0KPiA+ID4gPiA+ID4gZm9y IDUgb3IgNiBicGMgcGFuZWwsIHdlIG5lZWQgZW5hYmxlIGRpdGhlciBmdW5jdGlvbg0KPiA+ID4g PiA+ID4gdG8gaW1wcm92ZSB0aGUgZGlzcGxheSBxdWFsaXR5DQo+ID4gPiA+ID4gPg0KPiA+ID4g PiA+ID4gU2lnbmVkLW9mZi1ieTogWW9uZ3FpYW5nIE5pdSA8eW9uZ3FpYW5nLm5pdUBtZWRpYXRl ay5jb20+DQo+ID4gPiA+ID4gPiBTaWduZWQtb2ZmLWJ5OiBIc2luLVlpIFdhbmcgPGhzaW55aUBj aHJvbWl1bS5vcmc+DQo+ID4gPiA+ID4gPiAtLS0NCj4gPiA+ID4gPiA+ICBkcml2ZXJzL2dwdS9k cm0vbWVkaWF0ZWsvbXRrX2RybV9kZHBfY29tcC5jIHwgNDQgKysrKysrKysrKysrKysrKysrKyst DQo+ID4gPiA+ID4gPiAgMSBmaWxlIGNoYW5nZWQsIDQzIGluc2VydGlvbnMoKyksIDEgZGVsZXRp b24oLSkNCj4gPiA+ID4gPiA+DQo+ID4gPiA+ID4gPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUv ZHJtL21lZGlhdGVrL210a19kcm1fZGRwX2NvbXAuYyBiL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRl ay9tdGtfZHJtX2RkcF9jb21wLmMNCj4gPiA+ID4gPiA+IGluZGV4IDgxNzNmNzA5MjcyYmUuLmU4 NTYyNTcwNGQ2MTEgMTAwNjQ0DQo+ID4gPiA+ID4gPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vbWVk aWF0ZWsvbXRrX2RybV9kZHBfY29tcC5jDQo+ID4gPiA+ID4gPiArKysgYi9kcml2ZXJzL2dwdS9k cm0vbWVkaWF0ZWsvbXRrX2RybV9kZHBfY29tcC5jDQo+ID4gPiA+ID4gPiBAQCAtNTMsNyArNTMs OSBAQA0KPiA+ID4gPiA+ID4gICNkZWZpbmUgRElUSEVSX0VOICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgQklUKDApDQo+ID4gPiA+ID4gPiAgI2RlZmluZSBESVNQX0RJVEhFUl9DRkcgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgIDB4MDAyMA0KPiA+ID4gPiA+ID4gICNkZWZpbmUg RElUSEVSX1JFTEFZX01PREUgICAgICAgICAgICAgICAgICAgICAgQklUKDApDQo+ID4gPiA+ID4g PiArI2RlZmluZSBESVRIRVJfRU5HSU5FX0VOICAgICAgICAgICAgICAgICAgICAgICBCSVQoMSkN Cj4gPiA+ID4gPiA+ICAjZGVmaW5lIERJU1BfRElUSEVSX1NJWkUgICAgICAgICAgICAgICAgICAg ICAgIDB4MDAzMA0KPiA+ID4gPiA+ID4gKyNkZWZpbmUgRElUSEVSX1JFRyhpZHgpICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAoMHgxMDAgKyAoaWR4KSAqIDQpDQo+ID4gPiA+ID4gPg0K PiA+ID4gPiA+ID4gICNkZWZpbmUgTFVUXzEwQklUX01BU0sgICAgICAgICAgICAgICAgICAgICAg ICAgMHgwM2ZmDQo+ID4gPiA+ID4gPg0KPiA+ID4gPiA+ID4gQEAgLTMxMyw4ICszMTUsNDggQEAg c3RhdGljIHZvaWQgbXRrX2RpdGhlcl9jb25maWcoc3RydWN0IGRldmljZSAqZGV2LCB1bnNpZ25l ZCBpbnQgdywNCj4gPiA+ID4gPiA+ICB7DQo+ID4gPiA+ID4gPiAgICAgICAgIHN0cnVjdCBtdGtf ZGRwX2NvbXBfZGV2ICpwcml2ID0gZGV2X2dldF9kcnZkYXRhKGRldik7DQo+ID4gPiA+ID4gPg0K PiA+ID4gPiA+ID4gKyAgICAgICBib29sIGVuYWJsZSA9IGZhbHNlOw0KPiA+ID4gPiA+ID4gKw0K PiA+ID4gPiA+ID4gKyAgICAgICAvKiBkZWZhdWx0IHZhbHVlIGZvciBkaXRoZXIgcmVnIDUgdG8g MTQgKi8NCj4gPiA+ID4gPiA+ICsgICAgICAgY29uc3QgdTMyIGRpdGhlcl9zZXR0aW5nW10gPSB7 DQo+ID4gPiA+ID4gPiArICAgICAgICAgICAgICAgMHgwMDAwMDAwMCwgLyogNSAqLw0KPiA+ID4g PiA+ID4gKyAgICAgICAgICAgICAgIDB4MDAwMDMwMDIsIC8qIDYgKi8NCj4gPiA+ID4gPiA+ICsg ICAgICAgICAgICAgICAweDAwMDAwMDAwLCAvKiA3ICovDQo+ID4gPiA+ID4gPiArICAgICAgICAg ICAgICAgMHgwMDAwMDAwMCwgLyogOCAqLw0KPiA+ID4gPiA+ID4gKyAgICAgICAgICAgICAgIDB4 MDAwMDAwMDAsIC8qIDkgKi8NCj4gPiA+ID4gPiA+ICsgICAgICAgICAgICAgICAweDAwMDAwMDAw LCAvKiAxMCAqLw0KPiA+ID4gPiA+ID4gKyAgICAgICAgICAgICAgIDB4MDAwMDAwMDAsIC8qIDEx ICovDQo+ID4gPiA+ID4gPiArICAgICAgICAgICAgICAgMHgwMDAwMDAxMSwgLyogMTIgKi8NCj4g PiA+ID4gPiA+ICsgICAgICAgICAgICAgICAweDAwMDAwMDAwLCAvKiAxMyAqLw0KPiA+ID4gPiA+ ID4gKyAgICAgICAgICAgICAgIDB4MDAwMDAwMDAsIC8qIDE0ICovDQo+ID4gPiA+ID4NCj4gPiA+ ID4gPiBDb3VsZCB5b3UgZXhwbGFpbiB3aGF0IGlzIHRoaXM/DQo+ID4gPiA+DQo+ID4gPiA+IHRo aXMgaXMgZGl0aGVyIDUgdG8gZGl0aGVyIDE0IHNldHRpbmcNCj4gPiA+ID4gdGhpcyB3aWxsIGJl IHVzZWxlc3MsIHdlIGp1c3QgbmVlZCBzZXQgZGl0aGVyIDUgYW5kIGRpdGhlciA3IGxpa2UNCj4g PiA+ID4gbXRrX2RkcF93cml0ZShjbWRxX3BrdCwgMCwgY29tcCwgRElTUF9ESVRIRVJfNSk7DQo+ ID4gPiA+IG10a19kZHBfd3JpdGUoY21kcV9wa3QsIDAsIGNvbXAsIERJU1BfRElUSEVSXzcpOw0K PiA+ID4gPiBvdGhlciB2YWx1ZSBpcyBzYW1lIHdpdGggaGFyZHdhcmUgZGVmYXVsdCB2YWx1ZS4N Cj4gPiA+ID4NCj4gPiA+ID4NCj4gPiA+ID4gPg0KPiA+ID4gPiA+ID4gKyAgICAgICB9Ow0KPiA+ ID4gPiA+ID4gKw0KPiA+ID4gPiA+ID4gKyAgICAgICBpZiAoYnBjID09IDUgfHwgYnBjID09IDYp IHsNCj4gPiA+ID4gPiA+ICsgICAgICAgICAgICAgICBlbmFibGUgPSB0cnVlOw0KPiA+ID4gPiA+ ID4gKyAgICAgICAgICAgICAgIG10a19kZHBfd3JpdGUoY21kcV9wa3QsDQo+ID4gPiA+ID4gPiAr ICAgICAgICAgICAgICAgICAgICAgICAgICAgICBESVRIRVJfTFNCX0VSUl9TSElGVF9SKE1US19N QVhfQlBDIC0gYnBjKSB8DQo+ID4gPiA+ID4gPiArICAgICAgICAgICAgICAgICAgICAgICAgICAg ICBESVRIRVJfQUREX0xTSElGVF9SKE1US19NQVhfQlBDIC0gYnBjKSB8DQo+ID4gPiA+ID4gPiAr ICAgICAgICAgICAgICAgICAgICAgICAgICAgICBESVRIRVJfTkVXX0JJVF9NT0RFLA0KPiA+ID4g PiA+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgJnByaXYtPmNtZHFfcmVnLCBwcml2 LT5yZWdzLCBESVRIRVJfUkVHKDE1KSk7DQo+ID4gPiA+ID4gPiArICAgICAgICAgICAgICAgbXRr X2RkcF93cml0ZShjbWRxX3BrdCwNCj4gPiA+ID4gPiA+ICsgICAgICAgICAgICAgICAgICAgICAg ICAgICAgIERJVEhFUl9MU0JfRVJSX1NISUZUX0IoTVRLX01BWF9CUEMgLSBicGMpIHwNCj4gPiA+ ID4gPiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgIERJVEhFUl9BRERfTFNISUZUX0Io TVRLX01BWF9CUEMgLSBicGMpIHwNCj4gPiA+ID4gPiA+ICsgICAgICAgICAgICAgICAgICAgICAg ICAgICAgIERJVEhFUl9MU0JfRVJSX1NISUZUX0coTVRLX01BWF9CUEMgLSBicGMpIHwNCj4gPiA+ ID4gPiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgIERJVEhFUl9BRERfTFNISUZUX0co TVRLX01BWF9CUEMgLSBicGMpLA0KPiA+ID4gPiA+DQo+ID4gPiA+ID4gVGhpcyByZXN1bHQgaW4g MHg1MDUwNTA1MCwgYnV0IHByZXZpb3VzIHZlcnNpb24gaXMgMHg1MDUwNDA0MCwgc28gdGhpcw0K PiA+ID4gPiA+IHZlcnNpb24gaXMgY29ycmVjdCBhbmQgcHJldmlvdXMgdmVyc2lvbiBpcyBpbmNv cnJlY3Q/DQo+ID4gPiA+DQo+ID4gPiA+IHRoZSBuZXcgdmVyc2lvbiBzZXQgciBnIGIgMyBjaGFu bmVsIHNhbWUsIHNlYW1zIG1vcmUgcmVhc29uYWJsZQ0KPiA+ID4gPg0KPiA+ID4gPg0KPiA+ID4N Cj4gPiA+IFNvIGFsbCB0aGUgc2V0dGluZyBvZiBESVNQX0RJVEhFUl81LCBESVNQX0RJVEhFUl83 LCBESVNQX0RJVEhFUl8xNSwNCj4gPiA+IERJU1BfRElUSEVSXzE2IGlzIGlkZW50aWNhbCB0byBt dGtfZGl0aGVyX3NldCgpLCBzbyBjYWxsDQo+ID4gPiBtdGtfZGl0aGVyX3NldCgpIGluc3RlYWQg b2YgZHVwbGljYXRpb24gaGVyZS4NCj4gPiA+DQo+ID4NCj4gPiBkaXRoZXIgZW5hYmxlIHNldCBp biBtdGtfZGl0aGVyX3NldCBpcw0KPiA+IG10a19kZHBfd3JpdGUoY21kcV9wa3QsIERJU1BfRElU SEVSSU5HLCBjb21wLCBDRkcpOw0KPiA+DQo+ID4gdGhhdCBpcyBkaWZmZXJlbnQgODE4MyBhbmQg bXQ4MTkyLg0KPiA+IG10ODE3MyBkaXRoZXIgZW5hYmxlIGluIGdhbW1hIGlzIGJpdDINCj4gPiBt dDgxODMgYW5kIG10ODE5MiBkaXRoZXIgZW5naW5lIGVuYWJsZSBpcyBiaXQgMQ0KPiA+DQo+ID4N Cj4gDQo+IFdlIGNhbiBzdGlsbCBjYWxsIG10a19kaXRoZXJfc2V0KCkgZm9yIGJwYyBpcyA1IG9y IDYgaGVyZSwgdGhvdWdoIGl0DQo+IHdpbGwgYmUgc2V0IHRvIGJpdDIsDQo+IGJ1dCBsYXRlciBp biBtdGtfZGRwX3dyaXRlKGNtZHFfcGt0LCBlbmFibGUgPyBESVRIRVJfRU5HSU5FX0VOIDoNCj4g RElUSEVSX1JFTEFZX01PREUsICZwcml2LT5jbWRxX3JlZywgcHJpdi0+cmVncywgRElTUF9ESVRI RVJfQ0ZHKTsgaXQNCj4gd2lsbCBiZSBjb3JyZWN0IGJhY2sgdG8gYml0IDEuDQo+IA0KPiBJcyB0 aGlzIHJlYXNvbmFibGU/DQoNCnRoZSByZXN1bHQgaXMgb2suDQo+IA0KPiA+ID4gUmVnYXJkcywN Cj4gPiA+IENLDQo+ID4gPiA+ID4NCj4gPiA+ID4gPiBSZWdhcmRzLA0KPiA+ID4gPiA+IENLDQo+ ID4gPiA+ID4NCj4gPiA+ID4gPiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICZwcml2 LT5jbWRxX3JlZywgcHJpdi0+cmVncywgRElUSEVSX1JFRygxNikpOw0KPiA+ID4gPiA+ID4gKyAg ICAgICB9DQo+ID4gPiA+ID4gPiArDQo+ID4gPiA+ID4gPiArDQo+ID4gPiA+ID4gPiArICAgICAg IGlmIChlbmFibGUpIHsNCj4gPiA+ID4gPiA+ICsgICAgICAgICAgICAgICB1MzIgaWR4Ow0KPiA+ ID4gPiA+ID4gKw0KPiA+ID4gPiA+ID4gKyAgICAgICAgICAgICAgIGZvciAoaWR4ID0gMDsgaWR4 IDwgQVJSQVlfU0laRShkaXRoZXJfc2V0dGluZyk7IGlkeCsrKQ0KPiA+ID4gPiA+ID4gKyAgICAg ICAgICAgICAgICAgICAgICAgbXRrX2RkcF93cml0ZShjbWRxX3BrdCwgZGl0aGVyX3NldHRpbmdb aWR4XSwgJnByaXYtPmNtZHFfcmVnLCBwcml2LT5yZWdzLA0KPiA+ID4gPiA+ID4gKyAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICBESVRIRVJfUkVHKGlkeCArIDUpKTsNCj4gPiA+ ID4gPiA+ICsgICAgICAgfQ0KPiA+ID4gPiA+ID4gKw0KPiA+ID4gPiA+ID4gICAgICAgICBtdGtf ZGRwX3dyaXRlKGNtZHFfcGt0LCBoIDw8IDE2IHwgdywgJnByaXYtPmNtZHFfcmVnLCBwcml2LT5y ZWdzLCBESVNQX0RJVEhFUl9TSVpFKTsNCj4gPiA+ID4gPiA+IC0gICAgICAgbXRrX2RkcF93cml0 ZShjbWRxX3BrdCwgRElUSEVSX1JFTEFZX01PREUsICZwcml2LT5jbWRxX3JlZywgcHJpdi0+cmVn cywgRElTUF9ESVRIRVJfQ0ZHKTsNCj4gPiA+ID4gPiA+ICsgICAgICAgIG10a19kZHBfd3JpdGUo Y21kcV9wa3QsIGVuYWJsZSA/IERJVEhFUl9FTkdJTkVfRU4gOiBESVRIRVJfUkVMQVlfTU9ERSwg JnByaXYtPmNtZHFfcmVnLCBwcml2LT5yZWdzLCBESVNQX0RJVEhFUl9DRkcpOw0KPiA+ID4gPiA+ ID4gIH0NCj4gPiA+ID4gPiA+DQo+ID4gPiA+ID4gPiAgc3RhdGljIHZvaWQgbXRrX2RpdGhlcl9z dGFydChzdHJ1Y3QgZGV2aWNlICpkZXYpDQo+ID4gPiA+ID4NCj4gPiA+ID4gPg0KPiA+ID4gPg0K PiA+ID4gPg0KPiA+ID4NCj4gPiA+DQo+ID4NCg0K From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30023C433DB for ; Thu, 28 Jan 2021 08:29:09 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9702564DA1 for ; Thu, 28 Jan 2021 08:29:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9702564DA1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:Reply-To:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Date:To:From: Subject:Message-ID:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=j15VuJ41aXmUQffZQ/C7nVbWn7lrENvrgl1tldXyFyQ=; b=sWs29sv7G8v8yacumwSTEn5ynG 3NXDKLIJfF6Kac2KOgnjCYRar52p1ovA7g5W6TM8isEahc9edjw8ayGB2ftapLF4Ub9fCqeKcb4Jz O5JKXbTZ4kvSW2BN8yEd+cf2kk3z8hW63vyRTiaPg9yr4Dc593Hn2Ilm4unwcrTgHOEyCwDlzeDTJ q9EBMy9+1agxMvYieJ+rcYwRXv39YbgvsCQTXSXyNUkZxQ4LiNAUbenX8Dg3PjcoDIsGO0siRi+vn NiQpoAvhPH3m3eL28z6k2vbdSfn2PCL3n88Oj45bC9DJNtjfj3e9AbRl8nONVlC2jBN4buX8QTHFX qYd1v+lg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l52fe-0002RL-Fw; Thu, 28 Jan 2021 08:28:54 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l52fb-0002Qt-8P; Thu, 28 Jan 2021 08:28:52 +0000 X-UUID: 51deaffb798744b48055767b26ff29b9-20210128 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:Reply-To:From:Subject:Message-ID; bh=xuMAXwo6AmkpKMd7GIWUbcpQOz0B7oib5M57arUVcdY=; b=ODT4aWplJCcUN+8IAk/DRmMTo3FCEb8CmoBGmeHhorpfjRPMe5K8ClwTdqKTvtxDbtHhoVl023FebbqAb6lyTKKMFl6oTiXFQx9BbtE4oonwhwOvGgCKNJW8wfI7Fbof2DMmxncui0Gkcofa8gw4TSrroQBO6bPxdyt9+qOTAJ8=; X-UUID: 51deaffb798744b48055767b26ff29b9-20210128 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1534673603; Thu, 28 Jan 2021 00:28:46 -0800 Received: from mtkmbs05n2.mediatek.inc (172.21.101.140) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 00:28:44 -0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 16:28:43 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 Jan 2021 16:28:42 +0800 Message-ID: <1611822522.1947.12.camel@mhfsdcap03> Subject: Re: [PATCH v11 7/9] drm/mediatek: enable dither function From: Yongqiang Niu To: Hsin-Yi Wang Date: Thu, 28 Jan 2021 16:28:42 +0800 In-Reply-To: References: <20210128072802.830971-1-hsinyi@chromium.org> <20210128072802.830971-8-hsinyi@chromium.org> <1611819766.16091.4.camel@mtksdaap41> <1611820770.1947.8.camel@mhfsdcap03> <1611821233.18369.4.camel@mtksdaap41> <1611821396.1947.10.camel@mhfsdcap03> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210128_032851_592858_0849A470 X-CRM114-Status: GOOD ( 32.76 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Yongqiang Niu Cc: Mark Rutland , Devicetree List , Philipp Zabel , David Airlie , lkml , dri-devel , Matthias Brugger , "moderated list:ARM/Mediatek SoC support" , Daniel Vetter , CK Hu , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Thu, 2021-01-28 at 16:18 +0800, Hsin-Yi Wang wrote: > On Thu, Jan 28, 2021 at 4:10 PM Yongqiang Niu > wrote: > > > > On Thu, 2021-01-28 at 16:07 +0800, CK Hu wrote: > > > On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote: > > > > On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote: > > > > > Hi, Hsin-Yi: > > > > > > > > > > On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote: > > > > > > From: Yongqiang Niu > > > > > > > > > > > > for 5 or 6 bpc panel, we need enable dither function > > > > > > to improve the display quality > > > > > > > > > > > > Signed-off-by: Yongqiang Niu > > > > > > Signed-off-by: Hsin-Yi Wang > > > > > > --- > > > > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 ++++++++++++++++++++- > > > > > > 1 file changed, 43 insertions(+), 1 deletion(-) > > > > > > > > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > > > index 8173f709272be..e85625704d611 100644 > > > > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > > > @@ -53,7 +53,9 @@ > > > > > > #define DITHER_EN BIT(0) > > > > > > #define DISP_DITHER_CFG 0x0020 > > > > > > #define DITHER_RELAY_MODE BIT(0) > > > > > > +#define DITHER_ENGINE_EN BIT(1) > > > > > > #define DISP_DITHER_SIZE 0x0030 > > > > > > +#define DITHER_REG(idx) (0x100 + (idx) * 4) > > > > > > > > > > > > #define LUT_10BIT_MASK 0x03ff > > > > > > > > > > > > @@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev, unsigned int w, > > > > > > { > > > > > > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > > > > > > > > > > > > + bool enable = false; > > > > > > + > > > > > > + /* default value for dither reg 5 to 14 */ > > > > > > + const u32 dither_setting[] = { > > > > > > + 0x00000000, /* 5 */ > > > > > > + 0x00003002, /* 6 */ > > > > > > + 0x00000000, /* 7 */ > > > > > > + 0x00000000, /* 8 */ > > > > > > + 0x00000000, /* 9 */ > > > > > > + 0x00000000, /* 10 */ > > > > > > + 0x00000000, /* 11 */ > > > > > > + 0x00000011, /* 12 */ > > > > > > + 0x00000000, /* 13 */ > > > > > > + 0x00000000, /* 14 */ > > > > > > > > > > Could you explain what is this? > > > > > > > > this is dither 5 to dither 14 setting > > > > this will be useless, we just need set dither 5 and dither 7 like > > > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5); > > > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7); > > > > other value is same with hardware default value. > > > > > > > > > > > > > > > > > > > + }; > > > > > > + > > > > > > + if (bpc == 5 || bpc == 6) { > > > > > > + enable = true; > > > > > > + mtk_ddp_write(cmdq_pkt, > > > > > > + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | > > > > > > + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | > > > > > > + DITHER_NEW_BIT_MODE, > > > > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(15)); > > > > > > + mtk_ddp_write(cmdq_pkt, > > > > > > + DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | > > > > > > + DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | > > > > > > + DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | > > > > > > + DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), > > > > > > > > > > This result in 0x50505050, but previous version is 0x50504040, so this > > > > > version is correct and previous version is incorrect? > > > > > > > > the new version set r g b 3 channel same, seams more reasonable > > > > > > > > > > > > > > So all the setting of DISP_DITHER_5, DISP_DITHER_7, DISP_DITHER_15, > > > DISP_DITHER_16 is identical to mtk_dither_set(), so call > > > mtk_dither_set() instead of duplication here. > > > > > > > dither enable set in mtk_dither_set is > > mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, CFG); > > > > that is different 8183 and mt8192. > > mt8173 dither enable in gamma is bit2 > > mt8183 and mt8192 dither engine enable is bit 1 > > > > > > We can still call mtk_dither_set() for bpc is 5 or 6 here, though it > will be set to bit2, > but later in mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : > DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); it > will be correct back to bit 1. > > Is this reasonable? the result is ok. > > > > Regards, > > > CK > > > > > > > > > > Regards, > > > > > CK > > > > > > > > > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(16)); > > > > > > + } > > > > > > + > > > > > > + > > > > > > + if (enable) { > > > > > > + u32 idx; > > > > > > + > > > > > > + for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++) > > > > > > + mtk_ddp_write(cmdq_pkt, dither_setting[idx], &priv->cmdq_reg, priv->regs, > > > > > > + DITHER_REG(idx + 5)); > > > > > > + } > > > > > > + > > > > > > mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE); > > > > > > - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > > > > > + mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > > > > > } > > > > > > > > > > > > static void mtk_dither_start(struct device *dev) > > > > > > > > > > > > > > > > > > > > > > > > > > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8975EC433DB for ; Thu, 28 Jan 2021 08:30:17 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 301F064D9D for ; Thu, 28 Jan 2021 08:30:16 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 301F064D9D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:Reply-To:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Date:To:From: Subject:Message-ID:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=1PBr51BHFx0tAHXLxtK+xUJj0emHx/SYi6bMDXrA0Mo=; b=mjsSjlwpbopnozvZgNbf2oQ51G 3gYPj7LFb1lX9tgcClohDw/xW+DQLaHfJfVcUYPxkD76JfnL+3Ic2Wu9veVsldFh3mFtTOk3s/M3W XNGwGwu0CK0U6Jc0+FfVvIvdh/tofPxrcmJDKQbB5ibSxSmEZhG2zcqLR0oGFn7wDgzg8wOlaTaKq zf9XwkXeMbC9rUk+/t1tOT+K7pD9r3h2/BtN9Z6WOderRE0nk7FcmU9jFM/xdxv4pCt/eTVJBt8t1 brXmuKq5sRNCrltbk12rD5IMtxOiqwnMPjT8r9iRXU/u5+Sip1dzhxXHKEsHpa4/DV5LZXo9fy6FY 3torx2pQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l52ff-0002RS-IO; Thu, 28 Jan 2021 08:28:55 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l52fb-0002Qt-8P; Thu, 28 Jan 2021 08:28:52 +0000 X-UUID: 51deaffb798744b48055767b26ff29b9-20210128 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:Reply-To:From:Subject:Message-ID; bh=xuMAXwo6AmkpKMd7GIWUbcpQOz0B7oib5M57arUVcdY=; b=ODT4aWplJCcUN+8IAk/DRmMTo3FCEb8CmoBGmeHhorpfjRPMe5K8ClwTdqKTvtxDbtHhoVl023FebbqAb6lyTKKMFl6oTiXFQx9BbtE4oonwhwOvGgCKNJW8wfI7Fbof2DMmxncui0Gkcofa8gw4TSrroQBO6bPxdyt9+qOTAJ8=; X-UUID: 51deaffb798744b48055767b26ff29b9-20210128 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1534673603; Thu, 28 Jan 2021 00:28:46 -0800 Received: from mtkmbs05n2.mediatek.inc (172.21.101.140) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 00:28:44 -0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 16:28:43 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 Jan 2021 16:28:42 +0800 Message-ID: <1611822522.1947.12.camel@mhfsdcap03> Subject: Re: [PATCH v11 7/9] drm/mediatek: enable dither function From: Yongqiang Niu To: Hsin-Yi Wang Date: Thu, 28 Jan 2021 16:28:42 +0800 In-Reply-To: References: <20210128072802.830971-1-hsinyi@chromium.org> <20210128072802.830971-8-hsinyi@chromium.org> <1611819766.16091.4.camel@mtksdaap41> <1611820770.1947.8.camel@mhfsdcap03> <1611821233.18369.4.camel@mtksdaap41> <1611821396.1947.10.camel@mhfsdcap03> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210128_032851_592858_0849A470 X-CRM114-Status: GOOD ( 32.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Yongqiang Niu Cc: Mark Rutland , Devicetree List , Philipp Zabel , David Airlie , lkml , dri-devel , Matthias Brugger , "moderated list:ARM/Mediatek SoC support" , Daniel Vetter , CK Hu , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 2021-01-28 at 16:18 +0800, Hsin-Yi Wang wrote: > On Thu, Jan 28, 2021 at 4:10 PM Yongqiang Niu > wrote: > > > > On Thu, 2021-01-28 at 16:07 +0800, CK Hu wrote: > > > On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote: > > > > On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote: > > > > > Hi, Hsin-Yi: > > > > > > > > > > On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote: > > > > > > From: Yongqiang Niu > > > > > > > > > > > > for 5 or 6 bpc panel, we need enable dither function > > > > > > to improve the display quality > > > > > > > > > > > > Signed-off-by: Yongqiang Niu > > > > > > Signed-off-by: Hsin-Yi Wang > > > > > > --- > > > > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 ++++++++++++++++++++- > > > > > > 1 file changed, 43 insertions(+), 1 deletion(-) > > > > > > > > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > > > index 8173f709272be..e85625704d611 100644 > > > > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > > > @@ -53,7 +53,9 @@ > > > > > > #define DITHER_EN BIT(0) > > > > > > #define DISP_DITHER_CFG 0x0020 > > > > > > #define DITHER_RELAY_MODE BIT(0) > > > > > > +#define DITHER_ENGINE_EN BIT(1) > > > > > > #define DISP_DITHER_SIZE 0x0030 > > > > > > +#define DITHER_REG(idx) (0x100 + (idx) * 4) > > > > > > > > > > > > #define LUT_10BIT_MASK 0x03ff > > > > > > > > > > > > @@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev, unsigned int w, > > > > > > { > > > > > > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > > > > > > > > > > > > + bool enable = false; > > > > > > + > > > > > > + /* default value for dither reg 5 to 14 */ > > > > > > + const u32 dither_setting[] = { > > > > > > + 0x00000000, /* 5 */ > > > > > > + 0x00003002, /* 6 */ > > > > > > + 0x00000000, /* 7 */ > > > > > > + 0x00000000, /* 8 */ > > > > > > + 0x00000000, /* 9 */ > > > > > > + 0x00000000, /* 10 */ > > > > > > + 0x00000000, /* 11 */ > > > > > > + 0x00000011, /* 12 */ > > > > > > + 0x00000000, /* 13 */ > > > > > > + 0x00000000, /* 14 */ > > > > > > > > > > Could you explain what is this? > > > > > > > > this is dither 5 to dither 14 setting > > > > this will be useless, we just need set dither 5 and dither 7 like > > > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5); > > > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7); > > > > other value is same with hardware default value. > > > > > > > > > > > > > > > > > > > + }; > > > > > > + > > > > > > + if (bpc == 5 || bpc == 6) { > > > > > > + enable = true; > > > > > > + mtk_ddp_write(cmdq_pkt, > > > > > > + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | > > > > > > + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | > > > > > > + DITHER_NEW_BIT_MODE, > > > > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(15)); > > > > > > + mtk_ddp_write(cmdq_pkt, > > > > > > + DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | > > > > > > + DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | > > > > > > + DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | > > > > > > + DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), > > > > > > > > > > This result in 0x50505050, but previous version is 0x50504040, so this > > > > > version is correct and previous version is incorrect? > > > > > > > > the new version set r g b 3 channel same, seams more reasonable > > > > > > > > > > > > > > So all the setting of DISP_DITHER_5, DISP_DITHER_7, DISP_DITHER_15, > > > DISP_DITHER_16 is identical to mtk_dither_set(), so call > > > mtk_dither_set() instead of duplication here. > > > > > > > dither enable set in mtk_dither_set is > > mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, CFG); > > > > that is different 8183 and mt8192. > > mt8173 dither enable in gamma is bit2 > > mt8183 and mt8192 dither engine enable is bit 1 > > > > > > We can still call mtk_dither_set() for bpc is 5 or 6 here, though it > will be set to bit2, > but later in mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : > DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); it > will be correct back to bit 1. > > Is this reasonable? the result is ok. > > > > Regards, > > > CK > > > > > > > > > > Regards, > > > > > CK > > > > > > > > > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(16)); > > > > > > + } > > > > > > + > > > > > > + > > > > > > + if (enable) { > > > > > > + u32 idx; > > > > > > + > > > > > > + for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++) > > > > > > + mtk_ddp_write(cmdq_pkt, dither_setting[idx], &priv->cmdq_reg, priv->regs, > > > > > > + DITHER_REG(idx + 5)); > > > > > > + } > > > > > > + > > > > > > mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE); > > > > > > - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > > > > > + mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > > > > > } > > > > > > > > > > > > static void mtk_dither_start(struct device *dev) > > > > > > > > > > > > > > > > > > > > > > > > > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.0 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2944AC433DB for ; Thu, 28 Jan 2021 19:46:15 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E203764D99 for ; Thu, 28 Jan 2021 19:46:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E203764D99 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C95FA6EA17; Thu, 28 Jan 2021 19:46:12 +0000 (UTC) Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by gabe.freedesktop.org (Postfix) with ESMTP id 7AD1F6E93B for ; Thu, 28 Jan 2021 08:28:48 +0000 (UTC) X-UUID: a9e73fc880d84326a83f29bee8eadb6d-20210128 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:Reply-To:From:Subject:Message-ID; bh=xuMAXwo6AmkpKMd7GIWUbcpQOz0B7oib5M57arUVcdY=; b=ODT4aWplJCcUN+8IAk/DRmMTo3FCEb8CmoBGmeHhorpfjRPMe5K8ClwTdqKTvtxDbtHhoVl023FebbqAb6lyTKKMFl6oTiXFQx9BbtE4oonwhwOvGgCKNJW8wfI7Fbof2DMmxncui0Gkcofa8gw4TSrroQBO6bPxdyt9+qOTAJ8=; X-UUID: a9e73fc880d84326a83f29bee8eadb6d-20210128 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1238747793; Thu, 28 Jan 2021 16:28:44 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 16:28:43 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 Jan 2021 16:28:42 +0800 Message-ID: <1611822522.1947.12.camel@mhfsdcap03> Subject: Re: [PATCH v11 7/9] drm/mediatek: enable dither function From: Yongqiang Niu To: Hsin-Yi Wang Date: Thu, 28 Jan 2021 16:28:42 +0800 In-Reply-To: References: <20210128072802.830971-1-hsinyi@chromium.org> <20210128072802.830971-8-hsinyi@chromium.org> <1611819766.16091.4.camel@mtksdaap41> <1611820770.1947.8.camel@mhfsdcap03> <1611821233.18369.4.camel@mtksdaap41> <1611821396.1947.10.camel@mhfsdcap03> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-Mailman-Approved-At: Thu, 28 Jan 2021 19:44:34 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Yongqiang Niu Cc: Mark Rutland , Devicetree List , David Airlie , lkml , dri-devel , Matthias Brugger , "moderated list:ARM/Mediatek SoC support" , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Thu, 2021-01-28 at 16:18 +0800, Hsin-Yi Wang wrote: > On Thu, Jan 28, 2021 at 4:10 PM Yongqiang Niu > wrote: > > > > On Thu, 2021-01-28 at 16:07 +0800, CK Hu wrote: > > > On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote: > > > > On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote: > > > > > Hi, Hsin-Yi: > > > > > > > > > > On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote: > > > > > > From: Yongqiang Niu > > > > > > > > > > > > for 5 or 6 bpc panel, we need enable dither function > > > > > > to improve the display quality > > > > > > > > > > > > Signed-off-by: Yongqiang Niu > > > > > > Signed-off-by: Hsin-Yi Wang > > > > > > --- > > > > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 ++++++++++++++++++++- > > > > > > 1 file changed, 43 insertions(+), 1 deletion(-) > > > > > > > > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > > > index 8173f709272be..e85625704d611 100644 > > > > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > > > @@ -53,7 +53,9 @@ > > > > > > #define DITHER_EN BIT(0) > > > > > > #define DISP_DITHER_CFG 0x0020 > > > > > > #define DITHER_RELAY_MODE BIT(0) > > > > > > +#define DITHER_ENGINE_EN BIT(1) > > > > > > #define DISP_DITHER_SIZE 0x0030 > > > > > > +#define DITHER_REG(idx) (0x100 + (idx) * 4) > > > > > > > > > > > > #define LUT_10BIT_MASK 0x03ff > > > > > > > > > > > > @@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev, unsigned int w, > > > > > > { > > > > > > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > > > > > > > > > > > > + bool enable = false; > > > > > > + > > > > > > + /* default value for dither reg 5 to 14 */ > > > > > > + const u32 dither_setting[] = { > > > > > > + 0x00000000, /* 5 */ > > > > > > + 0x00003002, /* 6 */ > > > > > > + 0x00000000, /* 7 */ > > > > > > + 0x00000000, /* 8 */ > > > > > > + 0x00000000, /* 9 */ > > > > > > + 0x00000000, /* 10 */ > > > > > > + 0x00000000, /* 11 */ > > > > > > + 0x00000011, /* 12 */ > > > > > > + 0x00000000, /* 13 */ > > > > > > + 0x00000000, /* 14 */ > > > > > > > > > > Could you explain what is this? > > > > > > > > this is dither 5 to dither 14 setting > > > > this will be useless, we just need set dither 5 and dither 7 like > > > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5); > > > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7); > > > > other value is same with hardware default value. > > > > > > > > > > > > > > > > > > > + }; > > > > > > + > > > > > > + if (bpc == 5 || bpc == 6) { > > > > > > + enable = true; > > > > > > + mtk_ddp_write(cmdq_pkt, > > > > > > + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | > > > > > > + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | > > > > > > + DITHER_NEW_BIT_MODE, > > > > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(15)); > > > > > > + mtk_ddp_write(cmdq_pkt, > > > > > > + DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | > > > > > > + DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | > > > > > > + DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | > > > > > > + DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), > > > > > > > > > > This result in 0x50505050, but previous version is 0x50504040, so this > > > > > version is correct and previous version is incorrect? > > > > > > > > the new version set r g b 3 channel same, seams more reasonable > > > > > > > > > > > > > > So all the setting of DISP_DITHER_5, DISP_DITHER_7, DISP_DITHER_15, > > > DISP_DITHER_16 is identical to mtk_dither_set(), so call > > > mtk_dither_set() instead of duplication here. > > > > > > > dither enable set in mtk_dither_set is > > mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, CFG); > > > > that is different 8183 and mt8192. > > mt8173 dither enable in gamma is bit2 > > mt8183 and mt8192 dither engine enable is bit 1 > > > > > > We can still call mtk_dither_set() for bpc is 5 or 6 here, though it > will be set to bit2, > but later in mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : > DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); it > will be correct back to bit 1. > > Is this reasonable? the result is ok. > > > > Regards, > > > CK > > > > > > > > > > Regards, > > > > > CK > > > > > > > > > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(16)); > > > > > > + } > > > > > > + > > > > > > + > > > > > > + if (enable) { > > > > > > + u32 idx; > > > > > > + > > > > > > + for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++) > > > > > > + mtk_ddp_write(cmdq_pkt, dither_setting[idx], &priv->cmdq_reg, priv->regs, > > > > > > + DITHER_REG(idx + 5)); > > > > > > + } > > > > > > + > > > > > > mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE); > > > > > > - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > > > > > + mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > > > > > } > > > > > > > > > > > > static void mtk_dither_start(struct device *dev) > > > > > > > > > > > > > > > > > > > > > > > > > > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel