* [PATCH] drm/amdgpu/gfx10: update register offsets for VGH in the gfx_v10_0_setup_grbm_cam_remapping function
@ 2021-02-03 8:30 chen gong
2021-02-03 23:37 ` Alex Deucher
0 siblings, 1 reply; 4+ messages in thread
From: chen gong @ 2021-02-03 8:30 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, chen gong
For Vangogh, the offset values of some GC registers used in the
gfx_v10_0_setup_grbm_cam_remapping() function are not the same as those
of Sienna_Cichlid, so cannot be reused.
Although gfx_v10_0_setup_grbm_cam_remapping() is not called now for
Vangogh, it is necessary to implement this patch in case we enable this
code in the future.
Signed-off-by: chen gong <curry.gong@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 56 +++++++++++++++++++++++++++++++++-
1 file changed, 55 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 8ac2af2..a9ce2a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -7029,9 +7029,63 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
switch (adev->asic_type) {
+ case CHIP_VANGOGH:
+ /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
+ data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
+ GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
+ (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Vangogh) <<
+ GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
+
+ /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
+ data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
+ GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
+ (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Vangogh) <<
+ GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
+
+ /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
+ data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
+ GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
+ (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Vangogh) <<
+ GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
+
+ /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
+ data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
+ GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
+ (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Vangogh) <<
+ GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
+
+ /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
+ data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
+ GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
+ (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Vangogh) <<
+ GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
+
+ /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
+ data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
+ GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
+ (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Vangogh) <<
+ GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
+
+ /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
+ data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
+ GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
+ (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Vangogh) <<
+ GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
+ break;
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
- case CHIP_VANGOGH:
case CHIP_DIMGREY_CAVEFISH:
/* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/amdgpu/gfx10: update register offsets for VGH in the gfx_v10_0_setup_grbm_cam_remapping function
2021-02-03 8:30 [PATCH] drm/amdgpu/gfx10: update register offsets for VGH in the gfx_v10_0_setup_grbm_cam_remapping function chen gong
@ 2021-02-03 23:37 ` Alex Deucher
0 siblings, 0 replies; 4+ messages in thread
From: Alex Deucher @ 2021-02-03 23:37 UTC (permalink / raw)
To: chen gong; +Cc: Deucher, Alexander, amd-gfx list
On Wed, Feb 3, 2021 at 3:30 AM chen gong <curry.gong@amd.com> wrote:
>
> For Vangogh, the offset values of some GC registers used in the
> gfx_v10_0_setup_grbm_cam_remapping() function are not the same as those
> of Sienna_Cichlid, so cannot be reused.
>
> Although gfx_v10_0_setup_grbm_cam_remapping() is not called now for
> Vangogh, it is necessary to implement this patch in case we enable this
> code in the future.
>
> Signed-off-by: chen gong <curry.gong@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 56 +++++++++++++++++++++++++++++++++-
> 1 file changed, 55 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 8ac2af2..a9ce2a0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -7029,9 +7029,63 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
> WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
>
> switch (adev->asic_type) {
> + case CHIP_VANGOGH:
> + /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
> + data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
> + GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
> + (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Vangogh) <<
> + GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
> + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
> + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
> +
> + /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
> + data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
> + GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
> + (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Vangogh) <<
> + GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
> + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
> + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
> +
> + /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
> + data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
> + GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
> + (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Vangogh) <<
> + GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
> + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
> + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
> +
> + /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
> + data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
> + GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
> + (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Vangogh) <<
> + GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
> + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
> + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
> +
> + /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
> + data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
> + GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
> + (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Vangogh) <<
> + GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
> + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
> + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
> +
> + /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
> + data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
> + GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
> + (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Vangogh) <<
> + GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
> + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
> + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
> +
> + /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
> + data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
> + GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
> + (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Vangogh) <<
> + GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
> + break;
> case CHIP_SIENNA_CICHLID:
> case CHIP_NAVY_FLOUNDER:
> - case CHIP_VANGOGH:
> case CHIP_DIMGREY_CAVEFISH:
> /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
> data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/amdgpu/gfx10: update register offsets for VGH in the gfx_v10_0_setup_grbm_cam_remapping function
2021-02-01 9:07 chen gong
@ 2021-02-01 15:30 ` Alex Deucher
0 siblings, 0 replies; 4+ messages in thread
From: Alex Deucher @ 2021-02-01 15:30 UTC (permalink / raw)
To: chen gong; +Cc: amd-gfx list
On Mon, Feb 1, 2021 at 4:07 AM chen gong <curry.gong@amd.com> wrote:
>
Missing patch description.
Also, nothing wrong with the change per se, but
gfx_v10_0_check_grbm_cam_remapping() returns true for vangogh, so
gfx_v10_0_setup_grbm_cam_remapping() is never called for vangogh.
Alex
> Signed-off-by: chen gong <curry.gong@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 56 +++++++++++++++++++++++++++++++++-
> 1 file changed, 55 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 024460b..d7e9a18 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -7031,9 +7031,63 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
> WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
>
> switch (adev->asic_type) {
> + case CHIP_VANGOGH:
> + /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
> + data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
> + GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
> + (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Vangogh) <<
> + GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
> + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
> + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
> +
> + /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
> + data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
> + GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
> + (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Vangogh) <<
> + GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
> + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
> + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
> +
> + /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
> + data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
> + GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
> + (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Vangogh) <<
> + GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
> + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
> + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
> +
> + /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
> + data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
> + GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
> + (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Vangogh) <<
> + GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
> + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
> + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
> +
> + /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
> + data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
> + GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
> + (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Vangogh) <<
> + GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
> + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
> + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
> +
> + /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
> + data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
> + GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
> + (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Vangogh) <<
> + GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
> + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
> + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
> +
> + /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
> + data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
> + GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
> + (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Vangogh) <<
> + GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
> + break;
> case CHIP_SIENNA_CICHLID:
> case CHIP_NAVY_FLOUNDER:
> - case CHIP_VANGOGH:
> case CHIP_DIMGREY_CAVEFISH:
> /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
> data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH] drm/amdgpu/gfx10: update register offsets for VGH in the gfx_v10_0_setup_grbm_cam_remapping function
@ 2021-02-01 9:07 chen gong
2021-02-01 15:30 ` Alex Deucher
0 siblings, 1 reply; 4+ messages in thread
From: chen gong @ 2021-02-01 9:07 UTC (permalink / raw)
To: amd-gfx; +Cc: chen gong
Signed-off-by: chen gong <curry.gong@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 56 +++++++++++++++++++++++++++++++++-
1 file changed, 55 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 024460b..d7e9a18 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -7031,9 +7031,63 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
switch (adev->asic_type) {
+ case CHIP_VANGOGH:
+ /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
+ data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
+ GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
+ (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Vangogh) <<
+ GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
+
+ /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
+ data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
+ GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
+ (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Vangogh) <<
+ GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
+
+ /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
+ data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
+ GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
+ (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Vangogh) <<
+ GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
+
+ /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
+ data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
+ GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
+ (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Vangogh) <<
+ GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
+
+ /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
+ data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
+ GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
+ (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Vangogh) <<
+ GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
+
+ /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
+ data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
+ GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
+ (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Vangogh) <<
+ GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
+
+ /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
+ data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
+ GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
+ (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Vangogh) <<
+ GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
+ break;
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
- case CHIP_VANGOGH:
case CHIP_DIMGREY_CAVEFISH:
/* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-02-03 23:37 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-02-03 8:30 [PATCH] drm/amdgpu/gfx10: update register offsets for VGH in the gfx_v10_0_setup_grbm_cam_remapping function chen gong
2021-02-03 23:37 ` Alex Deucher
-- strict thread matches above, loose matches on Subject: below --
2021-02-01 9:07 chen gong
2021-02-01 15:30 ` Alex Deucher
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.