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Wed, 17 Feb 2021 20:49:59 -0800 Envelope-to: shubhrajyoti.datta@xilinx.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, mturquette@baylibre.com, sboyd@kernel.org, gregkh@linuxfoundation.org, shubhrajyoti.datta@gmail.com, miquel.raynal@bootlin.com Received: from [10.140.6.59] (port=35054 helo=xhdshubhraj40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1lCbGJ-0004qG-4P; Wed, 17 Feb 2021 20:49:59 -0800 From: Shubhrajyoti Datta To: CC: , , , , , , "Shubhrajyoti Datta" Subject: [PATCH v9 1/7] dt-bindings: add documentation of xilinx clocking wizard Date: Thu, 18 Feb 2021 10:19:45 +0530 Message-ID: <1613623791-4598-2-git-send-email-shubhrajyoti.datta@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1613623791-4598-1-git-send-email-shubhrajyoti.datta@xilinx.com> References: <1613623791-4598-1-git-send-email-shubhrajyoti.datta@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9abe0f89-1aeb-41b5-d62a-08d8d3c8a639 X-MS-TrafficTypeDiagnostic: MN2PR02MB7024: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:439; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Feb 2021 04:50:00.7753 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9abe0f89-1aeb-41b5-d62a-08d8d3c8a639 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: DM3NAM02FT010.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR02MB7024 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the devicetree binding for the xilinx clocking wizard. Signed-off-by: Shubhrajyoti Datta --- v6: Fix a yaml warning v7: Add vendor prefix speed-grade v8: Fix the warnings v9: Fix the warnings .../bindings/clock/xlnx,clocking-wizard.yaml | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml new file mode 100644 index 0000000..d209140 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Xilinx clocking wizard + +maintainers: + - Shubhrajyoti Datta + +description: + The clocking wizard is a soft ip clocking block of Xilinx versal. It + reads required input clock frequencies from the devicetree and acts as clock + clock output. + +properties: + compatible: + const: xlnx,clocking-wizard + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + clocks: + items: + - description: clock input + - description: axi clock + + clock-names: + items: + - const: clk_in1 + - const: s_axi_aclk + + clock-output-names: true + + xlnx,speed-grade: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3] + description: + Speed grade of the device. + +required: + - compatible + - reg + - "#clock-cells" + - clocks + - clock-names + - xlnx,speed-grade + +additionalProperties: false + +examples: + - | + clock-controller { + compatible = "xlnx,clocking-wizard"; + reg = <0xb0000000 0x10000>; + #clock-cells = <1>; + xlnx,speed-grade = <1>; + clock-names = "clk_in1", "s_axi_aclk"; + clocks = <&clkc 15>, <&clkc 15>; + }; +... -- 2.1.1